Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	787	1			T17	7		T19	10		T20	17
all_values[1]	787	1			T17	7		T19	10		T20	17
all_values[2]	787	1			T17	7		T19	10		T20	17
all_values[3]	787	1			T17	7		T19	10		T20	17
all_values[4]	787	1			T17	7		T19	10		T20	17
all_values[5]	787	1			T17	7		T19	10		T20	17
all_values[6]	787	1			T17	7		T19	10		T20	17
all_values[7]	787	1			T17	7		T19	10		T20	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3309

1

T17

26

T19

42

T20

68

auto[1]

2987

1

T17

30

T19

38

T20

68

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2473

1

T17

19

T19

39

T20

59

auto[1]

3823

1

T17

37

T19

41

T20

77

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3573

1

T17

27

T19

50

T20

72

auto[1]

2723

1

T17

29

T19

30

T20

64

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	134	1			T20	1		T31	1		T162	2
all_values[0]	auto[0]	auto[0]	auto[1]	102	1			T19	3		T20	1		T31	2
all_values[0]	auto[0]	auto[1]	auto[0]	137	1			T17	2		T19	3		T20	6
all_values[0]	auto[0]	auto[1]	auto[1]	71	1			T17	1		T20	2		T21	2
all_values[0]	auto[1]	auto[0]	auto[1]	193	1			T17	2		T20	2		T31	3
all_values[0]	auto[1]	auto[1]	auto[1]	150	1			T17	2		T19	4		T20	5
all_values[1]	auto[0]	auto[0]	auto[0]	139	1			T19	1		T20	3		T31	2
all_values[1]	auto[0]	auto[0]	auto[1]	72	1			T19	1		T36	2		T162	1
all_values[1]	auto[0]	auto[1]	auto[0]	135	1			T17	2		T19	4		T20	4
all_values[1]	auto[0]	auto[1]	auto[1]	77	1			T19	1		T20	1		T21	1
all_values[1]	auto[1]	auto[0]	auto[1]	199	1			T17	1		T19	1		T20	4
all_values[1]	auto[1]	auto[1]	auto[1]	165	1			T17	4		T19	2		T20	5
all_values[2]	auto[0]	auto[0]	auto[0]	154	1			T17	1		T19	4		T20	1
all_values[2]	auto[0]	auto[0]	auto[1]	71	1			T17	2		T162	1		T163	1
all_values[2]	auto[0]	auto[1]	auto[0]	146	1			T19	2		T20	3		T21	2
all_values[2]	auto[0]	auto[1]	auto[1]	81	1			T20	2		T21	1		T36	1
all_values[2]	auto[1]	auto[0]	auto[1]	168	1			T17	3		T19	2		T20	9
all_values[2]	auto[1]	auto[1]	auto[1]	167	1			T17	1		T19	2		T20	2
all_values[3]	auto[0]	auto[0]	auto[0]	138	1			T19	6		T20	4		T21	1
all_values[3]	auto[0]	auto[0]	auto[1]	83	1			T20	1		T21	1		T31	3
all_values[3]	auto[0]	auto[1]	auto[0]	139	1			T17	4		T20	1		T21	1
all_values[3]	auto[0]	auto[1]	auto[1]	79	1			T17	2		T20	2		T31	1
all_values[3]	auto[1]	auto[0]	auto[1]	203	1			T19	4		T20	6		T21	1
all_values[3]	auto[1]	auto[1]	auto[1]	145	1			T17	1		T20	3		T21	4
all_values[4]	auto[0]	auto[0]	auto[0]	157	1			T20	2		T21	2		T31	1
all_values[4]	auto[0]	auto[0]	auto[1]	77	1			T17	2		T19	1		T20	3
all_values[4]	auto[0]	auto[1]	auto[0]	154	1			T19	5		T20	3		T21	5
all_values[4]	auto[0]	auto[1]	auto[1]	73	1			T17	1		T20	1		T162	1
all_values[4]	auto[1]	auto[0]	auto[1]	180	1			T17	2		T19	4		T20	4
all_values[4]	auto[1]	auto[1]	auto[1]	146	1			T17	2		T20	4		T31	1
all_values[5]	auto[0]	auto[0]	auto[0]	238	1			T17	2		T19	2		T20	4
all_values[5]	auto[0]	auto[1]	auto[0]	219	1			T17	1		T19	4		T20	6
all_values[5]	auto[1]	auto[0]	auto[1]	171	1			T17	1		T19	1		T20	2
all_values[5]	auto[1]	auto[1]	auto[1]	159	1			T17	3		T19	3		T20	5
all_values[6]	auto[0]	auto[0]	auto[0]	169	1			T17	1		T19	4		T20	7
all_values[6]	auto[0]	auto[0]	auto[1]	89	1			T19	1		T36	1		T164	2
all_values[6]	auto[0]	auto[1]	auto[0]	139	1			T17	1		T19	1		T20	4
all_values[6]	auto[0]	auto[1]	auto[1]	73	1			T19	1		T21	1		T31	3
all_values[6]	auto[1]	auto[0]	auto[1]	189	1			T17	5		T19	1		T20	5
all_values[6]	auto[1]	auto[1]	auto[1]	128	1			T19	2		T20	1		T21	1
all_values[7]	auto[0]	auto[0]	auto[0]	140	1			T17	2		T19	2		T20	4
all_values[7]	auto[0]	auto[0]	auto[1]	70	1			T19	1		T31	1		T36	2
all_values[7]	auto[0]	auto[1]	auto[0]	135	1			T17	3		T19	1		T20	6
all_values[7]	auto[0]	auto[1]	auto[1]	82	1			T19	2		T21	3		T31	2
all_values[7]	auto[1]	auto[0]	auto[1]	173	1			T17	2		T19	3		T20	5
all_values[7]	auto[1]	auto[1]	auto[1]	187	1			T19	1		T20	2		T21	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal