Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51708

1

T2

341

T3

244

T4

151

auto[1]

17870

1

T2

61

T3

44

T4

28

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50615

1

T2

271

T3

183

T4

119

auto[1]

18963

1

T2

131

T3

105

T4

60

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35964	1			T2	212		T3	150		T4	80
others[1]	5903	1			T2	36		T3	26		T4	16
others[2]	5830	1			T2	31		T3	22		T4	20
others[3]	6638	1			T2	47		T3	25		T4	20
interest[1]	3812	1			T2	18		T3	16		T4	11
interest[4]	23541	1			T2	146		T3	93		T4	55
interest[64]	11431	1			T2	58		T3	49		T4	32

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16753	1			T2	112		T3	70		T4	38
auto[0]	auto[0]	others[1]	2822	1			T2	17		T3	12		T4	8
auto[0]	auto[0]	others[2]	2778	1			T2	23		T3	14		T4	14
auto[0]	auto[0]	others[3]	3184	1			T2	21		T3	15		T4	10
auto[0]	auto[0]	interest[1]	1791	1			T2	10		T3	6		T4	6
auto[0]	auto[0]	interest[4]	10936	1			T2	78		T3	47		T4	26
auto[0]	auto[0]	interest[64]	5417	1			T2	27		T3	22		T4	15
auto[0]	auto[1]	others[0]	9359	1			T2	31		T3	20		T4	9
auto[0]	auto[1]	others[1]	1497	1			T2	6		T3	1		T4	3
auto[0]	auto[1]	others[2]	1451	1			T2	3		T3	6		T4	4
auto[0]	auto[1]	others[3]	1671	1			T2	9		T3	4		T4	3
auto[0]	auto[1]	interest[1]	1023	1			T2	2		T3	4		T4	3
auto[0]	auto[1]	interest[4]	6194	1			T2	20		T3	10		T4	6
auto[0]	auto[1]	interest[64]	2869	1			T2	10		T3	9		T4	6
auto[1]	auto[0]	others[0]	9852	1			T2	69		T3	60		T4	33
auto[1]	auto[0]	others[1]	1584	1			T2	13		T3	13		T4	5
auto[1]	auto[0]	others[2]	1601	1			T2	5		T3	2		T4	2
auto[1]	auto[0]	others[3]	1783	1			T2	17		T3	6		T4	7
auto[1]	auto[0]	interest[1]	998	1			T2	6		T3	6		T4	2
auto[1]	auto[0]	interest[4]	6411	1			T2	48		T3	36		T4	23
auto[1]	auto[0]	interest[64]	3145	1			T2	21		T3	18		T4	11

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal