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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.35 94.02 98.62 89.36 97.23 95.43 99.25


Total test records in report: 1100
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1020 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4201719865 Jun 10 06:41:48 PM PDT 24 Jun 10 06:41:49 PM PDT 24 21987534 ps
T145 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2333307417 Jun 10 06:41:48 PM PDT 24 Jun 10 06:42:01 PM PDT 24 1644908863 ps
T1021 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.337061981 Jun 10 06:42:46 PM PDT 24 Jun 10 06:42:47 PM PDT 24 42377982 ps
T1022 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2010508374 Jun 10 06:42:24 PM PDT 24 Jun 10 06:42:28 PM PDT 24 127379263 ps
T173 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1856312410 Jun 10 06:42:35 PM PDT 24 Jun 10 06:42:57 PM PDT 24 7501425541 ps
T1023 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1551288802 Jun 10 06:42:23 PM PDT 24 Jun 10 06:42:25 PM PDT 24 50321365 ps
T1024 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1122148800 Jun 10 06:42:46 PM PDT 24 Jun 10 06:42:47 PM PDT 24 17811675 ps
T1025 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2801502228 Jun 10 06:42:35 PM PDT 24 Jun 10 06:42:38 PM PDT 24 72755281 ps
T1026 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3129476217 Jun 10 06:42:21 PM PDT 24 Jun 10 06:42:24 PM PDT 24 590096793 ps
T1027 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3880435544 Jun 10 06:42:56 PM PDT 24 Jun 10 06:42:57 PM PDT 24 34756438 ps
T73 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3854940511 Jun 10 06:41:35 PM PDT 24 Jun 10 06:41:37 PM PDT 24 81791269 ps
T1028 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1108750319 Jun 10 06:42:35 PM PDT 24 Jun 10 06:42:37 PM PDT 24 144093342 ps
T1029 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4281172741 Jun 10 06:41:51 PM PDT 24 Jun 10 06:41:52 PM PDT 24 20770683 ps
T1030 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2410576702 Jun 10 06:42:03 PM PDT 24 Jun 10 06:42:26 PM PDT 24 421820549 ps
T1031 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2117686029 Jun 10 06:42:24 PM PDT 24 Jun 10 06:42:26 PM PDT 24 51676480 ps
T1032 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.4001316416 Jun 10 06:42:50 PM PDT 24 Jun 10 06:42:51 PM PDT 24 17907214 ps
T174 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.4194879789 Jun 10 06:41:35 PM PDT 24 Jun 10 06:41:52 PM PDT 24 2026158934 ps
T118 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2397028053 Jun 10 06:41:57 PM PDT 24 Jun 10 06:42:00 PM PDT 24 61403416 ps
T120 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2815102752 Jun 10 06:41:42 PM PDT 24 Jun 10 06:41:45 PM PDT 24 68106290 ps
T1033 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1083488058 Jun 10 06:42:35 PM PDT 24 Jun 10 06:42:36 PM PDT 24 54385552 ps
T1034 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2223332563 Jun 10 06:42:30 PM PDT 24 Jun 10 06:42:34 PM PDT 24 479859984 ps
T99 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.625951588 Jun 10 06:42:31 PM PDT 24 Jun 10 06:42:33 PM PDT 24 27421620 ps
T1035 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2947979248 Jun 10 06:42:31 PM PDT 24 Jun 10 06:42:32 PM PDT 24 37324027 ps
T177 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2623980385 Jun 10 06:42:24 PM PDT 24 Jun 10 06:42:45 PM PDT 24 3156314588 ps
T1036 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2229622256 Jun 10 06:41:40 PM PDT 24 Jun 10 06:41:45 PM PDT 24 59517941 ps
T119 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3921656589 Jun 10 06:42:08 PM PDT 24 Jun 10 06:42:25 PM PDT 24 2548041082 ps
T1037 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.252054035 Jun 10 06:42:50 PM PDT 24 Jun 10 06:42:51 PM PDT 24 19262225 ps
T1038 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1006901659 Jun 10 06:42:46 PM PDT 24 Jun 10 06:42:48 PM PDT 24 41940781 ps
T1039 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2871168266 Jun 10 06:42:43 PM PDT 24 Jun 10 06:42:46 PM PDT 24 308248003 ps
T1040 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2001943729 Jun 10 06:42:11 PM PDT 24 Jun 10 06:42:20 PM PDT 24 463902419 ps
T102 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3504068205 Jun 10 06:42:12 PM PDT 24 Jun 10 06:42:14 PM PDT 24 35924416 ps
T74 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4030367728 Jun 10 06:41:33 PM PDT 24 Jun 10 06:41:35 PM PDT 24 24293876 ps
T1041 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.577914462 Jun 10 06:42:19 PM PDT 24 Jun 10 06:42:21 PM PDT 24 231539182 ps
T1042 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2089189366 Jun 10 06:42:43 PM PDT 24 Jun 10 06:42:44 PM PDT 24 76937644 ps
T1043 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3145830712 Jun 10 06:42:50 PM PDT 24 Jun 10 06:42:51 PM PDT 24 118609516 ps
T172 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.4203588982 Jun 10 06:42:20 PM PDT 24 Jun 10 06:42:45 PM PDT 24 3422975643 ps
T1044 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1628320468 Jun 10 06:41:31 PM PDT 24 Jun 10 06:41:33 PM PDT 24 124964504 ps
T1045 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.140698769 Jun 10 06:41:57 PM PDT 24 Jun 10 06:42:00 PM PDT 24 39008603 ps
T175 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1638872475 Jun 10 06:42:13 PM PDT 24 Jun 10 06:42:26 PM PDT 24 899754387 ps
T1046 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.161227961 Jun 10 06:41:43 PM PDT 24 Jun 10 06:41:44 PM PDT 24 17474489 ps
T96 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2101362618 Jun 10 06:42:34 PM PDT 24 Jun 10 06:42:37 PM PDT 24 305492314 ps
T75 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.834356889 Jun 10 06:41:57 PM PDT 24 Jun 10 06:41:59 PM PDT 24 44834755 ps
T1047 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1822404446 Jun 10 06:42:25 PM PDT 24 Jun 10 06:42:30 PM PDT 24 706939223 ps
T1048 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.306317373 Jun 10 06:42:45 PM PDT 24 Jun 10 06:42:53 PM PDT 24 1170372534 ps
T1049 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2495917526 Jun 10 06:41:43 PM PDT 24 Jun 10 06:41:44 PM PDT 24 19741972 ps
T1050 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2904670819 Jun 10 06:41:51 PM PDT 24 Jun 10 06:41:58 PM PDT 24 115760064 ps
T1051 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2469343328 Jun 10 06:42:38 PM PDT 24 Jun 10 06:42:40 PM PDT 24 97983424 ps
T121 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2931229269 Jun 10 06:41:56 PM PDT 24 Jun 10 06:42:04 PM PDT 24 117464451 ps
T1052 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1316664337 Jun 10 06:42:51 PM PDT 24 Jun 10 06:42:52 PM PDT 24 35355971 ps
T1053 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3107974626 Jun 10 06:42:09 PM PDT 24 Jun 10 06:42:11 PM PDT 24 292284654 ps
T1054 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2054257518 Jun 10 06:42:06 PM PDT 24 Jun 10 06:42:07 PM PDT 24 12418912 ps
T1055 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.628912469 Jun 10 06:42:23 PM PDT 24 Jun 10 06:42:26 PM PDT 24 149020557 ps
T1056 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.505852924 Jun 10 06:41:36 PM PDT 24 Jun 10 06:41:38 PM PDT 24 104492571 ps
T1057 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1515373758 Jun 10 06:41:55 PM PDT 24 Jun 10 06:41:58 PM PDT 24 288140444 ps
T1058 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.437820772 Jun 10 06:41:51 PM PDT 24 Jun 10 06:41:54 PM PDT 24 108130325 ps
T1059 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1769781048 Jun 10 06:42:44 PM PDT 24 Jun 10 06:42:45 PM PDT 24 49794690 ps
T1060 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.381460237 Jun 10 06:41:31 PM PDT 24 Jun 10 06:41:34 PM PDT 24 486314025 ps
T1061 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3458412319 Jun 10 06:41:44 PM PDT 24 Jun 10 06:41:46 PM PDT 24 28322333 ps
T1062 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4001514083 Jun 10 06:42:29 PM PDT 24 Jun 10 06:42:44 PM PDT 24 2725774757 ps
T1063 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3687137662 Jun 10 06:42:19 PM PDT 24 Jun 10 06:42:21 PM PDT 24 88618352 ps
T170 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1343929844 Jun 10 06:42:19 PM PDT 24 Jun 10 06:42:23 PM PDT 24 918165567 ps
T97 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2342879592 Jun 10 06:42:42 PM PDT 24 Jun 10 06:42:46 PM PDT 24 137858560 ps
T1064 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3204885556 Jun 10 06:42:54 PM PDT 24 Jun 10 06:42:55 PM PDT 24 134573628 ps
T1065 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2013598293 Jun 10 06:42:39 PM PDT 24 Jun 10 06:42:41 PM PDT 24 26760052 ps
T1066 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1233689849 Jun 10 06:41:40 PM PDT 24 Jun 10 06:41:42 PM PDT 24 164935968 ps
T1067 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2242801329 Jun 10 06:42:25 PM PDT 24 Jun 10 06:42:44 PM PDT 24 290777911 ps
T1068 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3877792066 Jun 10 06:42:48 PM PDT 24 Jun 10 06:42:49 PM PDT 24 169736820 ps
T1069 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1493302835 Jun 10 06:42:24 PM PDT 24 Jun 10 06:42:26 PM PDT 24 30243877 ps
T1070 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1614098343 Jun 10 06:42:02 PM PDT 24 Jun 10 06:42:03 PM PDT 24 33160675 ps
T1071 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3285025838 Jun 10 06:41:53 PM PDT 24 Jun 10 06:41:55 PM PDT 24 58277976 ps
T1072 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2734085762 Jun 10 06:42:12 PM PDT 24 Jun 10 06:42:13 PM PDT 24 30031855 ps
T1073 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1620478652 Jun 10 06:42:54 PM PDT 24 Jun 10 06:42:55 PM PDT 24 24640644 ps
T1074 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3619920163 Jun 10 06:42:26 PM PDT 24 Jun 10 06:42:27 PM PDT 24 43039395 ps
T1075 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.704370751 Jun 10 06:42:15 PM PDT 24 Jun 10 06:42:35 PM PDT 24 281451635 ps
T1076 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3388666848 Jun 10 06:42:34 PM PDT 24 Jun 10 06:42:37 PM PDT 24 115549336 ps
T1077 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.960154388 Jun 10 06:42:53 PM PDT 24 Jun 10 06:42:53 PM PDT 24 76862242 ps
T1078 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1172906916 Jun 10 06:41:55 PM PDT 24 Jun 10 06:41:57 PM PDT 24 86364561 ps
T1079 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1577516816 Jun 10 06:42:09 PM PDT 24 Jun 10 06:42:10 PM PDT 24 92252087 ps
T1080 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4178853186 Jun 10 06:42:12 PM PDT 24 Jun 10 06:42:16 PM PDT 24 572695756 ps
T1081 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.438422788 Jun 10 06:41:40 PM PDT 24 Jun 10 06:41:57 PM PDT 24 2714341601 ps
T76 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1309023600 Jun 10 06:42:03 PM PDT 24 Jun 10 06:42:05 PM PDT 24 79413015 ps
T1082 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3723114729 Jun 10 06:41:49 PM PDT 24 Jun 10 06:42:11 PM PDT 24 318430425 ps
T1083 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3670360281 Jun 10 06:41:32 PM PDT 24 Jun 10 06:41:47 PM PDT 24 641991315 ps
T1084 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3648921382 Jun 10 06:42:28 PM PDT 24 Jun 10 06:42:30 PM PDT 24 71114953 ps
T1085 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2941631810 Jun 10 06:42:49 PM PDT 24 Jun 10 06:42:50 PM PDT 24 45285553 ps
T1086 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2656104774 Jun 10 06:42:31 PM PDT 24 Jun 10 06:42:35 PM PDT 24 222165900 ps
T1087 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3836315688 Jun 10 06:42:56 PM PDT 24 Jun 10 06:42:57 PM PDT 24 33681017 ps
T1088 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3877254717 Jun 10 06:42:37 PM PDT 24 Jun 10 06:42:40 PM PDT 24 263075646 ps
T1089 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.103046962 Jun 10 06:42:54 PM PDT 24 Jun 10 06:42:55 PM PDT 24 34432789 ps
T1090 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1206664897 Jun 10 06:42:24 PM PDT 24 Jun 10 06:42:25 PM PDT 24 21434918 ps
T1091 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1148260773 Jun 10 06:42:24 PM PDT 24 Jun 10 06:42:25 PM PDT 24 17197017 ps
T1092 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3297954494 Jun 10 06:42:07 PM PDT 24 Jun 10 06:42:12 PM PDT 24 62049718 ps
T1093 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2937703852 Jun 10 06:41:31 PM PDT 24 Jun 10 06:41:32 PM PDT 24 29274572 ps
T1094 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.361492353 Jun 10 06:42:33 PM PDT 24 Jun 10 06:42:34 PM PDT 24 24153524 ps
T1095 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1966008894 Jun 10 06:42:08 PM PDT 24 Jun 10 06:42:12 PM PDT 24 311588965 ps
T1096 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1088629676 Jun 10 06:42:27 PM PDT 24 Jun 10 06:42:28 PM PDT 24 171286851 ps
T1097 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3040909573 Jun 10 06:42:49 PM PDT 24 Jun 10 06:42:50 PM PDT 24 11665425 ps
T1098 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.313862490 Jun 10 06:42:23 PM PDT 24 Jun 10 06:42:26 PM PDT 24 888143541 ps
T1099 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3668803771 Jun 10 06:42:49 PM PDT 24 Jun 10 06:42:50 PM PDT 24 43666234 ps
T1100 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3686743133 Jun 10 06:42:44 PM PDT 24 Jun 10 06:42:48 PM PDT 24 383572343 ps

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2184073563
Short name T2
Test name
Test status
Simulation time 116045416156 ps
CPU time 262.74 seconds
Started Jun 10 07:48:11 PM PDT 24
Finished Jun 10 07:52:35 PM PDT 24
Peak memory 250412 kb
Host smart-80816d89-5da4-44cd-841d-6617f087d472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184073563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2184073563
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1789393766
Short name T9
Test name
Test status
Simulation time 28567396697 ps
CPU time 133.17 seconds
Started Jun 10 07:47:53 PM PDT 24
Finished Jun 10 07:50:09 PM PDT 24
Peak memory 249072 kb
Host smart-80e06ed5-7709-452e-9a0e-d43197d2e615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789393766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1789393766
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2554130802
Short name T21
Test name
Test status
Simulation time 29056274645 ps
CPU time 178.76 seconds
Started Jun 10 07:48:48 PM PDT 24
Finished Jun 10 07:51:51 PM PDT 24
Peak memory 265196 kb
Host smart-55a65640-e19b-46b0-a304-5f876deb6b3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554130802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2554130802
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4030010835
Short name T85
Test name
Test status
Simulation time 404455942 ps
CPU time 2.77 seconds
Started Jun 10 06:42:19 PM PDT 24
Finished Jun 10 06:42:23 PM PDT 24
Peak memory 216648 kb
Host smart-9691991e-6fcf-41ae-be64-c6fd99d81677
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030010835 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.4030010835
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1822968315
Short name T19
Test name
Test status
Simulation time 25074009707 ps
CPU time 91.52 seconds
Started Jun 10 07:49:30 PM PDT 24
Finished Jun 10 07:51:04 PM PDT 24
Peak memory 262356 kb
Host smart-1eebb6b5-7b8c-44c8-92e2-c7dc2b96e103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822968315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1822968315
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3441711444
Short name T46
Test name
Test status
Simulation time 52180630621 ps
CPU time 202.69 seconds
Started Jun 10 07:49:28 PM PDT 24
Finished Jun 10 07:52:53 PM PDT 24
Peak memory 265096 kb
Host smart-973f646f-3ac0-4085-bfd0-0d011c850d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441711444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3441711444
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1138106192
Short name T57
Test name
Test status
Simulation time 19657248 ps
CPU time 0.74 seconds
Started Jun 10 07:47:33 PM PDT 24
Finished Jun 10 07:47:38 PM PDT 24
Peak memory 216008 kb
Host smart-9c5fa055-62d9-4911-bd41-3028b12bc560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138106192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1138106192
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2642292646
Short name T16
Test name
Test status
Simulation time 4400475317 ps
CPU time 98.95 seconds
Started Jun 10 07:48:43 PM PDT 24
Finished Jun 10 07:50:25 PM PDT 24
Peak memory 256452 kb
Host smart-90c67c1e-22e9-44e2-8172-92fb9067c65c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642292646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2642292646
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1661950479
Short name T124
Test name
Test status
Simulation time 82631540152 ps
CPU time 806.37 seconds
Started Jun 10 07:48:50 PM PDT 24
Finished Jun 10 08:02:21 PM PDT 24
Peak memory 283340 kb
Host smart-b94d4735-90e9-4d90-9180-e01b36fd1064
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661950479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1661950479
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2304135856
Short name T22
Test name
Test status
Simulation time 76538975 ps
CPU time 1.03 seconds
Started Jun 10 07:47:29 PM PDT 24
Finished Jun 10 07:47:33 PM PDT 24
Peak memory 235760 kb
Host smart-1f74c009-1df8-4202-ab09-1d8b4c87efae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304135856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2304135856
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1793092812
Short name T182
Test name
Test status
Simulation time 13911584760 ps
CPU time 143.92 seconds
Started Jun 10 07:47:26 PM PDT 24
Finished Jun 10 07:49:52 PM PDT 24
Peak memory 264728 kb
Host smart-9d806fab-7508-4feb-9080-e0e711285cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793092812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1793092812
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.435479173
Short name T123
Test name
Test status
Simulation time 43732485729 ps
CPU time 307.2 seconds
Started Jun 10 07:47:40 PM PDT 24
Finished Jun 10 07:52:52 PM PDT 24
Peak memory 273264 kb
Host smart-f3ba49ac-dd12-455e-9f17-df56abedf885
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435479173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.435479173
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.660754874
Short name T51
Test name
Test status
Simulation time 15771468447 ps
CPU time 47.46 seconds
Started Jun 10 07:47:39 PM PDT 24
Finished Jun 10 07:48:32 PM PDT 24
Peak memory 249496 kb
Host smart-fd14257b-1a5c-4bfa-99dc-2c13e28e8e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660754874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.660754874
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1125740861
Short name T107
Test name
Test status
Simulation time 1712507809 ps
CPU time 20.54 seconds
Started Jun 10 06:42:07 PM PDT 24
Finished Jun 10 06:42:28 PM PDT 24
Peak memory 215528 kb
Host smart-2666c785-e936-473e-91dd-4fc83118d7be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125740861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1125740861
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3039624854
Short name T221
Test name
Test status
Simulation time 79307623096 ps
CPU time 528.33 seconds
Started Jun 10 07:48:20 PM PDT 24
Finished Jun 10 07:57:13 PM PDT 24
Peak memory 256520 kb
Host smart-1a39bbfb-552b-4717-934a-e6fbe6b6ec34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039624854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3039624854
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.755724791
Short name T188
Test name
Test status
Simulation time 36979924739 ps
CPU time 204.33 seconds
Started Jun 10 07:48:08 PM PDT 24
Finished Jun 10 07:51:34 PM PDT 24
Peak memory 252664 kb
Host smart-5238d73e-bf7a-462e-82d5-51891946fcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755724791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.755724791
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3854940511
Short name T73
Test name
Test status
Simulation time 81791269 ps
CPU time 1.49 seconds
Started Jun 10 06:41:35 PM PDT 24
Finished Jun 10 06:41:37 PM PDT 24
Peak memory 207364 kb
Host smart-00e6ffb6-814c-496e-858c-b90c07b566af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854940511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3854940511
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.17041148
Short name T149
Test name
Test status
Simulation time 92598550950 ps
CPU time 472.32 seconds
Started Jun 10 07:47:37 PM PDT 24
Finished Jun 10 07:55:35 PM PDT 24
Peak memory 271344 kb
Host smart-3cf4b43b-c2f7-4aa5-8205-504559a59b45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17041148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_
all.17041148
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1219288466
Short name T95
Test name
Test status
Simulation time 1530237728 ps
CPU time 4.81 seconds
Started Jun 10 06:42:23 PM PDT 24
Finished Jun 10 06:42:28 PM PDT 24
Peak memory 215824 kb
Host smart-5088cf71-9c10-4881-9664-f8e23ff0d8a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219288466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1219288466
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1949927433
Short name T41
Test name
Test status
Simulation time 16443611475 ps
CPU time 91.23 seconds
Started Jun 10 07:48:04 PM PDT 24
Finished Jun 10 07:49:36 PM PDT 24
Peak memory 252276 kb
Host smart-ffed8c21-af9a-484a-bd7f-eb119dd9e3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949927433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1949927433
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.223130750
Short name T493
Test name
Test status
Simulation time 50309473 ps
CPU time 0.99 seconds
Started Jun 10 07:47:51 PM PDT 24
Finished Jun 10 07:47:55 PM PDT 24
Peak memory 217736 kb
Host smart-b6e683f6-e27d-438a-88fd-b1faf301ea63
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223130750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.223130750
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.4190035635
Short name T20
Test name
Test status
Simulation time 7613962608 ps
CPU time 114.57 seconds
Started Jun 10 07:47:27 PM PDT 24
Finished Jun 10 07:49:24 PM PDT 24
Peak memory 254932 kb
Host smart-cab008a3-deb4-42d1-a7e8-9430300b9d86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190035635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.4190035635
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3256996384
Short name T152
Test name
Test status
Simulation time 12588087806 ps
CPU time 177.45 seconds
Started Jun 10 07:48:20 PM PDT 24
Finished Jun 10 07:51:21 PM PDT 24
Peak memory 254960 kb
Host smart-00ca56ae-8b6d-43ad-8db4-c91d0f0c1119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256996384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3256996384
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2137829320
Short name T49
Test name
Test status
Simulation time 64539536381 ps
CPU time 191.98 seconds
Started Jun 10 07:48:06 PM PDT 24
Finished Jun 10 07:51:19 PM PDT 24
Peak memory 255804 kb
Host smart-358d91fd-d214-4c20-94e4-c039fffb331c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137829320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2137829320
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3048845786
Short name T122
Test name
Test status
Simulation time 7990027921 ps
CPU time 122.84 seconds
Started Jun 10 07:48:25 PM PDT 24
Finished Jun 10 07:50:33 PM PDT 24
Peak memory 255844 kb
Host smart-05f9b157-9253-4209-b549-7d35805f9a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048845786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3048845786
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3339805241
Short name T56
Test name
Test status
Simulation time 13609120 ps
CPU time 0.72 seconds
Started Jun 10 07:47:24 PM PDT 24
Finished Jun 10 07:47:27 PM PDT 24
Peak memory 205624 kb
Host smart-f4f18f4e-4386-4461-8849-e541b5b350fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339805241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
339805241
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2003368929
Short name T8
Test name
Test status
Simulation time 24819777561 ps
CPU time 98.42 seconds
Started Jun 10 07:49:33 PM PDT 24
Finished Jun 10 07:51:14 PM PDT 24
Peak memory 240232 kb
Host smart-15c09472-5db1-425e-84dc-3ad3c5688e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003368929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2003368929
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1935583570
Short name T137
Test name
Test status
Simulation time 2787287423 ps
CPU time 44.74 seconds
Started Jun 10 07:48:13 PM PDT 24
Finished Jun 10 07:49:00 PM PDT 24
Peak memory 232640 kb
Host smart-b5277364-45cb-4860-9e0f-e11a8314b88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935583570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1935583570
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1988884615
Short name T279
Test name
Test status
Simulation time 4538166218 ps
CPU time 97.29 seconds
Started Jun 10 07:48:45 PM PDT 24
Finished Jun 10 07:50:26 PM PDT 24
Peak memory 262212 kb
Host smart-ae94ff60-1eba-4868-b331-cf975f561b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988884615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1988884615
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2294831092
Short name T303
Test name
Test status
Simulation time 310546155149 ps
CPU time 454.74 seconds
Started Jun 10 07:48:37 PM PDT 24
Finished Jun 10 07:56:16 PM PDT 24
Peak memory 253876 kb
Host smart-eba96ced-e1ab-407a-940f-350e1e0156f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294831092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2294831092
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2751077122
Short name T98
Test name
Test status
Simulation time 167826795 ps
CPU time 3.8 seconds
Started Jun 10 06:42:08 PM PDT 24
Finished Jun 10 06:42:12 PM PDT 24
Peak memory 215748 kb
Host smart-cbef7519-28e5-49f1-be0c-f8ef3aab1695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751077122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
751077122
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1638872475
Short name T175
Test name
Test status
Simulation time 899754387 ps
CPU time 13.09 seconds
Started Jun 10 06:42:13 PM PDT 24
Finished Jun 10 06:42:26 PM PDT 24
Peak memory 216200 kb
Host smart-312b29ff-314f-45b5-ae40-c5f9a6e027b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638872475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1638872475
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3465977581
Short name T30
Test name
Test status
Simulation time 41542307760 ps
CPU time 222.57 seconds
Started Jun 10 07:49:29 PM PDT 24
Finished Jun 10 07:53:13 PM PDT 24
Peak memory 255532 kb
Host smart-f22db6b3-76c6-4f04-b918-db42a733a836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465977581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3465977581
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.593639725
Short name T201
Test name
Test status
Simulation time 167018123072 ps
CPU time 295.18 seconds
Started Jun 10 07:47:29 PM PDT 24
Finished Jun 10 07:52:27 PM PDT 24
Peak memory 249396 kb
Host smart-efa64fab-7671-48ed-bbfd-c7d36d93fc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593639725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
593639725
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.4206784246
Short name T164
Test name
Test status
Simulation time 30292426281 ps
CPU time 192.84 seconds
Started Jun 10 07:47:28 PM PDT 24
Finished Jun 10 07:50:43 PM PDT 24
Peak memory 261232 kb
Host smart-75433f2a-ffd6-4c96-a7ca-8a4ef2c5698c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206784246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.4206784246
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3557242295
Short name T31
Test name
Test status
Simulation time 196953940205 ps
CPU time 450.36 seconds
Started Jun 10 07:47:48 PM PDT 24
Finished Jun 10 07:55:21 PM PDT 24
Peak memory 254644 kb
Host smart-11b2d823-000e-4a60-bcab-801b0d961696
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557242295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3557242295
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.7835974
Short name T36
Test name
Test status
Simulation time 268679979074 ps
CPU time 561.35 seconds
Started Jun 10 07:48:13 PM PDT 24
Finished Jun 10 07:57:36 PM PDT 24
Peak memory 265540 kb
Host smart-3c337967-9f9a-4b46-b3be-bcf8e2b26112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7835974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_
all.7835974
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3381582864
Short name T302
Test name
Test status
Simulation time 18121600002 ps
CPU time 156.5 seconds
Started Jun 10 07:48:30 PM PDT 24
Finished Jun 10 07:51:11 PM PDT 24
Peak memory 257052 kb
Host smart-156ec931-3b85-4215-bdc7-fb01b6d9fe86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381582864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3381582864
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3964474832
Short name T913
Test name
Test status
Simulation time 320506684 ps
CPU time 5.24 seconds
Started Jun 10 07:49:28 PM PDT 24
Finished Jun 10 07:49:36 PM PDT 24
Peak memory 232552 kb
Host smart-ca995b8e-65c3-4675-ac96-e8d8cac54029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964474832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3964474832
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2623980385
Short name T177
Test name
Test status
Simulation time 3156314588 ps
CPU time 20.38 seconds
Started Jun 10 06:42:24 PM PDT 24
Finished Jun 10 06:42:45 PM PDT 24
Peak memory 215628 kb
Host smart-6957ec72-d8ef-4bc4-ba7d-9646abefc8b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623980385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2623980385
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1048649942
Short name T154
Test name
Test status
Simulation time 18929363113 ps
CPU time 145.99 seconds
Started Jun 10 07:47:14 PM PDT 24
Finished Jun 10 07:49:43 PM PDT 24
Peak memory 249124 kb
Host smart-e6f62474-8ef9-44fb-b205-476e9b659fce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048649942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1048649942
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1633364201
Short name T307
Test name
Test status
Simulation time 144654907623 ps
CPU time 165.92 seconds
Started Jun 10 07:47:22 PM PDT 24
Finished Jun 10 07:50:09 PM PDT 24
Peak memory 236744 kb
Host smart-66e58261-419c-4e7b-b9d6-8baad7da0d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633364201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1633364201
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2185199919
Short name T236
Test name
Test status
Simulation time 136638943245 ps
CPU time 194.34 seconds
Started Jun 10 07:47:42 PM PDT 24
Finished Jun 10 07:51:01 PM PDT 24
Peak memory 251840 kb
Host smart-eec5f347-0008-4e54-9876-902160ecff4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185199919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2185199919
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1695614341
Short name T337
Test name
Test status
Simulation time 59785997205 ps
CPU time 123.74 seconds
Started Jun 10 07:47:48 PM PDT 24
Finished Jun 10 07:49:54 PM PDT 24
Peak memory 249096 kb
Host smart-f57fa985-f108-4c6b-90ca-1d305fa526b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695614341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1695614341
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3178540873
Short name T323
Test name
Test status
Simulation time 6656610879 ps
CPU time 17.47 seconds
Started Jun 10 07:47:54 PM PDT 24
Finished Jun 10 07:48:14 PM PDT 24
Peak memory 232636 kb
Host smart-f91a151b-bfe8-4cbc-a126-172ffeec5618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178540873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3178540873
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2095584516
Short name T517
Test name
Test status
Simulation time 12484949326 ps
CPU time 55.45 seconds
Started Jun 10 07:48:19 PM PDT 24
Finished Jun 10 07:49:17 PM PDT 24
Peak memory 249032 kb
Host smart-de4ede4d-7f7f-4a9f-b830-bd435a906036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095584516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2095584516
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.4170068327
Short name T304
Test name
Test status
Simulation time 1206149070 ps
CPU time 6.49 seconds
Started Jun 10 07:48:30 PM PDT 24
Finished Jun 10 07:48:41 PM PDT 24
Peak memory 232528 kb
Host smart-0d9c9708-ebd1-414c-b3d3-7c7d028ee3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170068327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.4170068327
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3407218203
Short name T180
Test name
Test status
Simulation time 1139167424 ps
CPU time 5.54 seconds
Started Jun 10 07:48:38 PM PDT 24
Finished Jun 10 07:48:48 PM PDT 24
Peak memory 232520 kb
Host smart-94740c18-e073-47dc-a763-ade57879b377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407218203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3407218203
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1364303351
Short name T205
Test name
Test status
Simulation time 31377535704 ps
CPU time 107.18 seconds
Started Jun 10 07:48:47 PM PDT 24
Finished Jun 10 07:50:37 PM PDT 24
Peak memory 254188 kb
Host smart-3ef5cc3f-bfd7-407c-84f4-6281954a7b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364303351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1364303351
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3015664383
Short name T311
Test name
Test status
Simulation time 41452656564 ps
CPU time 57.31 seconds
Started Jun 10 07:48:51 PM PDT 24
Finished Jun 10 07:49:53 PM PDT 24
Peak memory 232720 kb
Host smart-83317b9e-a9b6-499a-b86e-a409b14365cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015664383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3015664383
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2082738729
Short name T216
Test name
Test status
Simulation time 17689914480 ps
CPU time 143.42 seconds
Started Jun 10 07:49:05 PM PDT 24
Finished Jun 10 07:51:30 PM PDT 24
Peak memory 256004 kb
Host smart-30a5bd3d-25ad-4fc3-919e-f98afe38c559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082738729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2082738729
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2139251408
Short name T247
Test name
Test status
Simulation time 3275083848 ps
CPU time 42.1 seconds
Started Jun 10 07:49:37 PM PDT 24
Finished Jun 10 07:50:23 PM PDT 24
Peak memory 239308 kb
Host smart-e8eaec6e-0bbf-4f51-81fc-61d99e59e674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139251408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2139251408
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1797313316
Short name T305
Test name
Test status
Simulation time 6606064592 ps
CPU time 36.11 seconds
Started Jun 10 07:49:44 PM PDT 24
Finished Jun 10 07:50:23 PM PDT 24
Peak memory 237884 kb
Host smart-6a4ea2d7-4180-4196-ad4f-b851704d1456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797313316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1797313316
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1113798604
Short name T317
Test name
Test status
Simulation time 21875480426 ps
CPU time 93.94 seconds
Started Jun 10 07:47:31 PM PDT 24
Finished Jun 10 07:49:09 PM PDT 24
Peak memory 253232 kb
Host smart-9eb36313-72fb-492d-bb4c-cdb3f41868f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113798604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1113798604
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2101362618
Short name T96
Test name
Test status
Simulation time 305492314 ps
CPU time 1.96 seconds
Started Jun 10 06:42:34 PM PDT 24
Finished Jun 10 06:42:37 PM PDT 24
Peak memory 215708 kb
Host smart-5739f8bf-6060-4d0d-a460-2856266a6f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101362618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2101362618
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1264378858
Short name T79
Test name
Test status
Simulation time 843668885 ps
CPU time 5.68 seconds
Started Jun 10 07:47:53 PM PDT 24
Finished Jun 10 07:48:01 PM PDT 24
Peak memory 232500 kb
Host smart-797bcdcb-2584-468f-a718-ad610ff8a2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264378858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1264378858
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2645856430
Short name T24
Test name
Test status
Simulation time 4139990379 ps
CPU time 9.48 seconds
Started Jun 10 07:47:53 PM PDT 24
Finished Jun 10 07:48:05 PM PDT 24
Peak memory 232620 kb
Host smart-93bdc496-cc11-4f9e-ba50-0102bade2cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645856430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2645856430
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3736680187
Short name T112
Test name
Test status
Simulation time 809509453 ps
CPU time 15.02 seconds
Started Jun 10 06:41:33 PM PDT 24
Finished Jun 10 06:41:48 PM PDT 24
Peak memory 215476 kb
Host smart-30827578-1fd3-40a3-b693-edef446d6b96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736680187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3736680187
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3670360281
Short name T1083
Test name
Test status
Simulation time 641991315 ps
CPU time 14.91 seconds
Started Jun 10 06:41:32 PM PDT 24
Finished Jun 10 06:41:47 PM PDT 24
Peak memory 207372 kb
Host smart-dde66490-8477-4283-8cc6-bce7bda9db15
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670360281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3670360281
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4030367728
Short name T74
Test name
Test status
Simulation time 24293876 ps
CPU time 1.32 seconds
Started Jun 10 06:41:33 PM PDT 24
Finished Jun 10 06:41:35 PM PDT 24
Peak memory 207272 kb
Host smart-b4fd58ca-8c4d-45b4-aa27-407cd740f6aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030367728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.4030367728
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.275564027
Short name T88
Test name
Test status
Simulation time 117414744 ps
CPU time 2.96 seconds
Started Jun 10 06:41:33 PM PDT 24
Finished Jun 10 06:41:36 PM PDT 24
Peak memory 218032 kb
Host smart-ac26286c-1558-4b16-8f57-ab6c61506b1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275564027 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.275564027
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1628320468
Short name T1044
Test name
Test status
Simulation time 124964504 ps
CPU time 1.84 seconds
Started Jun 10 06:41:31 PM PDT 24
Finished Jun 10 06:41:33 PM PDT 24
Peak memory 215428 kb
Host smart-83f744da-2786-4da9-86ed-81575c41e0fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628320468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
628320468
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2097011628
Short name T996
Test name
Test status
Simulation time 20234650 ps
CPU time 0.7 seconds
Started Jun 10 06:41:28 PM PDT 24
Finished Jun 10 06:41:29 PM PDT 24
Peak memory 203844 kb
Host smart-89d009b5-4bdc-4eeb-bf6e-9b3079d828cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097011628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
097011628
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2937703852
Short name T1093
Test name
Test status
Simulation time 29274572 ps
CPU time 1.36 seconds
Started Jun 10 06:41:31 PM PDT 24
Finished Jun 10 06:41:32 PM PDT 24
Peak memory 215576 kb
Host smart-ec14cb6c-d9c8-4765-a581-07ba84930dbe
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937703852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2937703852
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1945753848
Short name T987
Test name
Test status
Simulation time 128768910 ps
CPU time 0.66 seconds
Started Jun 10 06:41:31 PM PDT 24
Finished Jun 10 06:41:32 PM PDT 24
Peak memory 204172 kb
Host smart-3d8bf84d-32cc-40e4-b3d7-85746880142c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945753848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1945753848
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.381460237
Short name T1060
Test name
Test status
Simulation time 486314025 ps
CPU time 2.8 seconds
Started Jun 10 06:41:31 PM PDT 24
Finished Jun 10 06:41:34 PM PDT 24
Peak memory 215584 kb
Host smart-45f4f940-7502-4185-ba30-0622e05d2bc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381460237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.381460237
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4247658
Short name T91
Test name
Test status
Simulation time 79216175 ps
CPU time 2.37 seconds
Started Jun 10 06:41:23 PM PDT 24
Finished Jun 10 06:41:26 PM PDT 24
Peak memory 215676 kb
Host smart-9cbcd0b8-421d-49d4-9a75-713c68653456
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.4247658
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3716133601
Short name T999
Test name
Test status
Simulation time 1766812964 ps
CPU time 7.7 seconds
Started Jun 10 06:41:29 PM PDT 24
Finished Jun 10 06:41:37 PM PDT 24
Peak memory 215524 kb
Host smart-4ec7ac91-5c43-4f93-968a-944ef90f0506
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716133601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3716133601
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2219630759
Short name T989
Test name
Test status
Simulation time 3394601708 ps
CPU time 16.31 seconds
Started Jun 10 06:41:39 PM PDT 24
Finished Jun 10 06:41:56 PM PDT 24
Peak memory 215624 kb
Host smart-ef340e54-4b72-4806-8cb1-1704026e1157
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219630759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2219630759
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2335165260
Short name T113
Test name
Test status
Simulation time 2826003258 ps
CPU time 43.81 seconds
Started Jun 10 06:41:38 PM PDT 24
Finished Jun 10 06:42:22 PM PDT 24
Peak memory 207376 kb
Host smart-6b158e27-96e4-4f55-9e3e-69b66452a5b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335165260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2335165260
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2229622256
Short name T1036
Test name
Test status
Simulation time 59517941 ps
CPU time 4.44 seconds
Started Jun 10 06:41:40 PM PDT 24
Finished Jun 10 06:41:45 PM PDT 24
Peak memory 217688 kb
Host smart-94f8b003-bacb-4053-a4dd-5c7bdc82e44d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229622256 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2229622256
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.504067291
Short name T114
Test name
Test status
Simulation time 689784613 ps
CPU time 2.68 seconds
Started Jun 10 06:41:39 PM PDT 24
Finished Jun 10 06:41:42 PM PDT 24
Peak memory 215504 kb
Host smart-e95a8c3d-c052-43ee-9e85-4b481963a636
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504067291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.504067291
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1302711572
Short name T1018
Test name
Test status
Simulation time 23128998 ps
CPU time 0.67 seconds
Started Jun 10 06:41:35 PM PDT 24
Finished Jun 10 06:41:36 PM PDT 24
Peak memory 203896 kb
Host smart-89f830da-04d2-4a46-8555-ee0b14be5cd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302711572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
302711572
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.505852924
Short name T1056
Test name
Test status
Simulation time 104492571 ps
CPU time 1.69 seconds
Started Jun 10 06:41:36 PM PDT 24
Finished Jun 10 06:41:38 PM PDT 24
Peak memory 215556 kb
Host smart-b426d9a5-29d6-4131-be3f-8e40d95c2127
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505852924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.505852924
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1949965172
Short name T992
Test name
Test status
Simulation time 12786476 ps
CPU time 0.69 seconds
Started Jun 10 06:41:36 PM PDT 24
Finished Jun 10 06:41:37 PM PDT 24
Peak memory 204100 kb
Host smart-2c3fc2c4-8416-41a8-9f03-0c85273dd6d3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949965172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1949965172
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1440608577
Short name T1012
Test name
Test status
Simulation time 92457947 ps
CPU time 1.83 seconds
Started Jun 10 06:41:39 PM PDT 24
Finished Jun 10 06:41:41 PM PDT 24
Peak memory 215588 kb
Host smart-b861779c-866e-4f3b-b2f3-c7f404b63486
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440608577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1440608577
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4075224892
Short name T94
Test name
Test status
Simulation time 154536250 ps
CPU time 4.83 seconds
Started Jun 10 06:41:32 PM PDT 24
Finished Jun 10 06:41:37 PM PDT 24
Peak memory 215540 kb
Host smart-4f09d914-831c-497f-a07c-545d6a9b0267
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075224892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
075224892
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.4194879789
Short name T174
Test name
Test status
Simulation time 2026158934 ps
CPU time 17.05 seconds
Started Jun 10 06:41:35 PM PDT 24
Finished Jun 10 06:41:52 PM PDT 24
Peak memory 215500 kb
Host smart-4f0d0124-6c57-4cd9-a3a4-6353e922eaab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194879789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.4194879789
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1551288802
Short name T1023
Test name
Test status
Simulation time 50321365 ps
CPU time 2.08 seconds
Started Jun 10 06:42:23 PM PDT 24
Finished Jun 10 06:42:25 PM PDT 24
Peak memory 215580 kb
Host smart-7b7ead7a-eef9-4f40-9b93-f6f8cfa8ba98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551288802 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1551288802
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.628912469
Short name T1055
Test name
Test status
Simulation time 149020557 ps
CPU time 2.6 seconds
Started Jun 10 06:42:23 PM PDT 24
Finished Jun 10 06:42:26 PM PDT 24
Peak memory 207244 kb
Host smart-b6d8f614-75d9-451d-a4a5-8e08df62e627
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628912469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.628912469
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3687137662
Short name T1063
Test name
Test status
Simulation time 88618352 ps
CPU time 0.72 seconds
Started Jun 10 06:42:19 PM PDT 24
Finished Jun 10 06:42:21 PM PDT 24
Peak memory 203884 kb
Host smart-255683db-ceb6-4360-9352-c3ed59f13662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687137662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3687137662
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.931187309
Short name T128
Test name
Test status
Simulation time 60559704 ps
CPU time 4.17 seconds
Started Jun 10 06:42:25 PM PDT 24
Finished Jun 10 06:42:29 PM PDT 24
Peak memory 215544 kb
Host smart-50cb45e5-9aa3-4fc6-830e-725ee75c00ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931187309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.931187309
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1343929844
Short name T170
Test name
Test status
Simulation time 918165567 ps
CPU time 4.04 seconds
Started Jun 10 06:42:19 PM PDT 24
Finished Jun 10 06:42:23 PM PDT 24
Peak memory 215788 kb
Host smart-0b95adc6-9cb7-44d9-a6ee-a1646bca2006
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343929844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1343929844
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2010508374
Short name T1022
Test name
Test status
Simulation time 127379263 ps
CPU time 3.52 seconds
Started Jun 10 06:42:24 PM PDT 24
Finished Jun 10 06:42:28 PM PDT 24
Peak memory 218560 kb
Host smart-3d0d669b-2d13-4f78-b1de-20451d1be536
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010508374 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2010508374
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2650968548
Short name T117
Test name
Test status
Simulation time 504878816 ps
CPU time 2.65 seconds
Started Jun 10 06:42:22 PM PDT 24
Finished Jun 10 06:42:25 PM PDT 24
Peak memory 215552 kb
Host smart-84eb44bf-5995-4750-921f-3113dd39f0e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650968548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2650968548
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1206664897
Short name T1090
Test name
Test status
Simulation time 21434918 ps
CPU time 0.72 seconds
Started Jun 10 06:42:24 PM PDT 24
Finished Jun 10 06:42:25 PM PDT 24
Peak memory 203900 kb
Host smart-324c58f7-24b6-4189-a5b2-56400df28bbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206664897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1206664897
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1493302835
Short name T1069
Test name
Test status
Simulation time 30243877 ps
CPU time 1.74 seconds
Started Jun 10 06:42:24 PM PDT 24
Finished Jun 10 06:42:26 PM PDT 24
Peak memory 216048 kb
Host smart-cb6052ce-9e38-46cb-9ef4-7209bac47505
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493302835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1493302835
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.313862490
Short name T1098
Test name
Test status
Simulation time 888143541 ps
CPU time 2.63 seconds
Started Jun 10 06:42:23 PM PDT 24
Finished Jun 10 06:42:26 PM PDT 24
Peak memory 215600 kb
Host smart-4d2f3d7e-a692-4f75-87e6-b214a79258b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313862490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.313862490
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2242801329
Short name T1067
Test name
Test status
Simulation time 290777911 ps
CPU time 18.53 seconds
Started Jun 10 06:42:25 PM PDT 24
Finished Jun 10 06:42:44 PM PDT 24
Peak memory 215544 kb
Host smart-487cf604-f9bd-49b7-ab62-8f76649505cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242801329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2242801329
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4157332676
Short name T105
Test name
Test status
Simulation time 24983563 ps
CPU time 1.81 seconds
Started Jun 10 06:42:26 PM PDT 24
Finished Jun 10 06:42:28 PM PDT 24
Peak memory 215592 kb
Host smart-879b38d1-e178-4484-abe8-46ed610e7f3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157332676 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4157332676
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4205382128
Short name T1007
Test name
Test status
Simulation time 39828849 ps
CPU time 1.32 seconds
Started Jun 10 06:42:28 PM PDT 24
Finished Jun 10 06:42:29 PM PDT 24
Peak memory 215540 kb
Host smart-db14cf56-5cdc-4d0e-a4fc-3da4c6d9a727
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205382128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4205382128
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3619920163
Short name T1074
Test name
Test status
Simulation time 43039395 ps
CPU time 0.71 seconds
Started Jun 10 06:42:26 PM PDT 24
Finished Jun 10 06:42:27 PM PDT 24
Peak memory 203876 kb
Host smart-05b53990-89f2-4aa0-a773-6e54f208daec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619920163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3619920163
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2738212902
Short name T997
Test name
Test status
Simulation time 160523460 ps
CPU time 2.64 seconds
Started Jun 10 06:42:26 PM PDT 24
Finished Jun 10 06:42:29 PM PDT 24
Peak memory 215540 kb
Host smart-4d0888a0-042f-419b-bd99-fb06a13e32bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738212902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2738212902
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2081890296
Short name T176
Test name
Test status
Simulation time 200300348 ps
CPU time 14.5 seconds
Started Jun 10 06:42:23 PM PDT 24
Finished Jun 10 06:42:38 PM PDT 24
Peak memory 215496 kb
Host smart-c786219d-b952-4dcf-a3a2-77a515e93b3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081890296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2081890296
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.435483415
Short name T103
Test name
Test status
Simulation time 145351349 ps
CPU time 3.38 seconds
Started Jun 10 06:42:26 PM PDT 24
Finished Jun 10 06:42:29 PM PDT 24
Peak memory 217696 kb
Host smart-c22bf289-5c16-48bd-9c96-f3fa6048466f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435483415 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.435483415
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2381361366
Short name T1019
Test name
Test status
Simulation time 150478960 ps
CPU time 2.14 seconds
Started Jun 10 06:42:27 PM PDT 24
Finished Jun 10 06:42:29 PM PDT 24
Peak memory 219716 kb
Host smart-a0c6c740-8fff-42d5-bad8-9fe76b27876d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381361366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2381361366
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1088629676
Short name T1096
Test name
Test status
Simulation time 171286851 ps
CPU time 0.7 seconds
Started Jun 10 06:42:27 PM PDT 24
Finished Jun 10 06:42:28 PM PDT 24
Peak memory 203852 kb
Host smart-be6aff4b-522e-4b61-8599-0645193bb643
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088629676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1088629676
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1822404446
Short name T1047
Test name
Test status
Simulation time 706939223 ps
CPU time 4.2 seconds
Started Jun 10 06:42:25 PM PDT 24
Finished Jun 10 06:42:30 PM PDT 24
Peak memory 215580 kb
Host smart-87356a3e-8829-4f61-a1ac-c22c9ccee44d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822404446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1822404446
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3648921382
Short name T1084
Test name
Test status
Simulation time 71114953 ps
CPU time 2.3 seconds
Started Jun 10 06:42:28 PM PDT 24
Finished Jun 10 06:42:30 PM PDT 24
Peak memory 215708 kb
Host smart-1c368d4a-3ba9-45af-b599-9d2ae2b644d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648921382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3648921382
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4001514083
Short name T1062
Test name
Test status
Simulation time 2725774757 ps
CPU time 15.36 seconds
Started Jun 10 06:42:29 PM PDT 24
Finished Jun 10 06:42:44 PM PDT 24
Peak memory 216020 kb
Host smart-71f58992-7808-4ce7-839f-03570b988f91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001514083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.4001514083
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2223332563
Short name T1034
Test name
Test status
Simulation time 479859984 ps
CPU time 3.68 seconds
Started Jun 10 06:42:30 PM PDT 24
Finished Jun 10 06:42:34 PM PDT 24
Peak memory 217516 kb
Host smart-8080d51a-752a-49be-9dcc-2ec9b4b12256
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223332563 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2223332563
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3388666848
Short name T1076
Test name
Test status
Simulation time 115549336 ps
CPU time 2.77 seconds
Started Jun 10 06:42:34 PM PDT 24
Finished Jun 10 06:42:37 PM PDT 24
Peak memory 207364 kb
Host smart-1834bb0e-811e-43bf-a983-01aa3e3a5e8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388666848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3388666848
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2938446652
Short name T986
Test name
Test status
Simulation time 204466662 ps
CPU time 0.77 seconds
Started Jun 10 06:42:31 PM PDT 24
Finished Jun 10 06:42:32 PM PDT 24
Peak memory 203892 kb
Host smart-1e7d3a0b-e6b0-49da-b7b9-26f196a6c1d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938446652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2938446652
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1591258889
Short name T144
Test name
Test status
Simulation time 582944752 ps
CPU time 3.72 seconds
Started Jun 10 06:42:31 PM PDT 24
Finished Jun 10 06:42:35 PM PDT 24
Peak memory 215512 kb
Host smart-be3c48ba-acab-41f2-84cf-f3aabe993cbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591258889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1591258889
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3038009182
Short name T93
Test name
Test status
Simulation time 62133016 ps
CPU time 4.11 seconds
Started Jun 10 06:42:27 PM PDT 24
Finished Jun 10 06:42:32 PM PDT 24
Peak memory 216716 kb
Host smart-c6676c45-5e9d-4bbc-b471-d21953c99bef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038009182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3038009182
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1916675906
Short name T90
Test name
Test status
Simulation time 3727869754 ps
CPU time 18.8 seconds
Started Jun 10 06:42:31 PM PDT 24
Finished Jun 10 06:42:50 PM PDT 24
Peak memory 215676 kb
Host smart-86d09d22-3ed2-496e-8004-3d0190b488cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916675906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1916675906
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2907977284
Short name T108
Test name
Test status
Simulation time 43116062 ps
CPU time 2.86 seconds
Started Jun 10 06:42:31 PM PDT 24
Finished Jun 10 06:42:34 PM PDT 24
Peak memory 218452 kb
Host smart-c072cf1b-506d-4b79-81ed-e224fee56840
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907977284 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2907977284
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2722929320
Short name T141
Test name
Test status
Simulation time 51448359 ps
CPU time 1.48 seconds
Started Jun 10 06:42:33 PM PDT 24
Finished Jun 10 06:42:35 PM PDT 24
Peak memory 207352 kb
Host smart-56f7a0e8-253e-448d-be7d-4ebee62db37e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722929320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2722929320
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2947979248
Short name T1035
Test name
Test status
Simulation time 37324027 ps
CPU time 0.73 seconds
Started Jun 10 06:42:31 PM PDT 24
Finished Jun 10 06:42:32 PM PDT 24
Peak memory 203888 kb
Host smart-b9a70ca0-7b39-4ed2-89f5-107f8dc81954
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947979248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2947979248
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2656104774
Short name T1086
Test name
Test status
Simulation time 222165900 ps
CPU time 3.29 seconds
Started Jun 10 06:42:31 PM PDT 24
Finished Jun 10 06:42:35 PM PDT 24
Peak memory 215496 kb
Host smart-1e787a73-7a28-456d-b1e8-265887865bd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656104774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2656104774
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.625951588
Short name T99
Test name
Test status
Simulation time 27421620 ps
CPU time 1.49 seconds
Started Jun 10 06:42:31 PM PDT 24
Finished Jun 10 06:42:33 PM PDT 24
Peak memory 215688 kb
Host smart-9e5cc05c-3632-4180-9008-851f1c481a15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625951588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.625951588
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.269580620
Short name T171
Test name
Test status
Simulation time 2465037295 ps
CPU time 14.81 seconds
Started Jun 10 06:42:31 PM PDT 24
Finished Jun 10 06:42:46 PM PDT 24
Peak memory 215648 kb
Host smart-51b97330-f78e-4ec3-8985-32ea5a840e47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269580620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.269580620
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2801502228
Short name T1025
Test name
Test status
Simulation time 72755281 ps
CPU time 1.96 seconds
Started Jun 10 06:42:35 PM PDT 24
Finished Jun 10 06:42:38 PM PDT 24
Peak memory 215584 kb
Host smart-138c9eb7-f75f-45b2-b36d-2b4008f90348
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801502228 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2801502228
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1108750319
Short name T1028
Test name
Test status
Simulation time 144093342 ps
CPU time 1.53 seconds
Started Jun 10 06:42:35 PM PDT 24
Finished Jun 10 06:42:37 PM PDT 24
Peak memory 215568 kb
Host smart-2b47cf25-96f6-48ae-80ef-c1c055a74628
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108750319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1108750319
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.361492353
Short name T1094
Test name
Test status
Simulation time 24153524 ps
CPU time 0.74 seconds
Started Jun 10 06:42:33 PM PDT 24
Finished Jun 10 06:42:34 PM PDT 24
Peak memory 203876 kb
Host smart-647355dc-bf6f-43b5-b160-858ab632b1eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361492353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.361492353
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.392640175
Short name T129
Test name
Test status
Simulation time 59906084 ps
CPU time 1.89 seconds
Started Jun 10 06:42:33 PM PDT 24
Finished Jun 10 06:42:36 PM PDT 24
Peak memory 215492 kb
Host smart-9a5995da-a0c6-4799-b49d-a51cb723ebaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392640175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.392640175
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3877254717
Short name T1088
Test name
Test status
Simulation time 263075646 ps
CPU time 2.48 seconds
Started Jun 10 06:42:37 PM PDT 24
Finished Jun 10 06:42:40 PM PDT 24
Peak memory 215936 kb
Host smart-ceb6edea-075b-4c3a-8cf5-23f60cf6ea70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877254717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3877254717
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1856312410
Short name T173
Test name
Test status
Simulation time 7501425541 ps
CPU time 21.5 seconds
Started Jun 10 06:42:35 PM PDT 24
Finished Jun 10 06:42:57 PM PDT 24
Peak memory 215644 kb
Host smart-8b20ff60-1099-47ce-9627-dfd719bb06f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856312410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1856312410
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3356177844
Short name T1010
Test name
Test status
Simulation time 24122431 ps
CPU time 1.76 seconds
Started Jun 10 06:42:39 PM PDT 24
Finished Jun 10 06:42:41 PM PDT 24
Peak memory 216656 kb
Host smart-b391cfb5-0187-4500-a1fb-4817a20b7522
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356177844 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3356177844
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.374742769
Short name T993
Test name
Test status
Simulation time 54019412 ps
CPU time 2.14 seconds
Started Jun 10 06:42:39 PM PDT 24
Finished Jun 10 06:42:41 PM PDT 24
Peak memory 215536 kb
Host smart-08a784f1-1397-4624-a0f4-fbbb19f0fdea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374742769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.374742769
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1083488058
Short name T1033
Test name
Test status
Simulation time 54385552 ps
CPU time 0.72 seconds
Started Jun 10 06:42:35 PM PDT 24
Finished Jun 10 06:42:36 PM PDT 24
Peak memory 204208 kb
Host smart-c95f0129-3b3b-499a-91af-4813f2d24a0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083488058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1083488058
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1470151770
Short name T991
Test name
Test status
Simulation time 148179148 ps
CPU time 4.13 seconds
Started Jun 10 06:42:39 PM PDT 24
Finished Jun 10 06:42:43 PM PDT 24
Peak memory 215556 kb
Host smart-ec5ef1a4-95fb-407a-ac95-79950f8ba57a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470151770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1470151770
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1465163010
Short name T106
Test name
Test status
Simulation time 554255424 ps
CPU time 7.47 seconds
Started Jun 10 06:42:35 PM PDT 24
Finished Jun 10 06:42:43 PM PDT 24
Peak memory 215652 kb
Host smart-cc84eef5-94f4-4621-8228-4a8a2117abd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465163010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1465163010
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2013598293
Short name T1065
Test name
Test status
Simulation time 26760052 ps
CPU time 2.1 seconds
Started Jun 10 06:42:39 PM PDT 24
Finished Jun 10 06:42:41 PM PDT 24
Peak memory 215568 kb
Host smart-ad6b12a2-8455-408d-8c9e-21102546f512
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013598293 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2013598293
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4000812353
Short name T143
Test name
Test status
Simulation time 122982913 ps
CPU time 1.3 seconds
Started Jun 10 06:42:38 PM PDT 24
Finished Jun 10 06:42:40 PM PDT 24
Peak memory 215560 kb
Host smart-7bf0bc63-fa0d-4071-b928-4ce293cc110e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000812353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
4000812353
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2202338107
Short name T995
Test name
Test status
Simulation time 13568827 ps
CPU time 0.79 seconds
Started Jun 10 06:42:38 PM PDT 24
Finished Jun 10 06:42:39 PM PDT 24
Peak memory 204044 kb
Host smart-7d785ce4-dd8d-4fa9-98ff-736e4a2b8a01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202338107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2202338107
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2469343328
Short name T1051
Test name
Test status
Simulation time 97983424 ps
CPU time 1.66 seconds
Started Jun 10 06:42:38 PM PDT 24
Finished Jun 10 06:42:40 PM PDT 24
Peak memory 207388 kb
Host smart-e1dc4cc1-7c9a-422b-b9b3-d1b2e9fa9e1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469343328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2469343328
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4270530124
Short name T92
Test name
Test status
Simulation time 80953422 ps
CPU time 1.44 seconds
Started Jun 10 06:42:38 PM PDT 24
Finished Jun 10 06:42:40 PM PDT 24
Peak memory 215696 kb
Host smart-3aac7fae-fa8f-4932-852f-db431ed7a1ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270530124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
4270530124
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1290011733
Short name T86
Test name
Test status
Simulation time 580859649 ps
CPU time 19.79 seconds
Started Jun 10 06:42:40 PM PDT 24
Finished Jun 10 06:43:00 PM PDT 24
Peak memory 215572 kb
Host smart-c48ca37e-59d2-4e38-8e61-f982d48314fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290011733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1290011733
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2871168266
Short name T1039
Test name
Test status
Simulation time 308248003 ps
CPU time 2.84 seconds
Started Jun 10 06:42:43 PM PDT 24
Finished Jun 10 06:42:46 PM PDT 24
Peak memory 216692 kb
Host smart-42e165ed-6cab-4f9a-bfb0-1ebf5773a3c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871168266 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2871168266
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2089189366
Short name T1042
Test name
Test status
Simulation time 76937644 ps
CPU time 1.27 seconds
Started Jun 10 06:42:43 PM PDT 24
Finished Jun 10 06:42:44 PM PDT 24
Peak memory 207356 kb
Host smart-ef803149-e1e2-4a5e-8c1d-1ac730092b99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089189366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2089189366
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1769781048
Short name T1059
Test name
Test status
Simulation time 49794690 ps
CPU time 0.8 seconds
Started Jun 10 06:42:44 PM PDT 24
Finished Jun 10 06:42:45 PM PDT 24
Peak memory 203900 kb
Host smart-d4ef67a2-c4c8-44b0-a93d-801598412707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769781048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1769781048
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3686743133
Short name T1100
Test name
Test status
Simulation time 383572343 ps
CPU time 3.65 seconds
Started Jun 10 06:42:44 PM PDT 24
Finished Jun 10 06:42:48 PM PDT 24
Peak memory 215516 kb
Host smart-6dc33091-4f73-42e3-9246-996e7beb3c68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686743133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3686743133
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2342879592
Short name T97
Test name
Test status
Simulation time 137858560 ps
CPU time 3.39 seconds
Started Jun 10 06:42:42 PM PDT 24
Finished Jun 10 06:42:46 PM PDT 24
Peak memory 215716 kb
Host smart-48b0ed4a-805d-4977-8cd2-1867dd6ae82a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342879592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2342879592
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.306317373
Short name T1048
Test name
Test status
Simulation time 1170372534 ps
CPU time 7.96 seconds
Started Jun 10 06:42:45 PM PDT 24
Finished Jun 10 06:42:53 PM PDT 24
Peak memory 215564 kb
Host smart-42a219f5-740b-461a-a698-21e0c8602425
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306317373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.306317373
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3723114729
Short name T1082
Test name
Test status
Simulation time 318430425 ps
CPU time 21.86 seconds
Started Jun 10 06:41:49 PM PDT 24
Finished Jun 10 06:42:11 PM PDT 24
Peak memory 207320 kb
Host smart-0849db32-5da8-41e6-85cf-b0859aa646b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723114729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3723114729
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2333307417
Short name T145
Test name
Test status
Simulation time 1644908863 ps
CPU time 12.86 seconds
Started Jun 10 06:41:48 PM PDT 24
Finished Jun 10 06:42:01 PM PDT 24
Peak memory 207344 kb
Host smart-e9844da3-11b3-456b-86cf-bf872b4230fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333307417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2333307417
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3458412319
Short name T1061
Test name
Test status
Simulation time 28322333 ps
CPU time 0.95 seconds
Started Jun 10 06:41:44 PM PDT 24
Finished Jun 10 06:41:46 PM PDT 24
Peak memory 207180 kb
Host smart-d1fcc792-b911-4c65-9969-61618a444d63
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458412319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3458412319
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3039793808
Short name T1015
Test name
Test status
Simulation time 41802789 ps
CPU time 2.93 seconds
Started Jun 10 06:42:00 PM PDT 24
Finished Jun 10 06:42:03 PM PDT 24
Peak memory 216576 kb
Host smart-20d19772-7ebc-41fc-83c2-b185f32dbbcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039793808 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3039793808
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4201719865
Short name T1020
Test name
Test status
Simulation time 21987534 ps
CPU time 1.24 seconds
Started Jun 10 06:41:48 PM PDT 24
Finished Jun 10 06:41:49 PM PDT 24
Peak memory 207276 kb
Host smart-51c82867-07cb-4502-a926-2cee32a7d2c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201719865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
201719865
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2495917526
Short name T1049
Test name
Test status
Simulation time 19741972 ps
CPU time 0.75 seconds
Started Jun 10 06:41:43 PM PDT 24
Finished Jun 10 06:41:44 PM PDT 24
Peak memory 203892 kb
Host smart-6799a145-db0d-4e5d-8afa-b46c0f35bcdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495917526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
495917526
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2815102752
Short name T120
Test name
Test status
Simulation time 68106290 ps
CPU time 2.1 seconds
Started Jun 10 06:41:42 PM PDT 24
Finished Jun 10 06:41:45 PM PDT 24
Peak memory 215476 kb
Host smart-10711110-bc3c-402c-8b5d-0139f27cb261
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815102752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2815102752
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.161227961
Short name T1046
Test name
Test status
Simulation time 17474489 ps
CPU time 0.68 seconds
Started Jun 10 06:41:43 PM PDT 24
Finished Jun 10 06:41:44 PM PDT 24
Peak memory 203768 kb
Host smart-bfb36525-bec0-49fa-a136-3a544a473558
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161227961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.161227961
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.437820772
Short name T1058
Test name
Test status
Simulation time 108130325 ps
CPU time 3.01 seconds
Started Jun 10 06:41:51 PM PDT 24
Finished Jun 10 06:41:54 PM PDT 24
Peak memory 215556 kb
Host smart-95e39711-09ce-4d96-9b01-4a632f9511b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437820772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.437820772
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1233689849
Short name T1066
Test name
Test status
Simulation time 164935968 ps
CPU time 2.51 seconds
Started Jun 10 06:41:40 PM PDT 24
Finished Jun 10 06:41:42 PM PDT 24
Peak memory 215692 kb
Host smart-df3b618d-c1be-41b0-8751-e0bcd24b9695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233689849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
233689849
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.438422788
Short name T1081
Test name
Test status
Simulation time 2714341601 ps
CPU time 16.78 seconds
Started Jun 10 06:41:40 PM PDT 24
Finished Jun 10 06:41:57 PM PDT 24
Peak memory 215848 kb
Host smart-ce628664-f9e1-429b-91e0-f57f2ce8c33e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438422788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.438422788
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.355532336
Short name T983
Test name
Test status
Simulation time 20043059 ps
CPU time 0.76 seconds
Started Jun 10 06:42:47 PM PDT 24
Finished Jun 10 06:42:48 PM PDT 24
Peak memory 203892 kb
Host smart-b4369932-a350-4a49-9463-100c5f5d3ef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355532336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.355532336
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3877792066
Short name T1068
Test name
Test status
Simulation time 169736820 ps
CPU time 0.74 seconds
Started Jun 10 06:42:48 PM PDT 24
Finished Jun 10 06:42:49 PM PDT 24
Peak memory 204212 kb
Host smart-591c2838-4e03-4733-a0dc-8a5eec048b92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877792066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3877792066
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3040909573
Short name T1097
Test name
Test status
Simulation time 11665425 ps
CPU time 0.73 seconds
Started Jun 10 06:42:49 PM PDT 24
Finished Jun 10 06:42:50 PM PDT 24
Peak memory 203892 kb
Host smart-70e67123-3338-4c05-8a3e-71b9199f8b9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040909573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3040909573
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3402160218
Short name T984
Test name
Test status
Simulation time 16632094 ps
CPU time 0.7 seconds
Started Jun 10 06:42:46 PM PDT 24
Finished Jun 10 06:42:47 PM PDT 24
Peak memory 203896 kb
Host smart-554b60c8-0a52-4c4e-9da3-1c6d51282187
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402160218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3402160218
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2545176083
Short name T1011
Test name
Test status
Simulation time 12937245 ps
CPU time 0.73 seconds
Started Jun 10 06:42:46 PM PDT 24
Finished Jun 10 06:42:47 PM PDT 24
Peak memory 203944 kb
Host smart-ec11eb2c-30ea-4fa1-8425-4032e661cfcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545176083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2545176083
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1006901659
Short name T1038
Test name
Test status
Simulation time 41940781 ps
CPU time 0.74 seconds
Started Jun 10 06:42:46 PM PDT 24
Finished Jun 10 06:42:48 PM PDT 24
Peak memory 204196 kb
Host smart-ba4df4a3-c556-47e9-a95d-52297262330d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006901659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1006901659
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1017329298
Short name T1009
Test name
Test status
Simulation time 47893923 ps
CPU time 0.72 seconds
Started Jun 10 06:42:47 PM PDT 24
Finished Jun 10 06:42:48 PM PDT 24
Peak memory 204112 kb
Host smart-ccd639a5-042c-49fa-b619-d4235398a9a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017329298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1017329298
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2209638407
Short name T1008
Test name
Test status
Simulation time 46677224 ps
CPU time 0.73 seconds
Started Jun 10 06:42:47 PM PDT 24
Finished Jun 10 06:42:48 PM PDT 24
Peak memory 203876 kb
Host smart-cdaf0790-656d-4dcd-a4b6-fd7094e72214
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209638407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2209638407
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.954194283
Short name T988
Test name
Test status
Simulation time 18519021 ps
CPU time 0.77 seconds
Started Jun 10 06:42:47 PM PDT 24
Finished Jun 10 06:42:48 PM PDT 24
Peak memory 203960 kb
Host smart-8ef68c14-fb6b-41a6-bcae-ba067a9fafb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954194283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.954194283
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.337061981
Short name T1021
Test name
Test status
Simulation time 42377982 ps
CPU time 0.78 seconds
Started Jun 10 06:42:46 PM PDT 24
Finished Jun 10 06:42:47 PM PDT 24
Peak memory 203964 kb
Host smart-d6c821f5-95a7-4f73-a18d-b5ff79968b7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337061981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.337061981
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2931229269
Short name T121
Test name
Test status
Simulation time 117464451 ps
CPU time 8.24 seconds
Started Jun 10 06:41:56 PM PDT 24
Finished Jun 10 06:42:04 PM PDT 24
Peak memory 215496 kb
Host smart-a6a9c5a3-ccb8-419d-a456-b2ea5621f786
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931229269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2931229269
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3206559624
Short name T115
Test name
Test status
Simulation time 589502942 ps
CPU time 32.71 seconds
Started Jun 10 06:41:57 PM PDT 24
Finished Jun 10 06:42:30 PM PDT 24
Peak memory 215464 kb
Host smart-8a9c447e-5111-42d1-9b7f-eeaa7cd5c469
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206559624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3206559624
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.834356889
Short name T75
Test name
Test status
Simulation time 44834755 ps
CPU time 1.45 seconds
Started Jun 10 06:41:57 PM PDT 24
Finished Jun 10 06:41:59 PM PDT 24
Peak memory 207364 kb
Host smart-df655e3a-a3a7-48ca-8d26-3a91cb01b226
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834356889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.834356889
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.140698769
Short name T1045
Test name
Test status
Simulation time 39008603 ps
CPU time 2.85 seconds
Started Jun 10 06:41:57 PM PDT 24
Finished Jun 10 06:42:00 PM PDT 24
Peak memory 217004 kb
Host smart-409c58c9-748e-4b96-92ae-aad6e36d6f08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140698769 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.140698769
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1515373758
Short name T1057
Test name
Test status
Simulation time 288140444 ps
CPU time 2.16 seconds
Started Jun 10 06:41:55 PM PDT 24
Finished Jun 10 06:41:58 PM PDT 24
Peak memory 207372 kb
Host smart-cd2ffec1-1f56-4866-8e16-4a8fa98953c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515373758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
515373758
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4281172741
Short name T1029
Test name
Test status
Simulation time 20770683 ps
CPU time 0.72 seconds
Started Jun 10 06:41:51 PM PDT 24
Finished Jun 10 06:41:52 PM PDT 24
Peak memory 203868 kb
Host smart-ac55a11d-298e-40c3-9883-d685bc4be6ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281172741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.4
281172741
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2397028053
Short name T118
Test name
Test status
Simulation time 61403416 ps
CPU time 2.72 seconds
Started Jun 10 06:41:57 PM PDT 24
Finished Jun 10 06:42:00 PM PDT 24
Peak memory 215608 kb
Host smart-d3d72f3f-3ce8-4913-a418-ac9abbb1cf3e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397028053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2397028053
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.183577435
Short name T1000
Test name
Test status
Simulation time 18674653 ps
CPU time 0.64 seconds
Started Jun 10 06:41:51 PM PDT 24
Finished Jun 10 06:41:52 PM PDT 24
Peak memory 203872 kb
Host smart-0863dc0b-6110-4491-b346-27620a7929ff
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183577435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.183577435
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1172906916
Short name T1078
Test name
Test status
Simulation time 86364561 ps
CPU time 2.01 seconds
Started Jun 10 06:41:55 PM PDT 24
Finished Jun 10 06:41:57 PM PDT 24
Peak memory 215592 kb
Host smart-0b242029-ede7-468f-92fb-351f04cc3eda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172906916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1172906916
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3285025838
Short name T1071
Test name
Test status
Simulation time 58277976 ps
CPU time 1.83 seconds
Started Jun 10 06:41:53 PM PDT 24
Finished Jun 10 06:41:55 PM PDT 24
Peak memory 215716 kb
Host smart-3b867a31-00d6-4ef7-b9f4-a710c9051d0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285025838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
285025838
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2904670819
Short name T1050
Test name
Test status
Simulation time 115760064 ps
CPU time 6.47 seconds
Started Jun 10 06:41:51 PM PDT 24
Finished Jun 10 06:41:58 PM PDT 24
Peak memory 222732 kb
Host smart-8cfe30f4-1cf3-4d30-afbe-c93629545ad0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904670819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2904670819
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1122148800
Short name T1024
Test name
Test status
Simulation time 17811675 ps
CPU time 0.76 seconds
Started Jun 10 06:42:46 PM PDT 24
Finished Jun 10 06:42:47 PM PDT 24
Peak memory 203940 kb
Host smart-396d2b6b-35d6-4228-925c-aeea54ad129c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122148800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1122148800
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1097168379
Short name T985
Test name
Test status
Simulation time 23799598 ps
CPU time 0.73 seconds
Started Jun 10 06:42:44 PM PDT 24
Finished Jun 10 06:42:45 PM PDT 24
Peak memory 203776 kb
Host smart-ac33b6c4-d022-418e-8bd7-375aa85623f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097168379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1097168379
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2941631810
Short name T1085
Test name
Test status
Simulation time 45285553 ps
CPU time 0.77 seconds
Started Jun 10 06:42:49 PM PDT 24
Finished Jun 10 06:42:50 PM PDT 24
Peak memory 204188 kb
Host smart-c69eb9b3-a8cd-4014-8fe6-b48bffad7f43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941631810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2941631810
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3668803771
Short name T1099
Test name
Test status
Simulation time 43666234 ps
CPU time 0.74 seconds
Started Jun 10 06:42:49 PM PDT 24
Finished Jun 10 06:42:50 PM PDT 24
Peak memory 204216 kb
Host smart-95037599-f682-46f7-a51d-2deb22a37882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668803771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3668803771
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1316664337
Short name T1052
Test name
Test status
Simulation time 35355971 ps
CPU time 0.68 seconds
Started Jun 10 06:42:51 PM PDT 24
Finished Jun 10 06:42:52 PM PDT 24
Peak memory 203888 kb
Host smart-09124263-020a-4adf-ab88-3a1aac56a9e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316664337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1316664337
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.252054035
Short name T1037
Test name
Test status
Simulation time 19262225 ps
CPU time 0.77 seconds
Started Jun 10 06:42:50 PM PDT 24
Finished Jun 10 06:42:51 PM PDT 24
Peak memory 203880 kb
Host smart-006c378b-bf4c-49ef-985e-9efe4c82cbbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252054035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.252054035
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3145830712
Short name T1043
Test name
Test status
Simulation time 118609516 ps
CPU time 0.72 seconds
Started Jun 10 06:42:50 PM PDT 24
Finished Jun 10 06:42:51 PM PDT 24
Peak memory 203748 kb
Host smart-86a959d2-aba2-473e-89ac-5dd80b9afb2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145830712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3145830712
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2973056643
Short name T998
Test name
Test status
Simulation time 23421576 ps
CPU time 0.76 seconds
Started Jun 10 06:42:49 PM PDT 24
Finished Jun 10 06:42:50 PM PDT 24
Peak memory 203932 kb
Host smart-cc3f5c6e-6569-453a-a3e2-22b1b91f87d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973056643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2973056643
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1055047355
Short name T1002
Test name
Test status
Simulation time 48087409 ps
CPU time 0.72 seconds
Started Jun 10 06:42:49 PM PDT 24
Finished Jun 10 06:42:51 PM PDT 24
Peak memory 203820 kb
Host smart-f2f22a61-e9b9-4f61-8bed-420b87a50662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055047355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1055047355
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.4001316416
Short name T1032
Test name
Test status
Simulation time 17907214 ps
CPU time 0.9 seconds
Started Jun 10 06:42:50 PM PDT 24
Finished Jun 10 06:42:51 PM PDT 24
Peak memory 203956 kb
Host smart-545ab3ca-ec87-4c3b-b3bd-68c8ffe10786
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001316416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
4001316416
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3921656589
Short name T119
Test name
Test status
Simulation time 2548041082 ps
CPU time 16.01 seconds
Started Jun 10 06:42:08 PM PDT 24
Finished Jun 10 06:42:25 PM PDT 24
Peak memory 215488 kb
Host smart-7733b9ac-92ad-457c-a41f-c9587a4b2af7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921656589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3921656589
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2410576702
Short name T1030
Test name
Test status
Simulation time 421820549 ps
CPU time 23.33 seconds
Started Jun 10 06:42:03 PM PDT 24
Finished Jun 10 06:42:26 PM PDT 24
Peak memory 207460 kb
Host smart-1f9bd8e0-0d48-4700-bd11-7587e566a991
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410576702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2410576702
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1309023600
Short name T76
Test name
Test status
Simulation time 79413015 ps
CPU time 1.28 seconds
Started Jun 10 06:42:03 PM PDT 24
Finished Jun 10 06:42:05 PM PDT 24
Peak memory 207356 kb
Host smart-a70eec4a-d631-4da4-ac3d-e00798d4bd95
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309023600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1309023600
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2023631744
Short name T87
Test name
Test status
Simulation time 84674804 ps
CPU time 3.02 seconds
Started Jun 10 06:42:08 PM PDT 24
Finished Jun 10 06:42:11 PM PDT 24
Peak memory 217008 kb
Host smart-b6ecc599-285c-4e0f-80bb-6fcd22fd30a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023631744 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2023631744
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1560321560
Short name T111
Test name
Test status
Simulation time 134333224 ps
CPU time 2.02 seconds
Started Jun 10 06:42:02 PM PDT 24
Finished Jun 10 06:42:05 PM PDT 24
Peak memory 215496 kb
Host smart-184e5f09-88db-4ed8-8fad-34161b7d673e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560321560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
560321560
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2952085614
Short name T1006
Test name
Test status
Simulation time 18037865 ps
CPU time 0.78 seconds
Started Jun 10 06:41:59 PM PDT 24
Finished Jun 10 06:42:00 PM PDT 24
Peak memory 204224 kb
Host smart-94630b85-8409-461a-b341-dfc708c4a09e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952085614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
952085614
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1623692772
Short name T110
Test name
Test status
Simulation time 277191748 ps
CPU time 2.15 seconds
Started Jun 10 06:42:02 PM PDT 24
Finished Jun 10 06:42:05 PM PDT 24
Peak memory 215508 kb
Host smart-ae9d2162-c66a-4f94-8ae8-87df2a96164a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623692772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1623692772
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1614098343
Short name T1070
Test name
Test status
Simulation time 33160675 ps
CPU time 0.64 seconds
Started Jun 10 06:42:02 PM PDT 24
Finished Jun 10 06:42:03 PM PDT 24
Peak memory 204132 kb
Host smart-1d0cd623-fe3a-4ef1-a223-7137c8f497e0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614098343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1614098343
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1966008894
Short name T1095
Test name
Test status
Simulation time 311588965 ps
CPU time 3.86 seconds
Started Jun 10 06:42:08 PM PDT 24
Finished Jun 10 06:42:12 PM PDT 24
Peak memory 215584 kb
Host smart-5f9bbe25-06bc-4475-bd43-5d1ab39c5003
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966008894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1966008894
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1056416374
Short name T104
Test name
Test status
Simulation time 142012133 ps
CPU time 4 seconds
Started Jun 10 06:42:00 PM PDT 24
Finished Jun 10 06:42:04 PM PDT 24
Peak memory 215716 kb
Host smart-481644b2-fd3c-41e6-9259-e918e7121326
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056416374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
056416374
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1285147448
Short name T89
Test name
Test status
Simulation time 429072930 ps
CPU time 17.01 seconds
Started Jun 10 06:42:00 PM PDT 24
Finished Jun 10 06:42:17 PM PDT 24
Peak memory 216304 kb
Host smart-be179940-0de6-4840-870b-0b1dbc754384
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285147448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1285147448
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3613790079
Short name T1016
Test name
Test status
Simulation time 28238642 ps
CPU time 0.71 seconds
Started Jun 10 06:42:48 PM PDT 24
Finished Jun 10 06:42:49 PM PDT 24
Peak memory 204232 kb
Host smart-e428aa07-1693-4f82-9117-6b3466a80d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613790079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3613790079
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3693309580
Short name T994
Test name
Test status
Simulation time 14312336 ps
CPU time 0.7 seconds
Started Jun 10 06:42:54 PM PDT 24
Finished Jun 10 06:42:55 PM PDT 24
Peak memory 203860 kb
Host smart-e2f1763a-ac81-48c5-9730-54e213222d7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693309580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3693309580
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.486399729
Short name T1017
Test name
Test status
Simulation time 38795131 ps
CPU time 0.69 seconds
Started Jun 10 06:42:55 PM PDT 24
Finished Jun 10 06:42:56 PM PDT 24
Peak memory 203864 kb
Host smart-abaca787-fa21-49fd-90d9-a6a32292588c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486399729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.486399729
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1620478652
Short name T1073
Test name
Test status
Simulation time 24640644 ps
CPU time 0.68 seconds
Started Jun 10 06:42:54 PM PDT 24
Finished Jun 10 06:42:55 PM PDT 24
Peak memory 203728 kb
Host smart-51d85f48-3900-48ba-b22f-6616295acf69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620478652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1620478652
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3836315688
Short name T1087
Test name
Test status
Simulation time 33681017 ps
CPU time 0.8 seconds
Started Jun 10 06:42:56 PM PDT 24
Finished Jun 10 06:42:57 PM PDT 24
Peak memory 203904 kb
Host smart-ee9f13e7-94e0-4cad-a0f4-d762881233e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836315688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3836315688
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.960154388
Short name T1077
Test name
Test status
Simulation time 76862242 ps
CPU time 0.66 seconds
Started Jun 10 06:42:53 PM PDT 24
Finished Jun 10 06:42:53 PM PDT 24
Peak memory 203884 kb
Host smart-8e0cb16a-5a6e-460c-b242-482df84c3ca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960154388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.960154388
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.103046962
Short name T1089
Test name
Test status
Simulation time 34432789 ps
CPU time 0.69 seconds
Started Jun 10 06:42:54 PM PDT 24
Finished Jun 10 06:42:55 PM PDT 24
Peak memory 204128 kb
Host smart-75dced97-7921-4dcd-aa51-2d77ef68d58c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103046962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.103046962
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3880435544
Short name T1027
Test name
Test status
Simulation time 34756438 ps
CPU time 0.75 seconds
Started Jun 10 06:42:56 PM PDT 24
Finished Jun 10 06:42:57 PM PDT 24
Peak memory 203836 kb
Host smart-7aef4208-13e9-4b6e-a5ca-f0e4e7658ebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880435544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3880435544
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3204885556
Short name T1064
Test name
Test status
Simulation time 134573628 ps
CPU time 0.7 seconds
Started Jun 10 06:42:54 PM PDT 24
Finished Jun 10 06:42:55 PM PDT 24
Peak memory 203880 kb
Host smart-84a65b55-d71e-44a8-a351-e98d96db8a17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204885556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3204885556
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3333698349
Short name T1005
Test name
Test status
Simulation time 23169667 ps
CPU time 0.75 seconds
Started Jun 10 06:42:54 PM PDT 24
Finished Jun 10 06:42:55 PM PDT 24
Peak memory 203840 kb
Host smart-7df9097e-f7b1-4667-9462-616fc5f3affd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333698349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3333698349
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3107974626
Short name T1053
Test name
Test status
Simulation time 292284654 ps
CPU time 2.41 seconds
Started Jun 10 06:42:09 PM PDT 24
Finished Jun 10 06:42:11 PM PDT 24
Peak memory 215516 kb
Host smart-0bc5348f-1e6d-4e7d-a43a-f72e04fed0cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107974626 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3107974626
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1577516816
Short name T1079
Test name
Test status
Simulation time 92252087 ps
CPU time 1.43 seconds
Started Jun 10 06:42:09 PM PDT 24
Finished Jun 10 06:42:10 PM PDT 24
Peak memory 207252 kb
Host smart-2f7c060c-5b2b-4914-a454-23882fd0f8ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577516816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
577516816
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2054257518
Short name T1054
Test name
Test status
Simulation time 12418912 ps
CPU time 0.73 seconds
Started Jun 10 06:42:06 PM PDT 24
Finished Jun 10 06:42:07 PM PDT 24
Peak memory 203784 kb
Host smart-c91cf9ec-3e0f-486c-b828-3863a98cd4aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054257518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
054257518
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3297954494
Short name T1092
Test name
Test status
Simulation time 62049718 ps
CPU time 4.23 seconds
Started Jun 10 06:42:07 PM PDT 24
Finished Jun 10 06:42:12 PM PDT 24
Peak memory 215440 kb
Host smart-c8fa8b7b-9c08-42a6-8856-32a5c8e1606b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297954494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3297954494
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3504068205
Short name T102
Test name
Test status
Simulation time 35924416 ps
CPU time 2.33 seconds
Started Jun 10 06:42:12 PM PDT 24
Finished Jun 10 06:42:14 PM PDT 24
Peak memory 215712 kb
Host smart-93a460af-07c8-4027-934b-2792747ffc21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504068205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
504068205
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4178853186
Short name T1080
Test name
Test status
Simulation time 572695756 ps
CPU time 2.92 seconds
Started Jun 10 06:42:12 PM PDT 24
Finished Jun 10 06:42:16 PM PDT 24
Peak memory 216976 kb
Host smart-4b5d93b3-97d0-4d6c-9073-e5446ce97137
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178853186 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.4178853186
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1489078988
Short name T127
Test name
Test status
Simulation time 305734800 ps
CPU time 2.02 seconds
Started Jun 10 06:42:11 PM PDT 24
Finished Jun 10 06:42:14 PM PDT 24
Peak memory 215508 kb
Host smart-c590b670-f5c7-45f5-bc18-bb177997a372
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489078988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
489078988
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.738769623
Short name T1013
Test name
Test status
Simulation time 12193021 ps
CPU time 0.8 seconds
Started Jun 10 06:42:10 PM PDT 24
Finished Jun 10 06:42:11 PM PDT 24
Peak memory 203856 kb
Host smart-04c9fe62-8f2c-47fa-9908-f653459910dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738769623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.738769623
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3531911363
Short name T142
Test name
Test status
Simulation time 278779138 ps
CPU time 1.82 seconds
Started Jun 10 06:42:23 PM PDT 24
Finished Jun 10 06:42:25 PM PDT 24
Peak memory 215552 kb
Host smart-751f2d35-1f08-4acb-9946-47a42a0e8b87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531911363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3531911363
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2001943729
Short name T1040
Test name
Test status
Simulation time 463902419 ps
CPU time 8.95 seconds
Started Jun 10 06:42:11 PM PDT 24
Finished Jun 10 06:42:20 PM PDT 24
Peak memory 216744 kb
Host smart-05ef3ea7-beb7-489b-971d-30502faf6f33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001943729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2001943729
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.473614874
Short name T1004
Test name
Test status
Simulation time 43006226 ps
CPU time 3.54 seconds
Started Jun 10 06:42:15 PM PDT 24
Finished Jun 10 06:42:19 PM PDT 24
Peak memory 216924 kb
Host smart-6fa3510d-1f95-43ad-9aa0-6b631b586cc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473614874 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.473614874
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.855874793
Short name T140
Test name
Test status
Simulation time 39810263 ps
CPU time 1.28 seconds
Started Jun 10 06:42:21 PM PDT 24
Finished Jun 10 06:42:23 PM PDT 24
Peak memory 207364 kb
Host smart-d32278b5-6bd8-4979-bdc5-af3123b04ee9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855874793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.855874793
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2734085762
Short name T1072
Test name
Test status
Simulation time 30031855 ps
CPU time 0.73 seconds
Started Jun 10 06:42:12 PM PDT 24
Finished Jun 10 06:42:13 PM PDT 24
Peak memory 204200 kb
Host smart-71a0a6dd-f520-4b7b-bb89-0591a14a6ad7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734085762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
734085762
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3129476217
Short name T1026
Test name
Test status
Simulation time 590096793 ps
CPU time 2.86 seconds
Started Jun 10 06:42:21 PM PDT 24
Finished Jun 10 06:42:24 PM PDT 24
Peak memory 215492 kb
Host smart-efe3a834-b9e7-450c-b073-7d985e1b8ccf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129476217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3129476217
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3639778644
Short name T101
Test name
Test status
Simulation time 434296637 ps
CPU time 3.48 seconds
Started Jun 10 06:42:12 PM PDT 24
Finished Jun 10 06:42:16 PM PDT 24
Peak memory 215684 kb
Host smart-f76ed38d-9c01-4768-98c1-af8dba39858f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639778644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
639778644
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3538982978
Short name T116
Test name
Test status
Simulation time 97233729 ps
CPU time 2.53 seconds
Started Jun 10 06:42:15 PM PDT 24
Finished Jun 10 06:42:18 PM PDT 24
Peak memory 218380 kb
Host smart-8810e500-bb01-4eab-9ced-b352f556fbe6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538982978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
538982978
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1517206291
Short name T990
Test name
Test status
Simulation time 49429655 ps
CPU time 0.77 seconds
Started Jun 10 06:42:15 PM PDT 24
Finished Jun 10 06:42:17 PM PDT 24
Peak memory 204124 kb
Host smart-1dcdd362-3e73-417f-ac2f-535c65f2965d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517206291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
517206291
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3333863661
Short name T1003
Test name
Test status
Simulation time 46249563 ps
CPU time 2.9 seconds
Started Jun 10 06:42:15 PM PDT 24
Finished Jun 10 06:42:18 PM PDT 24
Peak memory 215556 kb
Host smart-ff251271-c6ce-42a7-98ec-a52079266e31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333863661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3333863661
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.730021057
Short name T100
Test name
Test status
Simulation time 115597388 ps
CPU time 2.09 seconds
Started Jun 10 06:42:14 PM PDT 24
Finished Jun 10 06:42:17 PM PDT 24
Peak memory 215832 kb
Host smart-a4705a00-9847-47df-b728-652eaa14aed5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730021057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.730021057
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.704370751
Short name T1075
Test name
Test status
Simulation time 281451635 ps
CPU time 19.54 seconds
Started Jun 10 06:42:15 PM PDT 24
Finished Jun 10 06:42:35 PM PDT 24
Peak memory 216516 kb
Host smart-e68c0769-ca3e-4eff-bc76-4c19ecf2a7eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704370751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.704370751
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2117686029
Short name T1031
Test name
Test status
Simulation time 51676480 ps
CPU time 1.76 seconds
Started Jun 10 06:42:24 PM PDT 24
Finished Jun 10 06:42:26 PM PDT 24
Peak memory 215728 kb
Host smart-9d63ff64-1506-41a1-adc9-cc82d6b66803
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117686029 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2117686029
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.803757591
Short name T1014
Test name
Test status
Simulation time 217500511 ps
CPU time 2.26 seconds
Started Jun 10 06:42:18 PM PDT 24
Finished Jun 10 06:42:20 PM PDT 24
Peak memory 215520 kb
Host smart-a0ab69bf-9e70-429a-a7ac-b80708c30263
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803757591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.803757591
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1148260773
Short name T1091
Test name
Test status
Simulation time 17197017 ps
CPU time 0.74 seconds
Started Jun 10 06:42:24 PM PDT 24
Finished Jun 10 06:42:25 PM PDT 24
Peak memory 204216 kb
Host smart-27028934-4efc-472f-bad2-036f371ec37e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148260773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
148260773
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2631062773
Short name T1001
Test name
Test status
Simulation time 236413752 ps
CPU time 4.1 seconds
Started Jun 10 06:42:19 PM PDT 24
Finished Jun 10 06:42:23 PM PDT 24
Peak memory 215512 kb
Host smart-36930891-ac1d-4386-87a7-5ded2d9a79d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631062773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2631062773
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.577914462
Short name T1041
Test name
Test status
Simulation time 231539182 ps
CPU time 1.74 seconds
Started Jun 10 06:42:19 PM PDT 24
Finished Jun 10 06:42:21 PM PDT 24
Peak memory 215692 kb
Host smart-84c0f380-15da-4459-a68e-91ededf09201
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577914462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.577914462
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.4203588982
Short name T172
Test name
Test status
Simulation time 3422975643 ps
CPU time 24.6 seconds
Started Jun 10 06:42:20 PM PDT 24
Finished Jun 10 06:42:45 PM PDT 24
Peak memory 215612 kb
Host smart-d4a9bb5a-792a-4934-afa0-d3224b5fbced
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203588982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.4203588982
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.4000491911
Short name T524
Test name
Test status
Simulation time 11676075 ps
CPU time 0.7 seconds
Started Jun 10 07:47:13 PM PDT 24
Finished Jun 10 07:47:18 PM PDT 24
Peak memory 204732 kb
Host smart-a8266d1a-cb50-4ccb-bd8a-ffc34e407f33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000491911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.4
000491911
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3983462235
Short name T673
Test name
Test status
Simulation time 1358070178 ps
CPU time 8.69 seconds
Started Jun 10 07:47:16 PM PDT 24
Finished Jun 10 07:47:28 PM PDT 24
Peak memory 232608 kb
Host smart-74c390ee-486e-4c6b-8097-4c78e1b50625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983462235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3983462235
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1799540586
Short name T608
Test name
Test status
Simulation time 33144905 ps
CPU time 0.79 seconds
Started Jun 10 07:47:12 PM PDT 24
Finished Jun 10 07:47:17 PM PDT 24
Peak memory 206388 kb
Host smart-396f34c6-b039-485c-bc91-8365292831af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799540586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1799540586
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2727464967
Short name T190
Test name
Test status
Simulation time 34409258429 ps
CPU time 41.3 seconds
Started Jun 10 07:47:11 PM PDT 24
Finished Jun 10 07:47:57 PM PDT 24
Peak memory 240724 kb
Host smart-38dcfc34-5a2a-4bdc-acdf-06b5f3df2e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727464967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2727464967
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1669887512
Short name T54
Test name
Test status
Simulation time 18057885414 ps
CPU time 172.58 seconds
Started Jun 10 07:47:12 PM PDT 24
Finished Jun 10 07:50:09 PM PDT 24
Peak memory 240924 kb
Host smart-44e1c929-6308-489a-9852-036af3c08ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669887512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1669887512
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.4234713329
Short name T782
Test name
Test status
Simulation time 8135331222 ps
CPU time 67.64 seconds
Started Jun 10 07:47:28 PM PDT 24
Finished Jun 10 07:48:39 PM PDT 24
Peak memory 224520 kb
Host smart-e6d6b6b5-e117-4510-8cc0-ef5854979459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234713329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.4234713329
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3977264588
Short name T767
Test name
Test status
Simulation time 3433535191 ps
CPU time 41.87 seconds
Started Jun 10 07:47:17 PM PDT 24
Finished Jun 10 07:48:02 PM PDT 24
Peak memory 248368 kb
Host smart-abb3f8cd-3466-4ab9-8ac5-a9d46837e6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977264588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3977264588
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2769651355
Short name T637
Test name
Test status
Simulation time 371195894 ps
CPU time 4.08 seconds
Started Jun 10 07:47:12 PM PDT 24
Finished Jun 10 07:47:20 PM PDT 24
Peak memory 232540 kb
Host smart-616973f9-a7d2-4b5c-bd7c-283d54c38707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769651355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2769651355
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2021169131
Short name T156
Test name
Test status
Simulation time 5226216356 ps
CPU time 24.57 seconds
Started Jun 10 07:47:13 PM PDT 24
Finished Jun 10 07:47:41 PM PDT 24
Peak memory 224368 kb
Host smart-30b4454e-cd3b-4d0e-8c75-471c92a566b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021169131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2021169131
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2044071525
Short name T658
Test name
Test status
Simulation time 188327147 ps
CPU time 1.02 seconds
Started Jun 10 07:47:14 PM PDT 24
Finished Jun 10 07:47:19 PM PDT 24
Peak memory 217780 kb
Host smart-00fe91c8-36f8-464d-ac4c-5a2199aa0eb0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044071525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2044071525
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.790593894
Short name T291
Test name
Test status
Simulation time 14038941351 ps
CPU time 9.91 seconds
Started Jun 10 07:47:14 PM PDT 24
Finished Jun 10 07:47:28 PM PDT 24
Peak memory 232612 kb
Host smart-589ea18f-4403-43b1-b582-dcbf42459089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790593894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
790593894
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.547633380
Short name T850
Test name
Test status
Simulation time 3675820066 ps
CPU time 2.55 seconds
Started Jun 10 07:47:31 PM PDT 24
Finished Jun 10 07:47:37 PM PDT 24
Peak memory 224384 kb
Host smart-27328e85-e57f-427a-b52a-4b00db4952ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547633380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.547633380
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1688520178
Short name T724
Test name
Test status
Simulation time 389952516 ps
CPU time 6.23 seconds
Started Jun 10 07:47:15 PM PDT 24
Finished Jun 10 07:47:24 PM PDT 24
Peak memory 222912 kb
Host smart-9ea065ff-05d0-43ff-b0dd-eedcef4c9d7f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1688520178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1688520178
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.317278745
Short name T59
Test name
Test status
Simulation time 155847500 ps
CPU time 1.16 seconds
Started Jun 10 07:47:14 PM PDT 24
Finished Jun 10 07:47:18 PM PDT 24
Peak memory 235484 kb
Host smart-47e81325-b9ce-46e1-9a20-1845fc8a55d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317278745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.317278745
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2563124737
Short name T490
Test name
Test status
Simulation time 6593249546 ps
CPU time 25.66 seconds
Started Jun 10 07:47:13 PM PDT 24
Finished Jun 10 07:47:42 PM PDT 24
Peak memory 216144 kb
Host smart-aeed0d5f-4176-46f8-8b0c-ac2e9933287e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563124737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2563124737
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3774835286
Short name T419
Test name
Test status
Simulation time 2880035799 ps
CPU time 6.09 seconds
Started Jun 10 07:47:13 PM PDT 24
Finished Jun 10 07:47:23 PM PDT 24
Peak memory 216204 kb
Host smart-8c5cde40-19fc-4ae3-a2a1-2fbdeca1b340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774835286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3774835286
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1338348126
Short name T375
Test name
Test status
Simulation time 166769038 ps
CPU time 2.73 seconds
Started Jun 10 07:47:15 PM PDT 24
Finished Jun 10 07:47:21 PM PDT 24
Peak memory 216140 kb
Host smart-7378731b-b3f0-48b2-b7e8-94a738977b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338348126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1338348126
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.699476939
Short name T846
Test name
Test status
Simulation time 172367498 ps
CPU time 0.86 seconds
Started Jun 10 07:47:12 PM PDT 24
Finished Jun 10 07:47:17 PM PDT 24
Peak memory 205732 kb
Host smart-ee631ccd-6522-4808-a81f-aa240d3d14ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699476939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.699476939
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.639316556
Short name T239
Test name
Test status
Simulation time 376669396 ps
CPU time 3.24 seconds
Started Jun 10 07:47:28 PM PDT 24
Finished Jun 10 07:47:33 PM PDT 24
Peak memory 224336 kb
Host smart-4ab09636-6fdb-4f3e-a885-6853d1abb77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639316556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.639316556
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2239788673
Short name T509
Test name
Test status
Simulation time 61507941 ps
CPU time 2.65 seconds
Started Jun 10 07:47:20 PM PDT 24
Finished Jun 10 07:47:25 PM PDT 24
Peak memory 232492 kb
Host smart-10346811-8406-4bbd-b4b0-d8ee9eab6c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239788673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2239788673
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1822734620
Short name T347
Test name
Test status
Simulation time 132188575 ps
CPU time 0.79 seconds
Started Jun 10 07:47:14 PM PDT 24
Finished Jun 10 07:47:19 PM PDT 24
Peak memory 206328 kb
Host smart-93214c30-7e1e-4999-87ef-ea6c279006bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822734620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1822734620
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.824855228
Short name T581
Test name
Test status
Simulation time 2672539358 ps
CPU time 29.91 seconds
Started Jun 10 07:47:29 PM PDT 24
Finished Jun 10 07:48:01 PM PDT 24
Peak memory 224492 kb
Host smart-8cc3a6da-4a91-4098-a94a-049e42401530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824855228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.824855228
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3399002796
Short name T568
Test name
Test status
Simulation time 1467616125 ps
CPU time 22.14 seconds
Started Jun 10 07:47:32 PM PDT 24
Finished Jun 10 07:47:59 PM PDT 24
Peak memory 232744 kb
Host smart-a4139d33-7c8c-48cd-998a-507f067f0bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399002796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3399002796
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3009962536
Short name T723
Test name
Test status
Simulation time 259671770 ps
CPU time 4.24 seconds
Started Jun 10 07:47:13 PM PDT 24
Finished Jun 10 07:47:21 PM PDT 24
Peak memory 224260 kb
Host smart-722394f4-72db-45e3-b231-551006f00dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009962536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3009962536
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2971606003
Short name T406
Test name
Test status
Simulation time 3612198605 ps
CPU time 4.59 seconds
Started Jun 10 07:47:13 PM PDT 24
Finished Jun 10 07:47:21 PM PDT 24
Peak memory 232632 kb
Host smart-53c0e961-d4dc-4066-80f0-e2fbe304f245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971606003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2971606003
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.4132232500
Short name T760
Test name
Test status
Simulation time 27132346 ps
CPU time 1.13 seconds
Started Jun 10 07:47:13 PM PDT 24
Finished Jun 10 07:47:18 PM PDT 24
Peak memory 216476 kb
Host smart-76ca484b-cdf8-4efb-9a65-ff1d176f6b36
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132232500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.4132232500
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.339649245
Short name T761
Test name
Test status
Simulation time 2333088313 ps
CPU time 6.11 seconds
Started Jun 10 07:47:13 PM PDT 24
Finished Jun 10 07:47:23 PM PDT 24
Peak memory 232636 kb
Host smart-8f8ca2c8-b6eb-4214-9819-684340074ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339649245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
339649245
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3862507508
Short name T243
Test name
Test status
Simulation time 19413551565 ps
CPU time 13.63 seconds
Started Jun 10 07:47:16 PM PDT 24
Finished Jun 10 07:47:33 PM PDT 24
Peak memory 224460 kb
Host smart-30e3749d-04f6-4d89-9def-f38fd122a1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862507508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3862507508
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1641260592
Short name T559
Test name
Test status
Simulation time 2013375338 ps
CPU time 9.02 seconds
Started Jun 10 07:47:28 PM PDT 24
Finished Jun 10 07:47:39 PM PDT 24
Peak memory 222804 kb
Host smart-7a0410c5-906a-4dbf-be84-f7555520aac3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1641260592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1641260592
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3699234907
Short name T60
Test name
Test status
Simulation time 799017587 ps
CPU time 1.09 seconds
Started Jun 10 07:47:22 PM PDT 24
Finished Jun 10 07:47:25 PM PDT 24
Peak memory 235444 kb
Host smart-962b45d5-b79e-4685-8f3a-a1a29701294e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699234907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3699234907
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2427869232
Short name T975
Test name
Test status
Simulation time 4282825092 ps
CPU time 4.63 seconds
Started Jun 10 07:47:14 PM PDT 24
Finished Jun 10 07:47:22 PM PDT 24
Peak memory 216436 kb
Host smart-b8f29698-cf5c-4d5b-8f15-fea0b21cbe68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427869232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2427869232
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1080753680
Short name T914
Test name
Test status
Simulation time 20738056938 ps
CPU time 18.28 seconds
Started Jun 10 07:47:30 PM PDT 24
Finished Jun 10 07:47:52 PM PDT 24
Peak memory 216172 kb
Host smart-b34bb056-0c80-4995-8b5b-0b87e92173f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080753680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1080753680
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2352789458
Short name T390
Test name
Test status
Simulation time 92185825 ps
CPU time 1.47 seconds
Started Jun 10 07:47:13 PM PDT 24
Finished Jun 10 07:47:19 PM PDT 24
Peak memory 216012 kb
Host smart-2ab548d5-1164-4c22-9075-79bca139a6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352789458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2352789458
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.4094735606
Short name T351
Test name
Test status
Simulation time 45619137 ps
CPU time 0.72 seconds
Started Jun 10 07:47:13 PM PDT 24
Finished Jun 10 07:47:18 PM PDT 24
Peak memory 205660 kb
Host smart-a1d52be5-7cb8-4ffe-9d6d-9e8c77d56f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094735606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.4094735606
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1784125973
Short name T574
Test name
Test status
Simulation time 4666488304 ps
CPU time 5.72 seconds
Started Jun 10 07:47:12 PM PDT 24
Finished Jun 10 07:47:22 PM PDT 24
Peak memory 240812 kb
Host smart-c37f5780-f7e2-4b5c-a309-10537ee1d47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784125973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1784125973
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2765338156
Short name T776
Test name
Test status
Simulation time 23522806 ps
CPU time 0.7 seconds
Started Jun 10 07:47:43 PM PDT 24
Finished Jun 10 07:47:47 PM PDT 24
Peak memory 205656 kb
Host smart-444668b8-d274-44f6-b0a0-fc17cfd694aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765338156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2765338156
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2765330122
Short name T829
Test name
Test status
Simulation time 184737345 ps
CPU time 4.83 seconds
Started Jun 10 07:47:52 PM PDT 24
Finished Jun 10 07:47:59 PM PDT 24
Peak memory 224360 kb
Host smart-550e06ac-2662-42da-8a44-3ba337fa4ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765330122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2765330122
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1405420220
Short name T5
Test name
Test status
Simulation time 86890823 ps
CPU time 0.76 seconds
Started Jun 10 07:47:41 PM PDT 24
Finished Jun 10 07:47:46 PM PDT 24
Peak memory 206704 kb
Host smart-b7691bab-9e51-4b09-a8c3-01492570755c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405420220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1405420220
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2339782034
Short name T200
Test name
Test status
Simulation time 211275238098 ps
CPU time 376.96 seconds
Started Jun 10 07:47:53 PM PDT 24
Finished Jun 10 07:54:13 PM PDT 24
Peak memory 264860 kb
Host smart-169452bc-1188-443d-9807-cf32c1b946a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339782034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2339782034
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.775833809
Short name T43
Test name
Test status
Simulation time 37220541616 ps
CPU time 142.78 seconds
Started Jun 10 07:47:41 PM PDT 24
Finished Jun 10 07:50:08 PM PDT 24
Peak memory 224484 kb
Host smart-15f910c8-6d7e-4a34-8311-d041a4c0e78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775833809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.775833809
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3383798903
Short name T754
Test name
Test status
Simulation time 515879495 ps
CPU time 6.62 seconds
Started Jun 10 07:47:45 PM PDT 24
Finished Jun 10 07:47:55 PM PDT 24
Peak memory 224296 kb
Host smart-a4e098b0-fc61-4e9a-9a5b-3af2c352a253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383798903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3383798903
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1302789399
Short name T978
Test name
Test status
Simulation time 105707676 ps
CPU time 2.5 seconds
Started Jun 10 07:47:42 PM PDT 24
Finished Jun 10 07:47:49 PM PDT 24
Peak memory 232500 kb
Host smart-8a1898b6-a4fb-4fca-8953-a0d8df1a9dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302789399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1302789399
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.311548475
Short name T882
Test name
Test status
Simulation time 13874399495 ps
CPU time 121.79 seconds
Started Jun 10 07:47:43 PM PDT 24
Finished Jun 10 07:49:49 PM PDT 24
Peak memory 250036 kb
Host smart-25f8b466-4792-408d-8852-f55ac992dda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311548475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.311548475
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.820550496
Short name T771
Test name
Test status
Simulation time 103977029 ps
CPU time 1.12 seconds
Started Jun 10 07:47:40 PM PDT 24
Finished Jun 10 07:47:46 PM PDT 24
Peak memory 216504 kb
Host smart-e50e1e05-8487-4a67-ba8d-7c205801814a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820550496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.820550496
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1046355298
Short name T261
Test name
Test status
Simulation time 1353099052 ps
CPU time 6.9 seconds
Started Jun 10 07:47:48 PM PDT 24
Finished Jun 10 07:47:58 PM PDT 24
Peak memory 224296 kb
Host smart-ed9a97fb-d0f4-4286-9160-7f5af2ea9251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046355298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1046355298
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3332138735
Short name T884
Test name
Test status
Simulation time 564728800 ps
CPU time 7.21 seconds
Started Jun 10 07:47:50 PM PDT 24
Finished Jun 10 07:47:59 PM PDT 24
Peak memory 219708 kb
Host smart-a09536cd-53e3-494a-b2a9-2fd3c06b1c2d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3332138735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3332138735
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.614314042
Short name T286
Test name
Test status
Simulation time 79969157342 ps
CPU time 276.21 seconds
Started Jun 10 07:47:42 PM PDT 24
Finished Jun 10 07:52:22 PM PDT 24
Peak memory 273260 kb
Host smart-aea521e1-17ca-453c-925f-6f3229a32737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614314042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.614314042
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.64977252
Short name T586
Test name
Test status
Simulation time 1918495520 ps
CPU time 13.42 seconds
Started Jun 10 07:47:40 PM PDT 24
Finished Jun 10 07:47:58 PM PDT 24
Peak memory 216088 kb
Host smart-5e748585-d6a9-4572-b010-2c605c2529d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64977252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.64977252
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1067279569
Short name T606
Test name
Test status
Simulation time 5306930718 ps
CPU time 14.11 seconds
Started Jun 10 07:47:41 PM PDT 24
Finished Jun 10 07:48:00 PM PDT 24
Peak memory 216212 kb
Host smart-0142338f-1cdf-4743-870a-a12073190250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067279569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1067279569
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3934225066
Short name T508
Test name
Test status
Simulation time 90736768 ps
CPU time 1.17 seconds
Started Jun 10 07:47:42 PM PDT 24
Finished Jun 10 07:47:47 PM PDT 24
Peak memory 207360 kb
Host smart-c37b18cc-0c12-488f-a048-baf53f97b828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934225066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3934225066
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3427972544
Short name T403
Test name
Test status
Simulation time 134902125 ps
CPU time 0.89 seconds
Started Jun 10 07:47:42 PM PDT 24
Finished Jun 10 07:47:47 PM PDT 24
Peak memory 206728 kb
Host smart-96b1a4c7-77e3-4a5f-a325-1f6c80d861e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427972544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3427972544
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1690035614
Short name T583
Test name
Test status
Simulation time 21154322227 ps
CPU time 15.03 seconds
Started Jun 10 07:47:54 PM PDT 24
Finished Jun 10 07:48:12 PM PDT 24
Peak memory 224384 kb
Host smart-b3c0a423-a503-4d17-924f-9c8b3280be1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690035614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1690035614
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.703988834
Short name T547
Test name
Test status
Simulation time 36049263 ps
CPU time 0.71 seconds
Started Jun 10 07:47:48 PM PDT 24
Finished Jun 10 07:47:51 PM PDT 24
Peak memory 205304 kb
Host smart-70d72c04-1cf6-425d-b094-653e99d4a8fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703988834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.703988834
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2708435423
Short name T865
Test name
Test status
Simulation time 1556232294 ps
CPU time 7.21 seconds
Started Jun 10 07:47:44 PM PDT 24
Finished Jun 10 07:47:55 PM PDT 24
Peak memory 224216 kb
Host smart-fc9f5832-a78f-4e22-b806-919a0d0d2846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708435423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2708435423
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3383584616
Short name T439
Test name
Test status
Simulation time 13341495 ps
CPU time 0.76 seconds
Started Jun 10 07:47:44 PM PDT 24
Finished Jun 10 07:47:49 PM PDT 24
Peak memory 205316 kb
Host smart-909ce132-f401-4e12-8476-9e870fb9e5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383584616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3383584616
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.176378003
Short name T167
Test name
Test status
Simulation time 31798148532 ps
CPU time 212.11 seconds
Started Jun 10 07:47:51 PM PDT 24
Finished Jun 10 07:51:25 PM PDT 24
Peak memory 253952 kb
Host smart-273e8018-1cbd-45d5-8180-cf29ca9ff53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176378003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.176378003
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.357785231
Short name T217
Test name
Test status
Simulation time 56006675804 ps
CPU time 128.35 seconds
Started Jun 10 07:47:47 PM PDT 24
Finished Jun 10 07:49:58 PM PDT 24
Peak memory 237616 kb
Host smart-08b92b0d-9aa1-4f70-8969-92879a5681eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357785231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.357785231
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1731366881
Short name T647
Test name
Test status
Simulation time 26794848534 ps
CPU time 260.4 seconds
Started Jun 10 07:47:53 PM PDT 24
Finished Jun 10 07:52:16 PM PDT 24
Peak memory 249104 kb
Host smart-787bdd75-712d-4f87-ae15-b3251ad32bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731366881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1731366881
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.4254181198
Short name T223
Test name
Test status
Simulation time 4480338756 ps
CPU time 18.17 seconds
Started Jun 10 07:47:56 PM PDT 24
Finished Jun 10 07:48:17 PM PDT 24
Peak memory 233796 kb
Host smart-e140d615-bc7c-4bbc-938a-6d1084e4f256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254181198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4254181198
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1027737302
Short name T249
Test name
Test status
Simulation time 2348323951 ps
CPU time 7.63 seconds
Started Jun 10 07:47:49 PM PDT 24
Finished Jun 10 07:47:59 PM PDT 24
Peak memory 232656 kb
Host smart-88ce9c7a-f265-42d9-868b-f547b2e81f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027737302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1027737302
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.4176460871
Short name T973
Test name
Test status
Simulation time 27799486350 ps
CPU time 46.31 seconds
Started Jun 10 07:47:47 PM PDT 24
Finished Jun 10 07:48:36 PM PDT 24
Peak memory 232580 kb
Host smart-98e73f2a-23b6-43aa-b50d-f272f5fff9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176460871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.4176460871
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.850327762
Short name T507
Test name
Test status
Simulation time 151819919 ps
CPU time 2.2 seconds
Started Jun 10 07:47:44 PM PDT 24
Finished Jun 10 07:47:50 PM PDT 24
Peak memory 222944 kb
Host smart-c86b7971-3274-4f03-8cc8-957e96ea79a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850327762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.850327762
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.330360934
Short name T652
Test name
Test status
Simulation time 450145159 ps
CPU time 5.11 seconds
Started Jun 10 07:47:46 PM PDT 24
Finished Jun 10 07:47:54 PM PDT 24
Peak memory 232536 kb
Host smart-28264613-2474-43c8-98dd-fcb1c6be7ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330360934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.330360934
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1157110915
Short name T645
Test name
Test status
Simulation time 192497452 ps
CPU time 4.09 seconds
Started Jun 10 07:47:47 PM PDT 24
Finished Jun 10 07:47:54 PM PDT 24
Peak memory 222956 kb
Host smart-b530abb2-5e8e-4ed3-a0ed-6980186dd392
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1157110915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1157110915
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.705582227
Short name T886
Test name
Test status
Simulation time 2336327978 ps
CPU time 33.78 seconds
Started Jun 10 07:47:45 PM PDT 24
Finished Jun 10 07:48:22 PM PDT 24
Peak memory 216200 kb
Host smart-42a783e3-70b9-4518-9655-c58acf9b655c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705582227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.705582227
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3240591125
Short name T452
Test name
Test status
Simulation time 533027886 ps
CPU time 1.46 seconds
Started Jun 10 07:47:51 PM PDT 24
Finished Jun 10 07:47:54 PM PDT 24
Peak memory 207532 kb
Host smart-ec80b809-d21c-48cb-aa8e-12513b5f6f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240591125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3240591125
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2980804970
Short name T643
Test name
Test status
Simulation time 581788853 ps
CPU time 4.93 seconds
Started Jun 10 07:47:43 PM PDT 24
Finished Jun 10 07:47:51 PM PDT 24
Peak memory 216020 kb
Host smart-723260d6-2d80-4105-bfdf-b4d7225f380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980804970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2980804970
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1120743645
Short name T370
Test name
Test status
Simulation time 203059960 ps
CPU time 0.85 seconds
Started Jun 10 07:47:42 PM PDT 24
Finished Jun 10 07:47:47 PM PDT 24
Peak memory 206112 kb
Host smart-cb9dc5e2-adcb-4e4c-ba97-d80abe218b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120743645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1120743645
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.576093489
Short name T256
Test name
Test status
Simulation time 904902839 ps
CPU time 5.53 seconds
Started Jun 10 07:47:47 PM PDT 24
Finished Jun 10 07:47:55 PM PDT 24
Peak memory 224252 kb
Host smart-71973442-c28c-415e-9ef2-38b5b3a030f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576093489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.576093489
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2806319130
Short name T418
Test name
Test status
Simulation time 14747274 ps
CPU time 0.72 seconds
Started Jun 10 07:47:53 PM PDT 24
Finished Jun 10 07:47:56 PM PDT 24
Peak memory 204732 kb
Host smart-71a3bcc2-bc7b-4b09-bbf4-4f9034bb12f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806319130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2806319130
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3182448150
Short name T593
Test name
Test status
Simulation time 3776032485 ps
CPU time 4.26 seconds
Started Jun 10 07:47:45 PM PDT 24
Finished Jun 10 07:47:53 PM PDT 24
Peak memory 224424 kb
Host smart-a128f200-4f7f-40a9-862a-af191470adea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182448150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3182448150
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2258753170
Short name T11
Test name
Test status
Simulation time 35088406 ps
CPU time 0.77 seconds
Started Jun 10 07:47:54 PM PDT 24
Finished Jun 10 07:47:57 PM PDT 24
Peak memory 206708 kb
Host smart-7fdf1ba8-5875-4153-87f3-b5f86813920f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258753170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2258753170
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2218446083
Short name T635
Test name
Test status
Simulation time 9156031291 ps
CPU time 62.23 seconds
Started Jun 10 07:47:48 PM PDT 24
Finished Jun 10 07:48:53 PM PDT 24
Peak memory 249048 kb
Host smart-71190b87-8b80-442a-ae41-e1ca0b699a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218446083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2218446083
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2369523519
Short name T890
Test name
Test status
Simulation time 5402214727 ps
CPU time 42.09 seconds
Started Jun 10 07:47:51 PM PDT 24
Finished Jun 10 07:48:35 PM PDT 24
Peak memory 235848 kb
Host smart-16ae2be9-3529-4eab-8013-7b644d627d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369523519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2369523519
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2376648786
Short name T213
Test name
Test status
Simulation time 126536709780 ps
CPU time 327.79 seconds
Started Jun 10 07:47:50 PM PDT 24
Finished Jun 10 07:53:19 PM PDT 24
Peak memory 255180 kb
Host smart-82329c79-b9b9-48a3-9d33-5ad6d3c9d01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376648786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2376648786
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3095569361
Short name T842
Test name
Test status
Simulation time 141427377 ps
CPU time 3.24 seconds
Started Jun 10 07:47:54 PM PDT 24
Finished Jun 10 07:48:00 PM PDT 24
Peak memory 224280 kb
Host smart-f0a3a4cc-90fd-4c9a-ae63-9cd30f5adf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095569361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3095569361
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.634112938
Short name T851
Test name
Test status
Simulation time 78986200 ps
CPU time 2.31 seconds
Started Jun 10 07:47:53 PM PDT 24
Finished Jun 10 07:47:58 PM PDT 24
Peak memory 224288 kb
Host smart-d64a3aef-4752-4455-8cde-c923036e017b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634112938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.634112938
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3248858350
Short name T229
Test name
Test status
Simulation time 5837571477 ps
CPU time 45.29 seconds
Started Jun 10 07:47:44 PM PDT 24
Finished Jun 10 07:48:33 PM PDT 24
Peak memory 224424 kb
Host smart-cb5f518c-4c0f-4441-8837-7b22bb42e0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248858350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3248858350
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2636610178
Short name T567
Test name
Test status
Simulation time 85261856 ps
CPU time 1.15 seconds
Started Jun 10 07:47:48 PM PDT 24
Finished Jun 10 07:47:51 PM PDT 24
Peak memory 216512 kb
Host smart-1436a60e-3f55-49bf-a72a-115d9e2f7d3e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636610178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2636610178
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1476158757
Short name T202
Test name
Test status
Simulation time 1114433359 ps
CPU time 4.3 seconds
Started Jun 10 07:48:01 PM PDT 24
Finished Jun 10 07:48:06 PM PDT 24
Peak memory 232528 kb
Host smart-34e0a296-0ea8-4b5a-b675-f9b5a211c767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476158757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1476158757
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.784317781
Short name T265
Test name
Test status
Simulation time 1190543891 ps
CPU time 4.13 seconds
Started Jun 10 07:48:08 PM PDT 24
Finished Jun 10 07:48:13 PM PDT 24
Peak memory 228496 kb
Host smart-e1d0fa06-022d-4044-8990-151a7d2083a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784317781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.784317781
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2053908459
Short name T866
Test name
Test status
Simulation time 2613113750 ps
CPU time 8.72 seconds
Started Jun 10 07:47:48 PM PDT 24
Finished Jun 10 07:47:59 PM PDT 24
Peak memory 220320 kb
Host smart-a5ac8309-39df-451d-a4ec-9deb611ec542
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2053908459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2053908459
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2108167444
Short name T332
Test name
Test status
Simulation time 6612023987 ps
CPU time 19.56 seconds
Started Jun 10 07:47:47 PM PDT 24
Finished Jun 10 07:48:10 PM PDT 24
Peak memory 216428 kb
Host smart-1205034c-e06b-4b3d-8aba-c7b7dea9c703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108167444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2108167444
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1803910381
Short name T70
Test name
Test status
Simulation time 5995179745 ps
CPU time 2.41 seconds
Started Jun 10 07:47:46 PM PDT 24
Finished Jun 10 07:47:51 PM PDT 24
Peak memory 207840 kb
Host smart-02af5592-6e44-4385-81e8-5765035d181c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803910381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1803910381
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.126819298
Short name T885
Test name
Test status
Simulation time 54160587 ps
CPU time 1.18 seconds
Started Jun 10 07:47:53 PM PDT 24
Finished Jun 10 07:47:57 PM PDT 24
Peak memory 207772 kb
Host smart-3c1d5e55-0746-4a15-be8b-a6e0938658a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126819298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.126819298
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3370128287
Short name T864
Test name
Test status
Simulation time 163234934 ps
CPU time 0.8 seconds
Started Jun 10 07:47:52 PM PDT 24
Finished Jun 10 07:47:56 PM PDT 24
Peak memory 205700 kb
Host smart-c4a8489f-c409-4f89-a427-35a0dd95ec42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370128287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3370128287
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.823817121
Short name T521
Test name
Test status
Simulation time 6228476645 ps
CPU time 21.07 seconds
Started Jun 10 07:47:50 PM PDT 24
Finished Jun 10 07:48:13 PM PDT 24
Peak memory 232620 kb
Host smart-c22393bb-b820-4f98-8880-4dfd6da04ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823817121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.823817121
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.4158770453
Short name T55
Test name
Test status
Simulation time 14826746 ps
CPU time 0.76 seconds
Started Jun 10 07:47:57 PM PDT 24
Finished Jun 10 07:48:00 PM PDT 24
Peak memory 204284 kb
Host smart-b923f6e4-8d98-4178-a378-546ba466cb1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158770453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
4158770453
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.820890608
Short name T478
Test name
Test status
Simulation time 46369122 ps
CPU time 0.78 seconds
Started Jun 10 07:47:47 PM PDT 24
Finished Jun 10 07:47:51 PM PDT 24
Peak memory 205320 kb
Host smart-3a1e4b77-8c36-452c-adee-3679d4b67221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820890608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.820890608
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.4170833151
Short name T964
Test name
Test status
Simulation time 3643079642 ps
CPU time 13.53 seconds
Started Jun 10 07:47:54 PM PDT 24
Finished Jun 10 07:48:10 PM PDT 24
Peak memory 234880 kb
Host smart-6024aa17-bcd8-4393-bc03-c174b65e4dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170833151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.4170833151
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.144661488
Short name T454
Test name
Test status
Simulation time 11489723202 ps
CPU time 57.84 seconds
Started Jun 10 07:48:01 PM PDT 24
Finished Jun 10 07:49:00 PM PDT 24
Peak memory 254984 kb
Host smart-892cd793-4e4f-4e1a-9734-f9babccd24c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144661488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.144661488
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2875728671
Short name T848
Test name
Test status
Simulation time 29077169287 ps
CPU time 55.05 seconds
Started Jun 10 07:48:00 PM PDT 24
Finished Jun 10 07:48:56 PM PDT 24
Peak memory 240832 kb
Host smart-e4b82731-dcaa-4b23-b82a-ccac47559423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875728671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2875728671
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_intercept.757431048
Short name T285
Test name
Test status
Simulation time 12259116823 ps
CPU time 23.49 seconds
Started Jun 10 07:47:50 PM PDT 24
Finished Jun 10 07:48:15 PM PDT 24
Peak memory 232680 kb
Host smart-2f370d9e-88a5-4a7f-986a-8406837c13e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757431048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.757431048
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1857473742
Short name T952
Test name
Test status
Simulation time 423905567 ps
CPU time 2.47 seconds
Started Jun 10 07:47:49 PM PDT 24
Finished Jun 10 07:47:53 PM PDT 24
Peak memory 224236 kb
Host smart-2a108e66-05a5-4049-b9ee-3a6caa6147f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857473742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1857473742
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3256127894
Short name T40
Test name
Test status
Simulation time 91499561 ps
CPU time 1.06 seconds
Started Jun 10 07:47:46 PM PDT 24
Finished Jun 10 07:47:50 PM PDT 24
Peak memory 216460 kb
Host smart-8a8f85b4-61a3-4995-9a39-1afcad2281be
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256127894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3256127894
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1367150165
Short name T648
Test name
Test status
Simulation time 324550014 ps
CPU time 2.32 seconds
Started Jun 10 07:47:51 PM PDT 24
Finished Jun 10 07:47:56 PM PDT 24
Peak memory 224276 kb
Host smart-cadd1ab4-b031-472e-8a64-abf9c29deb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367150165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1367150165
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2199312495
Short name T807
Test name
Test status
Simulation time 5184653350 ps
CPU time 8.07 seconds
Started Jun 10 07:47:53 PM PDT 24
Finished Jun 10 07:48:04 PM PDT 24
Peak memory 232676 kb
Host smart-ca85c066-8c67-4916-aa72-353636922614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199312495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2199312495
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3235851850
Short name T968
Test name
Test status
Simulation time 2039963475 ps
CPU time 6.85 seconds
Started Jun 10 07:47:57 PM PDT 24
Finished Jun 10 07:48:06 PM PDT 24
Peak memory 221588 kb
Host smart-22fb1d3f-edba-44a6-a2d2-b04e768d3b1f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3235851850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3235851850
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2177281120
Short name T824
Test name
Test status
Simulation time 62733396870 ps
CPU time 208.81 seconds
Started Jun 10 07:47:50 PM PDT 24
Finished Jun 10 07:51:21 PM PDT 24
Peak memory 254376 kb
Host smart-5649c1ac-37bc-4334-8539-30229b99606b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177281120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2177281120
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1503498668
Short name T4
Test name
Test status
Simulation time 5006389745 ps
CPU time 17.8 seconds
Started Jun 10 07:47:57 PM PDT 24
Finished Jun 10 07:48:17 PM PDT 24
Peak memory 216152 kb
Host smart-2b1fe606-8526-45d7-8037-2939d776b27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503498668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1503498668
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3677478508
Short name T705
Test name
Test status
Simulation time 1050085915 ps
CPU time 2.11 seconds
Started Jun 10 07:47:44 PM PDT 24
Finished Jun 10 07:47:50 PM PDT 24
Peak memory 215980 kb
Host smart-32eb4374-e33f-4146-bb7a-c5984eff532e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677478508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3677478508
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.356913227
Short name T159
Test name
Test status
Simulation time 229510190 ps
CPU time 1.54 seconds
Started Jun 10 07:48:12 PM PDT 24
Finished Jun 10 07:48:15 PM PDT 24
Peak memory 216160 kb
Host smart-a2307354-8656-439e-9123-d8ff305a5e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356913227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.356913227
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.999100842
Short name T440
Test name
Test status
Simulation time 82927650 ps
CPU time 0.97 seconds
Started Jun 10 07:47:51 PM PDT 24
Finished Jun 10 07:47:55 PM PDT 24
Peak memory 206716 kb
Host smart-d3156f30-70f1-4d3b-9159-dbadfd99b3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999100842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.999100842
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.441677390
Short name T487
Test name
Test status
Simulation time 4579367112 ps
CPU time 13.94 seconds
Started Jun 10 07:48:00 PM PDT 24
Finished Jun 10 07:48:15 PM PDT 24
Peak memory 224488 kb
Host smart-fd0c5c86-55e6-4502-8c83-3b633c1c04ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441677390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.441677390
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1903314778
Short name T362
Test name
Test status
Simulation time 13155100 ps
CPU time 0.69 seconds
Started Jun 10 07:47:53 PM PDT 24
Finished Jun 10 07:47:56 PM PDT 24
Peak memory 204720 kb
Host smart-16010fde-212b-4376-8e78-034abe7d4e75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903314778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1903314778
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3389509064
Short name T468
Test name
Test status
Simulation time 64758679 ps
CPU time 0.78 seconds
Started Jun 10 07:47:52 PM PDT 24
Finished Jun 10 07:47:55 PM PDT 24
Peak memory 206796 kb
Host smart-82667896-45b9-4836-9ef7-a56e2baf4fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389509064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3389509064
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.117048212
Short name T870
Test name
Test status
Simulation time 15888491 ps
CPU time 0.78 seconds
Started Jun 10 07:47:55 PM PDT 24
Finished Jun 10 07:47:58 PM PDT 24
Peak memory 215808 kb
Host smart-fa659e67-1655-40e4-8c01-9618bec2230a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117048212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.117048212
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.420960331
Short name T168
Test name
Test status
Simulation time 26770685958 ps
CPU time 56.22 seconds
Started Jun 10 07:48:08 PM PDT 24
Finished Jun 10 07:49:06 PM PDT 24
Peak memory 235524 kb
Host smart-7db70b44-d126-4f20-b209-6a80ec239c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420960331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.420960331
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2436194343
Short name T465
Test name
Test status
Simulation time 15067031456 ps
CPU time 154.23 seconds
Started Jun 10 07:47:55 PM PDT 24
Finished Jun 10 07:50:32 PM PDT 24
Peak memory 240916 kb
Host smart-dad41f4c-ca74-4bea-bb41-e46aa8a78d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436194343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2436194343
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3730325495
Short name T408
Test name
Test status
Simulation time 1526176337 ps
CPU time 9.79 seconds
Started Jun 10 07:47:55 PM PDT 24
Finished Jun 10 07:48:07 PM PDT 24
Peak memory 232512 kb
Host smart-88a8a52e-99d5-4cd9-a771-d5bb7b63b94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730325495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3730325495
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.169041459
Short name T380
Test name
Test status
Simulation time 33256270 ps
CPU time 2.46 seconds
Started Jun 10 07:48:01 PM PDT 24
Finished Jun 10 07:48:05 PM PDT 24
Peak memory 232420 kb
Host smart-0d25cb71-742d-4f05-b878-f127200c9247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169041459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.169041459
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3802931022
Short name T513
Test name
Test status
Simulation time 6337379510 ps
CPU time 66.15 seconds
Started Jun 10 07:48:16 PM PDT 24
Finished Jun 10 07:49:23 PM PDT 24
Peak memory 248784 kb
Host smart-b5adfb2c-3aed-4226-933c-c5f7d102d0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802931022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3802931022
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2833134013
Short name T38
Test name
Test status
Simulation time 57073257 ps
CPU time 1.08 seconds
Started Jun 10 07:48:08 PM PDT 24
Finished Jun 10 07:48:11 PM PDT 24
Peak memory 216500 kb
Host smart-b71429c9-9fb5-4cf5-a127-09df20bb7bdb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833134013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2833134013
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.277309345
Short name T566
Test name
Test status
Simulation time 345747178 ps
CPU time 2.54 seconds
Started Jun 10 07:47:57 PM PDT 24
Finished Jun 10 07:48:02 PM PDT 24
Peak memory 232560 kb
Host smart-84434ecc-7862-4cc5-a185-f1c399dad9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277309345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.277309345
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.808363007
Short name T33
Test name
Test status
Simulation time 16408322734 ps
CPU time 12.55 seconds
Started Jun 10 07:47:54 PM PDT 24
Finished Jun 10 07:48:09 PM PDT 24
Peak memory 232652 kb
Host smart-ff24cbe1-319e-436e-8162-35e373dc24fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808363007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.808363007
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.893852310
Short name T431
Test name
Test status
Simulation time 346800479 ps
CPU time 4.5 seconds
Started Jun 10 07:48:03 PM PDT 24
Finished Jun 10 07:48:09 PM PDT 24
Peak memory 219504 kb
Host smart-e80fe6cf-f550-4cdc-ad9b-ae02c003687b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=893852310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.893852310
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1309713446
Short name T833
Test name
Test status
Simulation time 293147810 ps
CPU time 0.96 seconds
Started Jun 10 07:48:07 PM PDT 24
Finished Jun 10 07:48:09 PM PDT 24
Peak memory 206552 kb
Host smart-30daaa05-1ea3-46bd-9813-0e66353dd340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309713446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1309713446
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2219281447
Short name T741
Test name
Test status
Simulation time 13094055028 ps
CPU time 27.04 seconds
Started Jun 10 07:47:52 PM PDT 24
Finished Jun 10 07:48:21 PM PDT 24
Peak memory 216324 kb
Host smart-3e595da2-d8d0-45f4-b075-e855990b5991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219281447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2219281447
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2114412104
Short name T361
Test name
Test status
Simulation time 38322768414 ps
CPU time 17.03 seconds
Started Jun 10 07:48:03 PM PDT 24
Finished Jun 10 07:48:21 PM PDT 24
Peak memory 216180 kb
Host smart-3076dfa7-d64b-4b59-ab46-f75a39b770ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114412104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2114412104
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.140666660
Short name T511
Test name
Test status
Simulation time 199831440 ps
CPU time 2.95 seconds
Started Jun 10 07:47:52 PM PDT 24
Finished Jun 10 07:47:58 PM PDT 24
Peak memory 216228 kb
Host smart-166d8670-66fa-4e8d-b367-9611e31fad87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140666660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.140666660
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2509283967
Short name T957
Test name
Test status
Simulation time 180718007 ps
CPU time 0.86 seconds
Started Jun 10 07:47:57 PM PDT 24
Finished Jun 10 07:48:00 PM PDT 24
Peak memory 205748 kb
Host smart-30011d22-1acd-40a3-8953-45e5d51992de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509283967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2509283967
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2399317257
Short name T570
Test name
Test status
Simulation time 2197722380 ps
CPU time 9.58 seconds
Started Jun 10 07:48:07 PM PDT 24
Finished Jun 10 07:48:18 PM PDT 24
Peak memory 232628 kb
Host smart-d5c70051-16c6-4753-b066-0bfa69826da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399317257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2399317257
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.4062722453
Short name T654
Test name
Test status
Simulation time 12191171 ps
CPU time 0.75 seconds
Started Jun 10 07:47:57 PM PDT 24
Finished Jun 10 07:48:00 PM PDT 24
Peak memory 205336 kb
Host smart-18d40974-f692-4bfe-bbaa-a32f52d53af5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062722453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
4062722453
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1470421705
Short name T364
Test name
Test status
Simulation time 60774122 ps
CPU time 2.11 seconds
Started Jun 10 07:48:03 PM PDT 24
Finished Jun 10 07:48:06 PM PDT 24
Peak memory 223688 kb
Host smart-6ec52002-db5c-4394-a7ab-61204d7f6c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470421705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1470421705
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1221813250
Short name T498
Test name
Test status
Simulation time 18448436 ps
CPU time 0.73 seconds
Started Jun 10 07:48:07 PM PDT 24
Finished Jun 10 07:48:09 PM PDT 24
Peak memory 205332 kb
Host smart-0bd162ad-fcf4-40c8-82f2-7ee584454fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221813250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1221813250
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.355467678
Short name T166
Test name
Test status
Simulation time 48127082497 ps
CPU time 98.4 seconds
Started Jun 10 07:48:03 PM PDT 24
Finished Jun 10 07:49:42 PM PDT 24
Peak memory 236424 kb
Host smart-04749aec-c414-4f70-9a36-aa1e902c5deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355467678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.355467678
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2628958756
Short name T308
Test name
Test status
Simulation time 7722090695 ps
CPU time 91.05 seconds
Started Jun 10 07:47:56 PM PDT 24
Finished Jun 10 07:49:30 PM PDT 24
Peak memory 256780 kb
Host smart-8728fd97-845e-437f-a526-4632ef29d0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628958756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2628958756
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3171106227
Short name T318
Test name
Test status
Simulation time 49779817000 ps
CPU time 132.9 seconds
Started Jun 10 07:48:07 PM PDT 24
Finished Jun 10 07:50:22 PM PDT 24
Peak memory 252684 kb
Host smart-32b770cb-8f43-4621-89da-ce7da3cb7ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171106227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3171106227
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2421475467
Short name T379
Test name
Test status
Simulation time 1773879767 ps
CPU time 26.97 seconds
Started Jun 10 07:47:56 PM PDT 24
Finished Jun 10 07:48:26 PM PDT 24
Peak memory 239292 kb
Host smart-ce3f5af0-ca38-40dc-a2ff-26e8ab390c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421475467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2421475467
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1761120087
Short name T187
Test name
Test status
Simulation time 7014726829 ps
CPU time 26.74 seconds
Started Jun 10 07:48:09 PM PDT 24
Finished Jun 10 07:48:37 PM PDT 24
Peak memory 232640 kb
Host smart-82fb8005-129f-431b-aae2-68196a82945d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761120087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1761120087
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.887445488
Short name T784
Test name
Test status
Simulation time 21784512459 ps
CPU time 96.3 seconds
Started Jun 10 07:48:18 PM PDT 24
Finished Jun 10 07:49:57 PM PDT 24
Peak memory 240244 kb
Host smart-cabb8e54-05de-4421-a099-00bb49693a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887445488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.887445488
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1503068591
Short name T563
Test name
Test status
Simulation time 37945696 ps
CPU time 0.98 seconds
Started Jun 10 07:47:48 PM PDT 24
Finished Jun 10 07:47:51 PM PDT 24
Peak memory 217668 kb
Host smart-a21519af-cbf0-4303-8893-e8c20da16a3e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503068591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1503068591
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2629975584
Short name T514
Test name
Test status
Simulation time 21683777129 ps
CPU time 21.47 seconds
Started Jun 10 07:47:56 PM PDT 24
Finished Jun 10 07:48:20 PM PDT 24
Peak memory 239732 kb
Host smart-c4795846-7c0e-4633-935d-2d563664dddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629975584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2629975584
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2713172798
Short name T738
Test name
Test status
Simulation time 73463257 ps
CPU time 2.39 seconds
Started Jun 10 07:48:04 PM PDT 24
Finished Jun 10 07:48:08 PM PDT 24
Peak memory 222708 kb
Host smart-d7908f6d-04e9-47da-8766-e07dafd584a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713172798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2713172798
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.4110007651
Short name T360
Test name
Test status
Simulation time 75254915 ps
CPU time 3.32 seconds
Started Jun 10 07:47:54 PM PDT 24
Finished Jun 10 07:48:01 PM PDT 24
Peak memory 218548 kb
Host smart-a975eba4-8e21-4961-891c-846d44e945c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4110007651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.4110007651
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.444569440
Short name T150
Test name
Test status
Simulation time 74733863735 ps
CPU time 219.38 seconds
Started Jun 10 07:47:57 PM PDT 24
Finished Jun 10 07:51:39 PM PDT 24
Peak memory 273640 kb
Host smart-0353dfd8-95c9-44e4-aec7-5077a0f821c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444569440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.444569440
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3306228458
Short name T616
Test name
Test status
Simulation time 7913866615 ps
CPU time 41.4 seconds
Started Jun 10 07:47:54 PM PDT 24
Finished Jun 10 07:48:39 PM PDT 24
Peak memory 216176 kb
Host smart-f719d126-6b76-42db-9e14-90c89e5a9540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306228458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3306228458
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.555385282
Short name T489
Test name
Test status
Simulation time 2841785991 ps
CPU time 12.37 seconds
Started Jun 10 07:47:57 PM PDT 24
Finished Jun 10 07:48:12 PM PDT 24
Peak memory 215764 kb
Host smart-d648a895-046c-425f-9147-0925bbba5930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555385282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.555385282
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2807388344
Short name T371
Test name
Test status
Simulation time 40161329 ps
CPU time 1.58 seconds
Started Jun 10 07:48:03 PM PDT 24
Finished Jun 10 07:48:05 PM PDT 24
Peak memory 216084 kb
Host smart-adc1c2a5-ca30-4e35-b82d-c55e386010ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807388344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2807388344
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2933506146
Short name T369
Test name
Test status
Simulation time 23143659 ps
CPU time 0.76 seconds
Started Jun 10 07:47:56 PM PDT 24
Finished Jun 10 07:47:59 PM PDT 24
Peak memory 205696 kb
Host smart-49b05993-6818-4f43-9b19-2306b7e7833d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933506146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2933506146
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1761711585
Short name T459
Test name
Test status
Simulation time 5619617335 ps
CPU time 23.23 seconds
Started Jun 10 07:47:56 PM PDT 24
Finished Jun 10 07:48:22 PM PDT 24
Peak memory 232680 kb
Host smart-17555b35-d0a9-4285-8cff-cf4edf7e53eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761711585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1761711585
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3171203181
Short name T661
Test name
Test status
Simulation time 34474139 ps
CPU time 0.72 seconds
Started Jun 10 07:47:54 PM PDT 24
Finished Jun 10 07:47:57 PM PDT 24
Peak memory 205284 kb
Host smart-f7eb11e5-d51c-4d6d-9b93-6dc793d2d056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171203181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3171203181
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1685510123
Short name T456
Test name
Test status
Simulation time 797673981 ps
CPU time 10.79 seconds
Started Jun 10 07:48:18 PM PDT 24
Finished Jun 10 07:48:31 PM PDT 24
Peak memory 232520 kb
Host smart-e716bcc2-6a51-48e9-b298-d70886a8aa3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685510123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1685510123
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2093798778
Short name T339
Test name
Test status
Simulation time 15360852 ps
CPU time 0.77 seconds
Started Jun 10 07:47:56 PM PDT 24
Finished Jun 10 07:47:59 PM PDT 24
Peak memory 206344 kb
Host smart-e29966fe-1695-4668-acd7-696d98fa3a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093798778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2093798778
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1914536717
Short name T278
Test name
Test status
Simulation time 29166133194 ps
CPU time 286.39 seconds
Started Jun 10 07:48:11 PM PDT 24
Finished Jun 10 07:52:59 PM PDT 24
Peak memory 250584 kb
Host smart-58bc976d-c166-48c6-bd60-912abe66a25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914536717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1914536717
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.102391791
Short name T348
Test name
Test status
Simulation time 712389698 ps
CPU time 4.57 seconds
Started Jun 10 07:48:11 PM PDT 24
Finished Jun 10 07:48:17 PM PDT 24
Peak memory 232484 kb
Host smart-75fe0529-36a1-40e0-b438-88c6923733a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102391791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.102391791
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2602591880
Short name T546
Test name
Test status
Simulation time 1890352429 ps
CPU time 12.21 seconds
Started Jun 10 07:47:59 PM PDT 24
Finished Jun 10 07:48:13 PM PDT 24
Peak memory 232556 kb
Host smart-91cd56dc-2ed7-42de-a1de-bbf33f001d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602591880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2602591880
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3709218708
Short name T14
Test name
Test status
Simulation time 804520795 ps
CPU time 6.77 seconds
Started Jun 10 07:47:58 PM PDT 24
Finished Jun 10 07:48:07 PM PDT 24
Peak memory 240632 kb
Host smart-c385c434-8733-4ee7-b54b-44f5cda55637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709218708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3709218708
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.869956315
Short name T708
Test name
Test status
Simulation time 90519685 ps
CPU time 1.03 seconds
Started Jun 10 07:48:05 PM PDT 24
Finished Jun 10 07:48:07 PM PDT 24
Peak memory 217712 kb
Host smart-22f8fa3f-f72c-4883-aacd-44234ea19d30
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869956315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.869956315
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.4025717885
Short name T282
Test name
Test status
Simulation time 1639424151 ps
CPU time 3.87 seconds
Started Jun 10 07:47:52 PM PDT 24
Finished Jun 10 07:47:58 PM PDT 24
Peak memory 224292 kb
Host smart-89a8a764-77ec-4fac-ad77-34bedf4b096a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025717885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.4025717885
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3494386196
Short name T898
Test name
Test status
Simulation time 856808544 ps
CPU time 3.63 seconds
Started Jun 10 07:48:14 PM PDT 24
Finished Jun 10 07:48:19 PM PDT 24
Peak memory 224312 kb
Host smart-cdf35709-c36f-493a-8568-6de0432cef4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494386196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3494386196
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.582667944
Short name T787
Test name
Test status
Simulation time 12440825110 ps
CPU time 7.71 seconds
Started Jun 10 07:47:58 PM PDT 24
Finished Jun 10 07:48:08 PM PDT 24
Peak memory 218788 kb
Host smart-2302b86a-6a92-4724-84f2-5ef1e84a8f63
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=582667944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.582667944
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1186931458
Short name T228
Test name
Test status
Simulation time 30177489214 ps
CPU time 254.93 seconds
Started Jun 10 07:47:54 PM PDT 24
Finished Jun 10 07:52:12 PM PDT 24
Peak memory 250720 kb
Host smart-848d87c3-e0ac-435c-afe8-582ce620fea7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186931458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1186931458
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3258885228
Short name T350
Test name
Test status
Simulation time 1857918355 ps
CPU time 11.01 seconds
Started Jun 10 07:47:55 PM PDT 24
Finished Jun 10 07:48:09 PM PDT 24
Peak memory 216100 kb
Host smart-88779353-709e-4437-893e-74698fc60888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258885228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3258885228
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2172061661
Short name T740
Test name
Test status
Simulation time 384535122 ps
CPU time 1.25 seconds
Started Jun 10 07:48:08 PM PDT 24
Finished Jun 10 07:48:11 PM PDT 24
Peak memory 206752 kb
Host smart-933bf515-18f0-4887-9cae-5abcd1b06a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172061661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2172061661
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1399795202
Short name T948
Test name
Test status
Simulation time 1896482435 ps
CPU time 2.99 seconds
Started Jun 10 07:48:04 PM PDT 24
Finished Jun 10 07:48:09 PM PDT 24
Peak memory 215988 kb
Host smart-00539fd1-1b9d-4053-aa74-0c7488513161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399795202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1399795202
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3569366704
Short name T775
Test name
Test status
Simulation time 13467823 ps
CPU time 0.69 seconds
Started Jun 10 07:47:58 PM PDT 24
Finished Jun 10 07:48:01 PM PDT 24
Peak memory 205412 kb
Host smart-7c442e34-f1ee-415c-b8f5-218b61c46f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569366704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3569366704
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3709780122
Short name T178
Test name
Test status
Simulation time 15995729519 ps
CPU time 11.98 seconds
Started Jun 10 07:48:06 PM PDT 24
Finished Jun 10 07:48:19 PM PDT 24
Peak memory 232596 kb
Host smart-f911f8dd-57ba-45b1-82da-32ee57fad8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709780122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3709780122
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3290214900
Short name T674
Test name
Test status
Simulation time 10899405 ps
CPU time 0.75 seconds
Started Jun 10 07:48:08 PM PDT 24
Finished Jun 10 07:48:10 PM PDT 24
Peak memory 205308 kb
Host smart-de8f0d78-c6c1-4263-ac3a-3cefe34e2f41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290214900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3290214900
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2980641390
Short name T264
Test name
Test status
Simulation time 119869981 ps
CPU time 2.48 seconds
Started Jun 10 07:47:52 PM PDT 24
Finished Jun 10 07:47:57 PM PDT 24
Peak memory 224296 kb
Host smart-c8a45125-5614-4416-bb48-6dee5578485d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980641390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2980641390
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.823960816
Short name T469
Test name
Test status
Simulation time 21154177 ps
CPU time 0.76 seconds
Started Jun 10 07:47:50 PM PDT 24
Finished Jun 10 07:47:53 PM PDT 24
Peak memory 206716 kb
Host smart-2f852444-076a-4623-9863-6a72af516645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823960816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.823960816
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.339358225
Short name T284
Test name
Test status
Simulation time 4107356225 ps
CPU time 54.61 seconds
Started Jun 10 07:48:02 PM PDT 24
Finished Jun 10 07:48:58 PM PDT 24
Peak memory 239312 kb
Host smart-a812fcbf-5db8-4f39-a079-155389807980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339358225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.339358225
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2166401728
Short name T52
Test name
Test status
Simulation time 170837812880 ps
CPU time 478.45 seconds
Started Jun 10 07:47:52 PM PDT 24
Finished Jun 10 07:55:53 PM PDT 24
Peak memory 255936 kb
Host smart-099bc4aa-8625-4920-a70f-336fe5a96430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166401728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2166401728
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1069533574
Short name T240
Test name
Test status
Simulation time 244025183 ps
CPU time 3.38 seconds
Started Jun 10 07:48:02 PM PDT 24
Finished Jun 10 07:48:06 PM PDT 24
Peak memory 224312 kb
Host smart-3c50bfd7-64d4-4287-bd70-af0e706a1162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069533574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1069533574
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.247236916
Short name T794
Test name
Test status
Simulation time 1747779816 ps
CPU time 12.73 seconds
Started Jun 10 07:48:13 PM PDT 24
Finished Jun 10 07:48:28 PM PDT 24
Peak memory 232512 kb
Host smart-8c9b8691-183d-4eb5-afad-6ad7beb3409e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247236916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.247236916
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2967634923
Short name T603
Test name
Test status
Simulation time 115015279 ps
CPU time 1.03 seconds
Started Jun 10 07:47:58 PM PDT 24
Finished Jun 10 07:48:01 PM PDT 24
Peak memory 217736 kb
Host smart-c912aa5a-10cf-4ff7-b8a7-4d93cd55620b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967634923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2967634923
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1760943390
Short name T622
Test name
Test status
Simulation time 1098020695 ps
CPU time 8.79 seconds
Started Jun 10 07:48:07 PM PDT 24
Finished Jun 10 07:48:17 PM PDT 24
Peak memory 232568 kb
Host smart-b90f5f66-0156-4f1d-b49a-ccf4df92b20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760943390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1760943390
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3696123652
Short name T871
Test name
Test status
Simulation time 1384721178 ps
CPU time 6.99 seconds
Started Jun 10 07:47:53 PM PDT 24
Finished Jun 10 07:48:03 PM PDT 24
Peak memory 232516 kb
Host smart-026a0332-f47f-4516-81b9-5280ee37fe9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696123652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3696123652
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2001895738
Short name T683
Test name
Test status
Simulation time 80150899 ps
CPU time 3.57 seconds
Started Jun 10 07:48:07 PM PDT 24
Finished Jun 10 07:48:12 PM PDT 24
Peak memory 219168 kb
Host smart-05b23b7e-5a1a-4d9f-a760-be8e9d0fd44b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2001895738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2001895738
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2392761072
Short name T730
Test name
Test status
Simulation time 3227389954 ps
CPU time 34.05 seconds
Started Jun 10 07:47:57 PM PDT 24
Finished Jun 10 07:48:34 PM PDT 24
Peak memory 217212 kb
Host smart-c8d90d76-75e4-4560-af5f-e03e4f768833
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392761072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2392761072
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2449238591
Short name T712
Test name
Test status
Simulation time 1828913311 ps
CPU time 9.67 seconds
Started Jun 10 07:47:50 PM PDT 24
Finished Jun 10 07:48:02 PM PDT 24
Peak memory 216052 kb
Host smart-1d495315-66b8-42fe-91eb-12483c2ded08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449238591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2449238591
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2661909314
Short name T795
Test name
Test status
Simulation time 2605923406 ps
CPU time 3.45 seconds
Started Jun 10 07:48:07 PM PDT 24
Finished Jun 10 07:48:12 PM PDT 24
Peak memory 216136 kb
Host smart-e4df27aa-8664-48ad-981d-7fa078b03954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661909314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2661909314
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.4231617818
Short name T713
Test name
Test status
Simulation time 921697883 ps
CPU time 3.55 seconds
Started Jun 10 07:47:53 PM PDT 24
Finished Jun 10 07:48:00 PM PDT 24
Peak memory 216096 kb
Host smart-f1e04094-27b1-46ce-af79-02043b862758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231617818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.4231617818
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1893562870
Short name T598
Test name
Test status
Simulation time 49294974 ps
CPU time 0.9 seconds
Started Jun 10 07:47:56 PM PDT 24
Finished Jun 10 07:47:59 PM PDT 24
Peak memory 206676 kb
Host smart-7dc2186a-8ba5-4e37-b417-e698b88e454f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893562870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1893562870
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3064632012
Short name T257
Test name
Test status
Simulation time 1007201567 ps
CPU time 3.59 seconds
Started Jun 10 07:47:57 PM PDT 24
Finished Jun 10 07:48:03 PM PDT 24
Peak memory 232580 kb
Host smart-cfd45a63-de71-40a3-8f26-02b46b7541e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064632012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3064632012
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1712240528
Short name T932
Test name
Test status
Simulation time 16051831 ps
CPU time 0.74 seconds
Started Jun 10 07:48:20 PM PDT 24
Finished Jun 10 07:48:24 PM PDT 24
Peak memory 205272 kb
Host smart-f52e3edd-6bf4-4799-9c04-7aff409eb97e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712240528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1712240528
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2693816559
Short name T897
Test name
Test status
Simulation time 36420499 ps
CPU time 2.47 seconds
Started Jun 10 07:48:11 PM PDT 24
Finished Jun 10 07:48:15 PM PDT 24
Peak memory 232504 kb
Host smart-409cc740-5803-4c99-bb2d-57621879d9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693816559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2693816559
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3636549857
Short name T758
Test name
Test status
Simulation time 27834556 ps
CPU time 0.76 seconds
Started Jun 10 07:47:52 PM PDT 24
Finished Jun 10 07:47:55 PM PDT 24
Peak memory 205356 kb
Host smart-3cc26a09-53aa-422a-b77b-ab19bf10e264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636549857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3636549857
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.940283999
Short name T778
Test name
Test status
Simulation time 62407255905 ps
CPU time 42.19 seconds
Started Jun 10 07:48:10 PM PDT 24
Finished Jun 10 07:48:53 PM PDT 24
Peak memory 224412 kb
Host smart-115cd34d-bd78-4617-a390-93acb8c1e088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940283999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.940283999
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1201944925
Short name T523
Test name
Test status
Simulation time 5517375086 ps
CPU time 77.54 seconds
Started Jun 10 07:48:20 PM PDT 24
Finished Jun 10 07:49:42 PM PDT 24
Peak memory 257288 kb
Host smart-6a27a4bd-13b4-47f3-aa4e-376e62079582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201944925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1201944925
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2667382162
Short name T161
Test name
Test status
Simulation time 1012927023 ps
CPU time 4.62 seconds
Started Jun 10 07:48:13 PM PDT 24
Finished Jun 10 07:48:19 PM PDT 24
Peak memory 224288 kb
Host smart-14973a12-5a0f-43bf-8a92-9ca82084895e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667382162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2667382162
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.361699409
Short name T908
Test name
Test status
Simulation time 4320285272 ps
CPU time 12.87 seconds
Started Jun 10 07:48:21 PM PDT 24
Finished Jun 10 07:48:38 PM PDT 24
Peak memory 232628 kb
Host smart-59d83761-4d2a-4ab8-a724-50dfa1153ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361699409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.361699409
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3409500448
Short name T921
Test name
Test status
Simulation time 25330299373 ps
CPU time 64.48 seconds
Started Jun 10 07:48:04 PM PDT 24
Finished Jun 10 07:49:10 PM PDT 24
Peak memory 224424 kb
Host smart-3628ddb1-4d07-4372-b438-823dbb1013e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409500448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3409500448
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2605678122
Short name T817
Test name
Test status
Simulation time 84298047 ps
CPU time 1.06 seconds
Started Jun 10 07:47:57 PM PDT 24
Finished Jun 10 07:48:00 PM PDT 24
Peak memory 216556 kb
Host smart-0fcb5593-acae-4daf-b0e6-e3b2bfb074ad
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605678122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2605678122
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2681966898
Short name T472
Test name
Test status
Simulation time 432844127 ps
CPU time 3.53 seconds
Started Jun 10 07:48:12 PM PDT 24
Finished Jun 10 07:48:17 PM PDT 24
Peak memory 224136 kb
Host smart-804d0c84-3f1d-447c-a595-56406e0700c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681966898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2681966898
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3247767152
Short name T435
Test name
Test status
Simulation time 10382797539 ps
CPU time 16.71 seconds
Started Jun 10 07:48:07 PM PDT 24
Finished Jun 10 07:48:25 PM PDT 24
Peak memory 232680 kb
Host smart-02f616a7-868b-4123-b451-e0f3f79f69c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247767152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3247767152
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1199405892
Short name T510
Test name
Test status
Simulation time 643165686 ps
CPU time 3.72 seconds
Started Jun 10 07:48:21 PM PDT 24
Finished Jun 10 07:48:29 PM PDT 24
Peak memory 219720 kb
Host smart-5803ba6b-418e-4ac0-9465-d8887226b985
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1199405892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1199405892
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2316960793
Short name T476
Test name
Test status
Simulation time 1101589822 ps
CPU time 6.08 seconds
Started Jun 10 07:47:55 PM PDT 24
Finished Jun 10 07:48:04 PM PDT 24
Peak memory 218740 kb
Host smart-6901b936-d17d-45de-a149-f32555d8d564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316960793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2316960793
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2202789494
Short name T748
Test name
Test status
Simulation time 4669629001 ps
CPU time 11.91 seconds
Started Jun 10 07:47:55 PM PDT 24
Finished Jun 10 07:48:09 PM PDT 24
Peak memory 216132 kb
Host smart-bb08ba59-1f81-4db0-9a5f-ed130ff0d8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202789494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2202789494
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3672054680
Short name T722
Test name
Test status
Simulation time 42760413 ps
CPU time 0.87 seconds
Started Jun 10 07:48:02 PM PDT 24
Finished Jun 10 07:48:04 PM PDT 24
Peak memory 206848 kb
Host smart-ba1d6ab8-b88b-4c08-88d6-d8c64bd4b715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672054680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3672054680
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1501216977
Short name T410
Test name
Test status
Simulation time 394483802 ps
CPU time 1.07 seconds
Started Jun 10 07:47:58 PM PDT 24
Finished Jun 10 07:48:01 PM PDT 24
Peak memory 206724 kb
Host smart-e454c2a0-6334-4bc8-878c-68b3619084ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501216977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1501216977
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3730332557
Short name T769
Test name
Test status
Simulation time 1781476100 ps
CPU time 8.52 seconds
Started Jun 10 07:48:16 PM PDT 24
Finished Jun 10 07:48:26 PM PDT 24
Peak memory 232452 kb
Host smart-899f3b27-4e71-47e8-8366-8602dbe67b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730332557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3730332557
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.59241520
Short name T961
Test name
Test status
Simulation time 78152397 ps
CPU time 0.7 seconds
Started Jun 10 07:48:07 PM PDT 24
Finished Jun 10 07:48:09 PM PDT 24
Peak memory 205344 kb
Host smart-4395f9b4-9c0c-4352-828b-ebb426fc791f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59241520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.59241520
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.918813054
Short name T82
Test name
Test status
Simulation time 285266441 ps
CPU time 5.81 seconds
Started Jun 10 07:48:09 PM PDT 24
Finished Jun 10 07:48:17 PM PDT 24
Peak memory 232528 kb
Host smart-10b38a1c-f358-4708-8143-6a6e6c94e689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918813054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.918813054
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2319194316
Short name T665
Test name
Test status
Simulation time 13761033 ps
CPU time 0.79 seconds
Started Jun 10 07:48:09 PM PDT 24
Finished Jun 10 07:48:11 PM PDT 24
Peak memory 206492 kb
Host smart-3062c4cb-270a-4b6e-8b1e-21629424c995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319194316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2319194316
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3299536907
Short name T715
Test name
Test status
Simulation time 12948430 ps
CPU time 0.76 seconds
Started Jun 10 07:48:05 PM PDT 24
Finished Jun 10 07:48:07 PM PDT 24
Peak memory 215800 kb
Host smart-78fee7b4-0e7c-4172-ac28-7430b23756d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299536907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3299536907
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.392633189
Short name T226
Test name
Test status
Simulation time 20323979571 ps
CPU time 73.07 seconds
Started Jun 10 07:48:04 PM PDT 24
Finished Jun 10 07:49:19 PM PDT 24
Peak memory 232656 kb
Host smart-a3ec91fd-a8b6-4264-93d2-da613960c22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392633189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.392633189
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.667528021
Short name T970
Test name
Test status
Simulation time 27345064611 ps
CPU time 141.42 seconds
Started Jun 10 07:48:06 PM PDT 24
Finished Jun 10 07:50:28 PM PDT 24
Peak memory 249036 kb
Host smart-8d2f0482-609e-479b-887a-b7fd742adc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667528021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.667528021
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2059718321
Short name T630
Test name
Test status
Simulation time 6579473846 ps
CPU time 13.13 seconds
Started Jun 10 07:48:10 PM PDT 24
Finished Jun 10 07:48:24 PM PDT 24
Peak memory 232668 kb
Host smart-4a067e51-caf0-4ac4-aaaf-8e1c94aa4945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059718321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2059718321
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.4162316072
Short name T881
Test name
Test status
Simulation time 1256831862 ps
CPU time 16.93 seconds
Started Jun 10 07:48:11 PM PDT 24
Finished Jun 10 07:48:29 PM PDT 24
Peak memory 224248 kb
Host smart-ccf76618-50cd-46c6-9db7-8edd97f5394d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162316072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.4162316072
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2134505087
Short name T426
Test name
Test status
Simulation time 15111818126 ps
CPU time 68.33 seconds
Started Jun 10 07:48:22 PM PDT 24
Finished Jun 10 07:49:35 PM PDT 24
Peak memory 248688 kb
Host smart-d185851f-320b-40d4-a2da-ece4043a7942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134505087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2134505087
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.155306846
Short name T735
Test name
Test status
Simulation time 50563630 ps
CPU time 1.05 seconds
Started Jun 10 07:48:05 PM PDT 24
Finished Jun 10 07:48:07 PM PDT 24
Peak memory 217728 kb
Host smart-9431b700-d0f9-481f-ae4d-ad2ce51d9b57
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155306846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.155306846
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3024074320
Short name T878
Test name
Test status
Simulation time 2396313165 ps
CPU time 9.44 seconds
Started Jun 10 07:48:05 PM PDT 24
Finished Jun 10 07:48:16 PM PDT 24
Peak memory 232632 kb
Host smart-cf62fe07-9337-4572-bb32-081ce44b4e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024074320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3024074320
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3060190555
Short name T479
Test name
Test status
Simulation time 121272315 ps
CPU time 2.03 seconds
Started Jun 10 07:48:06 PM PDT 24
Finished Jun 10 07:48:09 PM PDT 24
Peak memory 222456 kb
Host smart-4d481693-2745-41d3-b641-be0e1f30f786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060190555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3060190555
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2526347942
Short name T811
Test name
Test status
Simulation time 134104533 ps
CPU time 4.35 seconds
Started Jun 10 07:48:08 PM PDT 24
Finished Jun 10 07:48:14 PM PDT 24
Peak memory 219068 kb
Host smart-3e0da41f-3eac-4339-b729-a1325d7e7369
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2526347942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2526347942
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2039726341
Short name T925
Test name
Test status
Simulation time 3377039578 ps
CPU time 33.58 seconds
Started Jun 10 07:48:07 PM PDT 24
Finished Jun 10 07:48:42 PM PDT 24
Peak memory 218608 kb
Host smart-46c5adbf-cb6c-4331-95ca-8e6b1efe9278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039726341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2039726341
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3217003605
Short name T883
Test name
Test status
Simulation time 4312899045 ps
CPU time 6.85 seconds
Started Jun 10 07:48:18 PM PDT 24
Finished Jun 10 07:48:28 PM PDT 24
Peak memory 216224 kb
Host smart-af0fca1e-0b0d-46d6-9ef2-363bedf00235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217003605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3217003605
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.201492186
Short name T797
Test name
Test status
Simulation time 11186811 ps
CPU time 0.74 seconds
Started Jun 10 07:48:16 PM PDT 24
Finished Jun 10 07:48:18 PM PDT 24
Peak memory 205420 kb
Host smart-f20c8f7d-f93b-4dde-980f-d0eb66484b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201492186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.201492186
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3197225677
Short name T877
Test name
Test status
Simulation time 37781330 ps
CPU time 0.86 seconds
Started Jun 10 07:48:09 PM PDT 24
Finished Jun 10 07:48:11 PM PDT 24
Peak memory 205780 kb
Host smart-18d95628-d883-40c3-b2d2-6797a4bb9ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197225677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3197225677
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.119115769
Short name T416
Test name
Test status
Simulation time 7353404556 ps
CPU time 8.61 seconds
Started Jun 10 07:48:19 PM PDT 24
Finished Jun 10 07:48:30 PM PDT 24
Peak memory 240352 kb
Host smart-de026335-9745-48b1-b6b8-bd4abdcfa8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119115769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.119115769
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1637842496
Short name T384
Test name
Test status
Simulation time 13359295 ps
CPU time 0.73 seconds
Started Jun 10 07:47:23 PM PDT 24
Finished Jun 10 07:47:25 PM PDT 24
Peak memory 205336 kb
Host smart-1922280a-349c-4255-baea-23ac376383b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637842496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
637842496
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.4278809789
Short name T966
Test name
Test status
Simulation time 220621433 ps
CPU time 2.38 seconds
Started Jun 10 07:47:23 PM PDT 24
Finished Jun 10 07:47:27 PM PDT 24
Peak memory 224292 kb
Host smart-51a21699-7ea7-4fda-a317-53dbad967539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278809789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.4278809789
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3454677367
Short name T505
Test name
Test status
Simulation time 42495971 ps
CPU time 0.84 seconds
Started Jun 10 07:47:23 PM PDT 24
Finished Jun 10 07:47:25 PM PDT 24
Peak memory 206720 kb
Host smart-e070e3b9-f83a-4edc-8993-b44802d7afb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454677367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3454677367
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1642943046
Short name T906
Test name
Test status
Simulation time 3637079804 ps
CPU time 39.11 seconds
Started Jun 10 07:47:20 PM PDT 24
Finished Jun 10 07:48:01 PM PDT 24
Peak memory 249260 kb
Host smart-e2b6c87b-f5b0-4187-bd69-b5fad17882ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642943046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1642943046
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1622148903
Short name T330
Test name
Test status
Simulation time 30849585997 ps
CPU time 288.02 seconds
Started Jun 10 07:47:30 PM PDT 24
Finished Jun 10 07:52:21 PM PDT 24
Peak memory 251524 kb
Host smart-9e107101-382b-4185-95a8-623599326960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622148903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1622148903
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.573827483
Short name T326
Test name
Test status
Simulation time 10972295708 ps
CPU time 32.99 seconds
Started Jun 10 07:47:23 PM PDT 24
Finished Jun 10 07:47:59 PM PDT 24
Peak memory 240812 kb
Host smart-0e5b48e4-a4e6-4f36-8a38-5ed989eaa728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573827483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.573827483
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3158824302
Short name T260
Test name
Test status
Simulation time 77893068 ps
CPU time 2.8 seconds
Started Jun 10 07:47:31 PM PDT 24
Finished Jun 10 07:47:38 PM PDT 24
Peak memory 224284 kb
Host smart-6f145561-e1ca-4ba8-8c93-ca2cbc4bd19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158824302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3158824302
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3162310580
Short name T790
Test name
Test status
Simulation time 11238150004 ps
CPU time 72.89 seconds
Started Jun 10 07:47:31 PM PDT 24
Finished Jun 10 07:48:48 PM PDT 24
Peak memory 227700 kb
Host smart-119774c0-4b8c-476d-a35e-aa8b623f300e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162310580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3162310580
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3720501585
Short name T558
Test name
Test status
Simulation time 15042571 ps
CPU time 1.03 seconds
Started Jun 10 07:47:21 PM PDT 24
Finished Jun 10 07:47:23 PM PDT 24
Peak memory 217820 kb
Host smart-15850cd9-8467-41c7-a26d-d6a22289cd4f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720501585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3720501585
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.182566705
Short name T806
Test name
Test status
Simulation time 23358729848 ps
CPU time 19.49 seconds
Started Jun 10 07:47:22 PM PDT 24
Finished Jun 10 07:47:43 PM PDT 24
Peak memory 240776 kb
Host smart-a0e83c31-d064-4ad0-8013-4a5014d6d5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182566705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
182566705
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1936115597
Short name T290
Test name
Test status
Simulation time 5686627363 ps
CPU time 17.04 seconds
Started Jun 10 07:47:25 PM PDT 24
Finished Jun 10 07:47:44 PM PDT 24
Peak memory 239684 kb
Host smart-26e7dff1-0aa4-428f-bfca-710c728dde4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936115597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1936115597
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.181154446
Short name T953
Test name
Test status
Simulation time 3369707057 ps
CPU time 8.94 seconds
Started Jun 10 07:47:26 PM PDT 24
Finished Jun 10 07:47:37 PM PDT 24
Peak memory 222356 kb
Host smart-b37cc7b2-562d-43d5-816b-7aaae2ef9bba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=181154446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.181154446
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1163780998
Short name T61
Test name
Test status
Simulation time 70507038 ps
CPU time 0.98 seconds
Started Jun 10 07:47:31 PM PDT 24
Finished Jun 10 07:47:36 PM PDT 24
Peak memory 235468 kb
Host smart-2c96200f-99c2-437f-a14c-5cd615519431
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163780998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1163780998
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1101963370
Short name T212
Test name
Test status
Simulation time 127837647620 ps
CPU time 1246.63 seconds
Started Jun 10 07:47:24 PM PDT 24
Finished Jun 10 08:08:13 PM PDT 24
Peak memory 271596 kb
Host smart-f57a59d5-e359-4d2a-8406-b61b7c56a143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101963370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1101963370
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1864463394
Short name T909
Test name
Test status
Simulation time 39086763 ps
CPU time 0.72 seconds
Started Jun 10 07:47:30 PM PDT 24
Finished Jun 10 07:47:34 PM PDT 24
Peak memory 205512 kb
Host smart-0efdf0db-2c04-4155-bf2e-97d694422ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864463394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1864463394
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.566949094
Short name T496
Test name
Test status
Simulation time 175490344 ps
CPU time 1.05 seconds
Started Jun 10 07:47:21 PM PDT 24
Finished Jun 10 07:47:24 PM PDT 24
Peak memory 205772 kb
Host smart-309e3ad2-496a-4689-a997-181a4f6a2204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566949094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.566949094
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1054593970
Short name T366
Test name
Test status
Simulation time 13054619 ps
CPU time 0.74 seconds
Started Jun 10 07:47:22 PM PDT 24
Finished Jun 10 07:47:24 PM PDT 24
Peak memory 205368 kb
Host smart-c318950b-1dc5-42de-bae9-00e475246d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054593970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1054593970
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.516828146
Short name T950
Test name
Test status
Simulation time 42120555 ps
CPU time 0.72 seconds
Started Jun 10 07:47:29 PM PDT 24
Finished Jun 10 07:47:32 PM PDT 24
Peak memory 205664 kb
Host smart-43285fe2-e1c8-43e6-b0d8-1a90ebd76f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516828146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.516828146
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2105579151
Short name T757
Test name
Test status
Simulation time 1936523936 ps
CPU time 5.59 seconds
Started Jun 10 07:47:22 PM PDT 24
Finished Jun 10 07:47:29 PM PDT 24
Peak memory 224308 kb
Host smart-0eb176d1-a2d9-47d2-91e9-a3c703fe680f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105579151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2105579151
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.59838398
Short name T714
Test name
Test status
Simulation time 53051818 ps
CPU time 0.74 seconds
Started Jun 10 07:48:08 PM PDT 24
Finished Jun 10 07:48:10 PM PDT 24
Peak memory 205308 kb
Host smart-bdbcf1bd-80df-4b1d-b9c8-3423c658de8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59838398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.59838398
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3996518590
Short name T876
Test name
Test status
Simulation time 133776781 ps
CPU time 3.11 seconds
Started Jun 10 07:48:12 PM PDT 24
Finished Jun 10 07:48:17 PM PDT 24
Peak memory 224216 kb
Host smart-ae5f3820-abe0-4320-b81a-c1238608c2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996518590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3996518590
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.4098820376
Short name T600
Test name
Test status
Simulation time 24310570 ps
CPU time 0.81 seconds
Started Jun 10 07:48:09 PM PDT 24
Finished Jun 10 07:48:12 PM PDT 24
Peak memory 206352 kb
Host smart-1c41708b-bc30-4c40-908c-ad81d6747426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098820376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.4098820376
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1158947189
Short name T917
Test name
Test status
Simulation time 10521744514 ps
CPU time 93.2 seconds
Started Jun 10 07:48:18 PM PDT 24
Finished Jun 10 07:49:54 PM PDT 24
Peak memory 249040 kb
Host smart-5242b564-0313-4370-812e-5b0080f0a4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158947189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1158947189
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.4181347078
Short name T204
Test name
Test status
Simulation time 3996872936 ps
CPU time 70.13 seconds
Started Jun 10 07:48:18 PM PDT 24
Finished Jun 10 07:49:31 PM PDT 24
Peak memory 253236 kb
Host smart-d458109a-c2a2-4c47-92d9-73b08e499c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181347078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.4181347078
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.939844430
Short name T325
Test name
Test status
Simulation time 2284438128 ps
CPU time 33.35 seconds
Started Jun 10 07:48:12 PM PDT 24
Finished Jun 10 07:48:47 PM PDT 24
Peak memory 232544 kb
Host smart-f101e1dc-1f46-40d1-8457-24829d673360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939844430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.939844430
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2503666813
Short name T818
Test name
Test status
Simulation time 1560017281 ps
CPU time 9.34 seconds
Started Jun 10 07:48:22 PM PDT 24
Finished Jun 10 07:48:36 PM PDT 24
Peak memory 228344 kb
Host smart-6a7f0364-a5f8-44b9-9864-2ae6b4932a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503666813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2503666813
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1853155097
Short name T397
Test name
Test status
Simulation time 49002770 ps
CPU time 2.16 seconds
Started Jun 10 07:48:18 PM PDT 24
Finished Jun 10 07:48:23 PM PDT 24
Peak memory 222908 kb
Host smart-adeaaa39-7294-4ef2-81eb-89924a5aa198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853155097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1853155097
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3901269676
Short name T555
Test name
Test status
Simulation time 5762266224 ps
CPU time 7.03 seconds
Started Jun 10 07:48:05 PM PDT 24
Finished Jun 10 07:48:13 PM PDT 24
Peak memory 232652 kb
Host smart-f110d88f-27a6-48fd-857b-fc932e8a6c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901269676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3901269676
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1053113405
Short name T902
Test name
Test status
Simulation time 1749054602 ps
CPU time 7.96 seconds
Started Jun 10 07:48:11 PM PDT 24
Finished Jun 10 07:48:20 PM PDT 24
Peak memory 232588 kb
Host smart-b783bbe6-a762-4124-b976-412a22b6c871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053113405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1053113405
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1035047713
Short name T904
Test name
Test status
Simulation time 4232431029 ps
CPU time 4.53 seconds
Started Jun 10 07:48:07 PM PDT 24
Finished Jun 10 07:48:13 PM PDT 24
Peak memory 219212 kb
Host smart-7eb7fdb0-1e00-4760-ab8a-f423da783d6d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1035047713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1035047713
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2555033679
Short name T18
Test name
Test status
Simulation time 12565686034 ps
CPU time 59.56 seconds
Started Jun 10 07:48:18 PM PDT 24
Finished Jun 10 07:49:19 PM PDT 24
Peak memory 230948 kb
Host smart-c0072d5c-4ea8-4fec-8738-b6a4d3168812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555033679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2555033679
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3960567968
Short name T328
Test name
Test status
Simulation time 1459251256 ps
CPU time 13.28 seconds
Started Jun 10 07:48:07 PM PDT 24
Finished Jun 10 07:48:22 PM PDT 24
Peak memory 219160 kb
Host smart-d7758cfd-9631-441a-9527-c59c2d6abb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960567968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3960567968
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2486522750
Short name T363
Test name
Test status
Simulation time 37713011 ps
CPU time 0.75 seconds
Started Jun 10 07:48:18 PM PDT 24
Finished Jun 10 07:48:20 PM PDT 24
Peak memory 205504 kb
Host smart-18923356-6bdf-417b-b2f3-35b3665ee4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486522750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2486522750
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3740183778
Short name T545
Test name
Test status
Simulation time 779810902 ps
CPU time 2.32 seconds
Started Jun 10 07:48:22 PM PDT 24
Finished Jun 10 07:48:29 PM PDT 24
Peak memory 216132 kb
Host smart-e6555c42-c063-4ae6-87f4-c93cf2abd0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740183778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3740183778
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1627916315
Short name T428
Test name
Test status
Simulation time 30601683 ps
CPU time 0.82 seconds
Started Jun 10 07:48:18 PM PDT 24
Finished Jun 10 07:48:21 PM PDT 24
Peak memory 205696 kb
Host smart-cd96366d-3233-4122-bf42-dd32982141d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627916315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1627916315
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2973355743
Short name T578
Test name
Test status
Simulation time 618111449 ps
CPU time 2.99 seconds
Started Jun 10 07:48:19 PM PDT 24
Finished Jun 10 07:48:26 PM PDT 24
Peak memory 232496 kb
Host smart-37203d92-a49e-4496-99ec-ef875f27837b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973355743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2973355743
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1205124714
Short name T726
Test name
Test status
Simulation time 13283975 ps
CPU time 0.7 seconds
Started Jun 10 07:48:20 PM PDT 24
Finished Jun 10 07:48:25 PM PDT 24
Peak memory 205320 kb
Host smart-83d3eb44-4214-499b-95a1-301b8dd287ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205124714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1205124714
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.583587570
Short name T269
Test name
Test status
Simulation time 2304774901 ps
CPU time 8.07 seconds
Started Jun 10 07:48:09 PM PDT 24
Finished Jun 10 07:48:19 PM PDT 24
Peak memory 224448 kb
Host smart-10b0d5e5-9c34-47eb-aab5-396108f47b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583587570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.583587570
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2095803758
Short name T373
Test name
Test status
Simulation time 41383565 ps
CPU time 0.73 seconds
Started Jun 10 07:48:06 PM PDT 24
Finished Jun 10 07:48:08 PM PDT 24
Peak memory 205688 kb
Host smart-52d0b515-21e4-4739-bf7b-3af834d3714c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095803758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2095803758
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3544901096
Short name T322
Test name
Test status
Simulation time 16015667952 ps
CPU time 38.17 seconds
Started Jun 10 07:48:21 PM PDT 24
Finished Jun 10 07:49:03 PM PDT 24
Peak memory 233948 kb
Host smart-57dffd00-57dc-47ba-90be-ce9a6ce04552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544901096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3544901096
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3175061813
Short name T209
Test name
Test status
Simulation time 149707016 ps
CPU time 3.52 seconds
Started Jun 10 07:48:16 PM PDT 24
Finished Jun 10 07:48:20 PM PDT 24
Peak memory 224288 kb
Host smart-e9717c92-40a4-4b32-b0d3-503374fac486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175061813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3175061813
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2028344039
Short name T288
Test name
Test status
Simulation time 1817703612 ps
CPU time 11.8 seconds
Started Jun 10 07:48:10 PM PDT 24
Finished Jun 10 07:48:23 PM PDT 24
Peak memory 224252 kb
Host smart-008097b3-fa92-4623-8175-fbf012b7967c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028344039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2028344039
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.257279978
Short name T430
Test name
Test status
Simulation time 236095105 ps
CPU time 3.95 seconds
Started Jun 10 07:48:08 PM PDT 24
Finished Jun 10 07:48:14 PM PDT 24
Peak memory 224228 kb
Host smart-5751730b-5a1c-46d5-a446-e41f0ea86e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257279978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.257279978
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1228272319
Short name T225
Test name
Test status
Simulation time 1378053576 ps
CPU time 6.48 seconds
Started Jun 10 07:48:10 PM PDT 24
Finished Jun 10 07:48:18 PM PDT 24
Peak memory 232520 kb
Host smart-9094acce-3ff1-4abc-9756-432efec89cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228272319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1228272319
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1101920741
Short name T832
Test name
Test status
Simulation time 908206567 ps
CPU time 8.38 seconds
Started Jun 10 07:48:17 PM PDT 24
Finished Jun 10 07:48:27 PM PDT 24
Peak memory 219468 kb
Host smart-5c20d41c-d10e-4825-a380-7e9fbe7e7f5a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1101920741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1101920741
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3532045527
Short name T528
Test name
Test status
Simulation time 3541625131 ps
CPU time 29.69 seconds
Started Jun 10 07:48:21 PM PDT 24
Finished Jun 10 07:48:55 PM PDT 24
Peak memory 217300 kb
Host smart-8ca32d81-ccc6-4c7e-86f0-cdac6bbd4b69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532045527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3532045527
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.829653791
Short name T918
Test name
Test status
Simulation time 4152950280 ps
CPU time 13.51 seconds
Started Jun 10 07:48:07 PM PDT 24
Finished Jun 10 07:48:22 PM PDT 24
Peak memory 215972 kb
Host smart-577a97af-d8ed-4ef7-ad57-b060484bd30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829653791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.829653791
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3518291098
Short name T506
Test name
Test status
Simulation time 105067042 ps
CPU time 1.23 seconds
Started Jun 10 07:48:22 PM PDT 24
Finished Jun 10 07:48:28 PM PDT 24
Peak memory 207708 kb
Host smart-bb135688-1664-4baa-a7ff-1f1db5d5116c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518291098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3518291098
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.287480428
Short name T873
Test name
Test status
Simulation time 12987291 ps
CPU time 0.9 seconds
Started Jun 10 07:48:12 PM PDT 24
Finished Jun 10 07:48:15 PM PDT 24
Peak memory 207096 kb
Host smart-9ec034d9-d344-4337-86a3-c3da10ae1a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287480428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.287480428
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2388636560
Short name T557
Test name
Test status
Simulation time 100454148 ps
CPU time 0.98 seconds
Started Jun 10 07:48:19 PM PDT 24
Finished Jun 10 07:48:23 PM PDT 24
Peak memory 206684 kb
Host smart-f0a6fe7e-edba-4adf-9d23-78d50000eb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388636560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2388636560
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.673042213
Short name T831
Test name
Test status
Simulation time 213743007 ps
CPU time 3.84 seconds
Started Jun 10 07:48:19 PM PDT 24
Finished Jun 10 07:48:25 PM PDT 24
Peak memory 224300 kb
Host smart-4d6e4d60-ca1c-476a-8998-6a80e35eaa63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673042213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.673042213
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2971896501
Short name T501
Test name
Test status
Simulation time 141953059 ps
CPU time 0.72 seconds
Started Jun 10 07:48:24 PM PDT 24
Finished Jun 10 07:48:29 PM PDT 24
Peak memory 205308 kb
Host smart-6e06d0ff-d9e9-4682-8651-c5bf857010f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971896501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2971896501
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2759320284
Short name T475
Test name
Test status
Simulation time 3334809461 ps
CPU time 9.01 seconds
Started Jun 10 07:48:21 PM PDT 24
Finished Jun 10 07:48:35 PM PDT 24
Peak memory 224484 kb
Host smart-7a1643b4-315d-40c6-8cbc-fa70114cece9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759320284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2759320284
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.4248475317
Short name T604
Test name
Test status
Simulation time 42729077 ps
CPU time 0.8 seconds
Started Jun 10 07:48:24 PM PDT 24
Finished Jun 10 07:48:29 PM PDT 24
Peak memory 206404 kb
Host smart-5cdeb33f-bc6d-44a7-8cdf-dd89dc778df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248475317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.4248475317
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3637541479
Short name T185
Test name
Test status
Simulation time 8944740978 ps
CPU time 20.73 seconds
Started Jun 10 07:48:21 PM PDT 24
Finished Jun 10 07:48:46 PM PDT 24
Peak memory 253372 kb
Host smart-3078211e-e026-4df1-acf3-8c53e0d813b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637541479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3637541479
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1486629006
Short name T677
Test name
Test status
Simulation time 6332820871 ps
CPU time 45.68 seconds
Started Jun 10 07:48:25 PM PDT 24
Finished Jun 10 07:49:15 PM PDT 24
Peak memory 249096 kb
Host smart-9b49fc18-9d98-496e-999a-0afc3f48d2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486629006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1486629006
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.599926842
Short name T595
Test name
Test status
Simulation time 50763301569 ps
CPU time 497.72 seconds
Started Jun 10 07:48:19 PM PDT 24
Finished Jun 10 07:56:40 PM PDT 24
Peak memory 262052 kb
Host smart-39d10d88-543c-43e6-992f-1e76fa0d26c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599926842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.599926842
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.447345100
Short name T542
Test name
Test status
Simulation time 3120144262 ps
CPU time 12.52 seconds
Started Jun 10 07:48:24 PM PDT 24
Finished Jun 10 07:48:41 PM PDT 24
Peak memory 224408 kb
Host smart-56063cd6-3bc6-4a8e-b886-5b2cc0781cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447345100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.447345100
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2977060576
Short name T84
Test name
Test status
Simulation time 723010267 ps
CPU time 4.32 seconds
Started Jun 10 07:48:21 PM PDT 24
Finished Jun 10 07:48:29 PM PDT 24
Peak memory 224288 kb
Host smart-4d55fe68-397d-4258-a8df-7ac317d4e374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977060576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2977060576
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3375689287
Short name T298
Test name
Test status
Simulation time 797846860 ps
CPU time 9.33 seconds
Started Jun 10 07:48:22 PM PDT 24
Finished Jun 10 07:48:38 PM PDT 24
Peak memory 232504 kb
Host smart-c70ab317-d792-4d5e-9eb4-0838301a9b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375689287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3375689287
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3967997230
Short name T281
Test name
Test status
Simulation time 377066857 ps
CPU time 8.1 seconds
Started Jun 10 07:48:23 PM PDT 24
Finished Jun 10 07:48:36 PM PDT 24
Peak memory 232532 kb
Host smart-170a50da-978c-467a-bd95-e957770cfbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967997230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3967997230
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.956827512
Short name T809
Test name
Test status
Simulation time 2467399324 ps
CPU time 11.38 seconds
Started Jun 10 07:48:20 PM PDT 24
Finished Jun 10 07:48:35 PM PDT 24
Peak memory 224468 kb
Host smart-c0429bc7-20c3-483d-9a31-02c14fa37a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956827512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.956827512
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3904139041
Short name T486
Test name
Test status
Simulation time 6202016008 ps
CPU time 17.16 seconds
Started Jun 10 07:48:21 PM PDT 24
Finished Jun 10 07:48:43 PM PDT 24
Peak memory 223048 kb
Host smart-74b4f397-e0e4-405a-814c-ce57adef88d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3904139041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3904139041
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1529182932
Short name T153
Test name
Test status
Simulation time 329764591 ps
CPU time 1.45 seconds
Started Jun 10 07:48:18 PM PDT 24
Finished Jun 10 07:48:22 PM PDT 24
Peak memory 207572 kb
Host smart-a995ed59-4838-4165-9ddb-808d37fe130c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529182932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1529182932
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2638027327
Short name T594
Test name
Test status
Simulation time 10299675106 ps
CPU time 15.85 seconds
Started Jun 10 07:48:22 PM PDT 24
Finished Jun 10 07:48:42 PM PDT 24
Peak memory 217484 kb
Host smart-ef2f5453-9c9e-4303-b715-46372e7f54ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638027327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2638027327
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.607970505
Short name T449
Test name
Test status
Simulation time 563872445 ps
CPU time 2.32 seconds
Started Jun 10 07:48:21 PM PDT 24
Finished Jun 10 07:48:28 PM PDT 24
Peak memory 215880 kb
Host smart-cf324273-3a74-4593-8be0-0a034692d895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607970505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.607970505
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3505759904
Short name T412
Test name
Test status
Simulation time 151357943 ps
CPU time 6.31 seconds
Started Jun 10 07:48:18 PM PDT 24
Finished Jun 10 07:48:27 PM PDT 24
Peak memory 216112 kb
Host smart-f0428bd0-1217-4a44-bab5-8f1bfeb2d883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505759904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3505759904
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3568284378
Short name T655
Test name
Test status
Simulation time 351614783 ps
CPU time 0.98 seconds
Started Jun 10 07:48:25 PM PDT 24
Finished Jun 10 07:48:31 PM PDT 24
Peak memory 205708 kb
Host smart-15ed3ab5-c7b9-483b-b6c5-2c27d8bddd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568284378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3568284378
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2939801585
Short name T694
Test name
Test status
Simulation time 107869693 ps
CPU time 2.35 seconds
Started Jun 10 07:48:23 PM PDT 24
Finished Jun 10 07:48:30 PM PDT 24
Peak memory 223584 kb
Host smart-1e225a46-6c61-4e79-bf35-c3d8d2626f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939801585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2939801585
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3811258857
Short name T938
Test name
Test status
Simulation time 39481061 ps
CPU time 0.73 seconds
Started Jun 10 07:48:20 PM PDT 24
Finished Jun 10 07:48:25 PM PDT 24
Peak memory 205296 kb
Host smart-dab516cb-060f-4442-a112-241e7d71fcf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811258857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3811258857
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1088793042
Short name T589
Test name
Test status
Simulation time 322768328 ps
CPU time 5.24 seconds
Started Jun 10 07:48:21 PM PDT 24
Finished Jun 10 07:48:31 PM PDT 24
Peak memory 224352 kb
Host smart-f8c7e105-e97f-4a7e-ae99-b118fd3ced95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088793042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1088793042
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2115935761
Short name T900
Test name
Test status
Simulation time 38026464 ps
CPU time 0.78 seconds
Started Jun 10 07:48:21 PM PDT 24
Finished Jun 10 07:48:27 PM PDT 24
Peak memory 206404 kb
Host smart-a8847b82-dc28-4cc2-a092-7d08dac9b0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115935761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2115935761
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.698016197
Short name T963
Test name
Test status
Simulation time 480041696 ps
CPU time 5.12 seconds
Started Jun 10 07:48:21 PM PDT 24
Finished Jun 10 07:48:31 PM PDT 24
Peak memory 232528 kb
Host smart-867f2d8a-fa87-4b13-862c-e6069e364591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698016197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.698016197
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1403567271
Short name T238
Test name
Test status
Simulation time 2284941214 ps
CPU time 38.94 seconds
Started Jun 10 07:48:23 PM PDT 24
Finished Jun 10 07:49:06 PM PDT 24
Peak memory 249096 kb
Host smart-2d5c060b-25c1-449b-945e-374e81181d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403567271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1403567271
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3801617695
Short name T62
Test name
Test status
Simulation time 44863932641 ps
CPU time 381.26 seconds
Started Jun 10 07:48:25 PM PDT 24
Finished Jun 10 07:54:51 PM PDT 24
Peak memory 256464 kb
Host smart-77ca7289-7a01-4eb4-a479-c8f49b0f3d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801617695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3801617695
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3992206287
Short name T324
Test name
Test status
Simulation time 8097930161 ps
CPU time 44.63 seconds
Started Jun 10 07:48:22 PM PDT 24
Finished Jun 10 07:49:11 PM PDT 24
Peak memory 240468 kb
Host smart-638a8b08-8d8e-41e7-b161-00367f4e68cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992206287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3992206287
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3455867065
Short name T388
Test name
Test status
Simulation time 34067262 ps
CPU time 2.34 seconds
Started Jun 10 07:48:22 PM PDT 24
Finished Jun 10 07:48:29 PM PDT 24
Peak memory 232312 kb
Host smart-995a4fdb-147b-432b-9786-3eda5b57dbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455867065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3455867065
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.863289943
Short name T962
Test name
Test status
Simulation time 1739668673 ps
CPU time 10.48 seconds
Started Jun 10 07:48:31 PM PDT 24
Finished Jun 10 07:48:46 PM PDT 24
Peak memory 224304 kb
Host smart-6420b88e-f1d2-419f-b580-05317395395d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863289943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.863289943
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.322418279
Short name T815
Test name
Test status
Simulation time 33465671 ps
CPU time 2.48 seconds
Started Jun 10 07:48:20 PM PDT 24
Finished Jun 10 07:48:26 PM PDT 24
Peak memory 232420 kb
Host smart-5c00f997-072c-4d77-8b21-c4b2decad681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322418279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.322418279
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2485960546
Short name T922
Test name
Test status
Simulation time 19477547107 ps
CPU time 14.19 seconds
Started Jun 10 07:48:23 PM PDT 24
Finished Jun 10 07:48:42 PM PDT 24
Peak memory 230592 kb
Host smart-832ecf04-22f2-40d3-9829-0edba793086f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485960546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2485960546
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.4242980197
Short name T896
Test name
Test status
Simulation time 2048648790 ps
CPU time 5.07 seconds
Started Jun 10 07:48:21 PM PDT 24
Finished Jun 10 07:48:31 PM PDT 24
Peak memory 222916 kb
Host smart-e04cf4d0-f358-4822-b444-09487ca55678
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4242980197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.4242980197
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.325671328
Short name T162
Test name
Test status
Simulation time 51032426 ps
CPU time 0.99 seconds
Started Jun 10 07:48:23 PM PDT 24
Finished Jun 10 07:48:29 PM PDT 24
Peak memory 206684 kb
Host smart-1d2ea436-7412-491d-94f4-50dfeb2f1811
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325671328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.325671328
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2094967397
Short name T798
Test name
Test status
Simulation time 841464638 ps
CPU time 5.36 seconds
Started Jun 10 07:48:25 PM PDT 24
Finished Jun 10 07:48:35 PM PDT 24
Peak memory 216080 kb
Host smart-063b1645-7e08-4940-b243-b3daadafe2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094967397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2094967397
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1656580748
Short name T368
Test name
Test status
Simulation time 783876435 ps
CPU time 4.28 seconds
Started Jun 10 07:48:27 PM PDT 24
Finished Jun 10 07:48:36 PM PDT 24
Peak memory 216012 kb
Host smart-c97cdb11-5747-490e-a6c0-60c403dabb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656580748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1656580748
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.968998311
Short name T169
Test name
Test status
Simulation time 34411035 ps
CPU time 1.16 seconds
Started Jun 10 07:48:21 PM PDT 24
Finished Jun 10 07:48:27 PM PDT 24
Peak memory 207500 kb
Host smart-9901dd79-3784-4648-9520-e34c68834a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968998311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.968998311
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3593487553
Short name T768
Test name
Test status
Simulation time 35136829 ps
CPU time 0.67 seconds
Started Jun 10 07:48:25 PM PDT 24
Finished Jun 10 07:48:30 PM PDT 24
Peak memory 205380 kb
Host smart-0e800ab2-60ed-4027-89e9-9b2c42dd479f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593487553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3593487553
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3732857229
Short name T485
Test name
Test status
Simulation time 6550936988 ps
CPU time 11.1 seconds
Started Jun 10 07:48:29 PM PDT 24
Finished Jun 10 07:48:45 PM PDT 24
Peak memory 224424 kb
Host smart-e2a6be11-fb92-4fd1-aa5e-1e2ad2b70e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732857229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3732857229
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1753907859
Short name T455
Test name
Test status
Simulation time 18192216 ps
CPU time 0.69 seconds
Started Jun 10 07:48:35 PM PDT 24
Finished Jun 10 07:48:41 PM PDT 24
Peak memory 205272 kb
Host smart-b3fe1e6a-3488-48a1-8bf7-2aa5cafa77d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753907859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1753907859
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2340473671
Short name T83
Test name
Test status
Simulation time 367863992 ps
CPU time 4.59 seconds
Started Jun 10 07:48:29 PM PDT 24
Finished Jun 10 07:48:38 PM PDT 24
Peak memory 232480 kb
Host smart-f91a5da0-72ae-451a-9892-85edc2199935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340473671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2340473671
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3652779906
Short name T610
Test name
Test status
Simulation time 73834280 ps
CPU time 0.76 seconds
Started Jun 10 07:48:25 PM PDT 24
Finished Jun 10 07:48:31 PM PDT 24
Peak memory 206372 kb
Host smart-eb192755-913c-4414-8cff-0db07603a1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652779906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3652779906
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2057738795
Short name T717
Test name
Test status
Simulation time 10743283712 ps
CPU time 55.04 seconds
Started Jun 10 07:48:27 PM PDT 24
Finished Jun 10 07:49:26 PM PDT 24
Peak memory 249668 kb
Host smart-b9c004cb-85dc-475b-9199-1723e52bee11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057738795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2057738795
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.4125378658
Short name T315
Test name
Test status
Simulation time 16082898963 ps
CPU time 80.47 seconds
Started Jun 10 07:48:32 PM PDT 24
Finished Jun 10 07:49:57 PM PDT 24
Peak memory 256252 kb
Host smart-c28d3141-62ed-47bb-904b-ad7ee3a7fdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125378658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.4125378658
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2411308279
Short name T331
Test name
Test status
Simulation time 8183077639 ps
CPU time 41.86 seconds
Started Jun 10 07:48:30 PM PDT 24
Finished Jun 10 07:49:16 PM PDT 24
Peak memory 217188 kb
Host smart-0d60dd35-538f-429a-a8da-d10157f9d583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411308279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2411308279
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2974598423
Short name T136
Test name
Test status
Simulation time 14310837827 ps
CPU time 38.51 seconds
Started Jun 10 07:48:21 PM PDT 24
Finished Jun 10 07:49:04 PM PDT 24
Peak memory 240872 kb
Host smart-bf7c37ec-4c47-457b-a2f5-e7150ed86ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974598423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2974598423
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2149287798
Short name T841
Test name
Test status
Simulation time 417314055 ps
CPU time 6.24 seconds
Started Jun 10 07:48:22 PM PDT 24
Finished Jun 10 07:48:33 PM PDT 24
Peak memory 232560 kb
Host smart-cabee0fb-ac97-416e-8d4b-78f74ae71905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149287798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2149287798
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3838987922
Short name T458
Test name
Test status
Simulation time 73548051 ps
CPU time 2.27 seconds
Started Jun 10 07:48:21 PM PDT 24
Finished Jun 10 07:48:28 PM PDT 24
Peak memory 222708 kb
Host smart-9936cc0c-56d2-4ffb-87d8-7b0d3291526f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838987922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3838987922
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2593529164
Short name T731
Test name
Test status
Simulation time 114773413 ps
CPU time 2.7 seconds
Started Jun 10 07:48:23 PM PDT 24
Finished Jun 10 07:48:30 PM PDT 24
Peak memory 232408 kb
Host smart-3dcd4518-20f9-4c1d-95f7-ae2885cd45d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593529164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2593529164
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.446640727
Short name T295
Test name
Test status
Simulation time 230286266 ps
CPU time 2.81 seconds
Started Jun 10 07:48:26 PM PDT 24
Finished Jun 10 07:48:33 PM PDT 24
Peak memory 232496 kb
Host smart-2a15911b-24f4-4075-a008-908176b9707a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446640727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.446640727
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3423190321
Short name T27
Test name
Test status
Simulation time 3742226376 ps
CPU time 7.68 seconds
Started Jun 10 07:48:21 PM PDT 24
Finished Jun 10 07:48:32 PM PDT 24
Peak memory 222680 kb
Host smart-d0a566b5-c349-4238-a7d9-5cae4169808c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3423190321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3423190321
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1641547123
Short name T597
Test name
Test status
Simulation time 158110902173 ps
CPU time 491.87 seconds
Started Jun 10 07:48:29 PM PDT 24
Finished Jun 10 07:56:46 PM PDT 24
Peak memory 273660 kb
Host smart-fde71e70-741d-4569-bc5a-be1d31d2a553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641547123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1641547123
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.312332790
Short name T839
Test name
Test status
Simulation time 4632341744 ps
CPU time 6.2 seconds
Started Jun 10 07:48:30 PM PDT 24
Finished Jun 10 07:48:40 PM PDT 24
Peak memory 216136 kb
Host smart-dfe418f4-5102-4f9f-b9b7-1780e9ceeca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312332790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.312332790
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4210208198
Short name T382
Test name
Test status
Simulation time 204129261 ps
CPU time 1.55 seconds
Started Jun 10 07:48:25 PM PDT 24
Finished Jun 10 07:48:31 PM PDT 24
Peak memory 207708 kb
Host smart-1dfc6a43-379f-44d1-9aec-f5c814dcaf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210208198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4210208198
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.266198324
Short name T628
Test name
Test status
Simulation time 1052259131 ps
CPU time 4.94 seconds
Started Jun 10 07:48:15 PM PDT 24
Finished Jun 10 07:48:21 PM PDT 24
Peak memory 216036 kb
Host smart-7af32f47-a2c7-49e4-b505-83ab4c12a6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266198324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.266198324
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.4125966395
Short name T367
Test name
Test status
Simulation time 28275872 ps
CPU time 0.82 seconds
Started Jun 10 07:48:24 PM PDT 24
Finished Jun 10 07:48:30 PM PDT 24
Peak memory 205660 kb
Host smart-1b9e3d3a-fb97-4665-9faa-2aca8e34ee9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125966395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.4125966395
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2424140567
Short name T248
Test name
Test status
Simulation time 8550271862 ps
CPU time 28.78 seconds
Started Jun 10 07:48:24 PM PDT 24
Finished Jun 10 07:48:57 PM PDT 24
Peak memory 224516 kb
Host smart-c3fe1af7-c656-48ec-a9d3-6b0c81b6e086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424140567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2424140567
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3986114773
Short name T532
Test name
Test status
Simulation time 12923638 ps
CPU time 0.73 seconds
Started Jun 10 07:48:28 PM PDT 24
Finished Jun 10 07:48:33 PM PDT 24
Peak memory 205604 kb
Host smart-11e938ef-03a8-400f-9df4-e06481f6f083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986114773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3986114773
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.374933968
Short name T461
Test name
Test status
Simulation time 250785636 ps
CPU time 2.95 seconds
Started Jun 10 07:48:30 PM PDT 24
Finished Jun 10 07:48:37 PM PDT 24
Peak memory 232628 kb
Host smart-b7d07d59-209d-45dd-932e-4ce106358220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374933968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.374933968
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2399160265
Short name T596
Test name
Test status
Simulation time 19293085 ps
CPU time 0.78 seconds
Started Jun 10 07:48:34 PM PDT 24
Finished Jun 10 07:48:39 PM PDT 24
Peak memory 206772 kb
Host smart-003c5f6b-9ffb-4684-9238-372ec0fc3e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399160265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2399160265
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1817075828
Short name T237
Test name
Test status
Simulation time 159623621881 ps
CPU time 124.84 seconds
Started Jun 10 07:48:30 PM PDT 24
Finished Jun 10 07:50:39 PM PDT 24
Peak memory 249096 kb
Host smart-cfab56da-23d3-4a21-8b9c-8ec11b7c38f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817075828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1817075828
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3662678835
Short name T10
Test name
Test status
Simulation time 15311815942 ps
CPU time 88.58 seconds
Started Jun 10 07:48:37 PM PDT 24
Finished Jun 10 07:50:10 PM PDT 24
Peak memory 256144 kb
Host smart-9c8a7a16-4a3c-42a2-affe-cbc3eea1108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662678835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3662678835
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.4034625029
Short name T12
Test name
Test status
Simulation time 1237233176 ps
CPU time 8.19 seconds
Started Jun 10 07:48:35 PM PDT 24
Finished Jun 10 07:48:48 PM PDT 24
Peak memory 248128 kb
Host smart-2e7dda75-9a2d-43ef-97d1-d93469b64b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034625029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4034625029
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2758485944
Short name T227
Test name
Test status
Simulation time 12276937063 ps
CPU time 22.27 seconds
Started Jun 10 07:48:33 PM PDT 24
Finished Jun 10 07:49:00 PM PDT 24
Peak memory 224340 kb
Host smart-84c3647c-74b3-4b58-aa0e-fa8487cbb703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758485944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2758485944
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.4171466003
Short name T541
Test name
Test status
Simulation time 26355516722 ps
CPU time 61.15 seconds
Started Jun 10 07:48:30 PM PDT 24
Finished Jun 10 07:49:36 PM PDT 24
Peak memory 248992 kb
Host smart-53a3a89a-cf2f-4358-b729-9c92e32e4200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171466003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.4171466003
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3949625569
Short name T463
Test name
Test status
Simulation time 1120018056 ps
CPU time 3.28 seconds
Started Jun 10 07:48:30 PM PDT 24
Finished Jun 10 07:48:38 PM PDT 24
Peak memory 224316 kb
Host smart-e958d423-e502-4abb-84b1-8147a4a6e63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949625569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3949625569
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.857201361
Short name T130
Test name
Test status
Simulation time 313024187 ps
CPU time 5.48 seconds
Started Jun 10 07:48:30 PM PDT 24
Finished Jun 10 07:48:40 PM PDT 24
Peak memory 221180 kb
Host smart-2dadaf3a-9e6b-4531-91c8-f28651eaf866
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=857201361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.857201361
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.196253845
Short name T151
Test name
Test status
Simulation time 66608484 ps
CPU time 1.21 seconds
Started Jun 10 07:48:31 PM PDT 24
Finished Jun 10 07:48:37 PM PDT 24
Peak memory 206880 kb
Host smart-f7fc91a0-d479-4bf8-b03e-619624e261e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196253845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.196253845
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3340168976
Short name T732
Test name
Test status
Simulation time 974802912 ps
CPU time 8.2 seconds
Started Jun 10 07:48:33 PM PDT 24
Finished Jun 10 07:48:46 PM PDT 24
Peak memory 216056 kb
Host smart-b4865fc3-a5cc-42be-9d34-986ee0ec6b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340168976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3340168976
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2984373601
Short name T443
Test name
Test status
Simulation time 26377304655 ps
CPU time 18.06 seconds
Started Jun 10 07:48:34 PM PDT 24
Finished Jun 10 07:48:57 PM PDT 24
Peak memory 216196 kb
Host smart-32b615f5-c516-420c-8f03-4a53888edbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984373601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2984373601
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1953157586
Short name T427
Test name
Test status
Simulation time 15636784 ps
CPU time 0.79 seconds
Started Jun 10 07:48:33 PM PDT 24
Finished Jun 10 07:48:39 PM PDT 24
Peak memory 205708 kb
Host smart-bc395aba-19f7-4016-8aae-90c8b0ec6255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953157586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1953157586
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1559379635
Short name T344
Test name
Test status
Simulation time 84351819 ps
CPU time 0.78 seconds
Started Jun 10 07:48:36 PM PDT 24
Finished Jun 10 07:48:41 PM PDT 24
Peak memory 205668 kb
Host smart-ec575d4e-6a8c-43a6-93ae-be1ab7c89a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559379635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1559379635
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1921798970
Short name T835
Test name
Test status
Simulation time 1260361845 ps
CPU time 5.44 seconds
Started Jun 10 07:48:30 PM PDT 24
Finished Jun 10 07:48:40 PM PDT 24
Peak memory 232520 kb
Host smart-360a18c3-e0b1-419c-860f-895c711e0d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921798970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1921798970
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2102622473
Short name T972
Test name
Test status
Simulation time 38869507 ps
CPU time 0.74 seconds
Started Jun 10 07:48:28 PM PDT 24
Finished Jun 10 07:48:33 PM PDT 24
Peak memory 204740 kb
Host smart-8de79ab1-8ef2-487d-83ab-39b7dd92631f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102622473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2102622473
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3301226871
Short name T706
Test name
Test status
Simulation time 11696467183 ps
CPU time 25.89 seconds
Started Jun 10 07:48:35 PM PDT 24
Finished Jun 10 07:49:06 PM PDT 24
Peak memory 232676 kb
Host smart-b6b36bb7-4239-49f7-9d60-ce124f64dbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301226871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3301226871
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2996970828
Short name T821
Test name
Test status
Simulation time 19314263 ps
CPU time 0.75 seconds
Started Jun 10 07:48:35 PM PDT 24
Finished Jun 10 07:48:41 PM PDT 24
Peak memory 205648 kb
Host smart-fbc65d6a-a507-4297-8a8d-e810f0a22746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996970828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2996970828
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2815601973
Short name T208
Test name
Test status
Simulation time 213252937905 ps
CPU time 387.75 seconds
Started Jun 10 07:48:31 PM PDT 24
Finished Jun 10 07:55:03 PM PDT 24
Peak memory 257212 kb
Host smart-54e24769-a3ca-4525-a617-250d30ef710c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815601973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2815601973
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1693700855
Short name T186
Test name
Test status
Simulation time 7838474805 ps
CPU time 127.85 seconds
Started Jun 10 07:48:33 PM PDT 24
Finished Jun 10 07:50:45 PM PDT 24
Peak memory 249108 kb
Host smart-b784b1be-e295-4c5d-a5db-5a9ec8789c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693700855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1693700855
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2000516189
Short name T193
Test name
Test status
Simulation time 36164429471 ps
CPU time 192.1 seconds
Started Jun 10 07:48:32 PM PDT 24
Finished Jun 10 07:51:49 PM PDT 24
Peak memory 256588 kb
Host smart-0899abcf-98e9-452c-b2e2-db13d91218b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000516189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2000516189
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.729427846
Short name T495
Test name
Test status
Simulation time 906602471 ps
CPU time 11.44 seconds
Started Jun 10 07:48:28 PM PDT 24
Finished Jun 10 07:48:44 PM PDT 24
Peak memory 237696 kb
Host smart-8f3121c8-b593-48f7-9980-87b09c268a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729427846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.729427846
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.627831813
Short name T659
Test name
Test status
Simulation time 274109932 ps
CPU time 4.34 seconds
Started Jun 10 07:48:28 PM PDT 24
Finished Jun 10 07:48:37 PM PDT 24
Peak memory 224316 kb
Host smart-4d176917-8a56-4b89-b8f9-f5a2bada1381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627831813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.627831813
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1750672778
Short name T742
Test name
Test status
Simulation time 2635721566 ps
CPU time 7.72 seconds
Started Jun 10 07:48:30 PM PDT 24
Finished Jun 10 07:48:42 PM PDT 24
Peak memory 224444 kb
Host smart-c5d0e956-af3a-471d-90a1-2c8db2422984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750672778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1750672778
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3408542476
Short name T274
Test name
Test status
Simulation time 7519348721 ps
CPU time 19.76 seconds
Started Jun 10 07:48:33 PM PDT 24
Finished Jun 10 07:48:58 PM PDT 24
Peak memory 240652 kb
Host smart-47c2756a-740f-4c64-b082-b017ce18de3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408542476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3408542476
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2012820940
Short name T259
Test name
Test status
Simulation time 12888948301 ps
CPU time 5.96 seconds
Started Jun 10 07:48:29 PM PDT 24
Finished Jun 10 07:48:39 PM PDT 24
Peak memory 224468 kb
Host smart-925aa8db-da9d-491c-a214-3790b6d703d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012820940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2012820940
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3031010498
Short name T131
Test name
Test status
Simulation time 909783344 ps
CPU time 4.18 seconds
Started Jun 10 07:48:35 PM PDT 24
Finished Jun 10 07:48:44 PM PDT 24
Peak memory 219760 kb
Host smart-c3e1388e-aaa6-4a14-b04c-8fa34069b64a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3031010498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3031010498
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.777136488
Short name T163
Test name
Test status
Simulation time 44752664 ps
CPU time 1.07 seconds
Started Jun 10 07:48:29 PM PDT 24
Finished Jun 10 07:48:34 PM PDT 24
Peak memory 206720 kb
Host smart-eeb1c6bf-6c08-4db0-91fd-1ea6b01431fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777136488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.777136488
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3060234253
Short name T875
Test name
Test status
Simulation time 6182786998 ps
CPU time 26.36 seconds
Started Jun 10 07:48:29 PM PDT 24
Finished Jun 10 07:49:00 PM PDT 24
Peak memory 219552 kb
Host smart-30898422-f8c7-436b-b603-9eda860b88cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060234253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3060234253
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.395172638
Short name T634
Test name
Test status
Simulation time 964212571 ps
CPU time 6.62 seconds
Started Jun 10 07:48:30 PM PDT 24
Finished Jun 10 07:48:41 PM PDT 24
Peak memory 215972 kb
Host smart-fe66b3d8-0bc4-4b7e-b161-04ebacfcc9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395172638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.395172638
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.962049536
Short name T438
Test name
Test status
Simulation time 13861148 ps
CPU time 0.75 seconds
Started Jun 10 07:48:30 PM PDT 24
Finished Jun 10 07:48:36 PM PDT 24
Peak memory 205668 kb
Host smart-bb90410c-968e-4f85-bc29-05936443c8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962049536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.962049536
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.525990063
Short name T762
Test name
Test status
Simulation time 107829093 ps
CPU time 0.78 seconds
Started Jun 10 07:48:31 PM PDT 24
Finished Jun 10 07:48:37 PM PDT 24
Peak memory 205680 kb
Host smart-374fb5c9-58b3-4b23-b5fd-abdedb455695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525990063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.525990063
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.437312424
Short name T525
Test name
Test status
Simulation time 311126394 ps
CPU time 3.7 seconds
Started Jun 10 07:48:29 PM PDT 24
Finished Jun 10 07:48:38 PM PDT 24
Peak memory 240492 kb
Host smart-94bc27bf-6602-4d4b-b3a8-67ade47aa698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437312424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.437312424
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1997857732
Short name T747
Test name
Test status
Simulation time 15718959 ps
CPU time 0.72 seconds
Started Jun 10 07:48:37 PM PDT 24
Finished Jun 10 07:48:42 PM PDT 24
Peak memory 204816 kb
Host smart-4a5ee08d-0c3e-4690-bd7d-04ea61b0d38d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997857732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1997857732
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3463362023
Short name T387
Test name
Test status
Simulation time 175120394 ps
CPU time 3.07 seconds
Started Jun 10 07:48:34 PM PDT 24
Finished Jun 10 07:48:42 PM PDT 24
Peak memory 232500 kb
Host smart-8f6568cd-bad8-4b87-98f9-fe28a906483e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463362023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3463362023
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.659883133
Short name T393
Test name
Test status
Simulation time 56663136 ps
CPU time 0.75 seconds
Started Jun 10 07:48:34 PM PDT 24
Finished Jun 10 07:48:40 PM PDT 24
Peak memory 206344 kb
Host smart-cc189c3f-b034-47b5-97f5-1d1aa3b78984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659883133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.659883133
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2641676958
Short name T444
Test name
Test status
Simulation time 3326287598 ps
CPU time 18.8 seconds
Started Jun 10 07:48:34 PM PDT 24
Finished Jun 10 07:48:57 PM PDT 24
Peak memory 240468 kb
Host smart-4f8d00ca-462a-4703-9454-3ba312b14e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641676958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2641676958
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2143291122
Short name T230
Test name
Test status
Simulation time 3466808696 ps
CPU time 66.88 seconds
Started Jun 10 07:48:33 PM PDT 24
Finished Jun 10 07:49:45 PM PDT 24
Peak memory 249828 kb
Host smart-b37832f7-4af4-483f-b7ba-8efa1d468849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143291122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2143291122
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1972399731
Short name T316
Test name
Test status
Simulation time 38485352738 ps
CPU time 157.75 seconds
Started Jun 10 07:48:30 PM PDT 24
Finished Jun 10 07:51:12 PM PDT 24
Peak memory 269952 kb
Host smart-fcd8fe8a-4813-468c-b502-d7997c7f0057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972399731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1972399731
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2146681636
Short name T549
Test name
Test status
Simulation time 2280508848 ps
CPU time 18.14 seconds
Started Jun 10 07:48:40 PM PDT 24
Finished Jun 10 07:49:02 PM PDT 24
Peak memory 235812 kb
Host smart-bcc56789-144e-4e40-bdc3-c41f557551a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146681636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2146681636
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.40154537
Short name T671
Test name
Test status
Simulation time 1870538233 ps
CPU time 7.43 seconds
Started Jun 10 07:48:27 PM PDT 24
Finished Jun 10 07:48:39 PM PDT 24
Peak memory 232564 kb
Host smart-86f8c798-6387-4f9a-8527-a8074a11e8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40154537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.40154537
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.4250495003
Short name T338
Test name
Test status
Simulation time 6986673695 ps
CPU time 20.24 seconds
Started Jun 10 07:48:33 PM PDT 24
Finished Jun 10 07:48:58 PM PDT 24
Peak memory 240652 kb
Host smart-a293bc51-5a85-4e6f-9e50-c362045d1558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250495003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.4250495003
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.627224819
Short name T556
Test name
Test status
Simulation time 7075794400 ps
CPU time 9.84 seconds
Started Jun 10 07:48:34 PM PDT 24
Finished Jun 10 07:48:49 PM PDT 24
Peak memory 240048 kb
Host smart-748727c6-7c86-4dad-a423-322623833d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627224819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.627224819
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1635115874
Short name T447
Test name
Test status
Simulation time 6005635789 ps
CPU time 14.52 seconds
Started Jun 10 07:48:33 PM PDT 24
Finished Jun 10 07:48:52 PM PDT 24
Peak memory 224404 kb
Host smart-d2fa2aeb-c01e-4097-a5a4-18375780fc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635115874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1635115874
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.637957477
Short name T679
Test name
Test status
Simulation time 439818159 ps
CPU time 6.1 seconds
Started Jun 10 07:48:34 PM PDT 24
Finished Jun 10 07:48:45 PM PDT 24
Peak memory 218680 kb
Host smart-a89674b6-0bf0-4543-a8e6-a6fa7f9c5134
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=637957477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.637957477
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2463720526
Short name T853
Test name
Test status
Simulation time 17423330498 ps
CPU time 16.58 seconds
Started Jun 10 07:48:34 PM PDT 24
Finished Jun 10 07:48:55 PM PDT 24
Peak memory 217424 kb
Host smart-c463c674-69da-4508-8258-4eb68db6529e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463720526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2463720526
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.872377290
Short name T394
Test name
Test status
Simulation time 2096376207 ps
CPU time 5.53 seconds
Started Jun 10 07:48:33 PM PDT 24
Finished Jun 10 07:48:44 PM PDT 24
Peak memory 216012 kb
Host smart-8c4e1356-75e4-4733-830b-c27812bdce8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872377290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.872377290
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2295995472
Short name T432
Test name
Test status
Simulation time 49408875 ps
CPU time 1.08 seconds
Started Jun 10 07:48:31 PM PDT 24
Finished Jun 10 07:48:37 PM PDT 24
Peak memory 207016 kb
Host smart-ffcfe216-1382-4b41-9f5a-0dc2c94b1cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295995472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2295995472
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1586768983
Short name T733
Test name
Test status
Simulation time 66660959 ps
CPU time 0.76 seconds
Started Jun 10 07:48:36 PM PDT 24
Finished Jun 10 07:48:41 PM PDT 24
Peak memory 205700 kb
Host smart-fe8ddd28-7dc0-49be-89e6-db79bbec46ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586768983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1586768983
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3906855804
Short name T912
Test name
Test status
Simulation time 359754813 ps
CPU time 3.53 seconds
Started Jun 10 07:48:34 PM PDT 24
Finished Jun 10 07:48:42 PM PDT 24
Peak memory 232508 kb
Host smart-2e79097d-a64e-4259-96d8-1fe6115bffd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906855804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3906855804
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1622202040
Short name T553
Test name
Test status
Simulation time 13337123 ps
CPU time 0.72 seconds
Started Jun 10 07:48:32 PM PDT 24
Finished Jun 10 07:48:37 PM PDT 24
Peak memory 205608 kb
Host smart-2178ed11-8b10-419e-a000-a08bcfe1f840
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622202040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1622202040
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.786208092
Short name T690
Test name
Test status
Simulation time 571809064 ps
CPU time 5.33 seconds
Started Jun 10 07:48:34 PM PDT 24
Finished Jun 10 07:48:44 PM PDT 24
Peak memory 232564 kb
Host smart-11c8e450-781c-43db-890b-463167c454d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786208092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.786208092
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3416494494
Short name T460
Test name
Test status
Simulation time 50269419 ps
CPU time 0.73 seconds
Started Jun 10 07:48:30 PM PDT 24
Finished Jun 10 07:48:35 PM PDT 24
Peak memory 205364 kb
Host smart-57828bb5-6075-435d-a6f2-ca06c3a32060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416494494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3416494494
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.732403272
Short name T734
Test name
Test status
Simulation time 13595839339 ps
CPU time 126.19 seconds
Started Jun 10 07:48:33 PM PDT 24
Finished Jun 10 07:50:44 PM PDT 24
Peak memory 249068 kb
Host smart-99fa2f03-d4b8-4cdf-bee2-a924ac0013b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732403272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.732403272
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1979273702
Short name T502
Test name
Test status
Simulation time 7121063999 ps
CPU time 27.02 seconds
Started Jun 10 07:48:39 PM PDT 24
Finished Jun 10 07:49:10 PM PDT 24
Peak memory 239116 kb
Host smart-4105d643-f614-4771-9f0e-6c7660537953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979273702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1979273702
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.662244518
Short name T189
Test name
Test status
Simulation time 19162153905 ps
CPU time 187.69 seconds
Started Jun 10 07:48:34 PM PDT 24
Finished Jun 10 07:51:47 PM PDT 24
Peak memory 254180 kb
Host smart-093883c5-598f-4bb0-8a16-ca358c1af086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662244518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.662244518
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2436842882
Short name T365
Test name
Test status
Simulation time 375981440 ps
CPU time 2.52 seconds
Started Jun 10 07:48:39 PM PDT 24
Finished Jun 10 07:48:46 PM PDT 24
Peak memory 224324 kb
Host smart-a6451aae-efde-4e3d-9470-f72fd2751a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436842882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2436842882
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.13447299
Short name T203
Test name
Test status
Simulation time 2416103624 ps
CPU time 25.07 seconds
Started Jun 10 07:48:29 PM PDT 24
Finished Jun 10 07:48:58 PM PDT 24
Peak memory 232636 kb
Host smart-ac4fa226-e490-4da1-bdd3-65d3c6e1a17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13447299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.13447299
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1975376054
Short name T512
Test name
Test status
Simulation time 6911221458 ps
CPU time 15.59 seconds
Started Jun 10 07:48:34 PM PDT 24
Finished Jun 10 07:48:55 PM PDT 24
Peak memory 232600 kb
Host smart-0496ff6e-98cf-4f46-9ac3-3a4ca8e0c5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975376054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1975376054
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2304856089
Short name T825
Test name
Test status
Simulation time 4086030981 ps
CPU time 9.15 seconds
Started Jun 10 07:48:38 PM PDT 24
Finished Jun 10 07:48:51 PM PDT 24
Peak memory 224404 kb
Host smart-25e25ef0-0eb2-4a33-a1f2-55149e0e3b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304856089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2304856089
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3442171694
Short name T245
Test name
Test status
Simulation time 829087999 ps
CPU time 4.52 seconds
Started Jun 10 07:48:37 PM PDT 24
Finished Jun 10 07:48:46 PM PDT 24
Peak memory 232528 kb
Host smart-efce79f6-80d9-4132-854e-5bce1031797e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442171694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3442171694
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1643579999
Short name T132
Test name
Test status
Simulation time 115377718 ps
CPU time 4.01 seconds
Started Jun 10 07:48:33 PM PDT 24
Finished Jun 10 07:48:42 PM PDT 24
Peak memory 222648 kb
Host smart-8f05b1be-b049-4a10-ad1e-e480ee05c73f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1643579999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1643579999
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1324269233
Short name T53
Test name
Test status
Simulation time 305765288681 ps
CPU time 287.13 seconds
Started Jun 10 07:48:32 PM PDT 24
Finished Jun 10 07:53:24 PM PDT 24
Peak memory 252512 kb
Host smart-00195b8f-9ced-4eda-99c5-1ab529f07574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324269233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1324269233
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3747958991
Short name T935
Test name
Test status
Simulation time 3771436223 ps
CPU time 25.66 seconds
Started Jun 10 07:48:35 PM PDT 24
Finished Jun 10 07:49:06 PM PDT 24
Peak memory 216240 kb
Host smart-7a5cbc68-770c-498e-b0fc-c4cc4b5e4526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747958991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3747958991
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2431954140
Short name T29
Test name
Test status
Simulation time 41428665134 ps
CPU time 28.53 seconds
Started Jun 10 07:48:36 PM PDT 24
Finished Jun 10 07:49:09 PM PDT 24
Peak memory 216124 kb
Host smart-f1d9fe46-839f-48bd-9c4c-a01697462021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431954140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2431954140
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.285225843
Short name T629
Test name
Test status
Simulation time 842876592 ps
CPU time 2.24 seconds
Started Jun 10 07:48:36 PM PDT 24
Finished Jun 10 07:48:43 PM PDT 24
Peak memory 216112 kb
Host smart-ebe58da1-d99e-4eea-9cbf-1baad5456648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285225843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.285225843
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.256948656
Short name T353
Test name
Test status
Simulation time 35783171 ps
CPU time 0.72 seconds
Started Jun 10 07:48:38 PM PDT 24
Finished Jun 10 07:48:43 PM PDT 24
Peak memory 205712 kb
Host smart-ce773c10-96b7-4a55-8132-6f76823185d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256948656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.256948656
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1726833615
Short name T241
Test name
Test status
Simulation time 8258185984 ps
CPU time 15.96 seconds
Started Jun 10 07:48:48 PM PDT 24
Finished Jun 10 07:49:07 PM PDT 24
Peak memory 240228 kb
Host smart-5be13be0-0b62-4937-91a7-0ca78988c593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726833615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1726833615
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.4002772089
Short name T480
Test name
Test status
Simulation time 13003746 ps
CPU time 0.69 seconds
Started Jun 10 07:48:39 PM PDT 24
Finished Jun 10 07:48:44 PM PDT 24
Peak memory 204680 kb
Host smart-741fde80-0aa8-464f-b2a3-471b37d7d3cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002772089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
4002772089
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2944678380
Short name T901
Test name
Test status
Simulation time 503620735 ps
CPU time 3.25 seconds
Started Jun 10 07:48:38 PM PDT 24
Finished Jun 10 07:48:45 PM PDT 24
Peak memory 224348 kb
Host smart-6f3907f0-109f-4c2d-bb10-f6a505ab1fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944678380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2944678380
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2072358734
Short name T28
Test name
Test status
Simulation time 21850558 ps
CPU time 0.76 seconds
Started Jun 10 07:48:36 PM PDT 24
Finished Jun 10 07:48:41 PM PDT 24
Peak memory 206804 kb
Host smart-101d8bf5-b997-4008-b306-f9aeab828bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072358734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2072358734
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.133722033
Short name T314
Test name
Test status
Simulation time 80349997771 ps
CPU time 109.48 seconds
Started Jun 10 07:48:38 PM PDT 24
Finished Jun 10 07:50:32 PM PDT 24
Peak memory 251564 kb
Host smart-fcc2832e-eac9-452c-8da2-7abcbc42bcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133722033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.133722033
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2636794675
Short name T642
Test name
Test status
Simulation time 40661221530 ps
CPU time 358.69 seconds
Started Jun 10 07:48:37 PM PDT 24
Finished Jun 10 07:54:41 PM PDT 24
Peak memory 250612 kb
Host smart-cbca2232-7989-49e2-9bbe-9e7acb598e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636794675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2636794675
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.4031564280
Short name T340
Test name
Test status
Simulation time 933010666 ps
CPU time 6.69 seconds
Started Jun 10 07:48:41 PM PDT 24
Finished Jun 10 07:48:51 PM PDT 24
Peak memory 240708 kb
Host smart-71f77fdd-73e0-4089-b362-ce3d54fafdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031564280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.4031564280
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.225570710
Short name T780
Test name
Test status
Simulation time 269561961 ps
CPU time 5.1 seconds
Started Jun 10 07:48:36 PM PDT 24
Finished Jun 10 07:48:45 PM PDT 24
Peak memory 232524 kb
Host smart-173f7807-76cd-4c6e-b7b8-1001d3d5154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225570710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.225570710
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2853331478
Short name T253
Test name
Test status
Simulation time 52792881 ps
CPU time 2.82 seconds
Started Jun 10 07:48:38 PM PDT 24
Finished Jun 10 07:48:46 PM PDT 24
Peak memory 232504 kb
Host smart-bdb2afc5-b38a-456c-bc09-6eff1cc66a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853331478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2853331478
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1178781557
Short name T191
Test name
Test status
Simulation time 123415379 ps
CPU time 3.4 seconds
Started Jun 10 07:48:38 PM PDT 24
Finished Jun 10 07:48:46 PM PDT 24
Peak memory 232500 kb
Host smart-09477fbc-cbf2-4a85-adeb-0286d287e3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178781557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1178781557
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3997155260
Short name T244
Test name
Test status
Simulation time 2618778578 ps
CPU time 7.09 seconds
Started Jun 10 07:48:37 PM PDT 24
Finished Jun 10 07:48:49 PM PDT 24
Peak memory 232776 kb
Host smart-c10d657f-4bd9-4173-8f48-60ae843679b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997155260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3997155260
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.971972002
Short name T693
Test name
Test status
Simulation time 96608143 ps
CPU time 3.56 seconds
Started Jun 10 07:48:37 PM PDT 24
Finished Jun 10 07:48:46 PM PDT 24
Peak memory 219872 kb
Host smart-9a0f6df5-729b-49a6-98f4-14e7036f1217
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=971972002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.971972002
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1819258929
Short name T310
Test name
Test status
Simulation time 170319585855 ps
CPU time 339.97 seconds
Started Jun 10 07:48:41 PM PDT 24
Finished Jun 10 07:54:25 PM PDT 24
Peak memory 257316 kb
Host smart-31ca97f1-05a2-425d-88b6-7f2eed815ca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819258929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1819258929
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.4178381227
Short name T969
Test name
Test status
Simulation time 599625829 ps
CPU time 4.09 seconds
Started Jun 10 07:48:30 PM PDT 24
Finished Jun 10 07:48:39 PM PDT 24
Peak memory 216056 kb
Host smart-7878b1dd-5cb2-4705-adc6-d94c9ad9c158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178381227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4178381227
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2490466244
Short name T863
Test name
Test status
Simulation time 8527119372 ps
CPU time 21.08 seconds
Started Jun 10 07:48:36 PM PDT 24
Finished Jun 10 07:49:02 PM PDT 24
Peak memory 216284 kb
Host smart-2d609fe3-599e-4817-9ca3-4fc77d10cb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490466244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2490466244
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.175697110
Short name T678
Test name
Test status
Simulation time 48769884 ps
CPU time 1.12 seconds
Started Jun 10 07:48:37 PM PDT 24
Finished Jun 10 07:48:43 PM PDT 24
Peak memory 207484 kb
Host smart-d323d381-8304-40eb-aac6-c9b960366c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175697110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.175697110
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.4022808969
Short name T802
Test name
Test status
Simulation time 430251315 ps
CPU time 1.06 seconds
Started Jun 10 07:48:37 PM PDT 24
Finished Jun 10 07:48:43 PM PDT 24
Peak memory 205932 kb
Host smart-6b82c787-198d-4768-98d8-4795a52ed96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022808969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.4022808969
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2405314719
Short name T492
Test name
Test status
Simulation time 73652217165 ps
CPU time 24.91 seconds
Started Jun 10 07:48:48 PM PDT 24
Finished Jun 10 07:49:17 PM PDT 24
Peak memory 224184 kb
Host smart-e9316593-a023-470d-ba97-0ceb9aa03433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405314719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2405314719
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.676502487
Short name T1
Test name
Test status
Simulation time 13768908 ps
CPU time 0.73 seconds
Started Jun 10 07:47:33 PM PDT 24
Finished Jun 10 07:47:38 PM PDT 24
Peak memory 205656 kb
Host smart-85357d52-b034-4684-a3e1-e7697bfcedf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676502487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.676502487
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2999583922
Short name T139
Test name
Test status
Simulation time 474251452 ps
CPU time 4.71 seconds
Started Jun 10 07:47:23 PM PDT 24
Finished Jun 10 07:47:31 PM PDT 24
Peak memory 232496 kb
Host smart-a309fe0c-d016-4162-92d8-fab2bbd4db1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999583922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2999583922
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2286584198
Short name T977
Test name
Test status
Simulation time 70649473 ps
CPU time 0.77 seconds
Started Jun 10 07:47:27 PM PDT 24
Finished Jun 10 07:47:30 PM PDT 24
Peak memory 206344 kb
Host smart-902e9573-a5f2-42cb-afba-830f17a17564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286584198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2286584198
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1934706138
Short name T72
Test name
Test status
Simulation time 116861313920 ps
CPU time 196.75 seconds
Started Jun 10 07:47:24 PM PDT 24
Finished Jun 10 07:50:43 PM PDT 24
Peak memory 254120 kb
Host smart-73c695d0-c18c-4df8-9920-107125bc96cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934706138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1934706138
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3959836020
Short name T847
Test name
Test status
Simulation time 120164835396 ps
CPU time 220.68 seconds
Started Jun 10 07:47:31 PM PDT 24
Finished Jun 10 07:51:16 PM PDT 24
Peak memory 249252 kb
Host smart-13949d8c-e97c-475d-abb6-9a2fbd67b4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959836020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3959836020
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.4101331415
Short name T231
Test name
Test status
Simulation time 8251773586 ps
CPU time 47.6 seconds
Started Jun 10 07:47:31 PM PDT 24
Finished Jun 10 07:48:23 PM PDT 24
Peak memory 249004 kb
Host smart-3f015927-aff7-40a7-951f-0176c72a63e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101331415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.4101331415
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2539279198
Short name T327
Test name
Test status
Simulation time 11114236055 ps
CPU time 48.79 seconds
Started Jun 10 07:47:33 PM PDT 24
Finished Jun 10 07:48:26 PM PDT 24
Peak memory 233632 kb
Host smart-9e6952b7-8b27-47df-b5f8-849b87b73c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539279198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2539279198
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1796232341
Short name T414
Test name
Test status
Simulation time 1838820702 ps
CPU time 14.8 seconds
Started Jun 10 07:47:25 PM PDT 24
Finished Jun 10 07:47:41 PM PDT 24
Peak memory 224284 kb
Host smart-8ed41aac-6fe1-4563-bada-a82dec748e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796232341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1796232341
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.120204020
Short name T391
Test name
Test status
Simulation time 51838681 ps
CPU time 2 seconds
Started Jun 10 07:47:22 PM PDT 24
Finished Jun 10 07:47:26 PM PDT 24
Peak memory 222656 kb
Host smart-89a49f42-1641-44c1-a9d3-c93b09999317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120204020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.120204020
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2885665302
Short name T39
Test name
Test status
Simulation time 31660469 ps
CPU time 1.03 seconds
Started Jun 10 07:47:28 PM PDT 24
Finished Jun 10 07:47:31 PM PDT 24
Peak memory 216480 kb
Host smart-ce94b7e0-4046-470d-a142-e99a2527b89b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885665302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2885665302
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.209540143
Short name T565
Test name
Test status
Simulation time 388961050 ps
CPU time 5.87 seconds
Started Jun 10 07:47:23 PM PDT 24
Finished Jun 10 07:47:31 PM PDT 24
Peak memory 232484 kb
Host smart-1393913b-814a-477d-aaf3-34fb32516745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209540143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
209540143
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3722817912
Short name T246
Test name
Test status
Simulation time 3116155660 ps
CPU time 10.49 seconds
Started Jun 10 07:47:32 PM PDT 24
Finished Jun 10 07:47:47 PM PDT 24
Peak memory 232620 kb
Host smart-a1228564-c987-4f81-9f51-bee1274cb49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722817912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3722817912
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2231746607
Short name T526
Test name
Test status
Simulation time 1892244723 ps
CPU time 18.55 seconds
Started Jun 10 07:47:29 PM PDT 24
Finished Jun 10 07:47:51 PM PDT 24
Peak memory 218428 kb
Host smart-44183718-60bb-4971-8168-73ab0a3a387f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2231746607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2231746607
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3737633458
Short name T58
Test name
Test status
Simulation time 621117858 ps
CPU time 1.54 seconds
Started Jun 10 07:47:25 PM PDT 24
Finished Jun 10 07:47:28 PM PDT 24
Peak memory 235436 kb
Host smart-5b452370-f778-4205-8fc3-60e3addec507
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737633458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3737633458
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1388660273
Short name T656
Test name
Test status
Simulation time 17552250610 ps
CPU time 30.44 seconds
Started Jun 10 07:47:22 PM PDT 24
Finished Jun 10 07:47:54 PM PDT 24
Peak memory 216172 kb
Host smart-4a75331c-9865-482f-bbe3-cd1bde64c7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388660273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1388660273
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.302140051
Short name T354
Test name
Test status
Simulation time 1190120215 ps
CPU time 1.56 seconds
Started Jun 10 07:47:31 PM PDT 24
Finished Jun 10 07:47:36 PM PDT 24
Peak memory 207580 kb
Host smart-972ec5a0-ec80-4e58-b8b6-4ba31b933abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302140051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.302140051
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2795128293
Short name T530
Test name
Test status
Simulation time 1013932596 ps
CPU time 2.26 seconds
Started Jun 10 07:47:28 PM PDT 24
Finished Jun 10 07:47:32 PM PDT 24
Peak memory 216240 kb
Host smart-5628d0dc-586a-4265-9b83-35f802625c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795128293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2795128293
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3857195158
Short name T756
Test name
Test status
Simulation time 30360908 ps
CPU time 0.84 seconds
Started Jun 10 07:47:28 PM PDT 24
Finished Jun 10 07:47:31 PM PDT 24
Peak memory 205988 kb
Host smart-4f47c085-6bc1-4b35-83b3-3282665fd376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857195158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3857195158
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3885427474
Short name T543
Test name
Test status
Simulation time 3676296087 ps
CPU time 14.86 seconds
Started Jun 10 07:47:26 PM PDT 24
Finished Jun 10 07:47:43 PM PDT 24
Peak memory 232640 kb
Host smart-702af79f-abd4-4962-8554-583440114bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885427474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3885427474
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.647445783
Short name T497
Test name
Test status
Simulation time 19554542 ps
CPU time 0.71 seconds
Started Jun 10 07:48:40 PM PDT 24
Finished Jun 10 07:48:45 PM PDT 24
Peak memory 204752 kb
Host smart-dd02bc4e-0ae7-4a82-ba94-1442c832c293
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647445783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.647445783
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.974483305
Short name T377
Test name
Test status
Simulation time 20186945 ps
CPU time 0.76 seconds
Started Jun 10 07:48:41 PM PDT 24
Finished Jun 10 07:48:45 PM PDT 24
Peak memory 205364 kb
Host smart-836cd80c-41db-4303-b20a-cdfe847a94f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974483305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.974483305
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2709732369
Short name T222
Test name
Test status
Simulation time 28483896775 ps
CPU time 275.03 seconds
Started Jun 10 07:48:37 PM PDT 24
Finished Jun 10 07:53:17 PM PDT 24
Peak memory 237688 kb
Host smart-ef05971c-6c0d-44bc-93d9-0e1518ed8dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709732369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2709732369
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2283454902
Short name T588
Test name
Test status
Simulation time 32420052610 ps
CPU time 143.89 seconds
Started Jun 10 07:48:39 PM PDT 24
Finished Jun 10 07:51:07 PM PDT 24
Peak memory 252896 kb
Host smart-94df179f-417b-4907-abc7-1bc1e1e30f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283454902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2283454902
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1080377318
Short name T321
Test name
Test status
Simulation time 1937186670 ps
CPU time 14.94 seconds
Started Jun 10 07:48:44 PM PDT 24
Finished Jun 10 07:49:02 PM PDT 24
Peak memory 236696 kb
Host smart-248f2a9a-25c9-4daa-8c9c-ae86ccf996a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080377318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1080377318
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.366080758
Short name T699
Test name
Test status
Simulation time 5682198718 ps
CPU time 12.88 seconds
Started Jun 10 07:48:37 PM PDT 24
Finished Jun 10 07:48:55 PM PDT 24
Peak memory 224464 kb
Host smart-7857ecfd-aaff-4da7-b4c1-48f80447a32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366080758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.366080758
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2630422880
Short name T592
Test name
Test status
Simulation time 59266775702 ps
CPU time 114.53 seconds
Started Jun 10 07:48:39 PM PDT 24
Finished Jun 10 07:50:38 PM PDT 24
Peak memory 249064 kb
Host smart-1bc7b9d9-0fe2-4f7a-bfc9-3dcb2c702e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630422880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2630422880
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.4070716691
Short name T47
Test name
Test status
Simulation time 4239884158 ps
CPU time 14.93 seconds
Started Jun 10 07:48:49 PM PDT 24
Finished Jun 10 07:49:08 PM PDT 24
Peak memory 224428 kb
Host smart-ceeb1cbc-265e-4d0f-a446-ce441d585a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070716691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.4070716691
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1507333558
Short name T165
Test name
Test status
Simulation time 15473888782 ps
CPU time 12.69 seconds
Started Jun 10 07:48:37 PM PDT 24
Finished Jun 10 07:48:55 PM PDT 24
Peak memory 224492 kb
Host smart-7f703a1b-244c-4b0c-8c6f-cb4e57b5d565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507333558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1507333558
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2966080453
Short name T411
Test name
Test status
Simulation time 235137705 ps
CPU time 5.9 seconds
Started Jun 10 07:48:37 PM PDT 24
Finished Jun 10 07:48:48 PM PDT 24
Peak memory 222744 kb
Host smart-5504f712-9e33-49da-a45e-985b20129a97
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2966080453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2966080453
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3113506625
Short name T263
Test name
Test status
Simulation time 23125408286 ps
CPU time 148.46 seconds
Started Jun 10 07:48:48 PM PDT 24
Finished Jun 10 07:51:21 PM PDT 24
Peak memory 251420 kb
Host smart-2fadfdae-198c-4f26-a2a6-1bc7e203f0d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113506625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3113506625
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2322334466
Short name T333
Test name
Test status
Simulation time 3068348294 ps
CPU time 14.48 seconds
Started Jun 10 07:48:40 PM PDT 24
Finished Jun 10 07:48:58 PM PDT 24
Peak memory 216192 kb
Host smart-3b7f9e9a-a84f-4063-b4ab-d353235ab5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322334466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2322334466
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1843544791
Short name T764
Test name
Test status
Simulation time 2930061140 ps
CPU time 1.41 seconds
Started Jun 10 07:48:49 PM PDT 24
Finished Jun 10 07:48:54 PM PDT 24
Peak memory 207156 kb
Host smart-356448e6-69f4-480d-a035-79c63a1c9b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843544791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1843544791
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.932498740
Short name T623
Test name
Test status
Simulation time 13669653 ps
CPU time 0.78 seconds
Started Jun 10 07:48:43 PM PDT 24
Finished Jun 10 07:48:47 PM PDT 24
Peak memory 205724 kb
Host smart-2dec3de2-8928-4f3f-8847-74b27a088baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932498740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.932498740
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.785779872
Short name T791
Test name
Test status
Simulation time 126208592 ps
CPU time 0.83 seconds
Started Jun 10 07:48:39 PM PDT 24
Finished Jun 10 07:48:44 PM PDT 24
Peak memory 206732 kb
Host smart-64177cda-2d89-4aa1-9da8-ff2e25f62eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785779872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.785779872
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1669592713
Short name T6
Test name
Test status
Simulation time 2354158536 ps
CPU time 8.23 seconds
Started Jun 10 07:48:38 PM PDT 24
Finished Jun 10 07:48:51 PM PDT 24
Peak memory 232612 kb
Host smart-1d01a6ed-f7cf-417a-93ca-f15c101c26c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669592713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1669592713
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3214283081
Short name T409
Test name
Test status
Simulation time 12422563 ps
CPU time 0.73 seconds
Started Jun 10 07:48:38 PM PDT 24
Finished Jun 10 07:48:43 PM PDT 24
Peak memory 204744 kb
Host smart-0d51dfb3-9817-4e72-a46a-cc492046c653
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214283081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3214283081
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3752922289
Short name T619
Test name
Test status
Simulation time 1260207483 ps
CPU time 4.04 seconds
Started Jun 10 07:48:40 PM PDT 24
Finished Jun 10 07:48:48 PM PDT 24
Peak memory 232468 kb
Host smart-9f4bb6ad-67d9-4fd2-b6fe-1345c92e0c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752922289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3752922289
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3361575763
Short name T561
Test name
Test status
Simulation time 48611245 ps
CPU time 0.72 seconds
Started Jun 10 07:48:42 PM PDT 24
Finished Jun 10 07:48:46 PM PDT 24
Peak memory 205344 kb
Host smart-7176efb2-7ba0-4a34-9765-179f797ca07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361575763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3361575763
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.831644152
Short name T959
Test name
Test status
Simulation time 933166900 ps
CPU time 26.14 seconds
Started Jun 10 07:48:44 PM PDT 24
Finished Jun 10 07:49:13 PM PDT 24
Peak memory 250236 kb
Host smart-500a98a4-c8fe-426b-b625-bc12e27ce6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831644152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.831644152
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2957855667
Short name T770
Test name
Test status
Simulation time 36541669680 ps
CPU time 258.36 seconds
Started Jun 10 07:48:38 PM PDT 24
Finished Jun 10 07:53:01 PM PDT 24
Peak memory 257280 kb
Host smart-cec72544-ac81-4f06-a4a4-d5d492ccb10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957855667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2957855667
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1830469322
Short name T819
Test name
Test status
Simulation time 323031558 ps
CPU time 5.28 seconds
Started Jun 10 07:48:40 PM PDT 24
Finished Jun 10 07:48:49 PM PDT 24
Peak memory 224312 kb
Host smart-461fdf8d-f751-4e90-9705-f6ac2b9357ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830469322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1830469322
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1006798581
Short name T967
Test name
Test status
Simulation time 338426147 ps
CPU time 5.31 seconds
Started Jun 10 07:48:39 PM PDT 24
Finished Jun 10 07:48:48 PM PDT 24
Peak memory 218436 kb
Host smart-b4996487-4d91-4c49-8bfd-e45a15202eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006798581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1006798581
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.4159880022
Short name T198
Test name
Test status
Simulation time 5538329356 ps
CPU time 30.87 seconds
Started Jun 10 07:48:37 PM PDT 24
Finished Jun 10 07:49:13 PM PDT 24
Peak memory 232700 kb
Host smart-c3fd3585-88af-4b88-9ba3-355fb5dc71d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159880022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.4159880022
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.397624585
Short name T552
Test name
Test status
Simulation time 281045622 ps
CPU time 5.05 seconds
Started Jun 10 07:48:37 PM PDT 24
Finished Jun 10 07:48:47 PM PDT 24
Peak memory 232568 kb
Host smart-b68e03b2-1831-4553-82b1-030292164990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397624585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.397624585
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1522594162
Short name T931
Test name
Test status
Simulation time 185111506947 ps
CPU time 28.84 seconds
Started Jun 10 07:48:41 PM PDT 24
Finished Jun 10 07:49:13 PM PDT 24
Peak memory 240756 kb
Host smart-c204ffce-e244-4516-acd1-15acdafe63a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522594162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1522594162
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3127506737
Short name T779
Test name
Test status
Simulation time 2152879836 ps
CPU time 5.24 seconds
Started Jun 10 07:48:37 PM PDT 24
Finished Jun 10 07:48:47 PM PDT 24
Peak memory 218600 kb
Host smart-3a5738e4-5aa3-4f50-80b1-fd95a53581df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3127506737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3127506737
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.433220943
Short name T335
Test name
Test status
Simulation time 2230985284 ps
CPU time 17.99 seconds
Started Jun 10 07:48:38 PM PDT 24
Finished Jun 10 07:49:01 PM PDT 24
Peak memory 216124 kb
Host smart-a0652ba6-33a7-422b-98fe-a706fcd153a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433220943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.433220943
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1700618977
Short name T345
Test name
Test status
Simulation time 1762917592 ps
CPU time 7.56 seconds
Started Jun 10 07:48:42 PM PDT 24
Finished Jun 10 07:48:53 PM PDT 24
Peak memory 216072 kb
Host smart-83af29c8-e9de-4506-9cfc-1c84731b0bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700618977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1700618977
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1542123446
Short name T766
Test name
Test status
Simulation time 114145854 ps
CPU time 1.48 seconds
Started Jun 10 07:48:39 PM PDT 24
Finished Jun 10 07:48:44 PM PDT 24
Peak memory 215992 kb
Host smart-1d70f554-d021-4089-b592-b61da6254b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542123446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1542123446
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.210367947
Short name T843
Test name
Test status
Simulation time 35947820 ps
CPU time 0.81 seconds
Started Jun 10 07:48:38 PM PDT 24
Finished Jun 10 07:48:43 PM PDT 24
Peak memory 205676 kb
Host smart-b163a78b-0a1b-4082-bee6-6c161b9a249c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210367947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.210367947
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3244581461
Short name T751
Test name
Test status
Simulation time 1406947671 ps
CPU time 5.45 seconds
Started Jun 10 07:48:39 PM PDT 24
Finished Jun 10 07:48:49 PM PDT 24
Peak memory 224276 kb
Host smart-6d075a6b-1153-43c7-99bd-a58206401863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244581461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3244581461
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.642376641
Short name T429
Test name
Test status
Simulation time 22056018 ps
CPU time 0.71 seconds
Started Jun 10 07:48:49 PM PDT 24
Finished Jun 10 07:48:54 PM PDT 24
Peak memory 204724 kb
Host smart-6f81c3ab-43b6-4d2b-837f-610de8af7095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642376641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.642376641
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1394291643
Short name T352
Test name
Test status
Simulation time 121826632 ps
CPU time 3.62 seconds
Started Jun 10 07:48:46 PM PDT 24
Finished Jun 10 07:48:53 PM PDT 24
Peak memory 232444 kb
Host smart-8b908c58-f71f-41d0-8dae-e0e171af1674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394291643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1394291643
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.4094363924
Short name T569
Test name
Test status
Simulation time 21529691 ps
CPU time 0.89 seconds
Started Jun 10 07:48:37 PM PDT 24
Finished Jun 10 07:48:42 PM PDT 24
Peak memory 206444 kb
Host smart-5e4c8d0d-26a7-4ab4-827d-6df281d15993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094363924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.4094363924
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1104697081
Short name T926
Test name
Test status
Simulation time 5637610096 ps
CPU time 44.39 seconds
Started Jun 10 07:48:50 PM PDT 24
Finished Jun 10 07:49:39 PM PDT 24
Peak memory 236864 kb
Host smart-4084eb97-b385-4568-b51a-a75c57520e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104697081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1104697081
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1536576902
Short name T206
Test name
Test status
Simulation time 148252458243 ps
CPU time 152.2 seconds
Started Jun 10 07:48:50 PM PDT 24
Finished Jun 10 07:51:27 PM PDT 24
Peak memory 253232 kb
Host smart-c49d6457-8b79-4b5d-8014-eaf579716305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536576902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1536576902
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.4284086749
Short name T133
Test name
Test status
Simulation time 88669722 ps
CPU time 4.09 seconds
Started Jun 10 07:48:46 PM PDT 24
Finished Jun 10 07:48:53 PM PDT 24
Peak memory 232472 kb
Host smart-c72db0f5-be13-4f51-acc8-787936f8dfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284086749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.4284086749
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3668874570
Short name T551
Test name
Test status
Simulation time 1025461807 ps
CPU time 11.69 seconds
Started Jun 10 07:48:41 PM PDT 24
Finished Jun 10 07:48:56 PM PDT 24
Peak memory 224264 kb
Host smart-f9bacb1e-0b38-4001-b46c-7cc38156c670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668874570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3668874570
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.453122783
Short name T272
Test name
Test status
Simulation time 4081047155 ps
CPU time 44.84 seconds
Started Jun 10 07:48:39 PM PDT 24
Finished Jun 10 07:49:28 PM PDT 24
Peak memory 232596 kb
Host smart-d524d7cc-376e-4656-b8f6-6cd4892a04e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453122783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.453122783
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.83278474
Short name T183
Test name
Test status
Simulation time 456332154 ps
CPU time 2.52 seconds
Started Jun 10 07:48:46 PM PDT 24
Finished Jun 10 07:48:51 PM PDT 24
Peak memory 218440 kb
Host smart-102dfc36-d397-412b-a99c-505e880d3673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83278474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.83278474
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2881448032
Short name T692
Test name
Test status
Simulation time 41664514 ps
CPU time 2.5 seconds
Started Jun 10 07:48:46 PM PDT 24
Finished Jun 10 07:48:51 PM PDT 24
Peak memory 226592 kb
Host smart-5002eed2-dd4e-4091-82c1-c82052ed5062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881448032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2881448032
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.901137129
Short name T68
Test name
Test status
Simulation time 134468727 ps
CPU time 4.41 seconds
Started Jun 10 07:48:48 PM PDT 24
Finished Jun 10 07:48:57 PM PDT 24
Peak memory 222768 kb
Host smart-2041a7c3-7782-41e6-8b51-efa30918b1ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=901137129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.901137129
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.285538339
Short name T960
Test name
Test status
Simulation time 3389015880 ps
CPU time 14.27 seconds
Started Jun 10 07:48:48 PM PDT 24
Finished Jun 10 07:49:07 PM PDT 24
Peak memory 216220 kb
Host smart-b5724c9d-3a6c-4dc4-a951-7b171daf48bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285538339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.285538339
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2998384577
Short name T23
Test name
Test status
Simulation time 11790840 ps
CPU time 0.76 seconds
Started Jun 10 07:48:46 PM PDT 24
Finished Jun 10 07:48:49 PM PDT 24
Peak memory 205484 kb
Host smart-c6fc30de-ba4e-4d99-b872-9a4e6cc859cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998384577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2998384577
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3645531911
Short name T793
Test name
Test status
Simulation time 15864718 ps
CPU time 0.79 seconds
Started Jun 10 07:48:37 PM PDT 24
Finished Jun 10 07:48:42 PM PDT 24
Peak memory 205668 kb
Host smart-47116f1f-14fe-4244-8cef-2bab0d843adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645531911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3645531911
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.189573890
Short name T467
Test name
Test status
Simulation time 30875319 ps
CPU time 0.7 seconds
Started Jun 10 07:48:39 PM PDT 24
Finished Jun 10 07:48:44 PM PDT 24
Peak memory 205440 kb
Host smart-3a7e05a2-331e-465c-8ad0-3a773f5e079e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189573890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.189573890
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2904726849
Short name T837
Test name
Test status
Simulation time 1410168869 ps
CPU time 6.37 seconds
Started Jun 10 07:48:45 PM PDT 24
Finished Jun 10 07:48:54 PM PDT 24
Peak memory 224268 kb
Host smart-b0be2bcb-c13f-4991-a85c-76ab3ee73b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904726849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2904726849
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3816294693
Short name T378
Test name
Test status
Simulation time 66584416 ps
CPU time 0.76 seconds
Started Jun 10 07:48:49 PM PDT 24
Finished Jun 10 07:48:53 PM PDT 24
Peak memory 205648 kb
Host smart-2b90e7eb-6d17-48d8-bb6a-74d2edcb5752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816294693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3816294693
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1463427534
Short name T342
Test name
Test status
Simulation time 29502048 ps
CPU time 1.98 seconds
Started Jun 10 07:48:50 PM PDT 24
Finished Jun 10 07:48:56 PM PDT 24
Peak memory 222988 kb
Host smart-d04fcbce-beb3-48bf-8d14-0841ae2ac6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463427534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1463427534
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3629641690
Short name T980
Test name
Test status
Simulation time 38401316 ps
CPU time 0.79 seconds
Started Jun 10 07:48:48 PM PDT 24
Finished Jun 10 07:48:52 PM PDT 24
Peak memory 206360 kb
Host smart-0a234ead-3397-4ec5-9639-18edd4b62748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629641690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3629641690
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3905335929
Short name T481
Test name
Test status
Simulation time 21348467097 ps
CPU time 42 seconds
Started Jun 10 07:48:52 PM PDT 24
Finished Jun 10 07:49:38 PM PDT 24
Peak memory 237032 kb
Host smart-4f38db57-1ed9-4aec-8c17-361eadcda81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905335929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3905335929
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.4002955023
Short name T301
Test name
Test status
Simulation time 34188573264 ps
CPU time 118.16 seconds
Started Jun 10 07:48:47 PM PDT 24
Finished Jun 10 07:50:49 PM PDT 24
Peak memory 254264 kb
Host smart-9d864d15-ab03-49e0-8dc6-8fec03ea4f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002955023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.4002955023
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3214316420
Short name T813
Test name
Test status
Simulation time 467024157259 ps
CPU time 397.31 seconds
Started Jun 10 07:48:50 PM PDT 24
Finished Jun 10 07:55:32 PM PDT 24
Peak memory 263516 kb
Host smart-749d9f40-5b07-4776-96fc-6451ae73f6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214316420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3214316420
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2952674272
Short name T937
Test name
Test status
Simulation time 593555367 ps
CPU time 4.66 seconds
Started Jun 10 07:48:48 PM PDT 24
Finished Jun 10 07:48:56 PM PDT 24
Peak memory 232548 kb
Host smart-0111cd9e-fc1b-4792-96ac-1ad007b4c439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952674272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2952674272
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1376981659
Short name T653
Test name
Test status
Simulation time 20234262410 ps
CPU time 27.07 seconds
Started Jun 10 07:48:45 PM PDT 24
Finished Jun 10 07:49:15 PM PDT 24
Peak memory 224432 kb
Host smart-656ef697-7ae4-4239-99ee-270583a433bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376981659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1376981659
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.445183456
Short name T744
Test name
Test status
Simulation time 1172468696 ps
CPU time 10.34 seconds
Started Jun 10 07:48:46 PM PDT 24
Finished Jun 10 07:49:00 PM PDT 24
Peak memory 224300 kb
Host smart-c3378d45-fe1f-4159-a253-ec4c98f7a9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445183456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.445183456
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3848741541
Short name T631
Test name
Test status
Simulation time 631697377 ps
CPU time 2.46 seconds
Started Jun 10 07:48:49 PM PDT 24
Finished Jun 10 07:48:56 PM PDT 24
Peak memory 224364 kb
Host smart-5bacf1d6-e6e9-4370-a340-02824287348a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848741541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3848741541
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2662337514
Short name T651
Test name
Test status
Simulation time 1479466836 ps
CPU time 7.41 seconds
Started Jun 10 07:48:47 PM PDT 24
Finished Jun 10 07:48:59 PM PDT 24
Peak memory 232644 kb
Host smart-1382fdf9-7911-4eb2-8ff5-5d9e85711e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662337514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2662337514
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.4025550314
Short name T788
Test name
Test status
Simulation time 66117894 ps
CPU time 3.79 seconds
Started Jun 10 07:48:49 PM PDT 24
Finished Jun 10 07:48:57 PM PDT 24
Peak memory 222680 kb
Host smart-4f713b2b-fecd-40f4-9809-d7903878f0dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4025550314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.4025550314
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.654091356
Short name T32
Test name
Test status
Simulation time 6382891063 ps
CPU time 14.61 seconds
Started Jun 10 07:48:49 PM PDT 24
Finished Jun 10 07:49:07 PM PDT 24
Peak memory 236700 kb
Host smart-d043104a-703a-4d99-a407-c9b7b2e981ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654091356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.654091356
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3664864723
Short name T955
Test name
Test status
Simulation time 12906728470 ps
CPU time 39.6 seconds
Started Jun 10 07:48:50 PM PDT 24
Finished Jun 10 07:49:34 PM PDT 24
Peak memory 216156 kb
Host smart-b0f7c0f9-e848-473f-8cce-e74dacc2a5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664864723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3664864723
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3772869956
Short name T413
Test name
Test status
Simulation time 9804477380 ps
CPU time 24.67 seconds
Started Jun 10 07:48:51 PM PDT 24
Finished Jun 10 07:49:20 PM PDT 24
Peak memory 216216 kb
Host smart-01637b70-03f5-4be1-8df1-2047b9c46d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772869956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3772869956
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1354238332
Short name T949
Test name
Test status
Simulation time 149696289 ps
CPU time 1.73 seconds
Started Jun 10 07:48:49 PM PDT 24
Finished Jun 10 07:48:55 PM PDT 24
Peak memory 216032 kb
Host smart-7e15d7e8-59ec-4b12-b879-78c99b734be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354238332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1354238332
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3460279298
Short name T515
Test name
Test status
Simulation time 39952089 ps
CPU time 0.83 seconds
Started Jun 10 07:48:49 PM PDT 24
Finished Jun 10 07:48:54 PM PDT 24
Peak memory 205676 kb
Host smart-52175687-b064-420d-95d6-5a680f5429fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460279298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3460279298
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.356697919
Short name T297
Test name
Test status
Simulation time 260055642 ps
CPU time 3.73 seconds
Started Jun 10 07:48:46 PM PDT 24
Finished Jun 10 07:48:53 PM PDT 24
Peak memory 237108 kb
Host smart-715e7944-e3c6-4664-8c87-22725144840b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356697919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.356697919
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2247909246
Short name T943
Test name
Test status
Simulation time 13982091 ps
CPU time 0.73 seconds
Started Jun 10 07:48:45 PM PDT 24
Finished Jun 10 07:48:48 PM PDT 24
Peak memory 205324 kb
Host smart-ed1911a5-1f3a-4e60-aa0e-12ef1424ae0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247909246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2247909246
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.942706157
Short name T698
Test name
Test status
Simulation time 189950824 ps
CPU time 2.6 seconds
Started Jun 10 07:48:51 PM PDT 24
Finished Jun 10 07:48:58 PM PDT 24
Peak memory 224296 kb
Host smart-a98d950a-af22-4b17-81fa-cf28870ff05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942706157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.942706157
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2582597945
Short name T954
Test name
Test status
Simulation time 30507664 ps
CPU time 0.75 seconds
Started Jun 10 07:48:49 PM PDT 24
Finished Jun 10 07:48:54 PM PDT 24
Peak memory 205428 kb
Host smart-225cd98a-f7b4-452a-9b63-fba2d666b2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582597945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2582597945
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2674068003
Short name T971
Test name
Test status
Simulation time 198350678241 ps
CPU time 337.46 seconds
Started Jun 10 07:48:46 PM PDT 24
Finished Jun 10 07:54:27 PM PDT 24
Peak memory 250312 kb
Host smart-91d24028-a478-4e98-abb8-46676ed6ac44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674068003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2674068003
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.4279014325
Short name T45
Test name
Test status
Simulation time 11357818746 ps
CPU time 139.66 seconds
Started Jun 10 07:48:48 PM PDT 24
Finished Jun 10 07:51:11 PM PDT 24
Peak memory 251164 kb
Host smart-f5bdc460-0caa-46b2-a4d8-93f2e738400d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279014325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.4279014325
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2484656960
Short name T572
Test name
Test status
Simulation time 25730894429 ps
CPU time 258.58 seconds
Started Jun 10 07:48:49 PM PDT 24
Finished Jun 10 07:53:12 PM PDT 24
Peak memory 240904 kb
Host smart-0fec0740-c654-4d90-880a-b52a12c3fd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484656960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2484656960
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1035063351
Short name T319
Test name
Test status
Simulation time 1282469887 ps
CPU time 10.31 seconds
Started Jun 10 07:48:45 PM PDT 24
Finished Jun 10 07:48:59 PM PDT 24
Peak memory 233112 kb
Host smart-39de40fd-10c0-4029-b774-0b82b5383265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035063351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1035063351
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2301508864
Short name T924
Test name
Test status
Simulation time 1329697616 ps
CPU time 12.79 seconds
Started Jun 10 07:48:46 PM PDT 24
Finished Jun 10 07:49:01 PM PDT 24
Peak memory 227544 kb
Host smart-0ab9e929-0cea-4838-9771-0ea398f728a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301508864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2301508864
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2264458651
Short name T584
Test name
Test status
Simulation time 2731203194 ps
CPU time 27.51 seconds
Started Jun 10 07:48:46 PM PDT 24
Finished Jun 10 07:49:17 PM PDT 24
Peak memory 224396 kb
Host smart-63356f26-627a-44bb-814b-dddde858d7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264458651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2264458651
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1183175872
Short name T701
Test name
Test status
Simulation time 4188282162 ps
CPU time 18.79 seconds
Started Jun 10 07:48:49 PM PDT 24
Finished Jun 10 07:49:12 PM PDT 24
Peak memory 238432 kb
Host smart-578c1fc5-95cb-44b0-8d02-0bdaa742583d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183175872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1183175872
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.542960459
Short name T270
Test name
Test status
Simulation time 3181373564 ps
CPU time 7.61 seconds
Started Jun 10 07:48:48 PM PDT 24
Finished Jun 10 07:49:00 PM PDT 24
Peak memory 224444 kb
Host smart-15a50d8b-1155-4d98-8763-ce50839af132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542960459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.542960459
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.732135966
Short name T934
Test name
Test status
Simulation time 6923925244 ps
CPU time 10.93 seconds
Started Jun 10 07:48:47 PM PDT 24
Finished Jun 10 07:49:02 PM PDT 24
Peak memory 219760 kb
Host smart-99ce45b5-289b-4acd-945a-0d4fcb4f2e75
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=732135966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.732135966
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1998692339
Short name T500
Test name
Test status
Simulation time 91388757156 ps
CPU time 187.59 seconds
Started Jun 10 07:48:50 PM PDT 24
Finished Jun 10 07:52:03 PM PDT 24
Peak memory 250492 kb
Host smart-b30eed53-2e1c-476a-923b-bc02870ad682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998692339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1998692339
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.974919660
Short name T564
Test name
Test status
Simulation time 21427813682 ps
CPU time 28.07 seconds
Started Jun 10 07:48:49 PM PDT 24
Finished Jun 10 07:49:21 PM PDT 24
Peak memory 216160 kb
Host smart-d0598fc1-4b86-4d48-8d10-1e25623b8421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974919660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.974919660
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.349102889
Short name T372
Test name
Test status
Simulation time 2076255507 ps
CPU time 9.05 seconds
Started Jun 10 07:48:46 PM PDT 24
Finished Jun 10 07:48:59 PM PDT 24
Peak memory 216072 kb
Host smart-67916046-7939-4897-8216-4fd73fd5ee1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349102889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.349102889
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.4015059005
Short name T737
Test name
Test status
Simulation time 40022342 ps
CPU time 1.37 seconds
Started Jun 10 07:48:49 PM PDT 24
Finished Jun 10 07:48:54 PM PDT 24
Peak memory 216088 kb
Host smart-c65f7528-23bc-4140-b40c-10825a746cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015059005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.4015059005
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1965128246
Short name T907
Test name
Test status
Simulation time 212176769 ps
CPU time 0.86 seconds
Started Jun 10 07:48:49 PM PDT 24
Finished Jun 10 07:48:55 PM PDT 24
Peak memory 205732 kb
Host smart-4572fec6-3986-4c92-97b9-58db59d0594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965128246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1965128246
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.812111677
Short name T267
Test name
Test status
Simulation time 2086695011 ps
CPU time 5.77 seconds
Started Jun 10 07:48:48 PM PDT 24
Finished Jun 10 07:48:57 PM PDT 24
Peak memory 240532 kb
Host smart-74c6ce12-9d2f-42b7-955a-53a731db062a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812111677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.812111677
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.4002436691
Short name T685
Test name
Test status
Simulation time 33107103 ps
CPU time 0.7 seconds
Started Jun 10 07:48:56 PM PDT 24
Finished Jun 10 07:49:00 PM PDT 24
Peak memory 204732 kb
Host smart-338619ea-604a-45dd-be24-12ff841aac90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002436691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
4002436691
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2916987607
Short name T499
Test name
Test status
Simulation time 3475929221 ps
CPU time 10.68 seconds
Started Jun 10 07:48:59 PM PDT 24
Finished Jun 10 07:49:12 PM PDT 24
Peak memory 224420 kb
Host smart-1eae7876-658c-4b53-b095-02d1c6e03f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916987607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2916987607
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1147937500
Short name T860
Test name
Test status
Simulation time 70119761 ps
CPU time 0.8 seconds
Started Jun 10 07:48:47 PM PDT 24
Finished Jun 10 07:48:51 PM PDT 24
Peak memory 206360 kb
Host smart-404496b6-39e4-449a-8cdf-e484ab38d3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147937500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1147937500
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1035682344
Short name T774
Test name
Test status
Simulation time 17142193650 ps
CPU time 137.98 seconds
Started Jun 10 07:48:59 PM PDT 24
Finished Jun 10 07:51:20 PM PDT 24
Peak memory 249060 kb
Host smart-386e55e1-f434-4e91-9f50-9e2440749b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035682344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1035682344
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1724603181
Short name T232
Test name
Test status
Simulation time 5517012646 ps
CPU time 59.13 seconds
Started Jun 10 07:49:00 PM PDT 24
Finished Jun 10 07:50:02 PM PDT 24
Peak memory 249120 kb
Host smart-bdfea121-605d-49fe-90e4-b772c5ebe1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724603181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1724603181
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.762504721
Short name T874
Test name
Test status
Simulation time 4483004128 ps
CPU time 79.53 seconds
Started Jun 10 07:48:57 PM PDT 24
Finished Jun 10 07:50:20 PM PDT 24
Peak memory 254476 kb
Host smart-4ab8ffe8-a422-41f4-a1f5-fc16f030234d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762504721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.762504721
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2653571707
Short name T707
Test name
Test status
Simulation time 71009268 ps
CPU time 2.49 seconds
Started Jun 10 07:48:56 PM PDT 24
Finished Jun 10 07:49:02 PM PDT 24
Peak memory 224340 kb
Host smart-0578bcc8-bf13-46f8-9e5a-1c2df179c656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653571707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2653571707
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1713007652
Short name T235
Test name
Test status
Simulation time 2512620379 ps
CPU time 29.36 seconds
Started Jun 10 07:48:59 PM PDT 24
Finished Jun 10 07:49:31 PM PDT 24
Peak memory 232644 kb
Host smart-86804d32-b8dc-43b6-899c-bb53584df2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713007652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1713007652
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.595842519
Short name T66
Test name
Test status
Simulation time 1547892008 ps
CPU time 24.47 seconds
Started Jun 10 07:49:01 PM PDT 24
Finished Jun 10 07:49:28 PM PDT 24
Peak memory 232496 kb
Host smart-78d4482f-72c1-43bf-9f0e-9e0d6c69caf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595842519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.595842519
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2892529442
Short name T48
Test name
Test status
Simulation time 599364942 ps
CPU time 4.5 seconds
Started Jun 10 07:48:58 PM PDT 24
Finished Jun 10 07:49:05 PM PDT 24
Peak memory 224364 kb
Host smart-056c7d90-2048-464f-8214-e366731e8309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892529442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2892529442
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1829833016
Short name T560
Test name
Test status
Simulation time 106156017 ps
CPU time 2.39 seconds
Started Jun 10 07:48:50 PM PDT 24
Finished Jun 10 07:48:57 PM PDT 24
Peak memory 224208 kb
Host smart-392a61a8-2dff-4263-ab9e-bf0f0c063ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829833016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1829833016
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.124055569
Short name T25
Test name
Test status
Simulation time 763666223 ps
CPU time 3.95 seconds
Started Jun 10 07:48:58 PM PDT 24
Finished Jun 10 07:49:05 PM PDT 24
Peak memory 219012 kb
Host smart-397c7127-4d41-4b4a-bd7b-8ec5a6dd28f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=124055569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.124055569
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2784109561
Short name T219
Test name
Test status
Simulation time 4568812896 ps
CPU time 49.4 seconds
Started Jun 10 07:48:57 PM PDT 24
Finished Jun 10 07:49:50 PM PDT 24
Peak memory 249112 kb
Host smart-9cd9fc9d-5b4b-42d1-9e3e-67b225e29c7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784109561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2784109561
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1861263005
Short name T607
Test name
Test status
Simulation time 36548731 ps
CPU time 0.73 seconds
Started Jun 10 07:48:47 PM PDT 24
Finished Jun 10 07:48:52 PM PDT 24
Peak memory 205540 kb
Host smart-efa6e785-4108-4966-bffe-39b08e4fe26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861263005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1861263005
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1702840084
Short name T930
Test name
Test status
Simulation time 2708886762 ps
CPU time 1.89 seconds
Started Jun 10 07:48:48 PM PDT 24
Finished Jun 10 07:48:54 PM PDT 24
Peak memory 207896 kb
Host smart-30f21f70-e6bd-4d3b-ad16-4b5f12cd436b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702840084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1702840084
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1273425342
Short name T518
Test name
Test status
Simulation time 200611723 ps
CPU time 1.51 seconds
Started Jun 10 07:48:49 PM PDT 24
Finished Jun 10 07:48:55 PM PDT 24
Peak memory 216096 kb
Host smart-27cfff91-0aaa-4301-8e2f-791fb2d63e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273425342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1273425342
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1601962820
Short name T78
Test name
Test status
Simulation time 146919185 ps
CPU time 0.79 seconds
Started Jun 10 07:48:49 PM PDT 24
Finished Jun 10 07:48:55 PM PDT 24
Peak memory 205668 kb
Host smart-54b41550-4926-4f34-9679-8da8cb88a40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601962820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1601962820
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2124047606
Short name T710
Test name
Test status
Simulation time 348422974 ps
CPU time 5.02 seconds
Started Jun 10 07:48:58 PM PDT 24
Finished Jun 10 07:49:06 PM PDT 24
Peak memory 224372 kb
Host smart-a06f6da3-781e-4285-9109-1cf301a24cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124047606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2124047606
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2068177895
Short name T947
Test name
Test status
Simulation time 14670942 ps
CPU time 0.73 seconds
Started Jun 10 07:49:03 PM PDT 24
Finished Jun 10 07:49:05 PM PDT 24
Peak memory 204740 kb
Host smart-a990372c-5c83-4557-8f2f-f5cd394ce472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068177895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2068177895
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.102382303
Short name T868
Test name
Test status
Simulation time 258838272 ps
CPU time 3.9 seconds
Started Jun 10 07:48:57 PM PDT 24
Finished Jun 10 07:49:04 PM PDT 24
Peak memory 224252 kb
Host smart-d76ef8b5-e5ca-4503-a04b-0d9e7f351a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102382303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.102382303
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.366816068
Short name T529
Test name
Test status
Simulation time 17704305 ps
CPU time 0.77 seconds
Started Jun 10 07:48:57 PM PDT 24
Finished Jun 10 07:49:01 PM PDT 24
Peak memory 205652 kb
Host smart-461589e7-187b-4c71-b1c5-719eafe9fdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366816068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.366816068
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3133384627
Short name T920
Test name
Test status
Simulation time 80840492108 ps
CPU time 103.45 seconds
Started Jun 10 07:48:58 PM PDT 24
Finished Jun 10 07:50:45 PM PDT 24
Peak memory 249048 kb
Host smart-00bcfab0-0c75-47e1-a0f5-27600023c679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133384627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3133384627
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2242701178
Short name T638
Test name
Test status
Simulation time 10610610134 ps
CPU time 56.84 seconds
Started Jun 10 07:48:58 PM PDT 24
Finished Jun 10 07:49:58 PM PDT 24
Peak memory 249096 kb
Host smart-aa6d2128-ca30-456c-bfe1-53c6113cbe6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242701178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2242701178
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1011797499
Short name T273
Test name
Test status
Simulation time 158206783205 ps
CPU time 271.39 seconds
Started Jun 10 07:48:57 PM PDT 24
Finished Jun 10 07:53:32 PM PDT 24
Peak memory 249044 kb
Host smart-c33b49fa-f40c-48e3-bcc0-1159dc04eed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011797499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1011797499
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3889718960
Short name T752
Test name
Test status
Simulation time 2238023228 ps
CPU time 14.02 seconds
Started Jun 10 07:49:00 PM PDT 24
Finished Jun 10 07:49:17 PM PDT 24
Peak memory 232572 kb
Host smart-99ab1e6a-73a5-461f-a8d3-523b36a8d3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889718960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3889718960
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1515427513
Short name T945
Test name
Test status
Simulation time 75826338 ps
CPU time 3.59 seconds
Started Jun 10 07:48:58 PM PDT 24
Finished Jun 10 07:49:04 PM PDT 24
Peak memory 232520 kb
Host smart-d06c0c49-7659-4371-be4f-82b19b4403c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515427513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1515427513
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1074728600
Short name T845
Test name
Test status
Simulation time 6822179754 ps
CPU time 5.81 seconds
Started Jun 10 07:48:59 PM PDT 24
Finished Jun 10 07:49:08 PM PDT 24
Peak memory 224396 kb
Host smart-d57816fd-4627-4ecc-8ae7-102342ec077a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074728600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1074728600
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3697336387
Short name T296
Test name
Test status
Simulation time 187641126 ps
CPU time 2.97 seconds
Started Jun 10 07:48:59 PM PDT 24
Finished Jun 10 07:49:05 PM PDT 24
Peak memory 224320 kb
Host smart-b7c10476-6871-4bd9-92c0-2038414daca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697336387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3697336387
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3380894265
Short name T211
Test name
Test status
Simulation time 683248778 ps
CPU time 3.09 seconds
Started Jun 10 07:48:58 PM PDT 24
Finished Jun 10 07:49:04 PM PDT 24
Peak memory 224292 kb
Host smart-57f343ab-9373-4631-88ca-ed87a265f372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380894265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3380894265
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2892448773
Short name T417
Test name
Test status
Simulation time 227649593 ps
CPU time 4.25 seconds
Started Jun 10 07:49:02 PM PDT 24
Finished Jun 10 07:49:08 PM PDT 24
Peak memory 219044 kb
Host smart-e8c68eda-95d1-48ad-900a-ed6bd2eadcab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2892448773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2892448773
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3260912938
Short name T192
Test name
Test status
Simulation time 90763679901 ps
CPU time 211.7 seconds
Started Jun 10 07:49:03 PM PDT 24
Finished Jun 10 07:52:36 PM PDT 24
Peak memory 251112 kb
Host smart-a7144dba-cf19-40e2-9747-a65641a7584b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260912938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3260912938
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1983464150
Short name T457
Test name
Test status
Simulation time 2637844387 ps
CPU time 17.11 seconds
Started Jun 10 07:49:00 PM PDT 24
Finished Jun 10 07:49:20 PM PDT 24
Peak memory 216172 kb
Host smart-5d48df37-b957-489a-9322-d4199c3890a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983464150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1983464150
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3670433175
Short name T491
Test name
Test status
Simulation time 3296121061 ps
CPU time 6.49 seconds
Started Jun 10 07:48:59 PM PDT 24
Finished Jun 10 07:49:08 PM PDT 24
Peak memory 216192 kb
Host smart-10e0922c-74a6-4a79-989e-6718f16002f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670433175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3670433175
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.818334557
Short name T7
Test name
Test status
Simulation time 44583645 ps
CPU time 1.06 seconds
Started Jun 10 07:48:59 PM PDT 24
Finished Jun 10 07:49:03 PM PDT 24
Peak memory 206712 kb
Host smart-2f291929-a204-4780-8d7f-7b6883c1f238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818334557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.818334557
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.4282880613
Short name T721
Test name
Test status
Simulation time 418081271 ps
CPU time 0.83 seconds
Started Jun 10 07:49:05 PM PDT 24
Finished Jun 10 07:49:08 PM PDT 24
Peak memory 205668 kb
Host smart-8e4cd4d2-c5bd-43d4-937f-41774e63973f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282880613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.4282880613
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.4071074271
Short name T812
Test name
Test status
Simulation time 1383193689 ps
CPU time 9.71 seconds
Started Jun 10 07:49:00 PM PDT 24
Finished Jun 10 07:49:13 PM PDT 24
Peak memory 232500 kb
Host smart-09f88f5c-7d99-454f-a9de-7db4e2551aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071074271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.4071074271
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2413906696
Short name T400
Test name
Test status
Simulation time 36252437 ps
CPU time 0.74 seconds
Started Jun 10 07:49:07 PM PDT 24
Finished Jun 10 07:49:11 PM PDT 24
Peak memory 205296 kb
Host smart-e7f88541-a8dd-4cda-9096-e5e5787d467f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413906696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2413906696
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.4256695341
Short name T179
Test name
Test status
Simulation time 198946923 ps
CPU time 2.56 seconds
Started Jun 10 07:49:05 PM PDT 24
Finished Jun 10 07:49:10 PM PDT 24
Peak memory 232536 kb
Host smart-103e58bb-9f0f-41b8-97c3-b63286b93d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256695341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.4256695341
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1794367523
Short name T536
Test name
Test status
Simulation time 18020444 ps
CPU time 0.77 seconds
Started Jun 10 07:49:00 PM PDT 24
Finished Jun 10 07:49:04 PM PDT 24
Peak memory 206360 kb
Host smart-ecbdab98-016f-4ffb-ac6d-1d9c8d36462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794367523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1794367523
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2816563569
Short name T940
Test name
Test status
Simulation time 62163561364 ps
CPU time 120.89 seconds
Started Jun 10 07:49:05 PM PDT 24
Finished Jun 10 07:51:08 PM PDT 24
Peak memory 252052 kb
Host smart-a5e75ecf-8a00-4df3-aaed-4479c5ea76cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816563569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2816563569
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.551096473
Short name T872
Test name
Test status
Simulation time 20251705873 ps
CPU time 81.35 seconds
Started Jun 10 07:49:05 PM PDT 24
Finished Jun 10 07:50:28 PM PDT 24
Peak memory 249060 kb
Host smart-4550b939-660d-45a8-88b5-8c8b26260273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551096473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.551096473
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2992379171
Short name T383
Test name
Test status
Simulation time 1506546441 ps
CPU time 15.44 seconds
Started Jun 10 07:49:04 PM PDT 24
Finished Jun 10 07:49:21 PM PDT 24
Peak memory 232512 kb
Host smart-afd11aa1-c52e-4623-9fab-1e8fbf3bc021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992379171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2992379171
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3854042263
Short name T35
Test name
Test status
Simulation time 115855352 ps
CPU time 2.98 seconds
Started Jun 10 07:48:56 PM PDT 24
Finished Jun 10 07:49:02 PM PDT 24
Peak memory 232500 kb
Host smart-74251211-58fe-4bd5-948f-944fe9fd73d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854042263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3854042263
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3559371823
Short name T386
Test name
Test status
Simulation time 168161901 ps
CPU time 2.71 seconds
Started Jun 10 07:48:59 PM PDT 24
Finished Jun 10 07:49:04 PM PDT 24
Peak memory 232372 kb
Host smart-7e52ee05-de35-4853-ab91-56ef36aac63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559371823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3559371823
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1608178001
Short name T306
Test name
Test status
Simulation time 2120095738 ps
CPU time 6.57 seconds
Started Jun 10 07:49:00 PM PDT 24
Finished Jun 10 07:49:09 PM PDT 24
Peak memory 232468 kb
Host smart-8b652dd6-28f7-4625-ad2d-558a353136b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608178001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1608178001
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2362188447
Short name T573
Test name
Test status
Simulation time 4404533020 ps
CPU time 10.67 seconds
Started Jun 10 07:49:00 PM PDT 24
Finished Jun 10 07:49:13 PM PDT 24
Peak memory 232672 kb
Host smart-d64a01d4-220d-49ef-8031-96d6df36f2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362188447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2362188447
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2506541390
Short name T800
Test name
Test status
Simulation time 3415589041 ps
CPU time 10.95 seconds
Started Jun 10 07:49:05 PM PDT 24
Finished Jun 10 07:49:18 PM PDT 24
Peak memory 219136 kb
Host smart-0750d65d-9e25-41d6-8ba7-ea8cfc82aca1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2506541390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2506541390
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1896951770
Short name T856
Test name
Test status
Simulation time 20617187354 ps
CPU time 198.46 seconds
Started Jun 10 07:49:05 PM PDT 24
Finished Jun 10 07:52:26 PM PDT 24
Peak memory 253396 kb
Host smart-e8b5dbde-75cf-4c6f-8d3a-6923bb2ea2b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896951770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1896951770
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2752125580
Short name T933
Test name
Test status
Simulation time 4131592045 ps
CPU time 27.36 seconds
Started Jun 10 07:48:58 PM PDT 24
Finished Jun 10 07:49:29 PM PDT 24
Peak memory 216176 kb
Host smart-b348c32e-9d3e-498a-a523-b99ddd38d3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752125580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2752125580
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.4255285856
Short name T484
Test name
Test status
Simulation time 3697166552 ps
CPU time 11.41 seconds
Started Jun 10 07:48:56 PM PDT 24
Finished Jun 10 07:49:11 PM PDT 24
Peak memory 216204 kb
Host smart-ff00f4a9-ca58-41ec-a6ac-2c95b4016b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255285856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.4255285856
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2109681412
Short name T626
Test name
Test status
Simulation time 246876381 ps
CPU time 4.31 seconds
Started Jun 10 07:49:03 PM PDT 24
Finished Jun 10 07:49:09 PM PDT 24
Peak memory 215968 kb
Host smart-ca955806-7239-4c53-b890-548591cf9fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109681412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2109681412
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.930534988
Short name T688
Test name
Test status
Simulation time 84615155 ps
CPU time 0.8 seconds
Started Jun 10 07:49:04 PM PDT 24
Finished Jun 10 07:49:06 PM PDT 24
Peak memory 205700 kb
Host smart-08d24302-af03-4b8e-a08c-58947bcf726c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930534988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.930534988
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.899103651
Short name T801
Test name
Test status
Simulation time 173156519 ps
CPU time 3.11 seconds
Started Jun 10 07:49:05 PM PDT 24
Finished Jun 10 07:49:10 PM PDT 24
Peak memory 224328 kb
Host smart-a4f867aa-1f58-4bae-9463-4a42d56e30fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899103651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.899103651
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1692092677
Short name T451
Test name
Test status
Simulation time 56167289 ps
CPU time 0.83 seconds
Started Jun 10 07:49:04 PM PDT 24
Finished Jun 10 07:49:06 PM PDT 24
Peak memory 205664 kb
Host smart-04a9806e-4dff-4c08-a4df-71ce916a0f96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692092677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1692092677
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3813356819
Short name T516
Test name
Test status
Simulation time 105524769 ps
CPU time 4.28 seconds
Started Jun 10 07:49:09 PM PDT 24
Finished Jun 10 07:49:16 PM PDT 24
Peak memory 232516 kb
Host smart-9ca77c9a-6053-4895-b3cb-744662b63e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813356819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3813356819
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1149763271
Short name T640
Test name
Test status
Simulation time 34536259 ps
CPU time 0.83 seconds
Started Jun 10 07:49:07 PM PDT 24
Finished Jun 10 07:49:11 PM PDT 24
Peak memory 206688 kb
Host smart-48c9faf7-6eea-4c1c-ada2-fecdb5acaf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149763271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1149763271
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4094631152
Short name T750
Test name
Test status
Simulation time 4189158685 ps
CPU time 30.13 seconds
Started Jun 10 07:49:06 PM PDT 24
Finished Jun 10 07:49:39 PM PDT 24
Peak memory 249072 kb
Host smart-67da38ac-4f6e-46e9-add7-1c0ada658f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094631152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4094631152
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1652356141
Short name T660
Test name
Test status
Simulation time 14732706381 ps
CPU time 148.98 seconds
Started Jun 10 07:49:08 PM PDT 24
Finished Jun 10 07:51:40 PM PDT 24
Peak memory 249120 kb
Host smart-31c2f4ed-b79e-485b-bef5-7c702923c5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652356141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1652356141
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.580112351
Short name T816
Test name
Test status
Simulation time 4723617921 ps
CPU time 54.06 seconds
Started Jun 10 07:49:08 PM PDT 24
Finished Jun 10 07:50:04 PM PDT 24
Peak memory 240832 kb
Host smart-3213db3d-f3da-4694-8703-417c0bb3c187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580112351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.580112351
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.430835797
Short name T320
Test name
Test status
Simulation time 4228002552 ps
CPU time 49.23 seconds
Started Jun 10 07:49:03 PM PDT 24
Finished Jun 10 07:49:54 PM PDT 24
Peak memory 232664 kb
Host smart-7b6e820d-067e-4f30-ac1d-396e9d80f546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430835797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.430835797
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.770224709
Short name T50
Test name
Test status
Simulation time 5868127383 ps
CPU time 15.68 seconds
Started Jun 10 07:49:07 PM PDT 24
Finished Jun 10 07:49:25 PM PDT 24
Peak memory 232640 kb
Host smart-09e618d9-748b-4021-acc8-85cbeebda2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770224709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.770224709
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1358889381
Short name T252
Test name
Test status
Simulation time 563826167 ps
CPU time 4.67 seconds
Started Jun 10 07:49:06 PM PDT 24
Finished Jun 10 07:49:13 PM PDT 24
Peak memory 224352 kb
Host smart-17f20fd4-53db-4a76-a4a8-f13e01a1968d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358889381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1358889381
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.144059660
Short name T691
Test name
Test status
Simulation time 977675230 ps
CPU time 7.71 seconds
Started Jun 10 07:49:06 PM PDT 24
Finished Jun 10 07:49:16 PM PDT 24
Peak memory 240384 kb
Host smart-b30cdcb5-f550-457f-9a67-9ddd127e0846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144059660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.144059660
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3996577780
Short name T711
Test name
Test status
Simulation time 10394778860 ps
CPU time 10.38 seconds
Started Jun 10 07:49:07 PM PDT 24
Finished Jun 10 07:49:20 PM PDT 24
Peak memory 232636 kb
Host smart-ee14271d-9f7c-4b4e-8f9e-85d8f09cc3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996577780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3996577780
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2034976086
Short name T627
Test name
Test status
Simulation time 3261178033 ps
CPU time 11.46 seconds
Started Jun 10 07:49:06 PM PDT 24
Finished Jun 10 07:49:20 PM PDT 24
Peak memory 222524 kb
Host smart-91e60f4d-e0ff-4479-b06c-ffd0fe408c88
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2034976086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2034976086
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.322231381
Short name T17
Test name
Test status
Simulation time 201758612 ps
CPU time 1.02 seconds
Started Jun 10 07:49:07 PM PDT 24
Finished Jun 10 07:49:11 PM PDT 24
Peak memory 206596 kb
Host smart-aaf7a199-3199-4c45-b693-cb978ef64490
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322231381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.322231381
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2053442541
Short name T334
Test name
Test status
Simulation time 2743902156 ps
CPU time 7.54 seconds
Started Jun 10 07:49:07 PM PDT 24
Finished Jun 10 07:49:17 PM PDT 24
Peak memory 216200 kb
Host smart-c73de1f8-7c53-4f95-8d62-268c79d10d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053442541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2053442541
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1828563968
Short name T753
Test name
Test status
Simulation time 1666013525 ps
CPU time 9.58 seconds
Started Jun 10 07:49:06 PM PDT 24
Finished Jun 10 07:49:18 PM PDT 24
Peak memory 216016 kb
Host smart-c4a40777-05a7-44d7-887b-424d81865631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828563968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1828563968
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2619852653
Short name T664
Test name
Test status
Simulation time 60644294 ps
CPU time 1.04 seconds
Started Jun 10 07:49:38 PM PDT 24
Finished Jun 10 07:49:43 PM PDT 24
Peak memory 207168 kb
Host smart-1d473df2-604a-4dd2-9e03-c1b38e67a54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619852653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2619852653
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1050994680
Short name T441
Test name
Test status
Simulation time 81478407 ps
CPU time 0.77 seconds
Started Jun 10 07:49:09 PM PDT 24
Finished Jun 10 07:49:12 PM PDT 24
Peak memory 205720 kb
Host smart-4cdf779f-2304-40b6-8d6c-f1b6b5e08843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050994680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1050994680
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3327782744
Short name T224
Test name
Test status
Simulation time 694137341 ps
CPU time 3.08 seconds
Started Jun 10 07:49:07 PM PDT 24
Finished Jun 10 07:49:13 PM PDT 24
Peak memory 224516 kb
Host smart-9b7c7207-4243-4893-8d56-853bedf0c76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327782744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3327782744
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.460945597
Short name T587
Test name
Test status
Simulation time 18865543 ps
CPU time 0.73 seconds
Started Jun 10 07:49:06 PM PDT 24
Finished Jun 10 07:49:09 PM PDT 24
Peak memory 204720 kb
Host smart-159fc30d-a7f3-41e8-8101-7ff293f795e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460945597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.460945597
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3567702554
Short name T415
Test name
Test status
Simulation time 225451157 ps
CPU time 3.66 seconds
Started Jun 10 07:49:08 PM PDT 24
Finished Jun 10 07:49:15 PM PDT 24
Peak memory 232476 kb
Host smart-0020ba55-e70c-4181-84a4-19db5417ea9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567702554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3567702554
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1059438539
Short name T421
Test name
Test status
Simulation time 26274871 ps
CPU time 0.79 seconds
Started Jun 10 07:49:05 PM PDT 24
Finished Jun 10 07:49:08 PM PDT 24
Peak memory 206440 kb
Host smart-d041fcfa-0484-439a-9bef-f4b011034565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059438539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1059438539
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1981786922
Short name T44
Test name
Test status
Simulation time 7121191904 ps
CPU time 101.05 seconds
Started Jun 10 07:49:06 PM PDT 24
Finished Jun 10 07:50:49 PM PDT 24
Peak memory 240796 kb
Host smart-70b1962e-1eac-4322-b23f-a5bbd821fc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981786922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1981786922
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2911720573
Short name T233
Test name
Test status
Simulation time 10974928553 ps
CPU time 125.46 seconds
Started Jun 10 07:49:08 PM PDT 24
Finished Jun 10 07:51:17 PM PDT 24
Peak memory 249116 kb
Host smart-6ca7525a-e231-4069-9b6c-35cd0654cf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911720573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2911720573
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.600882803
Short name T808
Test name
Test status
Simulation time 3964285844 ps
CPU time 81.49 seconds
Started Jun 10 07:49:05 PM PDT 24
Finished Jun 10 07:50:29 PM PDT 24
Peak memory 257308 kb
Host smart-0b789ab2-f72f-4ab0-92ea-5c68d7250b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600882803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.600882803
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2270448238
Short name T214
Test name
Test status
Simulation time 542401744 ps
CPU time 11.72 seconds
Started Jun 10 07:49:09 PM PDT 24
Finished Jun 10 07:49:23 PM PDT 24
Peak memory 232512 kb
Host smart-23fbc303-942d-45f0-95dd-91dc83a015d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270448238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2270448238
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.365129070
Short name T773
Test name
Test status
Simulation time 250498203 ps
CPU time 2.54 seconds
Started Jun 10 07:49:10 PM PDT 24
Finished Jun 10 07:49:15 PM PDT 24
Peak memory 224280 kb
Host smart-3a5b6a47-7bcc-410a-a818-7962515736b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365129070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.365129070
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3714800150
Short name T929
Test name
Test status
Simulation time 255666103 ps
CPU time 7.12 seconds
Started Jun 10 07:49:08 PM PDT 24
Finished Jun 10 07:49:18 PM PDT 24
Peak memory 232544 kb
Host smart-60a5b023-e159-4547-b681-cc988ea9c322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714800150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3714800150
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.689981092
Short name T15
Test name
Test status
Simulation time 1056085400 ps
CPU time 5.1 seconds
Started Jun 10 07:49:08 PM PDT 24
Finished Jun 10 07:49:16 PM PDT 24
Peak memory 224308 kb
Host smart-70fe602c-05a2-4940-be12-2ce3a3195cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689981092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.689981092
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1344905737
Short name T625
Test name
Test status
Simulation time 1279630191 ps
CPU time 7.46 seconds
Started Jun 10 07:49:06 PM PDT 24
Finished Jun 10 07:49:16 PM PDT 24
Peak memory 232544 kb
Host smart-4c5506ce-315f-4a4c-bd79-7868e9890d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344905737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1344905737
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2897391456
Short name T395
Test name
Test status
Simulation time 21281224449 ps
CPU time 16.75 seconds
Started Jun 10 07:49:10 PM PDT 24
Finished Jun 10 07:49:29 PM PDT 24
Peak memory 223020 kb
Host smart-c679a4e8-5c8a-411a-b2ac-5e91368662b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2897391456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2897391456
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2408377828
Short name T927
Test name
Test status
Simulation time 24912439481 ps
CPU time 294 seconds
Started Jun 10 07:49:06 PM PDT 24
Finished Jun 10 07:54:03 PM PDT 24
Peak memory 250152 kb
Host smart-a668ba93-299f-4b3e-9758-eb528fc4b49c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408377828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2408377828
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.636469406
Short name T527
Test name
Test status
Simulation time 1206273814 ps
CPU time 4.39 seconds
Started Jun 10 07:49:06 PM PDT 24
Finished Jun 10 07:49:13 PM PDT 24
Peak memory 216072 kb
Host smart-d4c44c47-1ddd-41c7-9a36-0aef5189ea5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636469406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.636469406
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2522971843
Short name T534
Test name
Test status
Simulation time 217693894 ps
CPU time 1.15 seconds
Started Jun 10 07:49:08 PM PDT 24
Finished Jun 10 07:49:12 PM PDT 24
Peak memory 206796 kb
Host smart-48dff8d2-4da5-4333-9088-e1cf795f93fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522971843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2522971843
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2147585173
Short name T727
Test name
Test status
Simulation time 70924344 ps
CPU time 0.87 seconds
Started Jun 10 07:49:07 PM PDT 24
Finished Jun 10 07:49:11 PM PDT 24
Peak memory 206280 kb
Host smart-54c5a607-97f2-4737-a48d-ad5896a86fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147585173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2147585173
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.730206139
Short name T889
Test name
Test status
Simulation time 42329496 ps
CPU time 0.86 seconds
Started Jun 10 07:49:07 PM PDT 24
Finished Jun 10 07:49:10 PM PDT 24
Peak memory 206168 kb
Host smart-80e8e2f5-7f56-4139-a32c-22711389f66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730206139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.730206139
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.201163933
Short name T474
Test name
Test status
Simulation time 120132001 ps
CPU time 3.56 seconds
Started Jun 10 07:49:09 PM PDT 24
Finished Jun 10 07:49:15 PM PDT 24
Peak memory 232552 kb
Host smart-b681e26f-85b3-420a-9259-05c406a83126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201163933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.201163933
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2864934377
Short name T777
Test name
Test status
Simulation time 29828164 ps
CPU time 0.68 seconds
Started Jun 10 07:47:27 PM PDT 24
Finished Jun 10 07:47:30 PM PDT 24
Peak memory 205308 kb
Host smart-ecfd90dd-6b52-475e-87c6-9ea764b38e05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864934377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
864934377
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3411346018
Short name T80
Test name
Test status
Simulation time 685326186 ps
CPU time 8.5 seconds
Started Jun 10 07:47:27 PM PDT 24
Finished Jun 10 07:47:38 PM PDT 24
Peak memory 232544 kb
Host smart-3f2cd438-26ce-4765-9ec1-d932582508ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411346018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3411346018
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.859405000
Short name T618
Test name
Test status
Simulation time 161828746 ps
CPU time 0.79 seconds
Started Jun 10 07:47:25 PM PDT 24
Finished Jun 10 07:47:28 PM PDT 24
Peak memory 205304 kb
Host smart-4b3e275a-27a2-43e1-bd7a-a02df6def656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859405000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.859405000
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1372591264
Short name T312
Test name
Test status
Simulation time 16730520432 ps
CPU time 77.97 seconds
Started Jun 10 07:47:25 PM PDT 24
Finished Jun 10 07:48:45 PM PDT 24
Peak memory 236620 kb
Host smart-4c19f079-0f40-421a-940a-f629b49b3c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372591264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1372591264
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2593853106
Short name T436
Test name
Test status
Simulation time 25918351124 ps
CPU time 21.74 seconds
Started Jun 10 07:47:29 PM PDT 24
Finished Jun 10 07:47:53 PM PDT 24
Peak memory 223484 kb
Host smart-47078873-9914-4616-ae7c-e3a0e0712dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593853106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2593853106
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.14495372
Short name T946
Test name
Test status
Simulation time 25300256551 ps
CPU time 136.43 seconds
Started Jun 10 07:47:26 PM PDT 24
Finished Jun 10 07:49:44 PM PDT 24
Peak memory 254956 kb
Host smart-a494433b-7846-482d-ba40-9098f6026b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14495372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.14495372
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1401160917
Short name T621
Test name
Test status
Simulation time 78393317 ps
CPU time 5.47 seconds
Started Jun 10 07:47:25 PM PDT 24
Finished Jun 10 07:47:32 PM PDT 24
Peak memory 232748 kb
Host smart-d104cbfc-f9ef-4bf2-8bca-61b25ec550f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401160917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1401160917
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.292783077
Short name T666
Test name
Test status
Simulation time 68094582 ps
CPU time 2.3 seconds
Started Jun 10 07:47:25 PM PDT 24
Finished Jun 10 07:47:29 PM PDT 24
Peak memory 223372 kb
Host smart-85e8a89c-1262-4400-a77b-7960eaa41c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292783077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.292783077
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1257643699
Short name T650
Test name
Test status
Simulation time 2643588067 ps
CPU time 17.77 seconds
Started Jun 10 07:47:29 PM PDT 24
Finished Jun 10 07:47:49 PM PDT 24
Peak memory 232664 kb
Host smart-fedde0f5-fa62-43cd-9f9e-9cb0b471a74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257643699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1257643699
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1899469313
Short name T668
Test name
Test status
Simulation time 290249105 ps
CPU time 1.05 seconds
Started Jun 10 07:47:31 PM PDT 24
Finished Jun 10 07:47:37 PM PDT 24
Peak memory 217744 kb
Host smart-0ac3a273-0760-41de-833c-d806082aa515
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899469313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1899469313
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2721177713
Short name T792
Test name
Test status
Simulation time 620951937 ps
CPU time 4.14 seconds
Started Jun 10 07:47:27 PM PDT 24
Finished Jun 10 07:47:33 PM PDT 24
Peak memory 232484 kb
Host smart-f6c0adf0-2a24-485c-ab54-b4735b2f104d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721177713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2721177713
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3033805312
Short name T355
Test name
Test status
Simulation time 1682977308 ps
CPU time 8.44 seconds
Started Jun 10 07:47:30 PM PDT 24
Finished Jun 10 07:47:42 PM PDT 24
Peak memory 232540 kb
Host smart-58773d41-5f92-4261-9004-dd37e5c92a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033805312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3033805312
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3064889051
Short name T601
Test name
Test status
Simulation time 161253283 ps
CPU time 3.33 seconds
Started Jun 10 07:47:33 PM PDT 24
Finished Jun 10 07:47:40 PM PDT 24
Peak memory 218548 kb
Host smart-dc48e7d3-2ab8-4028-a55d-aab0b53bfadd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3064889051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3064889051
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.4076959124
Short name T158
Test name
Test status
Simulation time 11255589313 ps
CPU time 55.79 seconds
Started Jun 10 07:47:21 PM PDT 24
Finished Jun 10 07:48:19 PM PDT 24
Peak memory 249056 kb
Host smart-80128783-ab01-4f0b-9457-f4533506bfcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076959124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.4076959124
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1758887475
Short name T448
Test name
Test status
Simulation time 1055106242 ps
CPU time 17.38 seconds
Started Jun 10 07:47:24 PM PDT 24
Finished Jun 10 07:47:44 PM PDT 24
Peak memory 216348 kb
Host smart-9f3ea118-8832-42a4-b505-1f21ae3d1cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758887475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1758887475
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2333226936
Short name T445
Test name
Test status
Simulation time 187623569 ps
CPU time 1.79 seconds
Started Jun 10 07:47:23 PM PDT 24
Finished Jun 10 07:47:26 PM PDT 24
Peak memory 207728 kb
Host smart-e5d46742-7ed8-4c3c-88fb-36aaaf18210e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333226936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2333226936
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1621801293
Short name T828
Test name
Test status
Simulation time 789979949 ps
CPU time 1.1 seconds
Started Jun 10 07:47:26 PM PDT 24
Finished Jun 10 07:47:29 PM PDT 24
Peak memory 207828 kb
Host smart-c75cc9ab-f942-430e-a3ea-6f793aa7e487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621801293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1621801293
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3523909165
Short name T743
Test name
Test status
Simulation time 134546687 ps
CPU time 0.87 seconds
Started Jun 10 07:47:28 PM PDT 24
Finished Jun 10 07:47:31 PM PDT 24
Peak memory 205692 kb
Host smart-d291b9ed-cdea-40e0-8b25-7079bb0aca96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523909165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3523909165
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.913817470
Short name T299
Test name
Test status
Simulation time 13308140870 ps
CPU time 13.91 seconds
Started Jun 10 07:47:27 PM PDT 24
Finished Jun 10 07:47:43 PM PDT 24
Peak memory 232564 kb
Host smart-b5f84b60-4614-41d0-bfe9-3d404576650d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913817470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.913817470
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.262723645
Short name T893
Test name
Test status
Simulation time 13101754 ps
CPU time 0.76 seconds
Started Jun 10 07:49:15 PM PDT 24
Finished Jun 10 07:49:18 PM PDT 24
Peak memory 205616 kb
Host smart-f36ae9a2-c19d-4782-bef8-61f2781ed7fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262723645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.262723645
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3804952597
Short name T676
Test name
Test status
Simulation time 839993357 ps
CPU time 2.3 seconds
Started Jun 10 07:49:18 PM PDT 24
Finished Jun 10 07:49:23 PM PDT 24
Peak memory 224272 kb
Host smart-9f2b8159-11f5-443a-b51e-885b2cd04f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804952597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3804952597
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1544586344
Short name T672
Test name
Test status
Simulation time 63787167 ps
CPU time 0.82 seconds
Started Jun 10 07:49:06 PM PDT 24
Finished Jun 10 07:49:10 PM PDT 24
Peak memory 206348 kb
Host smart-636ea956-4a9a-4a23-993f-979eab3f5b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544586344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1544586344
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3788236764
Short name T277
Test name
Test status
Simulation time 148341234461 ps
CPU time 147.96 seconds
Started Jun 10 07:49:21 PM PDT 24
Finished Jun 10 07:51:51 PM PDT 24
Peak memory 254208 kb
Host smart-c704692f-e433-46d4-a6e0-22d3d71c3dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788236764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3788236764
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.584447573
Short name T582
Test name
Test status
Simulation time 427199810603 ps
CPU time 224.46 seconds
Started Jun 10 07:49:21 PM PDT 24
Finished Jun 10 07:53:07 PM PDT 24
Peak memory 255864 kb
Host smart-ed90e93b-5dc1-465e-afca-f8e633ceacaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584447573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.584447573
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3435114723
Short name T42
Test name
Test status
Simulation time 7131429575 ps
CPU time 141.78 seconds
Started Jun 10 07:49:15 PM PDT 24
Finished Jun 10 07:51:39 PM PDT 24
Peak memory 265512 kb
Host smart-a355f68c-bfcc-440d-aaab-71b249a64096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435114723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3435114723
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3777831741
Short name T376
Test name
Test status
Simulation time 377341523 ps
CPU time 6.88 seconds
Started Jun 10 07:49:15 PM PDT 24
Finished Jun 10 07:49:24 PM PDT 24
Peak memory 224320 kb
Host smart-4634773a-f33d-43c8-8189-0bd1312e779b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777831741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3777831741
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1860847259
Short name T294
Test name
Test status
Simulation time 438420209 ps
CPU time 3.78 seconds
Started Jun 10 07:49:20 PM PDT 24
Finished Jun 10 07:49:26 PM PDT 24
Peak memory 224296 kb
Host smart-44614b58-4c12-4cd2-9264-4354423f43f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860847259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1860847259
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3673419845
Short name T13
Test name
Test status
Simulation time 17339672205 ps
CPU time 48.82 seconds
Started Jun 10 07:49:16 PM PDT 24
Finished Jun 10 07:50:07 PM PDT 24
Peak memory 232652 kb
Host smart-2287aa60-123a-464a-bf57-5d5c33fbb661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673419845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3673419845
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2638680119
Short name T276
Test name
Test status
Simulation time 7644071381 ps
CPU time 14.37 seconds
Started Jun 10 07:49:08 PM PDT 24
Finished Jun 10 07:49:25 PM PDT 24
Peak memory 232656 kb
Host smart-de7c3498-07f7-4ce5-876b-c04f2c2520df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638680119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2638680119
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2301433572
Short name T488
Test name
Test status
Simulation time 261352461 ps
CPU time 3.33 seconds
Started Jun 10 07:49:05 PM PDT 24
Finished Jun 10 07:49:10 PM PDT 24
Peak memory 224260 kb
Host smart-a0177564-8291-4060-ac98-bb2a744377d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301433572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2301433572
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2836300167
Short name T700
Test name
Test status
Simulation time 309448410 ps
CPU time 6.14 seconds
Started Jun 10 07:49:16 PM PDT 24
Finished Jun 10 07:49:24 PM PDT 24
Peak memory 222628 kb
Host smart-5d12a48c-4e09-44c8-ba95-8e2ddebf9ad3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2836300167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2836300167
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.903478675
Short name T577
Test name
Test status
Simulation time 80418850699 ps
CPU time 186.26 seconds
Started Jun 10 07:49:18 PM PDT 24
Finished Jun 10 07:52:27 PM PDT 24
Peak memory 249872 kb
Host smart-3337d7ad-290e-4fa8-9529-1d46ad84cb4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903478675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.903478675
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1506062216
Short name T810
Test name
Test status
Simulation time 6489949482 ps
CPU time 14.89 seconds
Started Jun 10 07:49:07 PM PDT 24
Finished Jun 10 07:49:25 PM PDT 24
Peak memory 216200 kb
Host smart-58449c32-4e3b-4f0e-99dc-d053fb2276d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506062216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1506062216
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.215924578
Short name T617
Test name
Test status
Simulation time 21537871 ps
CPU time 0.69 seconds
Started Jun 10 07:49:06 PM PDT 24
Finished Jun 10 07:49:10 PM PDT 24
Peak memory 205488 kb
Host smart-9e3c2fd8-16cb-4865-969b-985102e70b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215924578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.215924578
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.132066529
Short name T941
Test name
Test status
Simulation time 306966899 ps
CPU time 1.58 seconds
Started Jun 10 07:49:05 PM PDT 24
Finished Jun 10 07:49:08 PM PDT 24
Peak memory 216144 kb
Host smart-2b92cf41-2177-43a2-b5a1-1a518c3635c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132066529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.132066529
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3744440284
Short name T899
Test name
Test status
Simulation time 110102212 ps
CPU time 0.99 seconds
Started Jun 10 07:49:05 PM PDT 24
Finished Jun 10 07:49:08 PM PDT 24
Peak memory 205676 kb
Host smart-dd20fd1c-03d0-4956-9bba-ddd18634423f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744440284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3744440284
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1999379225
Short name T251
Test name
Test status
Simulation time 14630894026 ps
CPU time 15.2 seconds
Started Jun 10 07:49:19 PM PDT 24
Finished Jun 10 07:49:37 PM PDT 24
Peak memory 232576 kb
Host smart-9355363e-1221-4ac4-90ba-75c46d4db399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999379225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1999379225
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.53619459
Short name T919
Test name
Test status
Simulation time 107013613 ps
CPU time 0.71 seconds
Started Jun 10 07:49:20 PM PDT 24
Finished Jun 10 07:49:23 PM PDT 24
Peak memory 205288 kb
Host smart-da4218df-1731-4de4-93a3-5e488b4e3499
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53619459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.53619459
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3118637790
Short name T550
Test name
Test status
Simulation time 341578031 ps
CPU time 5.42 seconds
Started Jun 10 07:49:17 PM PDT 24
Finished Jun 10 07:49:26 PM PDT 24
Peak memory 224376 kb
Host smart-ae5481dc-9e4b-40cf-81d2-c877a65f77d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118637790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3118637790
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.796431171
Short name T396
Test name
Test status
Simulation time 15966716 ps
CPU time 0.78 seconds
Started Jun 10 07:49:15 PM PDT 24
Finished Jun 10 07:49:18 PM PDT 24
Peak memory 206372 kb
Host smart-d9e3bed5-704f-423b-87d1-00ed1285315a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796431171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.796431171
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3970765359
Short name T675
Test name
Test status
Simulation time 3229880277 ps
CPU time 45.28 seconds
Started Jun 10 07:49:19 PM PDT 24
Finished Jun 10 07:50:07 PM PDT 24
Peak memory 249036 kb
Host smart-cf7d6445-813d-452c-b6ca-a242bcdbc2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970765359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3970765359
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3398694343
Short name T65
Test name
Test status
Simulation time 104502996732 ps
CPU time 241.88 seconds
Started Jun 10 07:49:17 PM PDT 24
Finished Jun 10 07:53:21 PM PDT 24
Peak memory 249436 kb
Host smart-8643b7a9-2abb-45fc-94a0-552f5a4ba069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398694343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3398694343
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2929858910
Short name T199
Test name
Test status
Simulation time 33502275086 ps
CPU time 160.99 seconds
Started Jun 10 07:49:17 PM PDT 24
Finished Jun 10 07:52:01 PM PDT 24
Peak memory 237048 kb
Host smart-ff89c88a-df57-4291-9d6a-493606cdf499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929858910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2929858910
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1961379877
Short name T346
Test name
Test status
Simulation time 483331028 ps
CPU time 3.54 seconds
Started Jun 10 07:49:17 PM PDT 24
Finished Jun 10 07:49:24 PM PDT 24
Peak memory 232528 kb
Host smart-eed6a79a-8900-4adb-9202-3152a237d7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961379877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1961379877
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1380287653
Short name T250
Test name
Test status
Simulation time 1028883664 ps
CPU time 7.26 seconds
Started Jun 10 07:49:18 PM PDT 24
Finished Jun 10 07:49:29 PM PDT 24
Peak memory 232620 kb
Host smart-24f25aa9-3ba2-4467-a972-b7f92faa9baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380287653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1380287653
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2518935200
Short name T554
Test name
Test status
Simulation time 302466459 ps
CPU time 2.28 seconds
Started Jun 10 07:49:17 PM PDT 24
Finished Jun 10 07:49:23 PM PDT 24
Peak memory 222552 kb
Host smart-8ebe67ab-3b7c-4e9b-9950-d0c572f42960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518935200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2518935200
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2720327225
Short name T494
Test name
Test status
Simulation time 391659553 ps
CPU time 3.64 seconds
Started Jun 10 07:49:16 PM PDT 24
Finished Jun 10 07:49:22 PM PDT 24
Peak memory 232528 kb
Host smart-337a0388-432b-401b-8209-378f04fe2156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720327225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2720327225
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3440697805
Short name T895
Test name
Test status
Simulation time 702874995 ps
CPU time 6.79 seconds
Started Jun 10 07:49:16 PM PDT 24
Finished Jun 10 07:49:26 PM PDT 24
Peak memory 224304 kb
Host smart-909e7c30-efa6-4f65-bb3e-be27eb088753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440697805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3440697805
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2497649306
Short name T613
Test name
Test status
Simulation time 329287620 ps
CPU time 5.72 seconds
Started Jun 10 07:49:15 PM PDT 24
Finished Jun 10 07:49:23 PM PDT 24
Peak memory 219124 kb
Host smart-eb7c5ebb-6579-44e5-a09c-0ad0f5968cc2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2497649306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2497649306
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2396919488
Short name T533
Test name
Test status
Simulation time 200319595 ps
CPU time 1.22 seconds
Started Jun 10 07:49:16 PM PDT 24
Finished Jun 10 07:49:20 PM PDT 24
Peak memory 206796 kb
Host smart-ec6bd488-abd2-4068-b503-0169637a1edd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396919488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2396919488
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3005674762
Short name T614
Test name
Test status
Simulation time 70729643672 ps
CPU time 47.16 seconds
Started Jun 10 07:49:16 PM PDT 24
Finished Jun 10 07:50:05 PM PDT 24
Peak memory 216204 kb
Host smart-63ac5866-cf20-4c71-a92f-4f89ca0688ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005674762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3005674762
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.435098196
Short name T820
Test name
Test status
Simulation time 15102284704 ps
CPU time 21.63 seconds
Started Jun 10 07:49:18 PM PDT 24
Finished Jun 10 07:49:43 PM PDT 24
Peak memory 216184 kb
Host smart-d28b8d33-1d8f-4691-96a0-84cb9f2dc59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435098196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.435098196
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2113028192
Short name T703
Test name
Test status
Simulation time 99786829 ps
CPU time 1.68 seconds
Started Jun 10 07:49:15 PM PDT 24
Finished Jun 10 07:49:19 PM PDT 24
Peak memory 216100 kb
Host smart-871e183d-9cd7-4a4a-b31d-0d97bed8f34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113028192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2113028192
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1813146641
Short name T420
Test name
Test status
Simulation time 64307850 ps
CPU time 0.88 seconds
Started Jun 10 07:49:17 PM PDT 24
Finished Jun 10 07:49:20 PM PDT 24
Peak memory 205748 kb
Host smart-f13f9c04-d46b-48d0-9c0a-d5845545ae05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813146641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1813146641
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2885543784
Short name T470
Test name
Test status
Simulation time 7217241859 ps
CPU time 25.64 seconds
Started Jun 10 07:49:20 PM PDT 24
Finished Jun 10 07:49:48 PM PDT 24
Peak memory 229264 kb
Host smart-a0fbc7cf-9bb6-4d55-9789-75f9b302067f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885543784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2885543784
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.255614035
Short name T745
Test name
Test status
Simulation time 24786451 ps
CPU time 0.71 seconds
Started Jun 10 07:49:34 PM PDT 24
Finished Jun 10 07:49:38 PM PDT 24
Peak memory 204748 kb
Host smart-02a3ce22-2ef4-4996-b300-dddbf3a83d35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255614035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.255614035
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.874506032
Short name T615
Test name
Test status
Simulation time 940476017 ps
CPU time 5.82 seconds
Started Jun 10 07:49:18 PM PDT 24
Finished Jun 10 07:49:27 PM PDT 24
Peak memory 224324 kb
Host smart-b71ab295-9153-4842-a120-e371c21c28a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874506032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.874506032
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2118426937
Short name T755
Test name
Test status
Simulation time 20844453 ps
CPU time 0.81 seconds
Started Jun 10 07:49:16 PM PDT 24
Finished Jun 10 07:49:19 PM PDT 24
Peak memory 206316 kb
Host smart-163c9e37-d9b4-4b4c-b19e-587a8407a747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118426937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2118426937
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.4180093750
Short name T686
Test name
Test status
Simulation time 13068501324 ps
CPU time 60.69 seconds
Started Jun 10 07:49:16 PM PDT 24
Finished Jun 10 07:50:20 PM PDT 24
Peak memory 251728 kb
Host smart-b452d2b0-15f2-47da-8410-2c8cd910255d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180093750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.4180093750
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3358445864
Short name T976
Test name
Test status
Simulation time 38819770805 ps
CPU time 280.04 seconds
Started Jun 10 07:49:19 PM PDT 24
Finished Jun 10 07:54:02 PM PDT 24
Peak memory 255304 kb
Host smart-3327aa07-ca90-4419-a0a5-1618ce81590a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358445864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3358445864
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3561253058
Short name T736
Test name
Test status
Simulation time 42303209568 ps
CPU time 128.39 seconds
Started Jun 10 07:49:33 PM PDT 24
Finished Jun 10 07:51:44 PM PDT 24
Peak memory 249056 kb
Host smart-570b75c3-7355-4e28-b16b-6304f2535a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561253058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3561253058
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2736421647
Short name T956
Test name
Test status
Simulation time 1292174785 ps
CPU time 15.87 seconds
Started Jun 10 07:49:18 PM PDT 24
Finished Jun 10 07:49:37 PM PDT 24
Peak memory 224296 kb
Host smart-30567269-d6ad-4a55-9c8a-f96dc7c1d34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736421647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2736421647
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1571041490
Short name T218
Test name
Test status
Simulation time 119204383 ps
CPU time 3.62 seconds
Started Jun 10 07:49:15 PM PDT 24
Finished Jun 10 07:49:21 PM PDT 24
Peak memory 224256 kb
Host smart-2c9d24f1-c8f7-423f-ad2b-3e8dc53063f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571041490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1571041490
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3543529535
Short name T197
Test name
Test status
Simulation time 53465016250 ps
CPU time 146.92 seconds
Started Jun 10 07:49:18 PM PDT 24
Finished Jun 10 07:51:48 PM PDT 24
Peak memory 232692 kb
Host smart-97ca475c-665f-4452-b9ac-82f72a686bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543529535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3543529535
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1993208219
Short name T280
Test name
Test status
Simulation time 1918270449 ps
CPU time 4.6 seconds
Started Jun 10 07:49:17 PM PDT 24
Finished Jun 10 07:49:25 PM PDT 24
Peak memory 240448 kb
Host smart-9850e526-df79-4e5b-8a27-40ec66393b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993208219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1993208219
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2668849509
Short name T840
Test name
Test status
Simulation time 352685489 ps
CPU time 6.07 seconds
Started Jun 10 07:49:17 PM PDT 24
Finished Jun 10 07:49:26 PM PDT 24
Peak memory 224220 kb
Host smart-95a8bff3-215f-41c1-a5a4-5025165508d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668849509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2668849509
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1810108902
Short name T826
Test name
Test status
Simulation time 709399306 ps
CPU time 7.59 seconds
Started Jun 10 07:49:18 PM PDT 24
Finished Jun 10 07:49:29 PM PDT 24
Peak memory 220364 kb
Host smart-e62afa1b-8f53-4dd7-b2c3-c87648e018f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1810108902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1810108902
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2164316187
Short name T910
Test name
Test status
Simulation time 36136539 ps
CPU time 0.97 seconds
Started Jun 10 07:49:26 PM PDT 24
Finished Jun 10 07:49:28 PM PDT 24
Peak memory 206400 kb
Host smart-ba19e953-bdae-4a93-a72a-9038da0f8431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164316187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2164316187
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2564783121
Short name T936
Test name
Test status
Simulation time 3756598587 ps
CPU time 23.64 seconds
Started Jun 10 07:49:17 PM PDT 24
Finished Jun 10 07:49:44 PM PDT 24
Peak memory 216212 kb
Host smart-d9c38b4e-ffa9-4b0c-854c-4b395ddf7f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564783121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2564783121
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3788788664
Short name T349
Test name
Test status
Simulation time 5470421715 ps
CPU time 16.47 seconds
Started Jun 10 07:49:18 PM PDT 24
Finished Jun 10 07:49:38 PM PDT 24
Peak memory 216140 kb
Host smart-9458aa2a-38ef-4fa7-8bc0-fd9b1f82b935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788788664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3788788664
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3644385146
Short name T359
Test name
Test status
Simulation time 19196130 ps
CPU time 0.75 seconds
Started Jun 10 07:49:22 PM PDT 24
Finished Jun 10 07:49:24 PM PDT 24
Peak memory 205708 kb
Host smart-ae0aefd0-b4a9-4cd4-a687-cc0f54f41b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644385146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3644385146
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3741098768
Short name T381
Test name
Test status
Simulation time 47089885 ps
CPU time 0.79 seconds
Started Jun 10 07:49:18 PM PDT 24
Finished Jun 10 07:49:22 PM PDT 24
Peak memory 205680 kb
Host smart-e9339e25-7213-4b19-ab54-d58a6ce48b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741098768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3741098768
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2891406321
Short name T268
Test name
Test status
Simulation time 4870735220 ps
CPU time 19.94 seconds
Started Jun 10 07:49:16 PM PDT 24
Finished Jun 10 07:49:38 PM PDT 24
Peak memory 232656 kb
Host smart-67639851-fd8a-458e-88a3-08103fbef84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891406321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2891406321
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.741159462
Short name T916
Test name
Test status
Simulation time 24185666 ps
CPU time 0.75 seconds
Started Jun 10 07:49:31 PM PDT 24
Finished Jun 10 07:49:34 PM PDT 24
Peak memory 205384 kb
Host smart-74dadbb4-d80e-4bf0-aec6-cb8582fc1236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741159462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.741159462
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2774459318
Short name T81
Test name
Test status
Simulation time 969882274 ps
CPU time 9.73 seconds
Started Jun 10 07:49:27 PM PDT 24
Finished Jun 10 07:49:38 PM PDT 24
Peak memory 232520 kb
Host smart-f51a0cd4-8947-40e5-a39b-48d8a41be9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774459318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2774459318
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.149023509
Short name T562
Test name
Test status
Simulation time 48883314 ps
CPU time 0.85 seconds
Started Jun 10 07:49:28 PM PDT 24
Finished Jun 10 07:49:31 PM PDT 24
Peak memory 206328 kb
Host smart-d8083f6e-6e96-47bd-9bf2-9f2321b85d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149023509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.149023509
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2981055825
Short name T965
Test name
Test status
Simulation time 3084866983 ps
CPU time 28.94 seconds
Started Jun 10 07:49:31 PM PDT 24
Finished Jun 10 07:50:03 PM PDT 24
Peak memory 249504 kb
Host smart-6142cbbd-892e-4451-a24e-89051408f14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981055825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2981055825
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1092025300
Short name T591
Test name
Test status
Simulation time 3313796300 ps
CPU time 49.64 seconds
Started Jun 10 07:49:30 PM PDT 24
Finished Jun 10 07:50:23 PM PDT 24
Peak memory 240916 kb
Host smart-4360702d-3c7c-4178-b28d-9667bcbcb334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092025300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1092025300
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2480126389
Short name T718
Test name
Test status
Simulation time 628782950 ps
CPU time 7.05 seconds
Started Jun 10 07:49:33 PM PDT 24
Finished Jun 10 07:49:43 PM PDT 24
Peak memory 233432 kb
Host smart-57dee062-c959-47e4-ac5a-b157ea8ab1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480126389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2480126389
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1514054913
Short name T822
Test name
Test status
Simulation time 3781345214 ps
CPU time 19.47 seconds
Started Jun 10 07:49:24 PM PDT 24
Finished Jun 10 07:49:45 PM PDT 24
Peak memory 232704 kb
Host smart-819e8173-56dd-493d-b5c4-e66a7c0610cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514054913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1514054913
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3043503944
Short name T287
Test name
Test status
Simulation time 35391553980 ps
CPU time 81.59 seconds
Started Jun 10 07:49:31 PM PDT 24
Finished Jun 10 07:50:55 PM PDT 24
Peak memory 240832 kb
Host smart-d38e30b6-d874-420e-8320-ff5b494a5cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043503944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3043503944
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3280382017
Short name T283
Test name
Test status
Simulation time 2387925452 ps
CPU time 9.08 seconds
Started Jun 10 07:49:32 PM PDT 24
Finished Jun 10 07:49:44 PM PDT 24
Peak memory 224344 kb
Host smart-8d16defd-602a-4a96-ba7c-186641fa46ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280382017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3280382017
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3938668481
Short name T644
Test name
Test status
Simulation time 91444728 ps
CPU time 2.39 seconds
Started Jun 10 07:49:30 PM PDT 24
Finished Jun 10 07:49:35 PM PDT 24
Peak memory 224392 kb
Host smart-61bb35e6-245d-4077-b42f-326bc03b4a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938668481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3938668481
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4070026663
Short name T772
Test name
Test status
Simulation time 3459172879 ps
CPU time 15.16 seconds
Started Jun 10 07:49:29 PM PDT 24
Finished Jun 10 07:49:47 PM PDT 24
Peak memory 222412 kb
Host smart-7471ca95-fdb4-47cc-9629-ffbc7f952967
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4070026663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4070026663
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2356376324
Short name T539
Test name
Test status
Simulation time 4931862329 ps
CPU time 31.77 seconds
Started Jun 10 07:49:30 PM PDT 24
Finished Jun 10 07:50:05 PM PDT 24
Peak memory 216220 kb
Host smart-f96ed366-eed5-49ee-ab2a-0dfdb3a31e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356376324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2356376324
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.556821436
Short name T944
Test name
Test status
Simulation time 3297268156 ps
CPU time 11.71 seconds
Started Jun 10 07:49:31 PM PDT 24
Finished Jun 10 07:49:46 PM PDT 24
Peak memory 216128 kb
Host smart-41580451-0f6b-4a9e-8766-cca427d68a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556821436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.556821436
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.989235166
Short name T343
Test name
Test status
Simulation time 136702785 ps
CPU time 2.38 seconds
Started Jun 10 07:49:28 PM PDT 24
Finished Jun 10 07:49:32 PM PDT 24
Peak memory 216040 kb
Host smart-302b12a7-3145-4ae5-aeb0-5492d17cecf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989235166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.989235166
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.963520717
Short name T402
Test name
Test status
Simulation time 25709628 ps
CPU time 0.77 seconds
Started Jun 10 07:49:28 PM PDT 24
Finished Jun 10 07:49:31 PM PDT 24
Peak memory 205676 kb
Host smart-1bedf1c7-88a8-4209-910d-ad15b337e631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963520717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.963520717
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2494829007
Short name T759
Test name
Test status
Simulation time 56229504 ps
CPU time 2.27 seconds
Started Jun 10 07:49:25 PM PDT 24
Finished Jun 10 07:49:29 PM PDT 24
Peak memory 224152 kb
Host smart-0248e4c0-319f-40cc-bb0c-53d4457db418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494829007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2494829007
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1085625624
Short name T405
Test name
Test status
Simulation time 23265744 ps
CPU time 0.69 seconds
Started Jun 10 07:49:36 PM PDT 24
Finished Jun 10 07:49:40 PM PDT 24
Peak memory 205628 kb
Host smart-95c70af1-8977-4ae3-b604-98e37c100424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085625624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1085625624
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2017946776
Short name T293
Test name
Test status
Simulation time 199995221 ps
CPU time 3.07 seconds
Started Jun 10 07:49:24 PM PDT 24
Finished Jun 10 07:49:29 PM PDT 24
Peak memory 224264 kb
Host smart-0d42f167-d365-4fdd-8546-eedd9c646e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017946776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2017946776
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3664972058
Short name T548
Test name
Test status
Simulation time 56205797 ps
CPU time 0.82 seconds
Started Jun 10 07:49:34 PM PDT 24
Finished Jun 10 07:49:37 PM PDT 24
Peak memory 206368 kb
Host smart-58f30c8a-4f92-462a-9e4e-0a0df525c53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664972058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3664972058
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3721131823
Short name T195
Test name
Test status
Simulation time 2545096637 ps
CPU time 53.42 seconds
Started Jun 10 07:49:23 PM PDT 24
Finished Jun 10 07:50:18 PM PDT 24
Peak memory 256656 kb
Host smart-56560636-c714-46fe-bec7-1ceba50a6333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721131823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3721131823
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1041385017
Short name T242
Test name
Test status
Simulation time 744150061278 ps
CPU time 727.23 seconds
Started Jun 10 07:49:27 PM PDT 24
Finished Jun 10 08:01:36 PM PDT 24
Peak memory 265480 kb
Host smart-cf14fc19-2f13-4fc5-a592-4d10b1265b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041385017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1041385017
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3501190723
Short name T194
Test name
Test status
Simulation time 2633232933 ps
CPU time 71.75 seconds
Started Jun 10 07:49:31 PM PDT 24
Finished Jun 10 07:50:45 PM PDT 24
Peak memory 250080 kb
Host smart-740b84d3-4906-4e6d-8b0b-6b7e5b21c132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501190723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3501190723
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.153372783
Short name T823
Test name
Test status
Simulation time 417016569 ps
CPU time 6.69 seconds
Started Jun 10 07:49:26 PM PDT 24
Finished Jun 10 07:49:34 PM PDT 24
Peak memory 224388 kb
Host smart-5ab64ae8-1288-4fd6-9dad-df2da19656b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153372783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.153372783
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2555084127
Short name T356
Test name
Test status
Simulation time 31434894 ps
CPU time 2.58 seconds
Started Jun 10 07:49:22 PM PDT 24
Finished Jun 10 07:49:27 PM PDT 24
Peak memory 232340 kb
Host smart-097dd545-0287-4d9c-b820-079fd309712d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555084127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2555084127
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2301857254
Short name T905
Test name
Test status
Simulation time 2328341380 ps
CPU time 10.03 seconds
Started Jun 10 07:49:36 PM PDT 24
Finished Jun 10 07:49:50 PM PDT 24
Peak memory 240752 kb
Host smart-1db44428-c100-4954-87e9-08b347245082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301857254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2301857254
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3803646950
Short name T684
Test name
Test status
Simulation time 3883207035 ps
CPU time 3.39 seconds
Started Jun 10 07:49:29 PM PDT 24
Finished Jun 10 07:49:35 PM PDT 24
Peak memory 224372 kb
Host smart-86a424df-6532-4592-858f-f58c3c0b1595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803646950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3803646950
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2492387289
Short name T612
Test name
Test status
Simulation time 1145882878 ps
CPU time 2.19 seconds
Started Jun 10 07:49:31 PM PDT 24
Finished Jun 10 07:49:36 PM PDT 24
Peak memory 224216 kb
Host smart-efb29b32-3d9a-4bc4-bee2-85169ed41c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492387289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2492387289
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3721880976
Short name T739
Test name
Test status
Simulation time 259235030 ps
CPU time 4.25 seconds
Started Jun 10 07:49:38 PM PDT 24
Finished Jun 10 07:49:46 PM PDT 24
Peak memory 219872 kb
Host smart-91180f5c-ac63-489b-8aff-bb6598372c38
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3721880976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3721880976
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2644038138
Short name T725
Test name
Test status
Simulation time 189205157 ps
CPU time 0.98 seconds
Started Jun 10 07:49:29 PM PDT 24
Finished Jun 10 07:49:33 PM PDT 24
Peak memory 206648 kb
Host smart-9e5becf7-ec07-468d-82a0-c6a17b314a9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644038138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2644038138
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.365709225
Short name T636
Test name
Test status
Simulation time 4701862777 ps
CPU time 26.7 seconds
Started Jun 10 07:49:32 PM PDT 24
Finished Jun 10 07:50:01 PM PDT 24
Peak memory 216196 kb
Host smart-b4338c98-c350-47f1-b3a0-159cd936aa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365709225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.365709225
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2290869864
Short name T814
Test name
Test status
Simulation time 696055046 ps
CPU time 5.57 seconds
Started Jun 10 07:49:31 PM PDT 24
Finished Jun 10 07:49:39 PM PDT 24
Peak memory 216016 kb
Host smart-3daaf438-f14f-40b4-8f4b-6fdf6630c644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290869864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2290869864
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1700837999
Short name T374
Test name
Test status
Simulation time 49992068 ps
CPU time 1.35 seconds
Started Jun 10 07:49:26 PM PDT 24
Finished Jun 10 07:49:29 PM PDT 24
Peak memory 216076 kb
Host smart-4d6ad454-4f78-4a97-937a-b0d762e92ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700837999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1700837999
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3497255592
Short name T697
Test name
Test status
Simulation time 356404981 ps
CPU time 1.02 seconds
Started Jun 10 07:49:27 PM PDT 24
Finished Jun 10 07:49:30 PM PDT 24
Peak memory 205704 kb
Host smart-170be2c7-8044-4221-b73c-6ad2f0e30f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497255592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3497255592
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.214395780
Short name T620
Test name
Test status
Simulation time 21540505247 ps
CPU time 18.28 seconds
Started Jun 10 07:49:32 PM PDT 24
Finished Jun 10 07:49:53 PM PDT 24
Peak memory 224372 kb
Host smart-3cde9569-4804-4a19-89af-d6eda85bfe15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214395780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.214395780
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.4028657313
Short name T503
Test name
Test status
Simulation time 22864234 ps
CPU time 0.71 seconds
Started Jun 10 07:49:32 PM PDT 24
Finished Jun 10 07:49:35 PM PDT 24
Peak memory 205276 kb
Host smart-96135a86-b386-4fac-8bff-bb22fc20d7fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028657313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4028657313
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1276219519
Short name T887
Test name
Test status
Simulation time 687994453 ps
CPU time 3.28 seconds
Started Jun 10 07:49:34 PM PDT 24
Finished Jun 10 07:49:40 PM PDT 24
Peak memory 232524 kb
Host smart-90ae9b2a-fd1a-4e44-8ec2-ff816cf824db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276219519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1276219519
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3413332115
Short name T891
Test name
Test status
Simulation time 29444857 ps
CPU time 0.78 seconds
Started Jun 10 07:49:26 PM PDT 24
Finished Jun 10 07:49:28 PM PDT 24
Peak memory 206388 kb
Host smart-eef50569-2746-4460-b36a-ca49ad7c045c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413332115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3413332115
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3658465010
Short name T309
Test name
Test status
Simulation time 20568886959 ps
CPU time 148.85 seconds
Started Jun 10 07:49:31 PM PDT 24
Finished Jun 10 07:52:03 PM PDT 24
Peak memory 254212 kb
Host smart-1a37e99e-9ac1-4890-bd5d-22d08300f079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658465010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3658465010
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.410094436
Short name T207
Test name
Test status
Simulation time 141720055821 ps
CPU time 362.16 seconds
Started Jun 10 07:49:33 PM PDT 24
Finished Jun 10 07:55:38 PM PDT 24
Peak memory 254964 kb
Host smart-612f46a6-a579-44a2-8366-e9e2f26e989e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410094436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.410094436
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1484096674
Short name T155
Test name
Test status
Simulation time 2985272888 ps
CPU time 9.43 seconds
Started Jun 10 07:49:31 PM PDT 24
Finished Jun 10 07:49:43 PM PDT 24
Peak memory 232684 kb
Host smart-76817ddc-66b0-4bd1-8f48-fc39dce83b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484096674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1484096674
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.4132489672
Short name T184
Test name
Test status
Simulation time 1768948232 ps
CPU time 8.92 seconds
Started Jun 10 07:49:33 PM PDT 24
Finished Jun 10 07:49:45 PM PDT 24
Peak memory 232528 kb
Host smart-86761585-4219-4711-92db-9732c4b3be4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132489672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.4132489672
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3920287450
Short name T785
Test name
Test status
Simulation time 1248640273 ps
CPU time 7.68 seconds
Started Jun 10 07:49:24 PM PDT 24
Finished Jun 10 07:49:34 PM PDT 24
Peak memory 232492 kb
Host smart-1338dc53-2b22-497e-85af-892bf854302a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920287450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3920287450
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3711175673
Short name T234
Test name
Test status
Simulation time 7058980420 ps
CPU time 9.68 seconds
Started Jun 10 07:49:25 PM PDT 24
Finished Jun 10 07:49:36 PM PDT 24
Peak memory 232692 kb
Host smart-db1e4ea5-9bd7-4568-b420-1ced352c01a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711175673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3711175673
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3408742128
Short name T135
Test name
Test status
Simulation time 786799112 ps
CPU time 6.66 seconds
Started Jun 10 07:49:36 PM PDT 24
Finished Jun 10 07:49:47 PM PDT 24
Peak memory 222740 kb
Host smart-9c08faf2-5783-4bcf-8106-7640eea6a949
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3408742128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3408742128
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4228345508
Short name T861
Test name
Test status
Simulation time 6828481566 ps
CPU time 24.5 seconds
Started Jun 10 07:49:31 PM PDT 24
Finished Jun 10 07:49:58 PM PDT 24
Peak memory 216376 kb
Host smart-6428868f-bf56-4909-b6f1-9d30d1f9a23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228345508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4228345508
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3623432790
Short name T830
Test name
Test status
Simulation time 17039874569 ps
CPU time 13.43 seconds
Started Jun 10 07:49:26 PM PDT 24
Finished Jun 10 07:49:41 PM PDT 24
Peak memory 216144 kb
Host smart-dd1af038-a182-4e25-b4e5-3ac943c14b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623432790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3623432790
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2777938712
Short name T433
Test name
Test status
Simulation time 182687731 ps
CPU time 4.95 seconds
Started Jun 10 07:49:23 PM PDT 24
Finished Jun 10 07:49:30 PM PDT 24
Peak memory 216408 kb
Host smart-d2f8dbf6-845a-4cc9-ae45-445c5a94fc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777938712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2777938712
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1703329163
Short name T804
Test name
Test status
Simulation time 25309544 ps
CPU time 0.7 seconds
Started Jun 10 07:49:34 PM PDT 24
Finished Jun 10 07:49:38 PM PDT 24
Peak memory 205720 kb
Host smart-93ecf87b-1afb-40e0-99c0-358ea68c14b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703329163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1703329163
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3856875360
Short name T680
Test name
Test status
Simulation time 2568759551 ps
CPU time 5.25 seconds
Started Jun 10 07:49:33 PM PDT 24
Finished Jun 10 07:49:41 PM PDT 24
Peak memory 232648 kb
Host smart-57021ed8-e024-4108-8936-fa93ec1966e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856875360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3856875360
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3692309329
Short name T407
Test name
Test status
Simulation time 24075686 ps
CPU time 0.74 seconds
Started Jun 10 07:49:35 PM PDT 24
Finished Jun 10 07:49:39 PM PDT 24
Peak memory 205296 kb
Host smart-1afce3a2-88bb-4d72-adea-3f05e7255484
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692309329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3692309329
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2448725493
Short name T939
Test name
Test status
Simulation time 32968207 ps
CPU time 2.13 seconds
Started Jun 10 07:49:33 PM PDT 24
Finished Jun 10 07:49:38 PM PDT 24
Peak memory 224260 kb
Host smart-8d6a1688-097a-419a-a9c8-29287e887775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448725493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2448725493
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2898576808
Short name T923
Test name
Test status
Simulation time 51138066 ps
CPU time 0.77 seconds
Started Jun 10 07:49:29 PM PDT 24
Finished Jun 10 07:49:32 PM PDT 24
Peak memory 206320 kb
Host smart-9d515b03-128e-45d2-ae68-d89afe523ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898576808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2898576808
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.316240616
Short name T696
Test name
Test status
Simulation time 13294828374 ps
CPU time 53.3 seconds
Started Jun 10 07:49:32 PM PDT 24
Finished Jun 10 07:50:28 PM PDT 24
Peak memory 249016 kb
Host smart-1c8f5b06-bc47-4071-bc41-8eea43d52eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316240616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.316240616
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1187469983
Short name T681
Test name
Test status
Simulation time 12349847065 ps
CPU time 74.14 seconds
Started Jun 10 07:49:37 PM PDT 24
Finished Jun 10 07:50:56 PM PDT 24
Peak memory 240416 kb
Host smart-a5526076-5849-42d2-bddb-336d9efa40a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187469983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1187469983
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3791365522
Short name T37
Test name
Test status
Simulation time 19719969583 ps
CPU time 81.29 seconds
Started Jun 10 07:49:39 PM PDT 24
Finished Jun 10 07:51:04 PM PDT 24
Peak memory 249196 kb
Host smart-fa573466-b10b-4e9b-b031-1b0de1f8e273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791365522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3791365522
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.867995488
Short name T424
Test name
Test status
Simulation time 388761449 ps
CPU time 4.65 seconds
Started Jun 10 07:49:32 PM PDT 24
Finished Jun 10 07:49:39 PM PDT 24
Peak memory 240744 kb
Host smart-535667c5-8219-4f46-9a65-084e88805f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867995488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.867995488
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3488265207
Short name T434
Test name
Test status
Simulation time 1367482063 ps
CPU time 16.43 seconds
Started Jun 10 07:49:37 PM PDT 24
Finished Jun 10 07:49:57 PM PDT 24
Peak memory 224260 kb
Host smart-a60fb73f-0cac-4117-a812-31be19bb54ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488265207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3488265207
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2883660503
Short name T575
Test name
Test status
Simulation time 9431213548 ps
CPU time 77.38 seconds
Started Jun 10 07:49:37 PM PDT 24
Finished Jun 10 07:50:58 PM PDT 24
Peak memory 232616 kb
Host smart-fb171025-b0b3-408c-994c-c986203c710d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883660503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2883660503
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2139013170
Short name T838
Test name
Test status
Simulation time 5675450578 ps
CPU time 10.37 seconds
Started Jun 10 07:49:34 PM PDT 24
Finished Jun 10 07:49:47 PM PDT 24
Peak memory 232584 kb
Host smart-96c144ff-2faa-4f31-bf0d-f6bc738f85c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139013170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2139013170
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2045762406
Short name T799
Test name
Test status
Simulation time 6027681615 ps
CPU time 18.38 seconds
Started Jun 10 07:49:27 PM PDT 24
Finished Jun 10 07:49:48 PM PDT 24
Peak memory 236512 kb
Host smart-9e5a6139-1974-4de8-897c-f5ff731b53e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045762406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2045762406
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1360373523
Short name T704
Test name
Test status
Simulation time 828556549 ps
CPU time 4.84 seconds
Started Jun 10 07:49:35 PM PDT 24
Finished Jun 10 07:49:43 PM PDT 24
Peak memory 219288 kb
Host smart-b1cd5ea8-5179-47e9-adf3-1ed103aef548
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1360373523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1360373523
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1277693331
Short name T147
Test name
Test status
Simulation time 1765017612 ps
CPU time 30.21 seconds
Started Jun 10 07:49:38 PM PDT 24
Finished Jun 10 07:50:12 PM PDT 24
Peak memory 224516 kb
Host smart-6915223f-2f49-4002-9052-21eeec23fb50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277693331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1277693331
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.482721586
Short name T477
Test name
Test status
Simulation time 4810397318 ps
CPU time 28 seconds
Started Jun 10 07:49:38 PM PDT 24
Finished Jun 10 07:50:10 PM PDT 24
Peak memory 216456 kb
Host smart-b926bae6-3584-46dc-b1d5-957fddc2ca92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482721586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.482721586
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.225823047
Short name T464
Test name
Test status
Simulation time 499625353 ps
CPU time 4.45 seconds
Started Jun 10 07:49:32 PM PDT 24
Finished Jun 10 07:49:39 PM PDT 24
Peak memory 216036 kb
Host smart-3d844207-7a02-4e21-83db-71fddbe5f78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225823047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.225823047
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1633174722
Short name T64
Test name
Test status
Simulation time 310405595 ps
CPU time 4.05 seconds
Started Jun 10 07:49:28 PM PDT 24
Finished Jun 10 07:49:34 PM PDT 24
Peak memory 216024 kb
Host smart-4733ce28-27d3-4509-aa04-4fecb3092fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633174722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1633174722
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3809921907
Short name T466
Test name
Test status
Simulation time 142693447 ps
CPU time 0.86 seconds
Started Jun 10 07:49:26 PM PDT 24
Finished Jun 10 07:49:28 PM PDT 24
Peak memory 205692 kb
Host smart-2bf62f84-454f-4cff-a05b-6ad28b85886b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809921907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3809921907
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.587692493
Short name T958
Test name
Test status
Simulation time 22580775007 ps
CPU time 12.7 seconds
Started Jun 10 07:49:34 PM PDT 24
Finished Jun 10 07:49:50 PM PDT 24
Peak memory 232600 kb
Host smart-22b0d2aa-d701-4464-8482-3fe8ae924e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587692493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.587692493
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2601797941
Short name T974
Test name
Test status
Simulation time 13044096 ps
CPU time 0.71 seconds
Started Jun 10 07:49:37 PM PDT 24
Finished Jun 10 07:49:42 PM PDT 24
Peak memory 205296 kb
Host smart-7e09f529-d623-4c4e-bb86-fce64ab72820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601797941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2601797941
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2150833606
Short name T292
Test name
Test status
Simulation time 187953994 ps
CPU time 2.26 seconds
Started Jun 10 07:49:41 PM PDT 24
Finished Jun 10 07:49:47 PM PDT 24
Peak memory 224300 kb
Host smart-b4f6ff93-9d5c-415f-9d5e-06690d6cf849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150833606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2150833606
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2014519304
Short name T385
Test name
Test status
Simulation time 51498248 ps
CPU time 0.79 seconds
Started Jun 10 07:49:40 PM PDT 24
Finished Jun 10 07:49:44 PM PDT 24
Peak memory 206328 kb
Host smart-53950c3e-283f-41e8-b35c-aae1a9bf039b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014519304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2014519304
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3585864056
Short name T404
Test name
Test status
Simulation time 1045771167 ps
CPU time 19.28 seconds
Started Jun 10 07:49:37 PM PDT 24
Finished Jun 10 07:50:01 PM PDT 24
Peak memory 235960 kb
Host smart-ac5eaeb6-96a5-4b8f-bf0a-9e115181b691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585864056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3585864056
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.408275820
Short name T125
Test name
Test status
Simulation time 29343420850 ps
CPU time 68.84 seconds
Started Jun 10 07:49:35 PM PDT 24
Finished Jun 10 07:50:47 PM PDT 24
Peak memory 257284 kb
Host smart-a433c3dd-08f3-4705-9a95-e5d6375290aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408275820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.408275820
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.984082203
Short name T579
Test name
Test status
Simulation time 3096607172 ps
CPU time 74.57 seconds
Started Jun 10 07:49:36 PM PDT 24
Finished Jun 10 07:50:53 PM PDT 24
Peak memory 253032 kb
Host smart-e9419294-7ede-4136-9960-5f628b869c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984082203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.984082203
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1006669927
Short name T783
Test name
Test status
Simulation time 115690882 ps
CPU time 6.5 seconds
Started Jun 10 07:49:38 PM PDT 24
Finished Jun 10 07:49:49 PM PDT 24
Peak memory 237628 kb
Host smart-05de2e43-582c-40e4-a1bc-7eb74f754879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006669927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1006669927
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.922370776
Short name T160
Test name
Test status
Simulation time 4724845955 ps
CPU time 5.18 seconds
Started Jun 10 07:49:38 PM PDT 24
Finished Jun 10 07:49:47 PM PDT 24
Peak memory 224400 kb
Host smart-c63aea0a-9a0b-463a-97ad-4949439d915b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922370776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.922370776
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.58293678
Short name T576
Test name
Test status
Simulation time 783123481 ps
CPU time 9.79 seconds
Started Jun 10 07:49:38 PM PDT 24
Finished Jun 10 07:49:52 PM PDT 24
Peak memory 232544 kb
Host smart-3fa4fa16-9d06-47b5-abdd-2aad919afd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58293678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.58293678
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3032921638
Short name T852
Test name
Test status
Simulation time 78781619 ps
CPU time 2.71 seconds
Started Jun 10 07:49:40 PM PDT 24
Finished Jun 10 07:49:47 PM PDT 24
Peak memory 232604 kb
Host smart-f7a0edcd-f266-4112-8207-2caa0c4ad188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032921638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3032921638
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.18889945
Short name T271
Test name
Test status
Simulation time 5950205059 ps
CPU time 11.33 seconds
Started Jun 10 07:49:40 PM PDT 24
Finished Jun 10 07:49:55 PM PDT 24
Peak memory 232612 kb
Host smart-406638d9-6874-4b48-8b40-cc85eaf2c101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18889945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.18889945
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3727385845
Short name T134
Test name
Test status
Simulation time 1008446763 ps
CPU time 3.85 seconds
Started Jun 10 07:49:34 PM PDT 24
Finished Jun 10 07:49:41 PM PDT 24
Peak memory 219864 kb
Host smart-50a5651f-bd5d-4863-b569-c936eb2f5759
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3727385845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3727385845
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2689621664
Short name T844
Test name
Test status
Simulation time 165481710 ps
CPU time 1.13 seconds
Started Jun 10 07:49:37 PM PDT 24
Finished Jun 10 07:49:42 PM PDT 24
Peak memory 206900 kb
Host smart-2ea01040-6bb3-4e8b-b69a-7f6c5b544b1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689621664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2689621664
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2159604424
Short name T657
Test name
Test status
Simulation time 3484659230 ps
CPU time 18.63 seconds
Started Jun 10 07:49:36 PM PDT 24
Finished Jun 10 07:49:58 PM PDT 24
Peak memory 216176 kb
Host smart-2dd199b1-0a25-4576-b9ff-ee93687d6a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159604424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2159604424
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2841609539
Short name T695
Test name
Test status
Simulation time 12109078652 ps
CPU time 18.89 seconds
Started Jun 10 07:49:35 PM PDT 24
Finished Jun 10 07:49:57 PM PDT 24
Peak memory 216236 kb
Host smart-9437858c-0344-491b-89ac-b1c6040b1293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841609539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2841609539
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.50310043
Short name T728
Test name
Test status
Simulation time 103852553 ps
CPU time 0.88 seconds
Started Jun 10 07:49:39 PM PDT 24
Finished Jun 10 07:49:43 PM PDT 24
Peak memory 206740 kb
Host smart-939cfe8d-0391-4a84-a3f7-101f3f67269d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50310043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.50310043
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.12149240
Short name T892
Test name
Test status
Simulation time 179374832 ps
CPU time 0.84 seconds
Started Jun 10 07:49:36 PM PDT 24
Finished Jun 10 07:49:40 PM PDT 24
Peak memory 205704 kb
Host smart-accb6258-0e3a-4588-b7ef-aa0e62d4f231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12149240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.12149240
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2322991166
Short name T649
Test name
Test status
Simulation time 56627328925 ps
CPU time 26.19 seconds
Started Jun 10 07:49:37 PM PDT 24
Finished Jun 10 07:50:08 PM PDT 24
Peak memory 224396 kb
Host smart-2eaf4819-89f9-4e42-b97b-cc24f26cb330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322991166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2322991166
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1459297872
Short name T716
Test name
Test status
Simulation time 42744251 ps
CPU time 0.71 seconds
Started Jun 10 07:49:39 PM PDT 24
Finished Jun 10 07:49:44 PM PDT 24
Peak memory 205280 kb
Host smart-62a12362-24f0-4cec-8d43-bce17ebb4e3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459297872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1459297872
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2870548796
Short name T258
Test name
Test status
Simulation time 380441958 ps
CPU time 2.84 seconds
Started Jun 10 07:49:36 PM PDT 24
Finished Jun 10 07:49:43 PM PDT 24
Peak memory 224344 kb
Host smart-4b75d2cf-2f89-4f98-b278-057fff496378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870548796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2870548796
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1747371787
Short name T624
Test name
Test status
Simulation time 14941350 ps
CPU time 0.73 seconds
Started Jun 10 07:49:40 PM PDT 24
Finished Jun 10 07:49:45 PM PDT 24
Peak memory 205360 kb
Host smart-99053996-27b0-427b-b02b-6e8708be9944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747371787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1747371787
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2889759625
Short name T313
Test name
Test status
Simulation time 16509259160 ps
CPU time 79.64 seconds
Started Jun 10 07:49:40 PM PDT 24
Finished Jun 10 07:51:04 PM PDT 24
Peak memory 254764 kb
Host smart-568f0e6a-0c59-4ea4-b736-3b9ba2c976a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889759625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2889759625
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.281697691
Short name T26
Test name
Test status
Simulation time 5107895923 ps
CPU time 67.86 seconds
Started Jun 10 07:49:41 PM PDT 24
Finished Jun 10 07:50:53 PM PDT 24
Peak memory 240324 kb
Host smart-aa5a7b17-7d40-4e26-b2c2-3c5e7612fefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281697691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.281697691
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2706221633
Short name T689
Test name
Test status
Simulation time 1288956395 ps
CPU time 7.99 seconds
Started Jun 10 07:49:40 PM PDT 24
Finished Jun 10 07:49:52 PM PDT 24
Peak memory 224272 kb
Host smart-eb0a7031-478c-49d3-8682-0e42c9688f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706221633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2706221633
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.562213740
Short name T633
Test name
Test status
Simulation time 268473185 ps
CPU time 4.02 seconds
Started Jun 10 07:49:40 PM PDT 24
Finished Jun 10 07:49:48 PM PDT 24
Peak memory 232484 kb
Host smart-e5fef465-9cb6-47f0-8c36-f4d00e71e7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562213740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.562213740
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.4126580826
Short name T453
Test name
Test status
Simulation time 9939973404 ps
CPU time 20.54 seconds
Started Jun 10 07:49:36 PM PDT 24
Finished Jun 10 07:50:00 PM PDT 24
Peak memory 224364 kb
Host smart-f12ea532-d15a-4c15-81e0-553a29b09e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126580826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4126580826
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.748958398
Short name T803
Test name
Test status
Simulation time 242383756 ps
CPU time 4.34 seconds
Started Jun 10 07:49:36 PM PDT 24
Finished Jun 10 07:49:44 PM PDT 24
Peak memory 232544 kb
Host smart-0b6262fb-95eb-4fda-8904-5064eb70efcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748958398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.748958398
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.400385094
Short name T398
Test name
Test status
Simulation time 929644638 ps
CPU time 5.36 seconds
Started Jun 10 07:49:37 PM PDT 24
Finished Jun 10 07:49:46 PM PDT 24
Peak memory 224240 kb
Host smart-7195b290-19ce-444c-8bcb-ed97cda2c4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400385094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.400385094
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2297589983
Short name T857
Test name
Test status
Simulation time 380153023 ps
CPU time 5.15 seconds
Started Jun 10 07:49:41 PM PDT 24
Finished Jun 10 07:49:49 PM PDT 24
Peak memory 222696 kb
Host smart-53fe07df-6145-4300-b896-6ee32d1b8bad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2297589983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2297589983
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.175916226
Short name T148
Test name
Test status
Simulation time 20123436900 ps
CPU time 72.07 seconds
Started Jun 10 07:49:39 PM PDT 24
Finished Jun 10 07:50:55 PM PDT 24
Peak memory 240884 kb
Host smart-fa827de1-0813-4cbd-8178-31f508e9a179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175916226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.175916226
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1437230299
Short name T329
Test name
Test status
Simulation time 737008311 ps
CPU time 11.11 seconds
Started Jun 10 07:49:39 PM PDT 24
Finished Jun 10 07:49:54 PM PDT 24
Peak memory 216132 kb
Host smart-aca3b2cf-7084-40f7-a1f4-b234224bd414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437230299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1437230299
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.4260911658
Short name T981
Test name
Test status
Simulation time 600710423 ps
CPU time 2.49 seconds
Started Jun 10 07:49:41 PM PDT 24
Finished Jun 10 07:49:47 PM PDT 24
Peak memory 215920 kb
Host smart-4eae148d-5cb5-40c2-9133-2db4585cbd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260911658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.4260911658
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3184131785
Short name T611
Test name
Test status
Simulation time 76662721 ps
CPU time 1.26 seconds
Started Jun 10 07:49:40 PM PDT 24
Finished Jun 10 07:49:45 PM PDT 24
Peak memory 216084 kb
Host smart-055c1c5b-3c49-4aad-b30e-92744c756369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184131785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3184131785
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.540194248
Short name T389
Test name
Test status
Simulation time 106641879 ps
CPU time 0.9 seconds
Started Jun 10 07:49:36 PM PDT 24
Finished Jun 10 07:49:41 PM PDT 24
Peak memory 205704 kb
Host smart-a0279044-6b3b-4b45-8910-11d1e47cbe6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540194248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.540194248
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1748286194
Short name T786
Test name
Test status
Simulation time 157760390 ps
CPU time 2.2 seconds
Started Jun 10 07:49:39 PM PDT 24
Finished Jun 10 07:49:45 PM PDT 24
Peak memory 223024 kb
Host smart-11795b1a-d5df-4444-842d-40bf2087316b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748286194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1748286194
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.120128376
Short name T571
Test name
Test status
Simulation time 11147753 ps
CPU time 0.73 seconds
Started Jun 10 07:49:45 PM PDT 24
Finished Jun 10 07:49:49 PM PDT 24
Peak memory 205304 kb
Host smart-0c6e4937-a4d2-4246-979c-f261265e0a09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120128376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.120128376
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3459379208
Short name T763
Test name
Test status
Simulation time 1987159896 ps
CPU time 5.7 seconds
Started Jun 10 07:49:39 PM PDT 24
Finished Jun 10 07:49:49 PM PDT 24
Peak memory 224276 kb
Host smart-bab73b2b-7e2f-4fba-bc39-86f58080ed11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459379208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3459379208
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1517512274
Short name T538
Test name
Test status
Simulation time 67178673 ps
CPU time 0.78 seconds
Started Jun 10 07:49:41 PM PDT 24
Finished Jun 10 07:49:45 PM PDT 24
Peak memory 206280 kb
Host smart-5aa272fc-c29a-432f-acdb-b1392b26ac5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517512274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1517512274
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.538577196
Short name T196
Test name
Test status
Simulation time 101011890092 ps
CPU time 88.82 seconds
Started Jun 10 07:49:45 PM PDT 24
Finished Jun 10 07:51:17 PM PDT 24
Peak memory 249304 kb
Host smart-c57ff04f-7fea-4d60-87f2-2b9ef631d531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538577196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.538577196
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3590751886
Short name T69
Test name
Test status
Simulation time 10061920738 ps
CPU time 46.49 seconds
Started Jun 10 07:49:46 PM PDT 24
Finished Jun 10 07:50:37 PM PDT 24
Peak memory 217424 kb
Host smart-46294fc4-4ce0-4cea-bb00-15229bb0395a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590751886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3590751886
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1226083042
Short name T3
Test name
Test status
Simulation time 6226170086 ps
CPU time 21.36 seconds
Started Jun 10 07:49:47 PM PDT 24
Finished Jun 10 07:50:12 PM PDT 24
Peak memory 238096 kb
Host smart-5e9e278a-3923-4a65-9ded-514521d7fa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226083042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1226083042
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.760786395
Short name T535
Test name
Test status
Simulation time 6322815630 ps
CPU time 38.71 seconds
Started Jun 10 07:49:37 PM PDT 24
Finished Jun 10 07:50:20 PM PDT 24
Peak memory 251952 kb
Host smart-d0f17a61-d68e-48a7-8d8f-08a585add66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760786395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.760786395
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.209487689
Short name T537
Test name
Test status
Simulation time 1801525683 ps
CPU time 16.93 seconds
Started Jun 10 07:49:34 PM PDT 24
Finished Jun 10 07:49:54 PM PDT 24
Peak memory 232536 kb
Host smart-ca06c6a8-a8ad-483c-9fcf-1aab473a458d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209487689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.209487689
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3722876415
Short name T859
Test name
Test status
Simulation time 1381110547 ps
CPU time 2.21 seconds
Started Jun 10 07:49:37 PM PDT 24
Finished Jun 10 07:49:44 PM PDT 24
Peak memory 218312 kb
Host smart-ca8d7dc6-c5fe-4d09-acc4-9958e91350d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722876415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3722876415
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.536658688
Short name T300
Test name
Test status
Simulation time 265638516 ps
CPU time 4.69 seconds
Started Jun 10 07:49:40 PM PDT 24
Finished Jun 10 07:49:49 PM PDT 24
Peak memory 232536 kb
Host smart-c96b9ded-4ee9-471d-a6e3-271c536392a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536658688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.536658688
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.692200882
Short name T858
Test name
Test status
Simulation time 2486284927 ps
CPU time 8.4 seconds
Started Jun 10 07:49:41 PM PDT 24
Finished Jun 10 07:49:53 PM PDT 24
Peak memory 232508 kb
Host smart-7878cac5-2ed9-435f-ad36-6b7411272102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692200882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.692200882
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3549489184
Short name T805
Test name
Test status
Simulation time 1088395572 ps
CPU time 16.04 seconds
Started Jun 10 07:49:44 PM PDT 24
Finished Jun 10 07:50:03 PM PDT 24
Peak memory 219084 kb
Host smart-747ec0af-42d7-46d7-9845-a8d49dbe5bdb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3549489184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3549489184
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3998213664
Short name T903
Test name
Test status
Simulation time 13641123115 ps
CPU time 28.61 seconds
Started Jun 10 07:49:40 PM PDT 24
Finished Jun 10 07:50:13 PM PDT 24
Peak memory 216248 kb
Host smart-be8a753f-ef18-45c7-95cc-be7de8ef0dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998213664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3998213664
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.630414111
Short name T609
Test name
Test status
Simulation time 13778342280 ps
CPU time 13.47 seconds
Started Jun 10 07:49:40 PM PDT 24
Finished Jun 10 07:49:57 PM PDT 24
Peak memory 216112 kb
Host smart-6924d41f-f6e9-4f9e-9b12-f7e0ce952e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630414111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.630414111
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.582103054
Short name T341
Test name
Test status
Simulation time 12361974 ps
CPU time 0.69 seconds
Started Jun 10 07:49:38 PM PDT 24
Finished Jun 10 07:49:43 PM PDT 24
Peak memory 205316 kb
Host smart-ed41f8df-0cb4-486c-ac27-20d3ed08245a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582103054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.582103054
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2787215115
Short name T602
Test name
Test status
Simulation time 144045861 ps
CPU time 0.95 seconds
Started Jun 10 07:49:38 PM PDT 24
Finished Jun 10 07:49:43 PM PDT 24
Peak memory 206668 kb
Host smart-502a591b-40a0-411a-974a-aa0976ff4c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787215115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2787215115
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.277309152
Short name T590
Test name
Test status
Simulation time 2966155598 ps
CPU time 9.78 seconds
Started Jun 10 07:49:37 PM PDT 24
Finished Jun 10 07:49:52 PM PDT 24
Peak memory 248768 kb
Host smart-7b54dee2-f0db-4027-a504-14e1cdec1b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277309152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.277309152
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2063624469
Short name T425
Test name
Test status
Simulation time 15651520 ps
CPU time 0.83 seconds
Started Jun 10 07:47:33 PM PDT 24
Finished Jun 10 07:47:38 PM PDT 24
Peak memory 204708 kb
Host smart-21159812-4295-4244-a572-9f3c7214f7a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063624469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
063624469
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.585179074
Short name T471
Test name
Test status
Simulation time 885773128 ps
CPU time 6.53 seconds
Started Jun 10 07:47:30 PM PDT 24
Finished Jun 10 07:47:39 PM PDT 24
Peak memory 224288 kb
Host smart-74d0a3a8-ec48-4bbb-ad23-83303eb730ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585179074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.585179074
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2293268507
Short name T473
Test name
Test status
Simulation time 84966702 ps
CPU time 0.75 seconds
Started Jun 10 07:47:29 PM PDT 24
Finished Jun 10 07:47:32 PM PDT 24
Peak memory 206716 kb
Host smart-4bc02369-0773-4d72-a7c9-3fc00483e9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293268507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2293268507
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3370372963
Short name T796
Test name
Test status
Simulation time 17743871 ps
CPU time 0.73 seconds
Started Jun 10 07:47:40 PM PDT 24
Finished Jun 10 07:47:46 PM PDT 24
Peak memory 215800 kb
Host smart-e9091346-d88c-4503-b3d5-9e69dbcd9e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370372963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3370372963
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3130420934
Short name T210
Test name
Test status
Simulation time 2171097756 ps
CPU time 58.96 seconds
Started Jun 10 07:47:33 PM PDT 24
Finished Jun 10 07:48:36 PM PDT 24
Peak memory 249176 kb
Host smart-194cd889-849b-46f0-9ae9-eff9477a72df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130420934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3130420934
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3616368003
Short name T392
Test name
Test status
Simulation time 66587040 ps
CPU time 3.92 seconds
Started Jun 10 07:47:39 PM PDT 24
Finished Jun 10 07:47:48 PM PDT 24
Peak memory 233240 kb
Host smart-317eef04-51ca-4781-b832-5d19d06f5447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616368003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3616368003
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4061620028
Short name T639
Test name
Test status
Simulation time 312594988 ps
CPU time 4.92 seconds
Started Jun 10 07:47:24 PM PDT 24
Finished Jun 10 07:47:31 PM PDT 24
Peak memory 224268 kb
Host smart-d1c420f6-5621-4e06-b39e-a684855ae64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061620028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4061620028
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.847750831
Short name T979
Test name
Test status
Simulation time 1934146968 ps
CPU time 14.08 seconds
Started Jun 10 07:47:28 PM PDT 24
Finished Jun 10 07:47:44 PM PDT 24
Peak memory 224228 kb
Host smart-c8263706-d394-485e-b730-23782e0dbc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847750831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.847750831
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3267315324
Short name T599
Test name
Test status
Simulation time 34863292 ps
CPU time 1.17 seconds
Started Jun 10 07:47:33 PM PDT 24
Finished Jun 10 07:47:38 PM PDT 24
Peak memory 216484 kb
Host smart-e5dec465-3385-4400-85ee-129d13969417
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267315324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3267315324
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2009276414
Short name T702
Test name
Test status
Simulation time 553078788 ps
CPU time 10.8 seconds
Started Jun 10 07:47:28 PM PDT 24
Finished Jun 10 07:47:40 PM PDT 24
Peak memory 232460 kb
Host smart-3db1f15d-5cb0-4a40-813f-b9339f7f7e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009276414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2009276414
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3822720887
Short name T605
Test name
Test status
Simulation time 6790887660 ps
CPU time 19.84 seconds
Started Jun 10 07:47:33 PM PDT 24
Finished Jun 10 07:47:57 PM PDT 24
Peak memory 240540 kb
Host smart-ab540ae3-19ae-41fe-978d-ca2ddb2da9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822720887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3822720887
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1871239869
Short name T401
Test name
Test status
Simulation time 440135594 ps
CPU time 5.37 seconds
Started Jun 10 07:47:32 PM PDT 24
Finished Jun 10 07:47:41 PM PDT 24
Peak memory 222900 kb
Host smart-68905e9a-b7da-42d4-8c4a-98751d75f6ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1871239869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1871239869
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.591539882
Short name T126
Test name
Test status
Simulation time 43619777179 ps
CPU time 393.03 seconds
Started Jun 10 07:47:29 PM PDT 24
Finished Jun 10 07:54:06 PM PDT 24
Peak memory 254116 kb
Host smart-6699eb6b-b7f2-453f-92ad-cb3f35f3786d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591539882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.591539882
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.4224304148
Short name T336
Test name
Test status
Simulation time 7850270648 ps
CPU time 17.1 seconds
Started Jun 10 07:47:23 PM PDT 24
Finished Jun 10 07:47:42 PM PDT 24
Peak memory 216240 kb
Host smart-4c8d9ede-045e-4266-aa83-87d07a8aa1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224304148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.4224304148
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1391240864
Short name T77
Test name
Test status
Simulation time 2256487009 ps
CPU time 5.98 seconds
Started Jun 10 07:47:23 PM PDT 24
Finished Jun 10 07:47:31 PM PDT 24
Peak memory 216040 kb
Host smart-d5c6503c-e429-4f35-b661-4021ae988a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391240864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1391240864
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1309044087
Short name T71
Test name
Test status
Simulation time 1120005121 ps
CPU time 3.97 seconds
Started Jun 10 07:47:34 PM PDT 24
Finished Jun 10 07:47:42 PM PDT 24
Peak memory 216012 kb
Host smart-93bfb9b9-fe70-4aa9-b8fe-93327e877787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309044087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1309044087
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3230434485
Short name T670
Test name
Test status
Simulation time 61311131 ps
CPU time 0.91 seconds
Started Jun 10 07:47:29 PM PDT 24
Finished Jun 10 07:47:32 PM PDT 24
Peak memory 206660 kb
Host smart-aeb5f736-851d-4832-ab5d-e5bd389675bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230434485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3230434485
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3135354202
Short name T289
Test name
Test status
Simulation time 822510976 ps
CPU time 4.83 seconds
Started Jun 10 07:47:30 PM PDT 24
Finished Jun 10 07:47:38 PM PDT 24
Peak memory 240664 kb
Host smart-bea1e6cb-3e9b-468b-99d6-ca97345d3f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135354202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3135354202
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1901906609
Short name T446
Test name
Test status
Simulation time 11967608 ps
CPU time 0.73 seconds
Started Jun 10 07:47:34 PM PDT 24
Finished Jun 10 07:47:40 PM PDT 24
Peak memory 205656 kb
Host smart-13a5f602-53ed-4562-b09a-5fc96377365e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901906609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
901906609
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1355462959
Short name T138
Test name
Test status
Simulation time 225843922 ps
CPU time 3.82 seconds
Started Jun 10 07:47:36 PM PDT 24
Finished Jun 10 07:47:43 PM PDT 24
Peak memory 224276 kb
Host smart-23305bf4-ee50-4393-b399-f3cfb738b82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355462959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1355462959
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2199346512
Short name T522
Test name
Test status
Simulation time 22915455 ps
CPU time 0.82 seconds
Started Jun 10 07:47:40 PM PDT 24
Finished Jun 10 07:47:46 PM PDT 24
Peak memory 206368 kb
Host smart-87caafd5-c364-42da-92fa-7beefe0a1490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199346512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2199346512
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.455856741
Short name T580
Test name
Test status
Simulation time 26422595308 ps
CPU time 75.74 seconds
Started Jun 10 07:47:39 PM PDT 24
Finished Jun 10 07:49:00 PM PDT 24
Peak memory 250144 kb
Host smart-1a2ce74f-920e-4c77-b45e-ba6a490ce8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455856741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.455856741
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2533716091
Short name T888
Test name
Test status
Simulation time 9291009032 ps
CPU time 45.13 seconds
Started Jun 10 07:47:39 PM PDT 24
Finished Jun 10 07:48:29 PM PDT 24
Peak memory 249136 kb
Host smart-07c36287-e478-46e3-8812-05fdf843a17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533716091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2533716091
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.238365957
Short name T836
Test name
Test status
Simulation time 79354074343 ps
CPU time 169.61 seconds
Started Jun 10 07:47:37 PM PDT 24
Finished Jun 10 07:50:31 PM PDT 24
Peak memory 232652 kb
Host smart-62ff0475-3fc4-4cc1-9e70-0e69244ba8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238365957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
238365957
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1658675600
Short name T942
Test name
Test status
Simulation time 9077944006 ps
CPU time 29.4 seconds
Started Jun 10 07:47:32 PM PDT 24
Finished Jun 10 07:48:05 PM PDT 24
Peak memory 232720 kb
Host smart-ac7a6ea4-4155-47f9-ac2b-04c29ff6cf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658675600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1658675600
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.106916687
Short name T854
Test name
Test status
Simulation time 9412946833 ps
CPU time 24.95 seconds
Started Jun 10 07:47:36 PM PDT 24
Finished Jun 10 07:48:05 PM PDT 24
Peak memory 232644 kb
Host smart-7c877a81-1834-4e8e-af6b-40d1123ef96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106916687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.106916687
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2323423079
Short name T982
Test name
Test status
Simulation time 49191040525 ps
CPU time 48.49 seconds
Started Jun 10 07:47:30 PM PDT 24
Finished Jun 10 07:48:22 PM PDT 24
Peak memory 235376 kb
Host smart-c2b0b3d7-bbaa-4082-8eae-e73b90f200f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323423079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2323423079
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.347114651
Short name T789
Test name
Test status
Simulation time 18260870 ps
CPU time 1.02 seconds
Started Jun 10 07:47:29 PM PDT 24
Finished Jun 10 07:47:33 PM PDT 24
Peak memory 216520 kb
Host smart-7b56d1cb-ad49-4fd5-bb3b-ddda549da231
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347114651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.347114651
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4124297904
Short name T275
Test name
Test status
Simulation time 1062695942 ps
CPU time 3.38 seconds
Started Jun 10 07:47:33 PM PDT 24
Finished Jun 10 07:47:41 PM PDT 24
Peak memory 224384 kb
Host smart-9b1a1db6-5fdc-4a40-b83f-e0c32c375a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124297904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.4124297904
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3592366838
Short name T157
Test name
Test status
Simulation time 1242194878 ps
CPU time 9.28 seconds
Started Jun 10 07:47:32 PM PDT 24
Finished Jun 10 07:47:45 PM PDT 24
Peak memory 232524 kb
Host smart-b738f92c-7baa-4605-a0a1-9f12d1d4acb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592366838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3592366838
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2594773429
Short name T437
Test name
Test status
Simulation time 2595584020 ps
CPU time 8.95 seconds
Started Jun 10 07:47:34 PM PDT 24
Finished Jun 10 07:47:48 PM PDT 24
Peak memory 221580 kb
Host smart-07b28036-e704-461b-b71a-8c112a737484
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2594773429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2594773429
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2965227435
Short name T749
Test name
Test status
Simulation time 3040170301 ps
CPU time 24.54 seconds
Started Jun 10 07:47:40 PM PDT 24
Finished Jun 10 07:48:10 PM PDT 24
Peak memory 216132 kb
Host smart-1cd14b87-2f99-4f30-89e3-524b507802dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965227435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2965227435
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.805480856
Short name T911
Test name
Test status
Simulation time 10562147782 ps
CPU time 12.53 seconds
Started Jun 10 07:47:42 PM PDT 24
Finished Jun 10 07:47:59 PM PDT 24
Peak memory 216240 kb
Host smart-85757719-48af-4d30-8fa4-dff5376cf759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805480856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.805480856
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3421426755
Short name T504
Test name
Test status
Simulation time 150156578 ps
CPU time 1.34 seconds
Started Jun 10 07:47:40 PM PDT 24
Finished Jun 10 07:47:46 PM PDT 24
Peak memory 216016 kb
Host smart-085e6846-e4d9-44d2-8648-4555b9a2b595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421426755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3421426755
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2095057707
Short name T662
Test name
Test status
Simulation time 90744504 ps
CPU time 0.84 seconds
Started Jun 10 07:47:36 PM PDT 24
Finished Jun 10 07:47:41 PM PDT 24
Peak memory 205780 kb
Host smart-ae640dd4-f4b0-4d16-8c00-7b5a3c78ee58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095057707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2095057707
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1457148787
Short name T719
Test name
Test status
Simulation time 737673793 ps
CPU time 3.58 seconds
Started Jun 10 07:47:29 PM PDT 24
Finished Jun 10 07:47:36 PM PDT 24
Peak memory 224300 kb
Host smart-a6a79b42-2f30-47dd-aaa9-dad0c1599648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457148787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1457148787
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.124019990
Short name T520
Test name
Test status
Simulation time 23047472 ps
CPU time 0.72 seconds
Started Jun 10 07:47:35 PM PDT 24
Finished Jun 10 07:47:40 PM PDT 24
Peak memory 205620 kb
Host smart-7f60933b-a811-494e-acef-52674a74337e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124019990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.124019990
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3933018518
Short name T255
Test name
Test status
Simulation time 1387253589 ps
CPU time 15.56 seconds
Started Jun 10 07:47:39 PM PDT 24
Finished Jun 10 07:48:00 PM PDT 24
Peak memory 224296 kb
Host smart-5f38d320-008e-4a01-8668-9debdde20437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933018518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3933018518
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.599967405
Short name T669
Test name
Test status
Simulation time 13128419 ps
CPU time 0.83 seconds
Started Jun 10 07:47:31 PM PDT 24
Finished Jun 10 07:47:35 PM PDT 24
Peak memory 206700 kb
Host smart-e0a17c91-49e5-4c55-a3f3-5615e59410a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599967405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.599967405
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2709387281
Short name T646
Test name
Test status
Simulation time 28163725643 ps
CPU time 177.53 seconds
Started Jun 10 07:47:39 PM PDT 24
Finished Jun 10 07:50:42 PM PDT 24
Peak memory 250168 kb
Host smart-fe766101-3f1f-49f9-8f50-5b216d31159b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709387281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2709387281
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3744539668
Short name T781
Test name
Test status
Simulation time 10126514874 ps
CPU time 111.61 seconds
Started Jun 10 07:47:31 PM PDT 24
Finished Jun 10 07:49:26 PM PDT 24
Peak memory 249040 kb
Host smart-349d063d-edc6-4f99-a0a7-9301f0a9cc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744539668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3744539668
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3815703945
Short name T928
Test name
Test status
Simulation time 16336843280 ps
CPU time 167.76 seconds
Started Jun 10 07:47:33 PM PDT 24
Finished Jun 10 07:50:25 PM PDT 24
Peak memory 249060 kb
Host smart-3094ad08-9adf-459a-8c89-4cd68be622f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815703945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3815703945
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3678035523
Short name T63
Test name
Test status
Simulation time 318102752 ps
CPU time 2.16 seconds
Started Jun 10 07:47:32 PM PDT 24
Finished Jun 10 07:47:38 PM PDT 24
Peak memory 224292 kb
Host smart-00c1f1c4-36be-4401-bac7-6fa99921a9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678035523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3678035523
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.4022567793
Short name T827
Test name
Test status
Simulation time 285158805 ps
CPU time 3.18 seconds
Started Jun 10 07:47:35 PM PDT 24
Finished Jun 10 07:47:42 PM PDT 24
Peak memory 232528 kb
Host smart-e3cbd603-5b2c-41bd-858d-80c774893045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022567793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.4022567793
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1552105955
Short name T663
Test name
Test status
Simulation time 45974346 ps
CPU time 1.06 seconds
Started Jun 10 07:47:39 PM PDT 24
Finished Jun 10 07:47:45 PM PDT 24
Peak memory 217816 kb
Host smart-a0bc6696-7a28-481c-9d69-d3915580ea68
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552105955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1552105955
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1545269881
Short name T894
Test name
Test status
Simulation time 51195169421 ps
CPU time 19.62 seconds
Started Jun 10 07:47:40 PM PDT 24
Finished Jun 10 07:48:05 PM PDT 24
Peak memory 239556 kb
Host smart-67b186ec-a435-4daf-b364-6152554b2d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545269881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1545269881
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1221874038
Short name T667
Test name
Test status
Simulation time 117744249 ps
CPU time 3.56 seconds
Started Jun 10 07:47:32 PM PDT 24
Finished Jun 10 07:47:40 PM PDT 24
Peak memory 232532 kb
Host smart-483a75bc-d34a-4f50-bbfa-7014eeb99ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221874038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1221874038
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.809901311
Short name T399
Test name
Test status
Simulation time 620463505 ps
CPU time 6.85 seconds
Started Jun 10 07:47:32 PM PDT 24
Finished Jun 10 07:47:43 PM PDT 24
Peak memory 220340 kb
Host smart-347cce15-b9a9-482d-85b4-175f3efb575a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=809901311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.809901311
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.792861894
Short name T146
Test name
Test status
Simulation time 14854112389 ps
CPU time 97.15 seconds
Started Jun 10 07:47:36 PM PDT 24
Finished Jun 10 07:49:17 PM PDT 24
Peak memory 256544 kb
Host smart-59e62000-75f3-4eb2-a519-49ac71dbf9f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792861894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.792861894
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.750142263
Short name T746
Test name
Test status
Simulation time 7258872458 ps
CPU time 23.22 seconds
Started Jun 10 07:47:36 PM PDT 24
Finished Jun 10 07:48:03 PM PDT 24
Peak memory 220152 kb
Host smart-d1359110-1635-436b-9aea-3d2e288d1d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750142263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.750142263
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1794660812
Short name T862
Test name
Test status
Simulation time 16660479503 ps
CPU time 14.09 seconds
Started Jun 10 07:47:36 PM PDT 24
Finished Jun 10 07:47:55 PM PDT 24
Peak memory 216104 kb
Host smart-9f845e13-abce-40c5-a37d-83cc0c4c69f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794660812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1794660812
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.548659466
Short name T531
Test name
Test status
Simulation time 83469441 ps
CPU time 1.04 seconds
Started Jun 10 07:47:38 PM PDT 24
Finished Jun 10 07:47:44 PM PDT 24
Peak memory 206688 kb
Host smart-3187d87f-dce5-42f5-a372-9ad3b8ab7ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548659466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.548659466
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3251592730
Short name T880
Test name
Test status
Simulation time 29375300 ps
CPU time 0.8 seconds
Started Jun 10 07:47:36 PM PDT 24
Finished Jun 10 07:47:41 PM PDT 24
Peak memory 205632 kb
Host smart-b683508e-3594-4eb6-814b-918b1bcb8c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251592730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3251592730
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2230715011
Short name T951
Test name
Test status
Simulation time 77441707 ps
CPU time 2.59 seconds
Started Jun 10 07:47:34 PM PDT 24
Finished Jun 10 07:47:41 PM PDT 24
Peak memory 234112 kb
Host smart-a9adbed6-8646-477e-87e5-5141feb6c8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230715011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2230715011
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.923973689
Short name T729
Test name
Test status
Simulation time 11796161 ps
CPU time 0.71 seconds
Started Jun 10 07:47:33 PM PDT 24
Finished Jun 10 07:47:39 PM PDT 24
Peak memory 204804 kb
Host smart-27356d9a-1975-45dd-a4b8-7649206f9ac6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923973689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.923973689
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1045231031
Short name T869
Test name
Test status
Simulation time 258041592 ps
CPU time 4.62 seconds
Started Jun 10 07:47:37 PM PDT 24
Finished Jun 10 07:47:46 PM PDT 24
Peak memory 232536 kb
Host smart-2eb65d0b-8cb4-445d-b54d-9335e83d7779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045231031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1045231031
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2756171923
Short name T867
Test name
Test status
Simulation time 44564294 ps
CPU time 0.77 seconds
Started Jun 10 07:47:39 PM PDT 24
Finished Jun 10 07:47:45 PM PDT 24
Peak memory 206760 kb
Host smart-19e0ce44-6afd-4273-99df-2270c0491f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756171923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2756171923
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1623588143
Short name T266
Test name
Test status
Simulation time 26404567738 ps
CPU time 93.49 seconds
Started Jun 10 07:47:32 PM PDT 24
Finished Jun 10 07:49:09 PM PDT 24
Peak memory 240848 kb
Host smart-e16e586b-0b2f-46b0-b421-8c001b84645c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623588143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1623588143
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1665293551
Short name T879
Test name
Test status
Simulation time 7480909021 ps
CPU time 75.01 seconds
Started Jun 10 07:47:37 PM PDT 24
Finished Jun 10 07:48:56 PM PDT 24
Peak memory 253260 kb
Host smart-64c4504f-a44d-4dd0-a39b-56fe9e7399aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665293551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1665293551
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3061787247
Short name T450
Test name
Test status
Simulation time 10290901058 ps
CPU time 133.75 seconds
Started Jun 10 07:47:39 PM PDT 24
Finished Jun 10 07:49:58 PM PDT 24
Peak memory 256772 kb
Host smart-13c16b9a-3370-4a20-8a7f-b69185a23543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061787247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3061787247
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3083828436
Short name T422
Test name
Test status
Simulation time 118758826 ps
CPU time 3.01 seconds
Started Jun 10 07:47:45 PM PDT 24
Finished Jun 10 07:47:51 PM PDT 24
Peak memory 224320 kb
Host smart-32b3b0f9-6f16-4632-8fae-bb572e1cfe70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083828436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3083828436
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2579231776
Short name T358
Test name
Test status
Simulation time 33611302 ps
CPU time 2.53 seconds
Started Jun 10 07:47:38 PM PDT 24
Finished Jun 10 07:47:45 PM PDT 24
Peak memory 232304 kb
Host smart-a1355a30-c43b-4f02-823b-8f29aba5d2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579231776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2579231776
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.832564484
Short name T254
Test name
Test status
Simulation time 19888338039 ps
CPU time 47.9 seconds
Started Jun 10 07:47:38 PM PDT 24
Finished Jun 10 07:48:31 PM PDT 24
Peak memory 240748 kb
Host smart-eeb0dd56-b6e7-414c-b905-1f1e827b6c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832564484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.832564484
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.625314919
Short name T687
Test name
Test status
Simulation time 54706259 ps
CPU time 1.05 seconds
Started Jun 10 07:47:33 PM PDT 24
Finished Jun 10 07:47:39 PM PDT 24
Peak memory 216484 kb
Host smart-1ce4cd7b-bfd4-461a-be88-36062d2833b7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625314919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.625314919
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.513322187
Short name T915
Test name
Test status
Simulation time 5066809887 ps
CPU time 17.96 seconds
Started Jun 10 07:47:37 PM PDT 24
Finished Jun 10 07:48:00 PM PDT 24
Peak memory 240576 kb
Host smart-99b38d7a-d46b-4b52-bf2f-89988e3ff7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513322187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
513322187
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3936533682
Short name T834
Test name
Test status
Simulation time 21099050098 ps
CPU time 9.93 seconds
Started Jun 10 07:47:38 PM PDT 24
Finished Jun 10 07:47:53 PM PDT 24
Peak memory 250028 kb
Host smart-c8119870-f437-4dac-97f8-6f63aa995a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936533682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3936533682
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2663639732
Short name T855
Test name
Test status
Simulation time 1550988903 ps
CPU time 9.06 seconds
Started Jun 10 07:47:37 PM PDT 24
Finished Jun 10 07:47:50 PM PDT 24
Peak memory 221588 kb
Host smart-ffc5db05-194f-4ee1-b29b-161540a78683
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2663639732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2663639732
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.753863
Short name T482
Test name
Test status
Simulation time 23219156273 ps
CPU time 28.42 seconds
Started Jun 10 07:47:44 PM PDT 24
Finished Jun 10 07:48:16 PM PDT 24
Peak memory 216172 kb
Host smart-5e472e99-fac3-4252-9ee3-c06ec72443a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.753863
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2967299316
Short name T632
Test name
Test status
Simulation time 3603106091 ps
CPU time 6.23 seconds
Started Jun 10 07:47:34 PM PDT 24
Finished Jun 10 07:47:45 PM PDT 24
Peak memory 216140 kb
Host smart-a19196fc-f746-401c-a30b-dae8ffefed12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967299316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2967299316
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2782715676
Short name T641
Test name
Test status
Simulation time 17726235 ps
CPU time 0.74 seconds
Started Jun 10 07:47:33 PM PDT 24
Finished Jun 10 07:47:39 PM PDT 24
Peak memory 205700 kb
Host smart-8af9ec7d-2711-4d15-91b5-668a99baa8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782715676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2782715676
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.483984110
Short name T483
Test name
Test status
Simulation time 171654664 ps
CPU time 0.86 seconds
Started Jun 10 07:47:39 PM PDT 24
Finished Jun 10 07:47:45 PM PDT 24
Peak memory 205700 kb
Host smart-c4bca2f9-3bc3-4da5-993e-7c468ee1a083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483984110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.483984110
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2556513964
Short name T462
Test name
Test status
Simulation time 17653625201 ps
CPU time 15.98 seconds
Started Jun 10 07:47:36 PM PDT 24
Finished Jun 10 07:47:57 PM PDT 24
Peak memory 232628 kb
Host smart-ca929128-12e5-4edd-bb88-0c5fbb0825e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556513964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2556513964
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2554944925
Short name T442
Test name
Test status
Simulation time 25210344 ps
CPU time 0.75 seconds
Started Jun 10 07:47:41 PM PDT 24
Finished Jun 10 07:47:47 PM PDT 24
Peak memory 204748 kb
Host smart-71dc090b-dc80-4c05-b6cc-6a0e62f1fbe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554944925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
554944925
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2089770407
Short name T423
Test name
Test status
Simulation time 592349544 ps
CPU time 3.16 seconds
Started Jun 10 07:47:47 PM PDT 24
Finished Jun 10 07:47:53 PM PDT 24
Peak memory 232504 kb
Host smart-6199e4bc-3b03-4589-9e4e-055e4ca6444a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089770407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2089770407
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1791653584
Short name T357
Test name
Test status
Simulation time 35833263 ps
CPU time 0.74 seconds
Started Jun 10 07:47:36 PM PDT 24
Finished Jun 10 07:47:42 PM PDT 24
Peak memory 206324 kb
Host smart-f756d456-48f5-4db1-b0e3-6fcf3281d67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791653584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1791653584
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3345022030
Short name T849
Test name
Test status
Simulation time 13046998953 ps
CPU time 44.72 seconds
Started Jun 10 07:47:51 PM PDT 24
Finished Jun 10 07:48:38 PM PDT 24
Peak memory 224384 kb
Host smart-299ce752-9cf7-4b07-9edd-13aa0af16fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345022030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3345022030
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1881171491
Short name T262
Test name
Test status
Simulation time 14145430314 ps
CPU time 162.28 seconds
Started Jun 10 07:47:50 PM PDT 24
Finished Jun 10 07:50:35 PM PDT 24
Peak memory 267940 kb
Host smart-ce2ca978-976c-45e4-9c9b-6aa6948f4fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881171491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1881171491
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3659881568
Short name T765
Test name
Test status
Simulation time 20112131003 ps
CPU time 198.78 seconds
Started Jun 10 07:47:47 PM PDT 24
Finished Jun 10 07:51:09 PM PDT 24
Peak memory 250120 kb
Host smart-4e685787-944d-46e8-8230-775962c28798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659881568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3659881568
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1148417942
Short name T220
Test name
Test status
Simulation time 1834538858 ps
CPU time 7.65 seconds
Started Jun 10 07:47:47 PM PDT 24
Finished Jun 10 07:47:57 PM PDT 24
Peak memory 232528 kb
Host smart-e4c3f0fc-9fd9-4f66-864d-cf5a631d90c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148417942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1148417942
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.4052201588
Short name T585
Test name
Test status
Simulation time 545495499 ps
CPU time 2.39 seconds
Started Jun 10 07:47:33 PM PDT 24
Finished Jun 10 07:47:40 PM PDT 24
Peak memory 226860 kb
Host smart-d8d6e1f0-7389-4ce7-830c-19c9c7338ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052201588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.4052201588
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.4208710886
Short name T109
Test name
Test status
Simulation time 848250751 ps
CPU time 10.69 seconds
Started Jun 10 07:47:32 PM PDT 24
Finished Jun 10 07:47:47 PM PDT 24
Peak memory 240608 kb
Host smart-7252992f-a3e6-4607-a263-251c6c1ec1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208710886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4208710886
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2903685312
Short name T544
Test name
Test status
Simulation time 117513761 ps
CPU time 1.03 seconds
Started Jun 10 07:47:32 PM PDT 24
Finished Jun 10 07:47:37 PM PDT 24
Peak memory 216488 kb
Host smart-8273f93c-f573-4f3e-88b8-ed2c94b92dc6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903685312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2903685312
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.4081389961
Short name T540
Test name
Test status
Simulation time 95677260 ps
CPU time 2.66 seconds
Started Jun 10 07:47:31 PM PDT 24
Finished Jun 10 07:47:38 PM PDT 24
Peak memory 232516 kb
Host smart-879c5d23-64af-4559-8d16-1b373612de0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081389961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.4081389961
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.266565799
Short name T709
Test name
Test status
Simulation time 362853682 ps
CPU time 3.32 seconds
Started Jun 10 07:47:33 PM PDT 24
Finished Jun 10 07:47:41 PM PDT 24
Peak memory 232648 kb
Host smart-81ff2b93-8517-4b81-930d-4aadb43bd553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266565799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.266565799
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.160080787
Short name T720
Test name
Test status
Simulation time 8376662864 ps
CPU time 15.96 seconds
Started Jun 10 07:47:41 PM PDT 24
Finished Jun 10 07:48:02 PM PDT 24
Peak memory 220812 kb
Host smart-218761f5-cff8-4ac6-b33e-14fe35e1d991
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=160080787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.160080787
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.420425437
Short name T215
Test name
Test status
Simulation time 46833633386 ps
CPU time 403.27 seconds
Started Jun 10 07:47:43 PM PDT 24
Finished Jun 10 07:54:30 PM PDT 24
Peak memory 256332 kb
Host smart-d22c5d2e-92ce-4f4b-b20d-269c836017d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420425437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.420425437
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2401415832
Short name T34
Test name
Test status
Simulation time 2660262801 ps
CPU time 13.15 seconds
Started Jun 10 07:47:37 PM PDT 24
Finished Jun 10 07:47:55 PM PDT 24
Peak memory 219176 kb
Host smart-b0dd7e12-a45a-45c2-9a8c-7e9da4130a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401415832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2401415832
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.217833206
Short name T519
Test name
Test status
Simulation time 242330620 ps
CPU time 2.29 seconds
Started Jun 10 07:47:38 PM PDT 24
Finished Jun 10 07:47:45 PM PDT 24
Peak memory 216096 kb
Host smart-ecb8cdaf-0181-42d3-bf09-272c0f4f36e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217833206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.217833206
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3506633575
Short name T682
Test name
Test status
Simulation time 10542347 ps
CPU time 0.71 seconds
Started Jun 10 07:47:34 PM PDT 24
Finished Jun 10 07:47:40 PM PDT 24
Peak memory 205384 kb
Host smart-53f06623-0acf-44ac-bcd8-106115e904c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506633575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3506633575
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.756950927
Short name T67
Test name
Test status
Simulation time 56153473 ps
CPU time 0.93 seconds
Started Jun 10 07:47:41 PM PDT 24
Finished Jun 10 07:47:46 PM PDT 24
Peak memory 205664 kb
Host smart-d1fded06-5e70-4950-8e41-6282a209d174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756950927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.756950927
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.4025996897
Short name T181
Test name
Test status
Simulation time 248032129 ps
CPU time 3.95 seconds
Started Jun 10 07:47:33 PM PDT 24
Finished Jun 10 07:47:41 PM PDT 24
Peak memory 232524 kb
Host smart-1b259567-876a-4ca3-8cee-50b5dd09e1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025996897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.4025996897
Directory /workspace/9.spi_device_upload/latest
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