Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2953887	1			T1	1		T2	1		T3	8
all_values[1]	2953887	1			T1	1		T2	1		T3	8
all_values[2]	2953887	1			T1	1		T2	1		T3	8
all_values[3]	2953887	1			T1	1		T2	1		T3	8
all_values[4]	2953887	1			T1	1		T2	1		T3	8
all_values[5]	2953887	1			T1	1		T2	1		T3	8
all_values[6]	2953887	1			T1	1		T2	1		T3	8
all_values[7]	2953887	1			T1	1		T2	1		T3	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23094116

1

T1

8

T2

8

T3

64

auto[1]

536980

1

T11

91809

T18

22

T21

42

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23608128

1

T1

8

T2

8

T3

64

auto[1]

22968

1

T11

13

T12

164

T23

8

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2893995	1			T1	1		T2	1		T3	8
all_values[0]	auto[0]	auto[1]	12396	1			T11	1		T12	57		T14	26
all_values[0]	auto[1]	auto[0]	47034	1			T11	15298		T18	1		T21	1
all_values[0]	auto[1]	auto[1]	462	1			T11	2		T18	3		T21	2
all_values[1]	auto[0]	auto[0]	2842706	1			T1	1		T2	1		T3	8
all_values[1]	auto[0]	auto[1]	5696	1			T12	57		T17	9		T46	41
all_values[1]	auto[1]	auto[0]	105126	1			T11	15298		T18	1		T21	3
all_values[1]	auto[1]	auto[1]	359	1			T11	4		T18	2		T21	1
all_values[2]	auto[0]	auto[0]	2911091	1			T1	1		T2	1		T3	8
all_values[2]	auto[0]	auto[1]	2036	1			T11	1		T12	50		T46	35
all_values[2]	auto[1]	auto[0]	40571	1			T11	15300		T18	2		T21	3
all_values[2]	auto[1]	auto[1]	189	1			T11	1		T18	2		T21	2
all_values[3]	auto[0]	auto[0]	2867914	1			T1	1		T2	1		T3	8
all_values[3]	auto[0]	auto[1]	182	1			T18	2		T21	2		T22	7
all_values[3]	auto[1]	auto[0]	85599	1			T11	15301		T18	1		T21	1
all_values[3]	auto[1]	auto[1]	192	1			T11	1		T18	1		T21	2
all_values[4]	auto[0]	auto[0]	2861639	1			T1	1		T2	1		T3	8
all_values[4]	auto[0]	auto[1]	170	1			T11	1		T18	2		T21	1
all_values[4]	auto[1]	auto[0]	91904	1			T11	15301		T18	1		T21	3
all_values[4]	auto[1]	auto[1]	174	1			T21	3		T22	5		T171	1
all_values[5]	auto[0]	auto[0]	2880421	1			T1	1		T2	1		T3	8
all_values[5]	auto[0]	auto[1]	295	1			T11	1		T23	8		T78	2
all_values[5]	auto[1]	auto[0]	73013	1			T11	1		T18	3		T21	1
all_values[5]	auto[1]	auto[1]	158	1			T11	1		T18	1		T21	5
all_values[6]	auto[0]	auto[0]	2884835	1			T1	1		T2	1		T3	8
all_values[6]	auto[0]	auto[1]	162	1			T18	2		T21	1		T22	2
all_values[6]	auto[1]	auto[0]	68725	1			T11	15300		T21	5		T22	12
all_values[6]	auto[1]	auto[1]	165	1			T21	4		T22	7		T31	1
all_values[7]	auto[0]	auto[0]	2930406	1			T1	1		T2	1		T3	8
all_values[7]	auto[0]	auto[1]	172	1			T21	4		T22	4		T139	5
all_values[7]	auto[1]	auto[0]	23149	1			T11	1		T18	2		T21	5
all_values[7]	auto[1]	auto[1]	160	1			T18	2		T21	1		T22	4