Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	28081	1			T1	6		T7	102		T8	8
auto[SpiFlashAddrCfg]	6425	1			T7	5		T8	6		T9	8
auto[SpiFlashAddr3b]	7705	1			T7	13		T8	4		T9	8
auto[SpiFlashAddr4b]	6528	1			T7	11		T8	4		T10	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28774

1

T1

6

T7

13

T8

22

auto[1]

19965

1

T7

118

T10

10

T11

19

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25441

1

T1

4

T7

57

T8

8

auto[1]

23298

1

T1

2

T7

74

T8

14

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	32056	1			T1	6		T7	107		T8	14
values[1]	914	1			T7	2		T8	2		T9	4
values[2]	1188	1			T10	2		T12	3		T14	2
values[3]	1241	1			T11	1		T12	2		T43	4
values[4]	1254	1			T7	1		T8	2		T11	6
values[5]	1195	1			T11	1		T12	2		T43	4
values[6]	1320	1			T7	4		T9	12		T10	2
values[7]	1268	1			T11	5		T12	3		T14	1
values[8]	8303	1			T7	17		T8	4		T10	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28268

1

T1

6

T7

131

T8

22

auto[1]

20471

1

T11

40

T13

2

T38

204

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

46967

1

T1

6

T7

129

T8

20

write

1772

1

T7

2

T8

2

T12

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16785

1

T7

23

T8

12

T10

4

valids[0x1]

31954

1

T1

6

T7

108

T8

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1315	1			T1	2		T8	4		T11	2
internal_process_ops[0x5a]	1284	1			T7	1		T8	2		T11	2
internal_process_ops[0x05]	16577	1			T1	4		T7	91		T10	2
internal_process_ops[0x35]	1291	1			T7	1		T10	2		T14	2
internal_process_ops[0x15]	1304	1			T7	1		T11	1		T12	2
internal_process_ops[0x03]	879	1			T7	3		T11	1		T12	2
internal_process_ops[0x0b]	866	1			T7	2		T8	2		T11	1
internal_process_ops[0x3b]	972	1			T8	2		T10	2		T11	1
internal_process_ops[0x6b]	892	1			T7	3		T12	2		T13	1
internal_process_ops[0xbb]	1004	1			T7	2		T12	3		T14	1
internal_process_ops[0xeb]	934	1			T12	3		T14	2		T40	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47859

1

T1

6

T7

129

T8

22

auto[1]

880

1

T7

2

T12

1

T40

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47033

1

T1

6

T7

127

T8

22

auto[1]

1706

1

T7

4

T12

3

T14

3

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9907

1

T1

6

T7

7

T8

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5550

1

T7

94

T10

4

T12

20

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1977

1

T8

6

T9

8

T12

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1667

1

T7

4

T10

2

T12

5

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2414

1

T7

3

T8

4

T9

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1978

1

T7

10

T10

2

T12

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2056

1

T7

3

T8

2

T12

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1730

1

T7

8

T10

2

T12

10

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

82

1

T40

1

T47

4

T31

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

53

1

T46

2

T47

4

T48

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

42

1

T45

2

T46

1

T56

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

56

1

T7

1

T46

1

T31

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

71

1

T46

1

T173

4

T169

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

69

1

T46

1

T88

1

T48

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

53

1

T12

1

T46

1

T47

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

52

1

T7

1

T88

1

T80

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

47

1

T14

1

T45

1

T44

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

57

1

T40

1

T47

1

T48

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

70

1

T88

1

T47

1

T44

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

72

1

T79

1

T42

2

T45

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

77

1

T8

2

T12

3

T80

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

52

1

T45

1

T88

1

T48

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

54

1

T12

1

T45

5

T80

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

82

1

T12

1

T46

1

T47

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7734

1

T11

9

T38

68

T54

247

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4440

1

T11

3

T38

36

T54

99

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1164

1

T11

1

T38

8

T51

1

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1182

1

T11

3

T38

9

T54

21

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1415

1

T11

9

T13

1

T38

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1464

1

T11

8

T38

29

T54

34

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1193

1

T11

2

T13

1

T38

17

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1096

1

T11

5

T38

19

T54

23

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

43

1

T17

2

T69

1

T18

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

64

1

T54

1

T69

2

T31

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

57

1

T54

1

T17

1

T18

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

53

1

T18

1

T31

2

T174

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

62

1

T38

2

T54

1

T17

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

36

1

T54

2

T69

5

T18

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

44

1

T17

1

T175

3

T176

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

48

1

T38

1

T69

2

T18

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

40

1

T69

1

T177

1

T175

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

54

1

T54

2

T17

3

T18

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

45

1

T19

1

T174

1

T178

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

49

1

T17

2

T18

1

T139

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

55

1

T54

2

T17

2

T179

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

52

1

T54

1

T69

3

T175

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

50

1

T18

3

T174

1

T180

7

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

31

1

T17

7

T69

1

T180

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3837	1			T7	7		T8	6		T12	9
auto[0]	values[0]	valids[0x1]	14209	1			T1	6		T7	100		T8	8
auto[0]	values[1]	valids[0x1]	477	1			T7	2		T8	2		T9	4
auto[0]	values[2]	valids[0x0]	489	1			T12	3		T14	2		T42	2
auto[0]	values[2]	valids[0x1]	259	1			T10	2		T94	2		T134	4
auto[0]	values[3]	valids[0x0]	484	1			T12	2		T40	1		T45	2
auto[0]	values[3]	valids[0x1]	261	1			T43	4		T40	2		T94	1
auto[0]	values[4]	valids[0x0]	493	1			T7	1		T8	2		T14	2
auto[0]	values[4]	valids[0x1]	248	1			T79	2		T46	4		T88	1
auto[0]	values[5]	valids[0x0]	462	1			T12	1		T43	4		T55	2
auto[0]	values[5]	valids[0x1]	270	1			T12	1		T45	2		T46	5
auto[0]	values[6]	valids[0x0]	526	1			T7	1		T10	2		T12	2
auto[0]	values[6]	valids[0x1]	325	1			T7	3		T9	12		T12	2
auto[0]	values[7]	valids[0x0]	570	1			T12	3		T14	1		T79	1
auto[0]	values[7]	valids[0x1]	234	1			T45	2		T46	4		T88	2
auto[0]	values[8]	valids[0x0]	3198	1			T7	14		T8	4		T10	2
auto[0]	values[8]	valids[0x1]	1926	1			T7	3		T12	9		T14	5
auto[1]	values[0]	valids[0x0]	3058	1			T11	6		T38	47		T54	73
auto[1]	values[0]	valids[0x1]	10952	1			T11	8		T38	77		T54	318
auto[1]	values[1]	valids[0x1]	437	1			T11	3		T38	7		T54	6
auto[1]	values[2]	valids[0x0]	288	1			T38	2		T54	5		T17	16
auto[1]	values[2]	valids[0x1]	152	1			T38	4		T54	2		T17	9
auto[1]	values[3]	valids[0x0]	314	1			T38	3		T54	9		T17	3
auto[1]	values[3]	valids[0x1]	182	1			T11	1		T54	5		T17	2
auto[1]	values[4]	valids[0x0]	332	1			T11	4		T38	1		T54	5
auto[1]	values[4]	valids[0x1]	181	1			T11	2		T38	1		T54	2
auto[1]	values[5]	valids[0x0]	282	1			T38	6		T54	4		T17	6
auto[1]	values[5]	valids[0x1]	181	1			T11	1		T38	1		T54	6
auto[1]	values[6]	valids[0x0]	294	1			T38	1		T54	13		T17	4
auto[1]	values[6]	valids[0x1]	175	1			T54	7		T17	5		T69	4
auto[1]	values[7]	valids[0x0]	265	1			T11	1		T38	6		T54	2
auto[1]	values[7]	valids[0x1]	199	1			T11	4		T38	5		T54	2
auto[1]	values[8]	valids[0x0]	1893	1			T11	4		T13	2		T38	26
auto[1]	values[8]	valids[0x1]	1286	1			T11	6		T38	17		T54	21