Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2982942

1

T1

5792

T2

1

T7

3062

auto[1]

15259

1

T7

91

T12

22

T14

4

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

976030

1

T1

4732

T2

1

T7

16

auto[1]

2022171

1

T1

1060

T7

3137

T11

207

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	570095	1			T1	407		T2	1		T8	1
auto[524288:1048575]	308445	1			T1	530		T7	41		T12	19
auto[1048576:1572863]	317161	1			T1	400		T11	4		T76	655
auto[1572864:2097151]	390993	1			T1	757		T11	1		T12	1
auto[2097152:2621439]	413259	1			T1	2		T7	2791		T12	256
auto[2621440:3145727]	332609	1			T1	67		T7	321		T12	4
auto[3145728:3670015]	308785	1			T1	2007		T12	9		T13	2
auto[3670016:4194303]	356854	1			T1	1622		T11	3		T12	256

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2040418

1

T1

1078

T2

1

T7

3152

auto[1]

957783

1

T1

4714

T7

1

T13

55

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2644774

1

T1

5792

T2

1

T7

3089

auto[1]

353427

1

T7

64

T14

144

T40

781

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	244117	1			T1	389		T2	1		T8	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	282303	1			T1	18		T11	207		T12	294
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	76228	1			T1	24		T7	3		T12	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	193671	1			T1	506		T7	1		T12	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	71107	1			T1	400		T11	4		T76	655
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	195254	1			T38	2462		T54	2534		T17	258
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	151260	1			T1	757		T11	1		T12	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	199990	1			T14	514		T76	512		T79	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	157278	1			T1	2		T7	1		T14	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	212089	1			T7	2790		T12	256		T14	1183
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	82794	1			T1	64		T7	1		T12	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	202761	1			T1	3		T7	256		T12	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	74939	1			T1	1489		T12	3		T13	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	177522	1			T1	518		T12	1		T38	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	111291	1			T1	1607		T11	3		T76	104
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	200041	1			T1	15		T12	256		T40	512
auto[0]	auto[1]	auto[0:524287]	auto[0]	271	1			T79	1		T38	1		T54	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	41320	1			T14	141		T17	385		T45	5
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	216	1			T17	3		T132	18		T46	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	36859	1			T38	512		T45	5		T46	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	388	1			T40	5		T54	1		T17	7
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	48259	1			T40	771		T38	512		T54	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	876	1			T45	4		T46	1		T69	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	36684	1			T46	384		T69	2		T18	2034
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	403	1			T54	2		T17	1		T132	127
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	41482	1			T54	128		T45	513		T46	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	520	1			T7	7		T38	4		T54	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	44874	1			T7	3		T38	1079		T54	128
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2413	1			T79	2		T38	4		T54	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	52172	1			T38	3		T17	512		T45	257
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	220	1			T14	1		T38	2		T54	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	43340	1			T14	1		T38	514		T54	2
auto[1]	auto[0]	auto[0:524287]	auto[0]	203	1			T40	1		T38	2		T54	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	1534	1			T40	13		T38	2		T54	33
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	157	1			T7	1		T12	1		T38	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1059	1			T7	36		T12	15		T38	7
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	161	1			T38	1		T54	1		T69	6
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1511	1			T38	1		T54	3		T69	117
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	185	1			T14	2		T54	3		T17	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1509	1			T14	1		T54	30		T17	71
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	155	1			T54	1		T17	2		T46	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1236	1			T54	13		T17	12		T47	11
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	174	1			T12	1		T54	2		T17	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1191	1			T54	43		T17	148		T69	38
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	151	1			T12	1		T54	1		T17	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1359	1			T12	4		T54	38		T17	55
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	184	1			T38	1		T46	2		T18	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1360	1			T46	1		T18	18		T47	38
auto[1]	auto[1]	auto[0:524287]	auto[0]	40	1			T17	1		T19	2		T240	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	307	1			T17	20		T19	6		T240	12
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	34	1			T18	2		T80	1		T56	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	221	1			T18	1		T80	7		T56	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	47	1			T40	1		T54	1		T17	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	434	1			T40	4		T54	1		T17	22
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	50	1			T69	2		T18	2		T48	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	439	1			T69	59		T48	1		T139	15
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	45	1			T45	1		T46	1		T47	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	571	1			T45	30		T47	28		T31	51
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	41	1			T7	3		T38	1		T18	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	254	1			T7	51		T38	3		T18	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	32	1			T45	1		T18	1		T48	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	197	1			T45	19		T18	16		T48	5
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	50	1			T14	1		T38	1		T54	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	368	1			T38	2		T54	26		T177	22

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1678520	1			T1	1078		T2	1		T7	3052
auto[0]	auto[0]	auto[1]	954125	1			T1	4714		T13	55		T76	7321
auto[0]	auto[1]	auto[0]	346932	1			T7	10		T14	143		T40	775
auto[0]	auto[1]	auto[1]	3365	1			T40	1		T54	2		T17	1
auto[1]	auto[0]	auto[0]	11904	1			T7	37		T12	22		T14	3
auto[1]	auto[0]	auto[1]	225	1			T40	1		T54	3		T17	1
auto[1]	auto[1]	auto[0]	3062	1			T7	53		T14	1		T40	4
auto[1]	auto[1]	auto[1]	68	1			T7	1		T40	1		T38	1