Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16862

1

T1

6

T7

13

T8

22

auto[1]

11406

1

T7

118

T10

10

T12

40

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3339	1			T10	10		T12	20		T14	21
values[1]	2959	1			T1	6		T7	54		T43	10
values[2]	4016	1			T134	14		T45	20		T46	24
values[3]	3868	1			T8	22		T40	34		T79	20
values[4]	3691	1			T12	25		T40	25		T94	20
values[5]	3550	1			T9	16		T12	37		T14	20
values[6]	3541	1			T7	77		T14	23		T45	40
values[7]	3304	1			T76	4		T95	10		T257	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3512	1			T12	20		T14	23		T76	4
values[1]	3494	1			T45	51		T46	43		T88	63
values[2]	3927	1			T1	6		T7	54		T9	16
values[3]	3123	1			T14	20		T95	10		T132	12
values[4]	3676	1			T10	10		T258	2		T46	20
values[5]	3180	1			T8	22		T12	25		T79	20
values[6]	3175	1			T45	40		T259	2		T260	4
values[7]	4181	1			T7	77		T12	37		T14	21

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	215	1			T12	10		T261	4		T262	14
auto[0]	values[0]	values[1]	205	1			T170	12		T48	15		T220	10
auto[0]	values[0]	values[2]	300	1			T136	24		T47	14		T208	15
auto[0]	values[0]	values[3]	203	1			T172	16		T195	24		T199	16
auto[0]	values[0]	values[4]	214	1			T48	16		T50	11		T244	13
auto[0]	values[0]	values[5]	265	1			T46	11		T48	9		T31	11
auto[0]	values[0]	values[6]	207	1			T45	10		T81	11		T195	15
auto[0]	values[0]	values[7]	215	1			T14	15		T50	12		T244	15
auto[0]	values[1]	values[0]	339	1			T31	9		T80	83		T201	10
auto[0]	values[1]	values[1]	275	1			T46	12		T31	98		T56	11
auto[0]	values[1]	values[2]	242	1			T1	6		T7	6		T43	10
auto[0]	values[1]	values[3]	165	1			T45	14		T56	13		T217	11
auto[0]	values[1]	values[4]	151	1			T18	13		T263	12		T264	4
auto[0]	values[1]	values[5]	148	1			T79	11		T246	20		T195	12
auto[0]	values[1]	values[6]	164	1			T215	13		T231	2		T243	14
auto[0]	values[1]	values[7]	418	1			T45	14		T48	15		T265	4
auto[0]	values[2]	values[0]	334	1			T134	14		T46	11		T216	11
auto[0]	values[2]	values[1]	377	1			T88	54		T48	10		T50	7
auto[0]	values[2]	values[2]	189	1			T45	9		T240	41		T227	14
auto[0]	values[2]	values[3]	270	1			T50	16		T172	11		T256	6
auto[0]	values[2]	values[4]	289	1			T80	8		T266	14		T140	10
auto[0]	values[2]	values[5]	242	1			T48	15		T81	9		T267	14
auto[0]	values[2]	values[6]	265	1			T47	11		T81	10		T268	20
auto[0]	values[2]	values[7]	367	1			T47	14		T208	9		T247	11
auto[0]	values[3]	values[0]	164	1			T219	2		T208	9		T220	11
auto[0]	values[3]	values[1]	384	1			T91	6		T217	13		T195	13
auto[0]	values[3]	values[2]	328	1			T40	24		T18	30		T247	13
auto[0]	values[3]	values[3]	311	1			T132	12		T208	11		T244	12
auto[0]	values[3]	values[4]	296	1			T47	10		T216	14		T254	24
auto[0]	values[3]	values[5]	345	1			T8	22		T138	2		T169	20
auto[0]	values[3]	values[6]	395	1			T47	10		T48	14		T56	11
auto[0]	values[3]	values[7]	328	1			T79	15		T46	15		T50	11
auto[0]	values[4]	values[0]	233	1			T81	11		T246	9		T269	14
auto[0]	values[4]	values[1]	208	1			T46	12		T245	15		T202	16
auto[0]	values[4]	values[2]	268	1			T44	10		T56	11		T201	11
auto[0]	values[4]	values[3]	316	1			T220	17		T172	36		T62	10
auto[0]	values[4]	values[4]	215	1			T215	12		T270	8		T56	9
auto[0]	values[4]	values[5]	235	1			T12	19		T94	10		T215	7
auto[0]	values[4]	values[6]	410	1			T89	14		T47	31		T172	18
auto[0]	values[4]	values[7]	217	1			T40	17		T46	27		T271	2
auto[0]	values[5]	values[0]	202	1			T49	79		T208	13		T215	9
auto[0]	values[5]	values[1]	306	1			T45	40		T272	22		T215	11
auto[0]	values[5]	values[2]	260	1			T9	16		T80	14		T172	33
auto[0]	values[5]	values[3]	151	1			T14	10		T200	6		T273	4
auto[0]	values[5]	values[4]	232	1			T47	9		T44	7		T208	48
auto[0]	values[5]	values[5]	239	1			T56	10		T81	10		T227	15
auto[0]	values[5]	values[6]	247	1			T45	6		T215	12		T244	12
auto[0]	values[5]	values[7]	211	1			T12	13		T274	2		T275	4
auto[0]	values[6]	values[0]	426	1			T14	16		T48	66		T172	90
auto[0]	values[6]	values[1]	258	1			T217	14		T202	9		T199	8
auto[0]	values[6]	values[2]	413	1			T45	30		T88	10		T80	81
auto[0]	values[6]	values[3]	294	1			T165	12		T276	62		T244	11
auto[0]	values[6]	values[4]	318	1			T258	2		T46	13		T47	21
auto[0]	values[6]	values[5]	181	1			T245	14		T220	8		T217	12
auto[0]	values[6]	values[6]	149	1			T48	9		T31	14		T208	15
auto[0]	values[6]	values[7]	247	1			T7	7		T47	14		T44	25
auto[0]	values[7]	values[0]	183	1			T76	4		T164	8		T48	6
auto[0]	values[7]	values[1]	163	1			T47	49		T195	9		T210	20
auto[0]	values[7]	values[2]	268	1			T166	6		T172	14		T227	29
auto[0]	values[7]	values[3]	250	1			T95	10		T47	13		T215	9
auto[0]	values[7]	values[4]	325	1			T88	12		T80	11		T215	28
auto[0]	values[7]	values[5]	318	1			T88	10		T225	10		T81	98
auto[0]	values[7]	values[6]	158	1			T48	15		T247	16		T80	40
auto[0]	values[7]	values[7]	351	1			T173	18		T48	15		T208	11
auto[1]	values[0]	values[0]	254	1			T12	10		T80	7		T172	64
auto[1]	values[0]	values[1]	322	1			T48	14		T220	14		T195	4
auto[1]	values[0]	values[2]	101	1			T47	6		T208	5		T195	9
auto[1]	values[0]	values[3]	152	1			T172	6		T195	17		T199	4
auto[1]	values[0]	values[4]	203	1			T10	10		T48	4		T50	9
auto[1]	values[0]	values[5]	132	1			T46	10		T48	11		T31	9
auto[1]	values[0]	values[6]	148	1			T45	10		T260	4		T81	15
auto[1]	values[0]	values[7]	203	1			T14	6		T50	8		T244	5
auto[1]	values[1]	values[0]	143	1			T31	11		T80	8		T201	12
auto[1]	values[1]	values[1]	160	1			T46	11		T31	7		T56	14
auto[1]	values[1]	values[2]	304	1			T7	48		T46	10		T44	5
auto[1]	values[1]	values[3]	96	1			T45	6		T277	6		T56	7
auto[1]	values[1]	values[4]	100	1			T18	7		T218	18		T159	15
auto[1]	values[1]	values[5]	91	1			T79	9		T246	16		T195	10
auto[1]	values[1]	values[6]	63	1			T215	12		T81	7		T210	4
auto[1]	values[1]	values[7]	100	1			T45	6		T48	5		T220	4
auto[1]	values[2]	values[0]	227	1			T46	13		T216	17		T49	7
auto[1]	values[2]	values[1]	223	1			T88	9		T48	25		T50	14
auto[1]	values[2]	values[2]	133	1			T45	11		T240	12		T227	9
auto[1]	values[2]	values[3]	200	1			T50	5		T172	9		T278	14
auto[1]	values[2]	values[4]	138	1			T279	4		T80	23		T140	10
auto[1]	values[2]	values[5]	118	1			T48	5		T81	11		T280	10
auto[1]	values[2]	values[6]	147	1			T47	9		T281	8		T81	20
auto[1]	values[2]	values[7]	497	1			T47	6		T208	40		T247	12
auto[1]	values[3]	values[0]	209	1			T208	31		T220	10		T201	9
auto[1]	values[3]	values[1]	143	1			T217	7		T195	7		T159	8
auto[1]	values[3]	values[2]	190	1			T40	10		T18	11		T247	8
auto[1]	values[3]	values[3]	127	1			T208	9		T244	18		T159	8
auto[1]	values[3]	values[4]	213	1			T47	19		T216	6		T80	12
auto[1]	values[3]	values[5]	153	1			T56	9		T242	6		T196	6
auto[1]	values[3]	values[6]	158	1			T47	16		T48	6		T232	16
auto[1]	values[3]	values[7]	124	1			T79	5		T46	7		T50	9
auto[1]	values[4]	values[0]	222	1			T81	9		T246	11		T195	10
auto[1]	values[4]	values[1]	93	1			T46	8		T245	5		T202	9
auto[1]	values[4]	values[2]	237	1			T44	10		T56	9		T201	16
auto[1]	values[4]	values[3]	173	1			T220	10		T172	4		T195	9
auto[1]	values[4]	values[4]	111	1			T215	8		T56	17		T217	3
auto[1]	values[4]	values[5]	275	1			T12	6		T94	10		T215	13
auto[1]	values[4]	values[6]	197	1			T259	2		T47	18		T172	3
auto[1]	values[4]	values[7]	281	1			T40	8		T46	14		T48	7
auto[1]	values[5]	values[0]	123	1			T42	16		T203	26		T49	20
auto[1]	values[5]	values[1]	131	1			T45	11		T215	12		T252	16
auto[1]	values[5]	values[2]	367	1			T55	8		T80	163		T172	3
auto[1]	values[5]	values[3]	181	1			T14	10		T282	5		T210	26
auto[1]	values[5]	values[4]	234	1			T47	43		T44	13		T208	20
auto[1]	values[5]	values[5]	170	1			T133	6		T56	18		T81	10
auto[1]	values[5]	values[6]	272	1			T45	14		T215	8		T244	23
auto[1]	values[5]	values[7]	224	1			T12	24		T80	91		T81	6
auto[1]	values[6]	values[0]	123	1			T14	7		T48	9		T172	5
auto[1]	values[6]	values[1]	124	1			T217	6		T202	11		T199	12
auto[1]	values[6]	values[2]	173	1			T45	10		T88	16		T80	8
auto[1]	values[6]	values[3]	83	1			T244	9		T220	13		T192	5
auto[1]	values[6]	values[4]	281	1			T46	7		T47	30		T244	18
auto[1]	values[6]	values[5]	154	1			T245	6		T220	16		T217	8
auto[1]	values[6]	values[6]	86	1			T48	11		T31	12		T208	5
auto[1]	values[6]	values[7]	231	1			T7	70		T47	9		T44	16
auto[1]	values[7]	values[0]	115	1			T48	14		T159	7		T199	9
auto[1]	values[7]	values[1]	122	1			T47	3		T195	11		T210	9
auto[1]	values[7]	values[2]	154	1			T172	6		T227	7		T242	8
auto[1]	values[7]	values[3]	151	1			T47	35		T215	11		T201	10
auto[1]	values[7]	values[4]	356	1			T88	70		T80	9		T215	21
auto[1]	values[7]	values[5]	114	1			T88	10		T81	6		T246	11
auto[1]	values[7]	values[6]	109	1			T48	5		T247	4		T80	6
auto[1]	values[7]	values[7]	167	1			T257	8		T48	7		T208	9