Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2953887	1			T1	1		T2	1		T3	8
all_pins[1]	2953887	1			T1	1		T2	1		T3	8
all_pins[2]	2953887	1			T1	1		T2	1		T3	8
all_pins[3]	2953887	1			T1	1		T2	1		T3	8
all_pins[4]	2953887	1			T1	1		T2	1		T3	8
all_pins[5]	2953887	1			T1	1		T2	1		T3	8
all_pins[6]	2953887	1			T1	1		T2	1		T3	8
all_pins[7]	2953887	1			T1	1		T2	1		T3	8

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	23558938	1			T1	8		T2	8		T3	64
values[0x1]	72158	1			T11	15252		T18	11		T21	20
transitions[0x0=>0x1]	70994	1			T11	15248		T18	5		T21	15
transitions[0x1=>0x0]	71003	1			T11	15248		T18	5		T21	15

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2953393	1			T1	1		T2	1		T3	8
all_pins[0]	values[0x1]	494	1			T11	2		T18	3		T21	2
all_pins[0]	transitions[0x0=>0x1]	323	1			T18	1		T21	1		T22	2
all_pins[0]	transitions[0x1=>0x0]	219	1			T11	2		T22	6		T139	5
all_pins[1]	values[0x0]	2953497	1			T1	1		T2	1		T3	8
all_pins[1]	values[0x1]	390	1			T11	4		T18	2		T21	1
all_pins[1]	transitions[0x0=>0x1]	338	1			T11	3		T21	1		T22	6
all_pins[1]	transitions[0x1=>0x0]	139	1			T21	2		T22	4		T171	2
all_pins[2]	values[0x0]	2953696	1			T1	1		T2	1		T3	8
all_pins[2]	values[0x1]	191	1			T11	1		T18	2		T21	2
all_pins[2]	transitions[0x0=>0x1]	140	1			T18	2		T21	2		T22	5
all_pins[2]	transitions[0x1=>0x0]	141	1			T18	1		T21	2		T22	3
all_pins[3]	values[0x0]	2953695	1			T1	1		T2	1		T3	8
all_pins[3]	values[0x1]	192	1			T11	1		T18	1		T21	2
all_pins[3]	transitions[0x0=>0x1]	140	1			T11	1		T18	1		T21	2
all_pins[3]	transitions[0x1=>0x0]	122	1			T21	3		T22	3		T139	4
all_pins[4]	values[0x0]	2953713	1			T1	1		T2	1		T3	8
all_pins[4]	values[0x1]	174	1			T21	3		T22	5		T171	1
all_pins[4]	transitions[0x0=>0x1]	144	1			T21	2		T22	5		T139	7
all_pins[4]	transitions[0x1=>0x0]	2037	1			T11	1		T18	1		T21	4
all_pins[5]	values[0x0]	2951820	1			T1	1		T2	1		T3	8
all_pins[5]	values[0x1]	2067	1			T11	1		T18	1		T21	5
all_pins[5]	transitions[0x0=>0x1]	1347	1			T11	1		T18	1		T21	2
all_pins[5]	transitions[0x1=>0x0]	67770	1			T11	15243		T21	1		T22	7
all_pins[6]	values[0x0]	2885397	1			T1	1		T2	1		T3	8
all_pins[6]	values[0x1]	68490	1			T11	15243		T21	4		T22	7
all_pins[6]	transitions[0x0=>0x1]	68455	1			T11	15243		T21	4		T22	6
all_pins[6]	transitions[0x1=>0x0]	125	1			T18	2		T21	1		T22	3
all_pins[7]	values[0x0]	2953727	1			T1	1		T2	1		T3	8
all_pins[7]	values[0x1]	160	1			T18	2		T21	1		T22	4
all_pins[7]	transitions[0x0=>0x1]	107	1			T21	1		T22	3		T171	1
all_pins[7]	transitions[0x1=>0x0]	450	1			T11	2		T18	1		T21	2