Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	363	1			T12	1		T79	1		T94	2
auto[ReadAddrCrossIntoMailbox]	288	1			T12	1		T14	1		T79	2
auto[ReadAddrCrossOutOfMailbox]	266	1			T14	2		T79	1		T94	2
auto[ReadAddrCrossAllMailbox]	202	1			T45	1		T88	1		T165	2
auto[ReadAddrOutsideMailbox]	3156	1			T7	10		T8	4		T10	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2144

1

T7

4

T8

2

T10

1

auto[1]

2131

1

T7

6

T8

2

T10

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	673	1			T7	3		T12	2		T14	5
read_ops[0x0b]	670	1			T7	2		T8	2		T12	4
read_ops[0x3b]	761	1			T8	2		T10	2		T12	2
read_ops[0x6b]	692	1			T7	3		T12	2		T14	1
read_ops[0xbb]	755	1			T7	2		T12	3		T14	1
read_ops[0xeb]	724	1			T12	3		T14	2		T40	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T94	1		T220	1		T172	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T79	1		T45	1		T47	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T47	1		T208	1		T217	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T14	1		T47	1		T48	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T44	1		T31	1		T80	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T14	2		T79	1		T47	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T283	2		T81	1		T199	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T245	1		T220	1		T283	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	262	1			T7	1		T12	1		T14	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	244	1			T7	2		T12	1		T40	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	22	1			T46	1		T47	1		T172	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T94	1		T48	1		T49	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T47	2		T216	1		T80	3
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T47	1		T49	2		T208	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T56	1		T217	1		T250	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T47	1		T216	1		T48	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T165	1		T80	1		T172	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T165	1		T48	1		T208	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	285	1			T7	1		T8	1		T12	4
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	221	1			T7	1		T8	1		T43	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T138	1		T45	1		T46	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T138	1		T169	1		T208	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T12	1		T169	2		T47	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T169	2		T47	1		T48	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T94	1		T47	2		T48	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T46	1		T215	1		T222	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	27	1			T47	1		T56	2		T217	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T208	2		T215	1		T56	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	256	1			T8	1		T10	1		T12	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	276	1			T8	1		T10	1		T14	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	22	1			T45	2		T165	2		T80	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T46	3		T165	2		T44	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T165	1		T172	1		T195	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T46	1		T165	1		T47	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T169	1		T31	1		T208	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T94	1		T169	1		T47	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T169	3		T47	1		T50	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T169	3		T47	1		T48	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	245	1			T7	2		T12	2		T46	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	254	1			T7	1		T14	1		T45	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T89	3		T47	1		T49	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T89	3		T44	1		T208	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T79	1		T47	1		T49	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T50	1		T240	1		T220	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T88	2		T47	3		T31	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T208	2		T256	1		T210	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T45	1		T88	1		T31	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T47	1		T48	1		T244	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	294	1			T12	1		T40	2		T79	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	271	1			T7	2		T12	2		T14	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T12	1		T169	1		T47	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T169	1		T47	1		T48	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T79	1		T49	1		T56	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T47	1		T48	1		T50	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	15	1			T244	1		T56	1		T227	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T47	1		T48	2		T215	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T56	1		T284	1		T58	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T47	1		T216	1		T208	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	263	1			T45	4		T203	3		T46	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	285	1			T12	2		T14	2		T40	2