Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2826	1			T14	21		T40	25		T79	20
values[1]	3480	1			T8	22		T9	16		T55	8
values[2]	3156	1			T76	4		T45	20		T271	2
values[3]	4064	1			T12	45		T132	12		T133	6
values[4]	4139	1			T12	37		T14	23		T40	34
values[5]	3431	1			T7	54		T10	10		T43	10
values[6]	3534	1			T1	6		T42	16		T134	14
values[7]	3638	1			T7	77		T14	20		T79	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3320	1			T7	77		T8	22		T14	64
values[1]	3930	1			T1	6		T45	51		T88	26
values[2]	2872	1			T12	37		T45	20		T258	2
values[3]	3577	1			T40	34		T219	2		T203	26
values[4]	3785	1			T7	54		T12	25		T132	12
values[5]	3539	1			T9	16		T43	10		T55	8
values[6]	3902	1			T12	20		T40	25		T260	4
values[7]	3343	1			T10	10		T76	4		T79	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27775

1

T1

6

T7

129

T8

22

auto[1]

493

1

T7

2

T12

1

T40

1

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	300	1			T14	21		T285	16		T250	23
auto[0]	values[0]	values[1]	508	1			T88	26		T44	20		T220	25
auto[0]	values[0]	values[2]	376	1			T44	20		T215	20		T217	20
auto[0]	values[0]	values[3]	396	1			T203	26		T48	40		T50	21
auto[0]	values[0]	values[4]	274	1			T202	25		T286	10		T250	19
auto[0]	values[0]	values[5]	337	1			T79	19		T208	20		T232	16
auto[0]	values[0]	values[6]	270	1			T40	25		T47	25		T244	22
auto[0]	values[0]	values[7]	321	1			T208	20		T269	14		T202	64
auto[0]	values[1]	values[0]	345	1			T8	22		T48	20		T31	25
auto[0]	values[1]	values[1]	332	1			T47	52		T208	20		T220	20
auto[0]	values[1]	values[2]	564	1			T217	20		T227	18		T287	20
auto[0]	values[1]	values[3]	389	1			T47	25		T80	43		T172	78
auto[0]	values[1]	values[4]	560	1			T45	20		T46	21		T48	25
auto[0]	values[1]	values[5]	517	1			T9	16		T55	8		T45	20
auto[0]	values[1]	values[6]	336	1			T46	20		T208	20		T281	8
auto[0]	values[1]	values[7]	360	1			T277	6		T279	4		T252	16
auto[0]	values[2]	values[0]	291	1			T45	20		T271	2		T288	2
auto[0]	values[2]	values[1]	482	1			T166	6		T47	20		T247	39
auto[0]	values[2]	values[2]	337	1			T50	21		T172	21		T206	12
auto[0]	values[2]	values[3]	421	1			T81	28		T246	20		T202	38
auto[0]	values[2]	values[4]	326	1			T47	29		T80	30		T215	67
auto[0]	values[2]	values[5]	317	1			T18	19		T48	20		T289	4
auto[0]	values[2]	values[6]	419	1			T272	22		T31	20		T208	48
auto[0]	values[2]	values[7]	504	1			T76	4		T173	18		T18	41
auto[0]	values[3]	values[0]	297	1			T246	19		T267	14		T242	20
auto[0]	values[3]	values[1]	494	1			T44	20		T205	14		T90	16
auto[0]	values[3]	values[2]	281	1			T50	20		T208	20		T242	20
auto[0]	values[3]	values[3]	707	1			T200	6		T46	20		T215	40
auto[0]	values[3]	values[4]	422	1			T12	24		T132	12		T133	6
auto[0]	values[3]	values[5]	538	1			T48	18		T172	20		T56	26
auto[0]	values[3]	values[6]	643	1			T12	20		T46	40		T215	20
auto[0]	values[3]	values[7]	610	1			T47	29		T44	41		T49	24
auto[0]	values[4]	values[0]	475	1			T14	23		T262	14		T80	197
auto[0]	values[4]	values[1]	644	1			T47	23		T225	10		T81	46
auto[0]	values[4]	values[2]	392	1			T12	37		T49	20		T265	4
auto[0]	values[4]	values[3]	451	1			T40	33		T219	2		T172	106
auto[0]	values[4]	values[4]	639	1			T47	20		T245	18		T80	61
auto[0]	values[4]	values[5]	427	1			T138	2		T46	22		T88	82
auto[0]	values[4]	values[6]	813	1			T46	22		T47	20		T48	19
auto[0]	values[4]	values[7]	220	1			T217	22		T222	20		T290	8
auto[0]	values[5]	values[0]	604	1			T257	8		T49	98		T208	38
auto[0]	values[5]	values[1]	588	1			T45	50		T80	33		T276	62
auto[0]	values[5]	values[2]	396	1			T45	20		T261	4		T47	20
auto[0]	values[5]	values[3]	250	1			T247	23		T244	29		T196	20
auto[0]	values[5]	values[4]	393	1			T7	52		T215	27		T220	27
auto[0]	values[5]	values[5]	304	1			T43	10		T47	47		T56	19
auto[0]	values[5]	values[6]	575	1			T260	4		T244	20		T220	20
auto[0]	values[5]	values[7]	268	1			T10	10		T95	10		T275	4
auto[0]	values[6]	values[0]	410	1			T48	75		T172	20		T222	20
auto[0]	values[6]	values[1]	428	1			T1	6		T80	20		T172	20
auto[0]	values[6]	values[2]	272	1			T88	80		T291	18		T197	20
auto[0]	values[6]	values[3]	224	1			T89	14		T169	20		T292	4
auto[0]	values[6]	values[4]	532	1			T48	20		T80	177		T293	4
auto[0]	values[6]	values[5]	558	1			T47	22		T208	20		T215	101
auto[0]	values[6]	values[6]	394	1			T46	20		T50	20		T208	47
auto[0]	values[6]	values[7]	661	1			T42	14		T134	14		T136	24
auto[0]	values[7]	values[0]	552	1			T7	77		T14	20		T47	52
auto[0]	values[7]	values[1]	386	1			T48	22		T31	20		T56	20
auto[0]	values[7]	values[2]	205	1			T258	2		T164	8		T165	12
auto[0]	values[7]	values[3]	654	1			T216	20		T81	20		T273	4
auto[0]	values[7]	values[4]	569	1			T45	59		T216	28		T50	20
auto[0]	values[7]	values[5]	472	1			T259	2		T80	86		T220	22
auto[0]	values[7]	values[6]	387	1			T170	12		T31	103		T254	24
auto[0]	values[7]	values[7]	358	1			T79	20		T94	20		T48	20
auto[1]	values[0]	values[0]	1	1			T294	1		-	-		-	-
auto[1]	values[0]	values[1]	14	1			T220	2		T202	3		T295	4
auto[1]	values[0]	values[2]	2	1			T207	1		T296	1		-	-
auto[1]	values[0]	values[3]	5	1			T220	2		T210	1		T297	2
auto[1]	values[0]	values[4]	7	1			T250	1		T298	1		T294	3
auto[1]	values[0]	values[5]	10	1			T79	1		T172	3		T299	1
auto[1]	values[0]	values[6]	4	1			T244	2		T300	2		-	-
auto[1]	values[0]	values[7]	1	1			T143	1		-	-		-	-
auto[1]	values[1]	values[0]	7	1			T31	1		T210	2		T196	1
auto[1]	values[1]	values[1]	12	1			T220	1		T56	4		T81	3
auto[1]	values[1]	values[2]	15	1			T227	2		T197	2		T296	2
auto[1]	values[1]	values[3]	5	1			T47	1		T80	3		T298	1
auto[1]	values[1]	values[4]	14	1			T46	1		T48	2		T301	2
auto[1]	values[1]	values[5]	9	1			T195	2		T199	2		T248	2
auto[1]	values[1]	values[6]	8	1			T46	1		T302	1		T303	1
auto[1]	values[1]	values[7]	7	1			T140	2		T299	2		T304	1
auto[1]	values[2]	values[0]	7	1			T32	1		T305	1		T306	3
auto[1]	values[2]	values[1]	9	1			T247	2		T217	1		T303	2
auto[1]	values[2]	values[2]	6	1			T172	1		T142	2		T307	2
auto[1]	values[2]	values[3]	18	1			T81	2		T202	1		T299	2
auto[1]	values[2]	values[4]	4	1			T80	1		T308	2		T304	1
auto[1]	values[2]	values[5]	6	1			T18	1		T143	1		T309	2
auto[1]	values[2]	values[6]	6	1			T208	1		T81	2		T224	1
auto[1]	values[2]	values[7]	3	1			T48	1		T310	1		T306	1
auto[1]	values[3]	values[0]	5	1			T246	1		T239	2		T311	2
auto[1]	values[3]	values[1]	6	1			T81	1		T224	1		T312	1
auto[1]	values[3]	values[2]	2	1			T313	2		-	-		-	-
auto[1]	values[3]	values[3]	20	1			T46	1		T58	2		T32	2
auto[1]	values[3]	values[4]	6	1			T12	1		T48	1		T220	2
auto[1]	values[3]	values[5]	15	1			T48	2		T159	2		T207	1
auto[1]	values[3]	values[6]	13	1			T46	1		T215	1		T81	1
auto[1]	values[3]	values[7]	5	1			T58	1		T248	1		T314	2
auto[1]	values[4]	values[0]	8	1			T80	2		T56	1		T195	2
auto[1]	values[4]	values[1]	8	1			T47	1		T309	4		T315	1
auto[1]	values[4]	values[2]	9	1			T239	1		T59	4		T316	1
auto[1]	values[4]	values[3]	11	1			T40	1		T172	1		T195	4
auto[1]	values[4]	values[4]	13	1			T245	2		T80	1		T278	2
auto[1]	values[4]	values[5]	8	1			T46	2		T88	1		T224	1
auto[1]	values[4]	values[6]	15	1			T46	1		T47	2		T48	1
auto[1]	values[4]	values[7]	6	1			T217	1		T196	2		T297	3
auto[1]	values[5]	values[0]	4	1			T49	1		T208	2		T197	1
auto[1]	values[5]	values[1]	10	1			T45	1		T248	2		T34	4
auto[1]	values[5]	values[2]	7	1			T222	2		T299	2		T305	3
auto[1]	values[5]	values[3]	8	1			T244	1		T310	4		T221	1
auto[1]	values[5]	values[4]	12	1			T7	2		T215	2		T256	2
auto[1]	values[5]	values[5]	5	1			T47	1		T56	1		T196	1
auto[1]	values[5]	values[6]	3	1			T217	1		T159	1		T317	1
auto[1]	values[5]	values[7]	4	1			T195	1		T312	2		T34	1
auto[1]	values[6]	values[0]	5	1			T318	1		T34	1		T253	3
auto[1]	values[6]	values[1]	6	1			T201	2		T239	2		T319	2
auto[1]	values[6]	values[2]	5	1			T88	2		T319	1		T320	2
auto[1]	values[6]	values[3]	6	1			T250	3		T192	1		T321	2
auto[1]	values[6]	values[4]	9	1			T302	2		T192	1		T322	4
auto[1]	values[6]	values[5]	7	1			T47	1		T215	2		T217	3
auto[1]	values[6]	values[6]	9	1			T208	1		T199	1		T59	2
auto[1]	values[6]	values[7]	8	1			T42	2		T46	1		T195	2
auto[1]	values[7]	values[0]	9	1			T207	2		T58	1		T142	3
auto[1]	values[7]	values[1]	3	1			T32	1		T321	1		T300	1
auto[1]	values[7]	values[2]	3	1			T224	2		T249	1		-	-
auto[1]	values[7]	values[3]	12	1			T282	4		T199	1		T303	2
auto[1]	values[7]	values[4]	5	1			T45	1		T227	2		T317	2
auto[1]	values[7]	values[5]	9	1			T80	3		T224	1		T310	1
auto[1]	values[7]	values[6]	7	1			T31	2		T56	2		T323	2
auto[1]	values[7]	values[7]	7	1			T217	2		T81	2		T140	1