Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1706

1

T4

2

T11

13

T12

7

auto[1]

1804

1

T11

16

T24

16

T25

12

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1956

1

T4

2

T11

28

T12

5

auto[1]

1554

1

T11

1

T12

2

T24

39

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2765

1

T4

1

T11

22

T12

5

auto[1]

745

1

T4

1

T11

7

T12

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	704	1			T4	1		T11	5		T12	1
valid[1]	727	1			T4	1		T11	7		T12	2
valid[2]	699	1			T11	6		T24	9		T25	8
valid[3]	700	1			T11	8		T12	1		T24	10
valid[4]	680	1			T11	3		T12	3		T24	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	116	1			T11	1		T12	1		T39	1
auto[0]	auto[0]	valid[0]	auto[1]	149	1			T24	5		T29	2		T30	2
auto[0]	auto[0]	valid[1]	auto[0]	114	1			T4	1		T11	1		T12	1
auto[0]	auto[0]	valid[1]	auto[1]	159	1			T12	1		T24	5		T25	4
auto[0]	auto[0]	valid[2]	auto[0]	109	1			T11	2		T38	1		T137	1
auto[0]	auto[0]	valid[2]	auto[1]	159	1			T11	1		T24	5		T25	2
auto[0]	auto[0]	valid[3]	auto[0]	96	1			T11	3		T14	1		T41	2
auto[0]	auto[0]	valid[3]	auto[1]	173	1			T12	1		T24	7		T25	3
auto[0]	auto[0]	valid[4]	auto[0]	118	1			T11	1		T12	1		T14	1
auto[0]	auto[0]	valid[4]	auto[1]	140	1			T24	1		T25	3		T29	4
auto[0]	auto[1]	valid[0]	auto[0]	152	1			T11	2		T41	2		T39	2
auto[0]	auto[1]	valid[0]	auto[1]	155	1			T24	4		T25	1		T29	1
auto[0]	auto[1]	valid[1]	auto[0]	126	1			T11	5		T14	2		T41	1
auto[0]	auto[1]	valid[1]	auto[1]	175	1			T24	2		T25	3		T29	5
auto[0]	auto[1]	valid[2]	auto[0]	110	1			T11	2		T14	1		T38	2
auto[0]	auto[1]	valid[2]	auto[1]	162	1			T24	4		T25	6		T29	4
auto[0]	auto[1]	valid[3]	auto[0]	133	1			T11	2		T14	1		T41	1
auto[0]	auto[1]	valid[3]	auto[1]	140	1			T24	3		T29	1		T30	1
auto[0]	auto[1]	valid[4]	auto[0]	137	1			T11	2		T14	1		T41	3
auto[0]	auto[1]	valid[4]	auto[1]	142	1			T24	3		T25	2		T29	1
auto[1]	auto[0]	valid[0]	auto[0]	65	1			T4	1		T11	1		T38	1
auto[1]	auto[0]	valid[1]	auto[0]	80	1			T39	1		T54	2		T137	1
auto[1]	auto[0]	valid[2]	auto[0]	70	1			T11	1		T14	1		T41	1
auto[1]	auto[0]	valid[3]	auto[0]	84	1			T11	2		T135	1		T137	1
auto[1]	auto[0]	valid[4]	auto[0]	74	1			T12	2		T14	1		T39	1
auto[1]	auto[1]	valid[0]	auto[0]	67	1			T11	1		T41	1		T54	1
auto[1]	auto[1]	valid[1]	auto[0]	73	1			T11	1		T41	1		T39	2
auto[1]	auto[1]	valid[2]	auto[0]	89	1			T41	1		T38	1		T54	1
auto[1]	auto[1]	valid[3]	auto[0]	74	1			T11	1		T330	1		T329	1
auto[1]	auto[1]	valid[4]	auto[0]	69	1			T39	1		T333	1		T46	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal