Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	718	1			T11	4		T18	4		T21	10
all_values[1]	718	1			T11	4		T18	4		T21	10
all_values[2]	718	1			T11	4		T18	4		T21	10
all_values[3]	718	1			T11	4		T18	4		T21	10
all_values[4]	718	1			T11	4		T18	4		T21	10
all_values[5]	718	1			T11	4		T18	4		T21	10
all_values[6]	718	1			T11	4		T18	4		T21	10
all_values[7]	718	1			T11	4		T18	4		T21	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3091

1

T11

17

T18

16

T21

50

auto[1]

2653

1

T11

15

T18

16

T21

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2233

1

T11

13

T18

12

T21

30

auto[1]

3511

1

T11

19

T18

20

T21

50

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3265

1

T11

18

T18

21

T21

42

auto[1]

2479

1

T11

14

T18

11

T21

38

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	133	1			T18	1		T21	3		T22	3
all_values[0]	auto[0]	auto[0]	auto[1]	61	1			T22	1		T31	1		T171	2
all_values[0]	auto[0]	auto[1]	auto[0]	108	1			T21	1		T22	4		T171	1
all_values[0]	auto[0]	auto[1]	auto[1]	89	1			T11	2		T18	2		T21	2
all_values[0]	auto[1]	auto[0]	auto[1]	174	1			T11	2		T18	1		T21	3
all_values[0]	auto[1]	auto[1]	auto[1]	153	1			T21	1		T22	4		T139	3
all_values[1]	auto[0]	auto[0]	auto[0]	166	1			T18	2		T21	3		T22	7
all_values[1]	auto[0]	auto[0]	auto[1]	77	1			T21	1		T22	1		T172	1
all_values[1]	auto[0]	auto[1]	auto[0]	107	1			T21	1		T22	1		T31	1
all_values[1]	auto[0]	auto[1]	auto[1]	71	1			T11	2		T18	1		T22	4
all_values[1]	auto[1]	auto[0]	auto[1]	168	1			T11	1		T18	1		T21	3
all_values[1]	auto[1]	auto[1]	auto[1]	129	1			T11	1		T21	2		T22	4
all_values[2]	auto[0]	auto[0]	auto[0]	147	1			T21	1		T22	5		T31	2
all_values[2]	auto[0]	auto[0]	auto[1]	64	1			T18	1		T21	1		T22	4
all_values[2]	auto[0]	auto[1]	auto[0]	112	1			T11	1		T18	1		T21	2
all_values[2]	auto[0]	auto[1]	auto[1]	92	1			T18	1		T21	1		T22	2
all_values[2]	auto[1]	auto[0]	auto[1]	170	1			T11	2		T21	4		T22	2
all_values[2]	auto[1]	auto[1]	auto[1]	133	1			T11	1		T18	1		T21	1
all_values[3]	auto[0]	auto[0]	auto[0]	128	1			T21	5		T22	6		T31	1
all_values[3]	auto[0]	auto[0]	auto[1]	67	1			T18	1		T21	1		T22	3
all_values[3]	auto[0]	auto[1]	auto[0]	118	1			T11	3		T18	1		T22	1
all_values[3]	auto[0]	auto[1]	auto[1]	88	1			T22	3		T171	3		T139	5
all_values[3]	auto[1]	auto[0]	auto[1]	177	1			T11	1		T21	3		T22	6
all_values[3]	auto[1]	auto[1]	auto[1]	140	1			T18	2		T21	1		T22	1
all_values[4]	auto[0]	auto[0]	auto[0]	143	1			T18	1		T21	3		T22	1
all_values[4]	auto[0]	auto[0]	auto[1]	75	1			T18	1		T21	1		T22	3
all_values[4]	auto[0]	auto[1]	auto[0]	124	1			T11	1		T21	1		T22	4
all_values[4]	auto[0]	auto[1]	auto[1]	74	1			T11	1		T21	1		T22	3
all_values[4]	auto[1]	auto[0]	auto[1]	165	1			T11	2		T18	1		T21	3
all_values[4]	auto[1]	auto[1]	auto[1]	137	1			T18	1		T21	1		T22	2
all_values[5]	auto[0]	auto[0]	auto[0]	230	1			T11	2		T18	1		T21	2
all_values[5]	auto[0]	auto[1]	auto[0]	164	1			T18	2		T21	1		T22	4
all_values[5]	auto[1]	auto[0]	auto[1]	186	1			T11	1		T21	3		T22	4
all_values[5]	auto[1]	auto[1]	auto[1]	138	1			T11	1		T18	1		T21	4
all_values[6]	auto[0]	auto[0]	auto[0]	163	1			T11	1		T18	1		T21	2
all_values[6]	auto[0]	auto[0]	auto[1]	71	1			T18	1		T21	1		T31	1
all_values[6]	auto[0]	auto[1]	auto[0]	119	1			T11	2		T21	2		T22	5
all_values[6]	auto[0]	auto[1]	auto[1]	59	1			T22	2		T171	1		T172	1
all_values[6]	auto[1]	auto[0]	auto[1]	163	1			T11	1		T18	2		T21	2
all_values[6]	auto[1]	auto[1]	auto[1]	143	1			T21	3		T22	6		T31	1
all_values[7]	auto[0]	auto[0]	auto[0]	131	1			T11	3		T21	2		T22	5
all_values[7]	auto[0]	auto[0]	auto[1]	79	1			T21	2		T22	3		T139	2
all_values[7]	auto[0]	auto[1]	auto[0]	140	1			T18	2		T21	1		T22	5
all_values[7]	auto[0]	auto[1]	auto[1]	65	1			T18	1		T21	1		T139	4
all_values[7]	auto[1]	auto[0]	auto[1]	153	1			T11	1		T18	1		T21	1
all_values[7]	auto[1]	auto[1]	auto[1]	150	1			T21	3		T22	7		T31	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal