Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52246

1

T3

1

T4

22

T11

734

auto[1]

17202

1

T4

8

T11

73

T12

11

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50398

1

T3

1

T4

17

T11

555

auto[1]

19050

1

T4

13

T11

252

T12

28

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35632	1			T4	17		T11	413		T12	39
others[1]	5839	1			T11	59		T12	6		T24	38
others[2]	5920	1			T4	2		T11	62		T12	5
others[3]	6710	1			T3	1		T4	2		T11	81
interest[1]	3805	1			T4	1		T11	51		T12	5
interest[4]	23194	1			T4	13		T11	278		T12	26
interest[64]	11542	1			T4	8		T11	141		T12	14

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16969	1			T4	4		T11	248		T12	19
auto[0]	auto[0]	others[1]	2769	1			T11	38		T12	2		T14	13
auto[0]	auto[0]	others[2]	2857	1			T4	1		T11	37		T12	2
auto[0]	auto[0]	others[3]	3200	1			T3	1		T11	50		T12	6
auto[0]	auto[0]	interest[1]	1880	1			T11	31		T12	3		T14	12
auto[0]	auto[0]	interest[4]	10916	1			T4	3		T11	173		T12	13
auto[0]	auto[0]	interest[64]	5521	1			T4	4		T11	78		T12	8
auto[0]	auto[1]	others[0]	8972	1			T4	6		T11	35		T12	5
auto[0]	auto[1]	others[1]	1425	1			T11	5		T12	1		T24	38
auto[0]	auto[1]	others[2]	1434	1			T11	7		T12	1		T24	57
auto[0]	auto[1]	others[3]	1623	1			T11	4		T24	46		T25	22
auto[0]	auto[1]	interest[1]	880	1			T11	7		T24	25		T25	14
auto[0]	auto[1]	interest[4]	5949	1			T4	5		T11	22		T12	4
auto[0]	auto[1]	interest[64]	2868	1			T4	2		T11	15		T12	4
auto[1]	auto[0]	others[0]	9691	1			T4	7		T11	130		T12	15
auto[1]	auto[0]	others[1]	1645	1			T11	16		T12	3		T14	4
auto[1]	auto[0]	others[2]	1629	1			T4	1		T11	18		T12	2
auto[1]	auto[0]	others[3]	1887	1			T4	2		T11	27		T12	4
auto[1]	auto[0]	interest[1]	1045	1			T4	1		T11	13		T12	2
auto[1]	auto[0]	interest[4]	6329	1			T4	5		T11	83		T12	9
auto[1]	auto[0]	interest[64]	3153	1			T4	2		T11	48		T12	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal