Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.35 94.02 98.62 89.36 97.23 95.43 99.20


Total test records in report: 1101
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T108 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1157761267 Jun 11 03:21:01 PM PDT 24 Jun 11 03:21:06 PM PDT 24 488559604 ps
T1017 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1831675654 Jun 11 03:21:12 PM PDT 24 Jun 11 03:21:14 PM PDT 24 49562085 ps
T156 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1957892879 Jun 11 03:20:40 PM PDT 24 Jun 11 03:20:43 PM PDT 24 74423005 ps
T1018 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1208551575 Jun 11 03:21:24 PM PDT 24 Jun 11 03:21:27 PM PDT 24 38830765 ps
T1019 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.822696498 Jun 11 03:21:01 PM PDT 24 Jun 11 03:21:03 PM PDT 24 14967694 ps
T1020 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.79111590 Jun 11 03:21:24 PM PDT 24 Jun 11 03:21:28 PM PDT 24 29262349 ps
T128 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.769394396 Jun 11 03:20:30 PM PDT 24 Jun 11 03:20:55 PM PDT 24 2330175779 ps
T111 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.754360310 Jun 11 03:21:16 PM PDT 24 Jun 11 03:21:19 PM PDT 24 223681251 ps
T129 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2689977092 Jun 11 03:21:04 PM PDT 24 Jun 11 03:21:07 PM PDT 24 671389295 ps
T1021 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3867073440 Jun 11 03:21:12 PM PDT 24 Jun 11 03:21:16 PM PDT 24 353126871 ps
T1022 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2500833653 Jun 11 03:21:12 PM PDT 24 Jun 11 03:21:15 PM PDT 24 40560197 ps
T157 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3889702431 Jun 11 03:21:00 PM PDT 24 Jun 11 03:21:03 PM PDT 24 353492931 ps
T1023 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.499127453 Jun 11 03:21:11 PM PDT 24 Jun 11 03:21:13 PM PDT 24 13448574 ps
T1024 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.80218229 Jun 11 03:21:01 PM PDT 24 Jun 11 03:21:06 PM PDT 24 104068373 ps
T1025 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1832545649 Jun 11 03:20:50 PM PDT 24 Jun 11 03:20:54 PM PDT 24 96943580 ps
T112 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1248212736 Jun 11 03:20:26 PM PDT 24 Jun 11 03:20:31 PM PDT 24 221495068 ps
T1026 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.407765553 Jun 11 03:20:51 PM PDT 24 Jun 11 03:20:53 PM PDT 24 23004240 ps
T114 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.175742266 Jun 11 03:21:01 PM PDT 24 Jun 11 03:21:06 PM PDT 24 59120849 ps
T1027 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2600521722 Jun 11 03:21:11 PM PDT 24 Jun 11 03:21:13 PM PDT 24 18269818 ps
T1028 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.296303054 Jun 11 03:20:42 PM PDT 24 Jun 11 03:20:53 PM PDT 24 618290266 ps
T1029 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4043161313 Jun 11 03:21:22 PM PDT 24 Jun 11 03:21:25 PM PDT 24 101658784 ps
T1030 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.866817726 Jun 11 03:20:38 PM PDT 24 Jun 11 03:20:48 PM PDT 24 428095775 ps
T1031 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2328324951 Jun 11 03:21:11 PM PDT 24 Jun 11 03:21:16 PM PDT 24 417179870 ps
T1032 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3543498465 Jun 11 03:20:28 PM PDT 24 Jun 11 03:20:33 PM PDT 24 73784434 ps
T1033 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3848968177 Jun 11 03:20:49 PM PDT 24 Jun 11 03:20:51 PM PDT 24 54312043 ps
T1034 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1450936848 Jun 11 03:21:11 PM PDT 24 Jun 11 03:21:14 PM PDT 24 12689493 ps
T130 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3024560094 Jun 11 03:20:50 PM PDT 24 Jun 11 03:20:54 PM PDT 24 294496994 ps
T1035 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.709878811 Jun 11 03:20:53 PM PDT 24 Jun 11 03:20:57 PM PDT 24 66237673 ps
T1036 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.526011993 Jun 11 03:20:43 PM PDT 24 Jun 11 03:20:46 PM PDT 24 212092245 ps
T188 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.933317420 Jun 11 03:21:04 PM PDT 24 Jun 11 03:21:24 PM PDT 24 296764341 ps
T189 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3411512396 Jun 11 03:20:52 PM PDT 24 Jun 11 03:21:16 PM PDT 24 853506895 ps
T1037 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.661169116 Jun 11 03:20:51 PM PDT 24 Jun 11 03:21:12 PM PDT 24 3487571531 ps
T1038 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1150542492 Jun 11 03:20:32 PM PDT 24 Jun 11 03:20:34 PM PDT 24 30807496 ps
T1039 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2837963282 Jun 11 03:20:28 PM PDT 24 Jun 11 03:20:32 PM PDT 24 18626010 ps
T1040 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1744638470 Jun 11 03:20:28 PM PDT 24 Jun 11 03:20:34 PM PDT 24 167343123 ps
T1041 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1881656148 Jun 11 03:21:24 PM PDT 24 Jun 11 03:21:28 PM PDT 24 55764726 ps
T1042 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1352104218 Jun 11 03:20:39 PM PDT 24 Jun 11 03:20:41 PM PDT 24 14058782 ps
T1043 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.313525897 Jun 11 03:20:50 PM PDT 24 Jun 11 03:20:53 PM PDT 24 255708560 ps
T158 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.563868773 Jun 11 03:20:51 PM PDT 24 Jun 11 03:20:54 PM PDT 24 111855157 ps
T1044 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2045899341 Jun 11 03:20:41 PM PDT 24 Jun 11 03:20:50 PM PDT 24 4491752975 ps
T1045 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4124243723 Jun 11 03:20:50 PM PDT 24 Jun 11 03:20:53 PM PDT 24 30080640 ps
T1046 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.844060034 Jun 11 03:21:02 PM PDT 24 Jun 11 03:21:07 PM PDT 24 312713988 ps
T1047 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1176649364 Jun 11 03:20:54 PM PDT 24 Jun 11 03:20:57 PM PDT 24 266483658 ps
T1048 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3253402083 Jun 11 03:20:53 PM PDT 24 Jun 11 03:20:56 PM PDT 24 118167062 ps
T1049 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.698537548 Jun 11 03:21:23 PM PDT 24 Jun 11 03:21:26 PM PDT 24 23004714 ps
T1050 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3294469618 Jun 11 03:21:11 PM PDT 24 Jun 11 03:21:13 PM PDT 24 12301815 ps
T85 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1376248629 Jun 11 03:20:32 PM PDT 24 Jun 11 03:20:35 PM PDT 24 133641595 ps
T1051 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3763175836 Jun 11 03:21:22 PM PDT 24 Jun 11 03:21:26 PM PDT 24 14440875 ps
T1052 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3948597330 Jun 11 03:21:02 PM PDT 24 Jun 11 03:21:07 PM PDT 24 611606698 ps
T1053 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3940836646 Jun 11 03:20:42 PM PDT 24 Jun 11 03:20:57 PM PDT 24 2533183124 ps
T190 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3556817041 Jun 11 03:21:01 PM PDT 24 Jun 11 03:21:17 PM PDT 24 1321956841 ps
T1054 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.117159611 Jun 11 03:20:42 PM PDT 24 Jun 11 03:20:49 PM PDT 24 422613732 ps
T131 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2159532952 Jun 11 03:20:52 PM PDT 24 Jun 11 03:20:56 PM PDT 24 201376898 ps
T1055 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3361581610 Jun 11 03:20:39 PM PDT 24 Jun 11 03:20:42 PM PDT 24 89876053 ps
T1056 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1592497033 Jun 11 03:21:21 PM PDT 24 Jun 11 03:21:23 PM PDT 24 13547876 ps
T1057 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2698389787 Jun 11 03:20:33 PM PDT 24 Jun 11 03:20:36 PM PDT 24 35767554 ps
T1058 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1429803749 Jun 11 03:21:25 PM PDT 24 Jun 11 03:21:28 PM PDT 24 16035170 ps
T1059 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1400016682 Jun 11 03:21:01 PM PDT 24 Jun 11 03:21:05 PM PDT 24 514809245 ps
T1060 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.984906353 Jun 11 03:20:27 PM PDT 24 Jun 11 03:20:44 PM PDT 24 791375338 ps
T1061 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2067442771 Jun 11 03:20:30 PM PDT 24 Jun 11 03:20:36 PM PDT 24 132943259 ps
T1062 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.595172796 Jun 11 03:20:29 PM PDT 24 Jun 11 03:20:58 PM PDT 24 2417026699 ps
T1063 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2338501321 Jun 11 03:20:42 PM PDT 24 Jun 11 03:20:45 PM PDT 24 139664170 ps
T1064 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1806521463 Jun 11 03:20:41 PM PDT 24 Jun 11 03:20:44 PM PDT 24 48992937 ps
T1065 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.103252019 Jun 11 03:21:11 PM PDT 24 Jun 11 03:21:13 PM PDT 24 47909638 ps
T1066 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1151345886 Jun 11 03:21:11 PM PDT 24 Jun 11 03:21:16 PM PDT 24 1010557404 ps
T1067 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3639835248 Jun 11 03:21:02 PM PDT 24 Jun 11 03:21:04 PM PDT 24 58038953 ps
T1068 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3393433272 Jun 11 03:20:28 PM PDT 24 Jun 11 03:20:35 PM PDT 24 201533890 ps
T1069 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1666400867 Jun 11 03:20:29 PM PDT 24 Jun 11 03:20:40 PM PDT 24 107044324 ps
T1070 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3103802619 Jun 11 03:21:05 PM PDT 24 Jun 11 03:21:07 PM PDT 24 34519394 ps
T1071 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.5822305 Jun 11 03:21:21 PM PDT 24 Jun 11 03:21:23 PM PDT 24 23680435 ps
T1072 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1998642143 Jun 11 03:20:40 PM PDT 24 Jun 11 03:20:45 PM PDT 24 115725860 ps
T1073 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2490099171 Jun 11 03:21:10 PM PDT 24 Jun 11 03:21:12 PM PDT 24 21279051 ps
T1074 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1745889760 Jun 11 03:21:11 PM PDT 24 Jun 11 03:21:14 PM PDT 24 55178086 ps
T1075 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3194864982 Jun 11 03:21:23 PM PDT 24 Jun 11 03:21:26 PM PDT 24 24354435 ps
T1076 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2739801891 Jun 11 03:20:52 PM PDT 24 Jun 11 03:20:55 PM PDT 24 64256880 ps
T1077 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1832800017 Jun 11 03:20:41 PM PDT 24 Jun 11 03:20:46 PM PDT 24 287552763 ps
T1078 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1449987730 Jun 11 03:20:28 PM PDT 24 Jun 11 03:20:33 PM PDT 24 161299001 ps
T181 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2147444843 Jun 11 03:21:01 PM PDT 24 Jun 11 03:21:06 PM PDT 24 266949835 ps
T1079 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2809727749 Jun 11 03:21:25 PM PDT 24 Jun 11 03:21:28 PM PDT 24 36217845 ps
T1080 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3377204818 Jun 11 03:20:37 PM PDT 24 Jun 11 03:20:39 PM PDT 24 12356909 ps
T1081 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.895858354 Jun 11 03:20:42 PM PDT 24 Jun 11 03:20:46 PM PDT 24 340383648 ps
T1082 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1202076132 Jun 11 03:21:23 PM PDT 24 Jun 11 03:21:26 PM PDT 24 14131386 ps
T1083 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2589097902 Jun 11 03:21:04 PM PDT 24 Jun 11 03:21:09 PM PDT 24 127541103 ps
T1084 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.467413490 Jun 11 03:21:12 PM PDT 24 Jun 11 03:21:20 PM PDT 24 460777954 ps
T1085 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2340570034 Jun 11 03:20:40 PM PDT 24 Jun 11 03:20:43 PM PDT 24 102769763 ps
T1086 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.846725363 Jun 11 03:20:51 PM PDT 24 Jun 11 03:20:55 PM PDT 24 67507316 ps
T1087 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.781233745 Jun 11 03:20:52 PM PDT 24 Jun 11 03:21:07 PM PDT 24 213007014 ps
T1088 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.137559606 Jun 11 03:20:28 PM PDT 24 Jun 11 03:20:33 PM PDT 24 266481138 ps
T1089 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1013902153 Jun 11 03:20:28 PM PDT 24 Jun 11 03:20:32 PM PDT 24 13799799 ps
T1090 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1400519922 Jun 11 03:21:12 PM PDT 24 Jun 11 03:21:16 PM PDT 24 68200412 ps
T1091 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.494922430 Jun 11 03:20:52 PM PDT 24 Jun 11 03:21:00 PM PDT 24 108091854 ps
T1092 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.128290359 Jun 11 03:20:51 PM PDT 24 Jun 11 03:21:15 PM PDT 24 822042257 ps
T1093 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2340152105 Jun 11 03:21:23 PM PDT 24 Jun 11 03:21:27 PM PDT 24 18945706 ps
T1094 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.89954436 Jun 11 03:20:50 PM PDT 24 Jun 11 03:20:54 PM PDT 24 48325451 ps
T1095 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2078228563 Jun 11 03:20:38 PM PDT 24 Jun 11 03:20:41 PM PDT 24 87932248 ps
T1096 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.114011102 Jun 11 03:20:39 PM PDT 24 Jun 11 03:20:44 PM PDT 24 98021142 ps
T1097 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.571303929 Jun 11 03:20:50 PM PDT 24 Jun 11 03:20:52 PM PDT 24 19202206 ps
T1098 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.81664723 Jun 11 03:20:29 PM PDT 24 Jun 11 03:20:32 PM PDT 24 107666258 ps
T1099 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3975201281 Jun 11 03:20:38 PM PDT 24 Jun 11 03:20:40 PM PDT 24 29270011 ps
T1100 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3997037923 Jun 11 03:20:29 PM PDT 24 Jun 11 03:20:34 PM PDT 24 160274793 ps
T1101 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.863951131 Jun 11 03:20:38 PM PDT 24 Jun 11 03:20:56 PM PDT 24 620066243 ps

Test location /workspace/coverage/default/37.spi_device_flash_all.386433371
Short name T7
Test name
Test status
Simulation time 8783311916 ps
CPU time 20.13 seconds
Started Jun 11 03:23:52 PM PDT 24
Finished Jun 11 03:24:13 PM PDT 24
Peak memory 224452 kb
Host smart-5211366d-e6e2-4999-b5ac-4ccfaf43d5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386433371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.386433371
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3745271020
Short name T11
Test name
Test status
Simulation time 29292019753 ps
CPU time 111.86 seconds
Started Jun 11 03:24:39 PM PDT 24
Finished Jun 11 03:26:33 PM PDT 24
Peak memory 240892 kb
Host smart-b37a760a-f9d3-4181-b868-852f68148d32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745271020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3745271020
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2879234815
Short name T47
Test name
Test status
Simulation time 120927402958 ps
CPU time 185.08 seconds
Started Jun 11 03:23:56 PM PDT 24
Finished Jun 11 03:27:03 PM PDT 24
Peak memory 257132 kb
Host smart-2909b84a-c2e0-4627-b63e-7d85b75fd237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879234815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2879234815
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1977654569
Short name T98
Test name
Test status
Simulation time 12476468636 ps
CPU time 23.33 seconds
Started Jun 11 03:20:39 PM PDT 24
Finished Jun 11 03:21:04 PM PDT 24
Peak memory 215704 kb
Host smart-a2d53c8a-ab2d-4859-b05e-8db1b660f34d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977654569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1977654569
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3933943455
Short name T18
Test name
Test status
Simulation time 360858611325 ps
CPU time 393.31 seconds
Started Jun 11 03:23:26 PM PDT 24
Finished Jun 11 03:30:01 PM PDT 24
Peak memory 257064 kb
Host smart-c4e2155f-758f-4fe3-bf70-f68a1a4decf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933943455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3933943455
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.230833272
Short name T81
Test name
Test status
Simulation time 23125610142 ps
CPU time 126.01 seconds
Started Jun 11 03:22:42 PM PDT 24
Finished Jun 11 03:24:49 PM PDT 24
Peak memory 263464 kb
Host smart-c66efdb2-4454-4d4f-a7e9-27ab430c49a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230833272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.230833272
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1131996291
Short name T73
Test name
Test status
Simulation time 35803254 ps
CPU time 0.82 seconds
Started Jun 11 03:21:27 PM PDT 24
Finished Jun 11 03:21:31 PM PDT 24
Peak memory 216196 kb
Host smart-f4bee11c-d628-4dea-8e13-a2624f5980e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131996291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1131996291
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.4042736148
Short name T56
Test name
Test status
Simulation time 33967814329 ps
CPU time 379.44 seconds
Started Jun 11 03:23:19 PM PDT 24
Finished Jun 11 03:29:41 PM PDT 24
Peak memory 264828 kb
Host smart-45c53048-0501-41ee-86dd-4d5a92149bd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042736148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.4042736148
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3902358116
Short name T54
Test name
Test status
Simulation time 9882303615 ps
CPU time 104.08 seconds
Started Jun 11 03:21:31 PM PDT 24
Finished Jun 11 03:23:17 PM PDT 24
Peak memory 255056 kb
Host smart-8418f145-4ef7-4fbe-9266-fb8f61ba332b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902358116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3902358116
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2363384492
Short name T195
Test name
Test status
Simulation time 602402745321 ps
CPU time 578.4 seconds
Started Jun 11 03:22:20 PM PDT 24
Finished Jun 11 03:32:01 PM PDT 24
Peak memory 273392 kb
Host smart-3fb23a4f-3d3f-453f-ac91-7e2ebabfc2ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363384492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2363384492
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1122257199
Short name T215
Test name
Test status
Simulation time 11492354807 ps
CPU time 183.62 seconds
Started Jun 11 03:23:25 PM PDT 24
Finished Jun 11 03:26:31 PM PDT 24
Peak memory 256688 kb
Host smart-f82a7f5c-7819-4bcc-a94e-bb866969a540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122257199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1122257199
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.4169141153
Short name T199
Test name
Test status
Simulation time 13676850227 ps
CPU time 217.58 seconds
Started Jun 11 03:24:47 PM PDT 24
Finished Jun 11 03:28:26 PM PDT 24
Peak memory 272692 kb
Host smart-97a9012f-e8e2-4b11-beca-0a57e834fd62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169141153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.4169141153
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2310326475
Short name T15
Test name
Test status
Simulation time 443888455 ps
CPU time 1.2 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:21:29 PM PDT 24
Peak memory 236444 kb
Host smart-6270c218-9803-4e4c-8651-8ef9bac592e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310326475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2310326475
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1411912795
Short name T52
Test name
Test status
Simulation time 7901217818 ps
CPU time 17.02 seconds
Started Jun 11 03:22:32 PM PDT 24
Finished Jun 11 03:22:51 PM PDT 24
Peak memory 232692 kb
Host smart-2fc6b7c1-724e-4a7f-b364-fda1c7d70df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411912795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1411912795
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1930262033
Short name T103
Test name
Test status
Simulation time 274493193 ps
CPU time 3.29 seconds
Started Jun 11 03:21:04 PM PDT 24
Finished Jun 11 03:21:08 PM PDT 24
Peak memory 215612 kb
Host smart-0dcbb64d-a589-41f7-a360-229ffd82aef1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930262033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1930262033
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.876642888
Short name T299
Test name
Test status
Simulation time 54817024708 ps
CPU time 549.93 seconds
Started Jun 11 03:21:41 PM PDT 24
Finished Jun 11 03:30:52 PM PDT 24
Peak memory 267424 kb
Host smart-e02b3b9a-ecb1-470d-8e5f-6973041e3387
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876642888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.876642888
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2812605620
Short name T46
Test name
Test status
Simulation time 213307856733 ps
CPU time 445.58 seconds
Started Jun 11 03:23:16 PM PDT 24
Finished Jun 11 03:30:43 PM PDT 24
Peak memory 253904 kb
Host smart-34930757-e53f-4c29-ae00-53ca5275209c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812605620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2812605620
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2688930585
Short name T217
Test name
Test status
Simulation time 828842906655 ps
CPU time 505.33 seconds
Started Jun 11 03:24:22 PM PDT 24
Finished Jun 11 03:32:49 PM PDT 24
Peak memory 253940 kb
Host smart-cea6996c-bdf5-476a-b2c9-14b4afc7cc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688930585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2688930585
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3337010906
Short name T121
Test name
Test status
Simulation time 123061406 ps
CPU time 3.18 seconds
Started Jun 11 03:21:00 PM PDT 24
Finished Jun 11 03:21:04 PM PDT 24
Peak memory 215568 kb
Host smart-443c4b62-a052-467c-beb9-2239076a0088
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337010906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3337010906
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1700003439
Short name T192
Test name
Test status
Simulation time 19777561122 ps
CPU time 141.78 seconds
Started Jun 11 03:22:58 PM PDT 24
Finished Jun 11 03:25:21 PM PDT 24
Peak memory 249732 kb
Host smart-4e31a64d-fd67-454e-a867-e933516dff94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700003439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1700003439
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3429379931
Short name T202
Test name
Test status
Simulation time 87928355265 ps
CPU time 141.12 seconds
Started Jun 11 03:23:58 PM PDT 24
Finished Jun 11 03:26:22 PM PDT 24
Peak memory 273008 kb
Host smart-470c2ba1-f5ba-4e44-9331-8edbe26168a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429379931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3429379931
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.4026611306
Short name T665
Test name
Test status
Simulation time 64527706 ps
CPU time 1.13 seconds
Started Jun 11 03:21:22 PM PDT 24
Finished Jun 11 03:21:26 PM PDT 24
Peak memory 216492 kb
Host smart-0de4cf04-80e7-45c2-a9c7-256149186f82
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026611306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.4026611306
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.114767241
Short name T29
Test name
Test status
Simulation time 1584980371 ps
CPU time 4.24 seconds
Started Jun 11 03:22:25 PM PDT 24
Finished Jun 11 03:22:31 PM PDT 24
Peak memory 215940 kb
Host smart-7d308ba6-cd3f-4e6e-bc94-f6d2a70d23c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114767241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.114767241
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.4257222803
Short name T48
Test name
Test status
Simulation time 21206493261 ps
CPU time 97.28 seconds
Started Jun 11 03:23:18 PM PDT 24
Finished Jun 11 03:24:58 PM PDT 24
Peak memory 257220 kb
Host smart-e70b15e9-70ae-48bc-9190-cc43585f3584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257222803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.4257222803
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2458968918
Short name T210
Test name
Test status
Simulation time 34309297131 ps
CPU time 295.62 seconds
Started Jun 11 03:24:15 PM PDT 24
Finished Jun 11 03:29:12 PM PDT 24
Peak memory 250900 kb
Host smart-1bc04012-67ae-4534-8271-d9c3c4858c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458968918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2458968918
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1979574304
Short name T32
Test name
Test status
Simulation time 405994704726 ps
CPU time 1011.14 seconds
Started Jun 11 03:22:01 PM PDT 24
Finished Jun 11 03:38:54 PM PDT 24
Peak memory 270276 kb
Host smart-66bf0f72-08db-40f2-b77f-3d8c59e37761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979574304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1979574304
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1172095129
Short name T319
Test name
Test status
Simulation time 443100919205 ps
CPU time 281.9 seconds
Started Jun 11 03:22:32 PM PDT 24
Finished Jun 11 03:27:16 PM PDT 24
Peak memory 273488 kb
Host smart-85e2dadb-b8a6-4d5f-99ea-b5efc9858145
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172095129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1172095129
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.175742266
Short name T114
Test name
Test status
Simulation time 59120849 ps
CPU time 3.93 seconds
Started Jun 11 03:21:01 PM PDT 24
Finished Jun 11 03:21:06 PM PDT 24
Peak memory 216740 kb
Host smart-881bf410-5acb-425d-a23a-933a3e601859
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175742266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.175742266
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3378801258
Short name T349
Test name
Test status
Simulation time 28364671 ps
CPU time 0.75 seconds
Started Jun 11 03:22:07 PM PDT 24
Finished Jun 11 03:22:09 PM PDT 24
Peak memory 204748 kb
Host smart-d69026be-9089-442f-ace4-c06aea0c7f89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378801258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3378801258
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.4167317674
Short name T40
Test name
Test status
Simulation time 11195357086 ps
CPU time 22.05 seconds
Started Jun 11 03:22:22 PM PDT 24
Finished Jun 11 03:22:47 PM PDT 24
Peak memory 233588 kb
Host smart-dfdf2394-a6e5-4578-84dc-c51eea756cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167317674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.4167317674
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1037028237
Short name T197
Test name
Test status
Simulation time 89616982468 ps
CPU time 201.11 seconds
Started Jun 11 03:22:44 PM PDT 24
Finished Jun 11 03:26:08 PM PDT 24
Peak memory 256124 kb
Host smart-2b0a676e-d854-4921-96ac-624f1f9869b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037028237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1037028237
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.933317420
Short name T188
Test name
Test status
Simulation time 296764341 ps
CPU time 18.77 seconds
Started Jun 11 03:21:04 PM PDT 24
Finished Jun 11 03:21:24 PM PDT 24
Peak memory 215504 kb
Host smart-ede0f2fd-dec6-4719-8737-34270d1f2a49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933317420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.933317420
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3521275693
Short name T19
Test name
Test status
Simulation time 4408684662 ps
CPU time 65.69 seconds
Started Jun 11 03:22:52 PM PDT 24
Finished Jun 11 03:24:00 PM PDT 24
Peak memory 249076 kb
Host smart-9afed84b-94ec-47e6-b049-eb9226890e17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521275693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3521275693
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2930553506
Short name T314
Test name
Test status
Simulation time 27046218722 ps
CPU time 296.73 seconds
Started Jun 11 03:23:20 PM PDT 24
Finished Jun 11 03:28:20 PM PDT 24
Peak memory 254900 kb
Host smart-22dec394-bcef-4cda-a376-19eb6b2e62ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930553506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2930553506
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.4145277757
Short name T614
Test name
Test status
Simulation time 151080801 ps
CPU time 9.42 seconds
Started Jun 11 03:24:07 PM PDT 24
Finished Jun 11 03:24:19 PM PDT 24
Peak memory 233388 kb
Host smart-76e00614-bdec-4154-bb97-d1b1e7bef1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145277757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.4145277757
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2159227601
Short name T246
Test name
Test status
Simulation time 36636812949 ps
CPU time 93.71 seconds
Started Jun 11 03:22:42 PM PDT 24
Finished Jun 11 03:24:18 PM PDT 24
Peak memory 240496 kb
Host smart-9d010b78-214e-4966-9110-3cc56f20a1c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159227601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2159227601
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2061270722
Short name T224
Test name
Test status
Simulation time 110838469221 ps
CPU time 95.79 seconds
Started Jun 11 03:22:53 PM PDT 24
Finished Jun 11 03:24:31 PM PDT 24
Peak memory 263528 kb
Host smart-d1ca6c03-dbb5-4468-abfd-780dba31c911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061270722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2061270722
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2284783092
Short name T89
Test name
Test status
Simulation time 247237589 ps
CPU time 5.3 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:21:33 PM PDT 24
Peak memory 232560 kb
Host smart-22864911-ee77-4b68-8808-0289e3262bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284783092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2284783092
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3556817041
Short name T190
Test name
Test status
Simulation time 1321956841 ps
CPU time 15.13 seconds
Started Jun 11 03:21:01 PM PDT 24
Finished Jun 11 03:21:17 PM PDT 24
Peak memory 215628 kb
Host smart-217bc6ac-c0ba-4849-8245-b9ae49fa4c98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556817041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3556817041
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.589253511
Short name T296
Test name
Test status
Simulation time 55214058711 ps
CPU time 283.71 seconds
Started Jun 11 03:22:33 PM PDT 24
Finished Jun 11 03:27:19 PM PDT 24
Peak memory 261196 kb
Host smart-af3f07ad-cf4f-457e-a800-331f1866ff54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589253511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.589253511
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3103488436
Short name T294
Test name
Test status
Simulation time 79132384808 ps
CPU time 517.84 seconds
Started Jun 11 03:22:47 PM PDT 24
Finished Jun 11 03:31:27 PM PDT 24
Peak memory 266684 kb
Host smart-a1669ab7-213c-418a-9e7c-dc79a45f6b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103488436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3103488436
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.446699465
Short name T313
Test name
Test status
Simulation time 275958158738 ps
CPU time 573.42 seconds
Started Jun 11 03:22:52 PM PDT 24
Finished Jun 11 03:32:28 PM PDT 24
Peak memory 264820 kb
Host smart-f3f8eb6e-c40c-485d-8264-71936cf5d5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446699465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.446699465
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3554965476
Short name T308
Test name
Test status
Simulation time 84402497452 ps
CPU time 221.33 seconds
Started Jun 11 03:23:05 PM PDT 24
Finished Jun 11 03:26:48 PM PDT 24
Peak memory 252352 kb
Host smart-3d04f742-0200-4fa3-989e-2f1e801a9a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554965476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3554965476
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2968168747
Short name T248
Test name
Test status
Simulation time 9441195446 ps
CPU time 117.09 seconds
Started Jun 11 03:23:53 PM PDT 24
Finished Jun 11 03:25:53 PM PDT 24
Peak memory 272008 kb
Host smart-806a00d1-6b96-4313-8bb4-805426bc7e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968168747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2968168747
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3955581349
Short name T180
Test name
Test status
Simulation time 498506556297 ps
CPU time 279.73 seconds
Started Jun 11 03:21:59 PM PDT 24
Finished Jun 11 03:26:41 PM PDT 24
Peak memory 249048 kb
Host smart-729de0c8-e61b-495b-97d4-d9a522b6ffc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955581349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3955581349
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1860832364
Short name T728
Test name
Test status
Simulation time 6441266191 ps
CPU time 45.93 seconds
Started Jun 11 03:22:15 PM PDT 24
Finished Jun 11 03:23:03 PM PDT 24
Peak memory 237452 kb
Host smart-18f782a4-55fa-4353-b3c7-58ffe7873492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860832364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1860832364
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.985984767
Short name T317
Test name
Test status
Simulation time 145354129223 ps
CPU time 336.67 seconds
Started Jun 11 03:22:33 PM PDT 24
Finished Jun 11 03:28:12 PM PDT 24
Peak memory 255500 kb
Host smart-9a423330-60b2-41f0-818f-8a7c7589213b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985984767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.985984767
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1690768594
Short name T307
Test name
Test status
Simulation time 1485684505 ps
CPU time 3.16 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:21:31 PM PDT 24
Peak memory 224312 kb
Host smart-23a88299-d289-44cb-bbec-a1be27af6ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690768594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1690768594
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3372543322
Short name T253
Test name
Test status
Simulation time 32728569706 ps
CPU time 343.73 seconds
Started Jun 11 03:23:16 PM PDT 24
Finished Jun 11 03:29:01 PM PDT 24
Peak memory 257236 kb
Host smart-18f19fba-61db-4525-865f-2e350014ca7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372543322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3372543322
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1730721530
Short name T143
Test name
Test status
Simulation time 35642225728 ps
CPU time 320.32 seconds
Started Jun 11 03:23:53 PM PDT 24
Finished Jun 11 03:29:15 PM PDT 24
Peak memory 249364 kb
Host smart-7553eccf-e6c6-4b47-9be2-be4452969d7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730721530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1730721530
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.202977529
Short name T300
Test name
Test status
Simulation time 19264014232 ps
CPU time 177.5 seconds
Started Jun 11 03:24:04 PM PDT 24
Finished Jun 11 03:27:04 PM PDT 24
Peak memory 251308 kb
Host smart-d42f5a33-1cc5-4763-abae-93dbbbda394f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202977529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.202977529
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2983739361
Short name T107
Test name
Test status
Simulation time 696580597 ps
CPU time 5.27 seconds
Started Jun 11 03:21:01 PM PDT 24
Finished Jun 11 03:21:08 PM PDT 24
Peak memory 215940 kb
Host smart-ab405e47-82e6-474b-b010-bd241e8f9922
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983739361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2983739361
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2615007503
Short name T836
Test name
Test status
Simulation time 510395514 ps
CPU time 6.42 seconds
Started Jun 11 03:21:28 PM PDT 24
Finished Jun 11 03:21:38 PM PDT 24
Peak memory 219044 kb
Host smart-6b30778f-317c-4583-83e3-991e07ce0d3e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2615007503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2615007503
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.444988397
Short name T84
Test name
Test status
Simulation time 186862933 ps
CPU time 1.4 seconds
Started Jun 11 03:20:31 PM PDT 24
Finished Jun 11 03:20:35 PM PDT 24
Peak memory 207364 kb
Host smart-99edb12b-8a0d-43f7-905b-14140cec9cb7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444988397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.444988397
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3108600607
Short name T8
Test name
Test status
Simulation time 105359399483 ps
CPU time 17.4 seconds
Started Jun 11 03:22:01 PM PDT 24
Finished Jun 11 03:22:21 PM PDT 24
Peak memory 240720 kb
Host smart-e24c404e-fdb1-442e-a00d-ad7dacf83b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108600607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3108600607
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2919663620
Short name T123
Test name
Test status
Simulation time 224823492 ps
CPU time 14.96 seconds
Started Jun 11 03:20:27 PM PDT 24
Finished Jun 11 03:20:45 PM PDT 24
Peak memory 215500 kb
Host smart-5f28dbc0-8768-411a-8ea2-b619c951452c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919663620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2919663620
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.769394396
Short name T128
Test name
Test status
Simulation time 2330175779 ps
CPU time 22.09 seconds
Started Jun 11 03:20:30 PM PDT 24
Finished Jun 11 03:20:55 PM PDT 24
Peak memory 207368 kb
Host smart-0c50acc7-b3f9-4180-85d0-7d93017ae4ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769394396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.769394396
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2067442771
Short name T1061
Test name
Test status
Simulation time 132943259 ps
CPU time 2.78 seconds
Started Jun 11 03:20:30 PM PDT 24
Finished Jun 11 03:20:36 PM PDT 24
Peak memory 216996 kb
Host smart-46f1cd17-f43b-40e6-a96c-89b312c4ddf1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067442771 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2067442771
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2657541587
Short name T122
Test name
Test status
Simulation time 58811627 ps
CPU time 1.19 seconds
Started Jun 11 03:20:32 PM PDT 24
Finished Jun 11 03:20:35 PM PDT 24
Peak memory 207356 kb
Host smart-43f310d8-b509-4d1e-8513-7a98ef686dd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657541587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
657541587
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1013902153
Short name T1089
Test name
Test status
Simulation time 13799799 ps
CPU time 0.74 seconds
Started Jun 11 03:20:28 PM PDT 24
Finished Jun 11 03:20:32 PM PDT 24
Peak memory 203868 kb
Host smart-5c2f210a-72f8-4a0f-9e6b-edd2d9e9cebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013902153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
013902153
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.170402973
Short name T125
Test name
Test status
Simulation time 141045577 ps
CPU time 1.28 seconds
Started Jun 11 03:20:29 PM PDT 24
Finished Jun 11 03:20:34 PM PDT 24
Peak memory 215672 kb
Host smart-58baaf08-34da-4907-9741-5ff4ccb39f2c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170402973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.170402973
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2837963282
Short name T1039
Test name
Test status
Simulation time 18626010 ps
CPU time 0.64 seconds
Started Jun 11 03:20:28 PM PDT 24
Finished Jun 11 03:20:32 PM PDT 24
Peak memory 203904 kb
Host smart-3c499800-0fb3-4e8a-899d-a8f593dadb9b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837963282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2837963282
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3393433272
Short name T1068
Test name
Test status
Simulation time 201533890 ps
CPU time 4.43 seconds
Started Jun 11 03:20:28 PM PDT 24
Finished Jun 11 03:20:35 PM PDT 24
Peak memory 215460 kb
Host smart-0be8db07-19c4-4485-bf9e-0fd229c91375
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393433272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3393433272
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.137559606
Short name T1088
Test name
Test status
Simulation time 266481138 ps
CPU time 2.15 seconds
Started Jun 11 03:20:28 PM PDT 24
Finished Jun 11 03:20:33 PM PDT 24
Peak memory 215656 kb
Host smart-b946fa6f-cd2c-475a-81dd-aaa2ee0b6ab5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137559606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.137559606
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3880043564
Short name T154
Test name
Test status
Simulation time 1333401200 ps
CPU time 7.42 seconds
Started Jun 11 03:20:28 PM PDT 24
Finished Jun 11 03:20:38 PM PDT 24
Peak memory 216856 kb
Host smart-8945ab47-24ea-4711-8297-1c1c5bc50de1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880043564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3880043564
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1666400867
Short name T1069
Test name
Test status
Simulation time 107044324 ps
CPU time 8 seconds
Started Jun 11 03:20:29 PM PDT 24
Finished Jun 11 03:20:40 PM PDT 24
Peak memory 215564 kb
Host smart-3c3cf02f-41c9-492a-a43c-316c61796e04
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666400867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1666400867
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.595172796
Short name T1062
Test name
Test status
Simulation time 2417026699 ps
CPU time 25.66 seconds
Started Jun 11 03:20:29 PM PDT 24
Finished Jun 11 03:20:58 PM PDT 24
Peak memory 207276 kb
Host smart-c54e3866-1890-4291-833c-ab9adefe9784
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595172796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.595172796
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1376248629
Short name T85
Test name
Test status
Simulation time 133641595 ps
CPU time 1.2 seconds
Started Jun 11 03:20:32 PM PDT 24
Finished Jun 11 03:20:35 PM PDT 24
Peak memory 207280 kb
Host smart-e9f91d0e-d711-4f3a-b151-be5226c35649
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376248629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1376248629
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1744638470
Short name T1040
Test name
Test status
Simulation time 167343123 ps
CPU time 2.69 seconds
Started Jun 11 03:20:28 PM PDT 24
Finished Jun 11 03:20:34 PM PDT 24
Peak memory 217576 kb
Host smart-f655668e-00aa-4a92-b88d-d0867456666b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744638470 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1744638470
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3543498465
Short name T1032
Test name
Test status
Simulation time 73784434 ps
CPU time 2.39 seconds
Started Jun 11 03:20:28 PM PDT 24
Finished Jun 11 03:20:33 PM PDT 24
Peak memory 215520 kb
Host smart-d4e8e928-6f16-406d-aad0-102b022bf4d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543498465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
543498465
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.321520465
Short name T987
Test name
Test status
Simulation time 50202118 ps
CPU time 0.75 seconds
Started Jun 11 03:20:28 PM PDT 24
Finished Jun 11 03:20:32 PM PDT 24
Peak memory 203928 kb
Host smart-54d4af04-1b76-4303-a96f-28076901d7a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321520465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.321520465
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4123780608
Short name T119
Test name
Test status
Simulation time 103575214 ps
CPU time 1.81 seconds
Started Jun 11 03:20:27 PM PDT 24
Finished Jun 11 03:20:31 PM PDT 24
Peak memory 215536 kb
Host smart-673709dd-6d2e-4cbd-a8b6-4930529d39a8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123780608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.4123780608
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3217901923
Short name T986
Test name
Test status
Simulation time 10292469 ps
CPU time 0.68 seconds
Started Jun 11 03:20:29 PM PDT 24
Finished Jun 11 03:20:32 PM PDT 24
Peak memory 203872 kb
Host smart-e58fa81a-87b9-485c-8729-00a08702200b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217901923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3217901923
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3997037923
Short name T1100
Test name
Test status
Simulation time 160274793 ps
CPU time 2.73 seconds
Started Jun 11 03:20:29 PM PDT 24
Finished Jun 11 03:20:34 PM PDT 24
Peak memory 215588 kb
Host smart-ce0dfe49-904f-4f9e-b5de-e87158d30894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997037923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3997037923
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1248212736
Short name T112
Test name
Test status
Simulation time 221495068 ps
CPU time 3.26 seconds
Started Jun 11 03:20:26 PM PDT 24
Finished Jun 11 03:20:31 PM PDT 24
Peak memory 215824 kb
Host smart-3d29d321-3149-4605-9d49-9f95c0b0f6f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248212736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
248212736
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.95400773
Short name T182
Test name
Test status
Simulation time 1748837525 ps
CPU time 19.09 seconds
Started Jun 11 03:20:28 PM PDT 24
Finished Jun 11 03:20:50 PM PDT 24
Peak memory 215596 kb
Host smart-f2c95d2e-51f9-4f75-9f47-63eccce04720
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95400773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_t
l_intg_err.95400773
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1832545649
Short name T1025
Test name
Test status
Simulation time 96943580 ps
CPU time 1.98 seconds
Started Jun 11 03:20:50 PM PDT 24
Finished Jun 11 03:20:54 PM PDT 24
Peak memory 216632 kb
Host smart-36ad159e-dfcd-4bc2-b164-b23f20795f3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832545649 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1832545649
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.846725363
Short name T1086
Test name
Test status
Simulation time 67507316 ps
CPU time 2.25 seconds
Started Jun 11 03:20:51 PM PDT 24
Finished Jun 11 03:20:55 PM PDT 24
Peak memory 215544 kb
Host smart-bb053393-62fe-4cf6-af30-d0105b60b764
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846725363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.846725363
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.571303929
Short name T1097
Test name
Test status
Simulation time 19202206 ps
CPU time 0.79 seconds
Started Jun 11 03:20:50 PM PDT 24
Finished Jun 11 03:20:52 PM PDT 24
Peak memory 203952 kb
Host smart-f5c18030-597d-4103-8904-ddb2412b2ebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571303929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.571303929
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2739801891
Short name T1076
Test name
Test status
Simulation time 64256880 ps
CPU time 1.88 seconds
Started Jun 11 03:20:52 PM PDT 24
Finished Jun 11 03:20:55 PM PDT 24
Peak memory 215528 kb
Host smart-749dd108-3be3-4756-af8c-16423c952fe8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739801891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2739801891
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.709878811
Short name T1035
Test name
Test status
Simulation time 66237673 ps
CPU time 3.34 seconds
Started Jun 11 03:20:53 PM PDT 24
Finished Jun 11 03:20:57 PM PDT 24
Peak memory 215736 kb
Host smart-43ac5e0b-abe7-4d39-a6ad-7c9556099ab7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709878811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.709878811
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.661169116
Short name T1037
Test name
Test status
Simulation time 3487571531 ps
CPU time 19.32 seconds
Started Jun 11 03:20:51 PM PDT 24
Finished Jun 11 03:21:12 PM PDT 24
Peak memory 215932 kb
Host smart-66442321-0276-47be-bae6-c13078adc338
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661169116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.661169116
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.605945815
Short name T97
Test name
Test status
Simulation time 90321618 ps
CPU time 2.75 seconds
Started Jun 11 03:21:04 PM PDT 24
Finished Jun 11 03:21:08 PM PDT 24
Peak memory 218068 kb
Host smart-164651c3-2f92-4e87-b889-e39586fb601e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605945815 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.605945815
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2689977092
Short name T129
Test name
Test status
Simulation time 671389295 ps
CPU time 1.35 seconds
Started Jun 11 03:21:04 PM PDT 24
Finished Jun 11 03:21:07 PM PDT 24
Peak memory 215736 kb
Host smart-9a97283d-9e77-4ab4-b382-2d493af8ba57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689977092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2689977092
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3848968177
Short name T1033
Test name
Test status
Simulation time 54312043 ps
CPU time 0.75 seconds
Started Jun 11 03:20:49 PM PDT 24
Finished Jun 11 03:20:51 PM PDT 24
Peak memory 203892 kb
Host smart-8079a3be-bf1e-481b-8b9f-bd71200c9a73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848968177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3848968177
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2437317143
Short name T145
Test name
Test status
Simulation time 200475465 ps
CPU time 3.14 seconds
Started Jun 11 03:21:00 PM PDT 24
Finished Jun 11 03:21:05 PM PDT 24
Peak memory 215500 kb
Host smart-3173ca50-3d15-41af-9dbc-3774ddc53e2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437317143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2437317143
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3253402083
Short name T1048
Test name
Test status
Simulation time 118167062 ps
CPU time 1.63 seconds
Started Jun 11 03:20:53 PM PDT 24
Finished Jun 11 03:20:56 PM PDT 24
Peak memory 215688 kb
Host smart-c083f210-d91e-49b8-ba74-ea31046a501f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253402083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3253402083
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.781233745
Short name T1087
Test name
Test status
Simulation time 213007014 ps
CPU time 13.05 seconds
Started Jun 11 03:20:52 PM PDT 24
Finished Jun 11 03:21:07 PM PDT 24
Peak memory 215552 kb
Host smart-73f26317-9e46-41d4-be78-6ea38108af69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781233745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.781233745
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2736724743
Short name T99
Test name
Test status
Simulation time 166164912 ps
CPU time 1.68 seconds
Started Jun 11 03:21:02 PM PDT 24
Finished Jun 11 03:21:05 PM PDT 24
Peak memory 216612 kb
Host smart-bfc9e05e-7a43-4eb5-8d7a-c899cd447f4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736724743 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2736724743
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3639835248
Short name T1067
Test name
Test status
Simulation time 58038953 ps
CPU time 0.74 seconds
Started Jun 11 03:21:02 PM PDT 24
Finished Jun 11 03:21:04 PM PDT 24
Peak memory 203896 kb
Host smart-803c35b1-8900-4ae0-a226-287ecda253ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639835248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3639835248
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1400016682
Short name T1059
Test name
Test status
Simulation time 514809245 ps
CPU time 3.09 seconds
Started Jun 11 03:21:01 PM PDT 24
Finished Jun 11 03:21:05 PM PDT 24
Peak memory 215456 kb
Host smart-d7277d89-68ba-4482-9a14-9595792f0550
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400016682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1400016682
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.449484337
Short name T187
Test name
Test status
Simulation time 348248497 ps
CPU time 7 seconds
Started Jun 11 03:21:04 PM PDT 24
Finished Jun 11 03:21:12 PM PDT 24
Peak memory 216000 kb
Host smart-87e1b423-11fc-42ac-9969-8254bbe2cdce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449484337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.449484337
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2589097902
Short name T1083
Test name
Test status
Simulation time 127541103 ps
CPU time 3.8 seconds
Started Jun 11 03:21:04 PM PDT 24
Finished Jun 11 03:21:09 PM PDT 24
Peak memory 217872 kb
Host smart-ffc0907e-624c-4b02-8d33-0caf33ee5dfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589097902 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2589097902
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2551189714
Short name T126
Test name
Test status
Simulation time 374732499 ps
CPU time 2.12 seconds
Started Jun 11 03:21:01 PM PDT 24
Finished Jun 11 03:21:05 PM PDT 24
Peak memory 215552 kb
Host smart-159bc7a0-90e0-45e0-99ad-852ebcdef834
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551189714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2551189714
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2931297251
Short name T999
Test name
Test status
Simulation time 16788894 ps
CPU time 0.74 seconds
Started Jun 11 03:21:00 PM PDT 24
Finished Jun 11 03:21:02 PM PDT 24
Peak memory 204200 kb
Host smart-f089f8cf-5460-4c13-8df2-43ea9bb6a266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931297251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2931297251
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3889702431
Short name T157
Test name
Test status
Simulation time 353492931 ps
CPU time 2.1 seconds
Started Jun 11 03:21:00 PM PDT 24
Finished Jun 11 03:21:03 PM PDT 24
Peak memory 215556 kb
Host smart-d69cce70-e96e-4a00-bd36-6c3a0b02bccd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889702431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3889702431
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2147444843
Short name T181
Test name
Test status
Simulation time 266949835 ps
CPU time 3.37 seconds
Started Jun 11 03:21:01 PM PDT 24
Finished Jun 11 03:21:06 PM PDT 24
Peak memory 215812 kb
Host smart-70e7e1ca-cdd4-4b07-8222-02e66c6b0f29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147444843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2147444843
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3993292575
Short name T101
Test name
Test status
Simulation time 379950576 ps
CPU time 7 seconds
Started Jun 11 03:20:59 PM PDT 24
Finished Jun 11 03:21:07 PM PDT 24
Peak memory 215508 kb
Host smart-fc686ebd-20f3-48ad-94aa-a3434491806f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993292575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3993292575
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2870996960
Short name T113
Test name
Test status
Simulation time 55014156 ps
CPU time 3.81 seconds
Started Jun 11 03:21:03 PM PDT 24
Finished Jun 11 03:21:07 PM PDT 24
Peak memory 217676 kb
Host smart-abbf1ab2-6419-4474-8e8f-01552b7b3f7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870996960 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2870996960
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.80218229
Short name T1024
Test name
Test status
Simulation time 104068373 ps
CPU time 2.84 seconds
Started Jun 11 03:21:01 PM PDT 24
Finished Jun 11 03:21:06 PM PDT 24
Peak memory 215716 kb
Host smart-abc68e84-e8ef-4337-a2d3-3608462d10eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80218229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.80218229
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.822696498
Short name T1019
Test name
Test status
Simulation time 14967694 ps
CPU time 0.75 seconds
Started Jun 11 03:21:01 PM PDT 24
Finished Jun 11 03:21:03 PM PDT 24
Peak memory 203848 kb
Host smart-4766a76d-7390-4f7b-81f9-44357d53c0c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822696498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.822696498
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2575469944
Short name T1006
Test name
Test status
Simulation time 163144269 ps
CPU time 4.19 seconds
Started Jun 11 03:21:03 PM PDT 24
Finished Jun 11 03:21:08 PM PDT 24
Peak memory 215480 kb
Host smart-dd9a052a-81a7-4598-b6bd-45043eca0391
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575469944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2575469944
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2761571683
Short name T186
Test name
Test status
Simulation time 1088718806 ps
CPU time 16.11 seconds
Started Jun 11 03:21:01 PM PDT 24
Finished Jun 11 03:21:18 PM PDT 24
Peak memory 215528 kb
Host smart-d4725d09-9d79-4f77-89b1-8c7a3e96033e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761571683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2761571683
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3902273188
Short name T1009
Test name
Test status
Simulation time 51678328 ps
CPU time 1.94 seconds
Started Jun 11 03:21:02 PM PDT 24
Finished Jun 11 03:21:05 PM PDT 24
Peak memory 215752 kb
Host smart-107612cf-2271-4364-8967-429afdaf7725
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902273188 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3902273188
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.7473805
Short name T1012
Test name
Test status
Simulation time 35152996 ps
CPU time 1.28 seconds
Started Jun 11 03:20:59 PM PDT 24
Finished Jun 11 03:21:01 PM PDT 24
Peak memory 215576 kb
Host smart-f4119af0-b35d-4e0f-866d-1fffb3126674
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7473805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.7473805
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2580046183
Short name T990
Test name
Test status
Simulation time 49807667 ps
CPU time 0.77 seconds
Started Jun 11 03:21:03 PM PDT 24
Finished Jun 11 03:21:05 PM PDT 24
Peak memory 204216 kb
Host smart-254a0722-6c12-496f-8d46-0255426e8f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580046183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2580046183
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3948597330
Short name T1052
Test name
Test status
Simulation time 611606698 ps
CPU time 4.18 seconds
Started Jun 11 03:21:02 PM PDT 24
Finished Jun 11 03:21:07 PM PDT 24
Peak memory 215496 kb
Host smart-aae85133-2706-4134-9d9c-ed02f05b3634
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948597330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3948597330
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.844060034
Short name T1046
Test name
Test status
Simulation time 312713988 ps
CPU time 3.59 seconds
Started Jun 11 03:21:02 PM PDT 24
Finished Jun 11 03:21:07 PM PDT 24
Peak memory 216004 kb
Host smart-5495dfeb-4733-4a23-935f-1ed957822849
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844060034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.844060034
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3345503802
Short name T1013
Test name
Test status
Simulation time 86836143 ps
CPU time 1.52 seconds
Started Jun 11 03:21:03 PM PDT 24
Finished Jun 11 03:21:05 PM PDT 24
Peak memory 215548 kb
Host smart-b9486818-313e-45bb-88b0-d5b6a9468339
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345503802 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3345503802
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1466665939
Short name T118
Test name
Test status
Simulation time 248103174 ps
CPU time 1.42 seconds
Started Jun 11 03:21:05 PM PDT 24
Finished Jun 11 03:21:08 PM PDT 24
Peak memory 215468 kb
Host smart-8707adc8-7bb2-47c6-af09-34fad8eedafb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466665939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1466665939
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3254660647
Short name T1002
Test name
Test status
Simulation time 18762929 ps
CPU time 0.78 seconds
Started Jun 11 03:21:00 PM PDT 24
Finished Jun 11 03:21:02 PM PDT 24
Peak memory 204212 kb
Host smart-0196fd19-84aa-4812-83dc-cb443d8afc7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254660647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3254660647
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2425759502
Short name T1000
Test name
Test status
Simulation time 226897182 ps
CPU time 3.98 seconds
Started Jun 11 03:21:04 PM PDT 24
Finished Jun 11 03:21:10 PM PDT 24
Peak memory 215480 kb
Host smart-7469f65f-9a3c-4c78-ae56-1390ad072425
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425759502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2425759502
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1157761267
Short name T108
Test name
Test status
Simulation time 488559604 ps
CPU time 3.87 seconds
Started Jun 11 03:21:01 PM PDT 24
Finished Jun 11 03:21:06 PM PDT 24
Peak memory 215672 kb
Host smart-2e248e90-f09b-447f-ac31-e77ecc12e314
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157761267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1157761267
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3589579360
Short name T184
Test name
Test status
Simulation time 3973625603 ps
CPU time 8.24 seconds
Started Jun 11 03:21:00 PM PDT 24
Finished Jun 11 03:21:09 PM PDT 24
Peak memory 215592 kb
Host smart-89109c67-7cdd-4011-b96f-092c0e9644a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589579360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3589579360
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2328324951
Short name T1031
Test name
Test status
Simulation time 417179870 ps
CPU time 3.78 seconds
Started Jun 11 03:21:11 PM PDT 24
Finished Jun 11 03:21:16 PM PDT 24
Peak memory 217596 kb
Host smart-eba52046-504f-4343-9f9d-f40198295a91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328324951 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2328324951
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3103802619
Short name T1070
Test name
Test status
Simulation time 34519394 ps
CPU time 1.28 seconds
Started Jun 11 03:21:05 PM PDT 24
Finished Jun 11 03:21:07 PM PDT 24
Peak memory 207172 kb
Host smart-00cdcf55-24eb-471d-beb2-53f239629b93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103802619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3103802619
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2424161747
Short name T996
Test name
Test status
Simulation time 23835094 ps
CPU time 0.7 seconds
Started Jun 11 03:21:05 PM PDT 24
Finished Jun 11 03:21:07 PM PDT 24
Peak memory 203764 kb
Host smart-dc3db75b-2b78-455e-bee3-c7e75e7a853f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424161747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2424161747
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3163631287
Short name T1015
Test name
Test status
Simulation time 167908413 ps
CPU time 3.08 seconds
Started Jun 11 03:21:12 PM PDT 24
Finished Jun 11 03:21:17 PM PDT 24
Peak memory 215484 kb
Host smart-2a71d767-4fa0-479d-be7b-ea8f787ffe43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163631287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3163631287
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.754360310
Short name T111
Test name
Test status
Simulation time 223681251 ps
CPU time 1.71 seconds
Started Jun 11 03:21:16 PM PDT 24
Finished Jun 11 03:21:19 PM PDT 24
Peak memory 215656 kb
Host smart-0e47de6e-f12c-4a81-870a-868692a70d19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754360310 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.754360310
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1400519922
Short name T1090
Test name
Test status
Simulation time 68200412 ps
CPU time 2.15 seconds
Started Jun 11 03:21:12 PM PDT 24
Finished Jun 11 03:21:16 PM PDT 24
Peak memory 207372 kb
Host smart-1fef437b-8e00-4780-b801-6511a60cc88f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400519922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1400519922
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3422333429
Short name T1008
Test name
Test status
Simulation time 34084387 ps
CPU time 0.73 seconds
Started Jun 11 03:21:21 PM PDT 24
Finished Jun 11 03:21:24 PM PDT 24
Peak memory 203972 kb
Host smart-1fe2bf96-153b-4c4e-bd44-6ea13fafcbbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422333429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3422333429
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2589340934
Short name T1007
Test name
Test status
Simulation time 85417878 ps
CPU time 1.68 seconds
Started Jun 11 03:21:16 PM PDT 24
Finished Jun 11 03:21:19 PM PDT 24
Peak memory 215556 kb
Host smart-04eee36e-1430-4ce2-a38d-dcd9b075c588
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589340934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2589340934
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1112830986
Short name T104
Test name
Test status
Simulation time 405098130 ps
CPU time 2.76 seconds
Started Jun 11 03:21:14 PM PDT 24
Finished Jun 11 03:21:18 PM PDT 24
Peak memory 215864 kb
Host smart-3a2d966b-9ae6-4fe7-b642-c3a6349d5f21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112830986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1112830986
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.467413490
Short name T1084
Test name
Test status
Simulation time 460777954 ps
CPU time 6.42 seconds
Started Jun 11 03:21:12 PM PDT 24
Finished Jun 11 03:21:20 PM PDT 24
Peak memory 215752 kb
Host smart-f9c4c780-3cb4-4166-9b75-73540c96bc54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467413490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.467413490
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3867073440
Short name T1021
Test name
Test status
Simulation time 353126871 ps
CPU time 2.48 seconds
Started Jun 11 03:21:12 PM PDT 24
Finished Jun 11 03:21:16 PM PDT 24
Peak memory 216600 kb
Host smart-0cdadfed-8ea5-4bd0-aca8-d35bcbfe415f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867073440 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3867073440
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1745889760
Short name T1074
Test name
Test status
Simulation time 55178086 ps
CPU time 1.8 seconds
Started Jun 11 03:21:11 PM PDT 24
Finished Jun 11 03:21:14 PM PDT 24
Peak memory 207244 kb
Host smart-ca654885-bcc5-4d11-a921-5bf9569e98ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745889760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1745889760
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2600521722
Short name T1027
Test name
Test status
Simulation time 18269818 ps
CPU time 0.73 seconds
Started Jun 11 03:21:11 PM PDT 24
Finished Jun 11 03:21:13 PM PDT 24
Peak memory 203884 kb
Host smart-8624bdf7-a836-4e8c-8335-f3340f47844e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600521722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2600521722
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1151345886
Short name T1066
Test name
Test status
Simulation time 1010557404 ps
CPU time 2.89 seconds
Started Jun 11 03:21:11 PM PDT 24
Finished Jun 11 03:21:16 PM PDT 24
Peak memory 215504 kb
Host smart-6f71d4cb-abe0-4062-a344-90b6923b57f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151345886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1151345886
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4241280452
Short name T110
Test name
Test status
Simulation time 60459832 ps
CPU time 1.98 seconds
Started Jun 11 03:21:11 PM PDT 24
Finished Jun 11 03:21:15 PM PDT 24
Peak memory 215680 kb
Host smart-52e65de5-fa21-4900-8bfc-900833deb062
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241280452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
4241280452
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1345539261
Short name T100
Test name
Test status
Simulation time 281739705 ps
CPU time 7.82 seconds
Started Jun 11 03:21:10 PM PDT 24
Finished Jun 11 03:21:19 PM PDT 24
Peak memory 215684 kb
Host smart-590ccc66-33bf-4b14-9c5f-a1dc34dbb35d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345539261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1345539261
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.296303054
Short name T1028
Test name
Test status
Simulation time 618290266 ps
CPU time 8.95 seconds
Started Jun 11 03:20:42 PM PDT 24
Finished Jun 11 03:20:53 PM PDT 24
Peak memory 207392 kb
Host smart-1dfb0118-fbdf-4eb5-a576-7628f2a79a8e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296303054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.296303054
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.715262486
Short name T127
Test name
Test status
Simulation time 3603817044 ps
CPU time 25.77 seconds
Started Jun 11 03:20:40 PM PDT 24
Finished Jun 11 03:21:08 PM PDT 24
Peak memory 207320 kb
Host smart-262b6a65-8a8e-4eb9-b47f-5bbd4d62dbeb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715262486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.715262486
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2698389787
Short name T1057
Test name
Test status
Simulation time 35767554 ps
CPU time 1.17 seconds
Started Jun 11 03:20:33 PM PDT 24
Finished Jun 11 03:20:36 PM PDT 24
Peak memory 207356 kb
Host smart-51020944-5aea-4195-a6e9-b4662ef2a498
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698389787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2698389787
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.553491095
Short name T1005
Test name
Test status
Simulation time 90828683 ps
CPU time 2.95 seconds
Started Jun 11 03:20:41 PM PDT 24
Finished Jun 11 03:20:46 PM PDT 24
Peak memory 217992 kb
Host smart-2695a109-817d-412d-aaf1-c489cce5a8d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553491095 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.553491095
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2681072670
Short name T120
Test name
Test status
Simulation time 107608414 ps
CPU time 1.92 seconds
Started Jun 11 03:20:30 PM PDT 24
Finished Jun 11 03:20:35 PM PDT 24
Peak memory 207340 kb
Host smart-1ab970e0-4b0d-4fff-a642-ea03bdc9094a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681072670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
681072670
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.81664723
Short name T1098
Test name
Test status
Simulation time 107666258 ps
CPU time 0.72 seconds
Started Jun 11 03:20:29 PM PDT 24
Finished Jun 11 03:20:32 PM PDT 24
Peak memory 203924 kb
Host smart-7bc38b8f-f44e-4238-853c-cbc5134d6c3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81664723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.81664723
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1449987730
Short name T1078
Test name
Test status
Simulation time 161299001 ps
CPU time 2.1 seconds
Started Jun 11 03:20:28 PM PDT 24
Finished Jun 11 03:20:33 PM PDT 24
Peak memory 215516 kb
Host smart-8226c600-aa0a-4c55-8982-0710e65e6926
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449987730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1449987730
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1150542492
Short name T1038
Test name
Test status
Simulation time 30807496 ps
CPU time 0.65 seconds
Started Jun 11 03:20:32 PM PDT 24
Finished Jun 11 03:20:34 PM PDT 24
Peak memory 203856 kb
Host smart-6eb65935-969c-45a1-85e1-e78ff66df5a9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150542492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1150542492
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.117159611
Short name T1054
Test name
Test status
Simulation time 422613732 ps
CPU time 4.98 seconds
Started Jun 11 03:20:42 PM PDT 24
Finished Jun 11 03:20:49 PM PDT 24
Peak memory 215424 kb
Host smart-a2dce996-8ccb-48a7-b921-ade7efe1f0b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117159611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.117159611
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2703458890
Short name T106
Test name
Test status
Simulation time 740548160 ps
CPU time 5.16 seconds
Started Jun 11 03:20:33 PM PDT 24
Finished Jun 11 03:20:40 PM PDT 24
Peak memory 215700 kb
Host smart-5650b6f6-9bdf-4914-bd43-b77f6cfd85d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703458890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
703458890
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.984906353
Short name T1060
Test name
Test status
Simulation time 791375338 ps
CPU time 14.42 seconds
Started Jun 11 03:20:27 PM PDT 24
Finished Jun 11 03:20:44 PM PDT 24
Peak memory 215556 kb
Host smart-a447eef3-8e63-4359-b00f-6a3779a3034f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984906353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.984906353
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.464468564
Short name T984
Test name
Test status
Simulation time 41818405 ps
CPU time 0.74 seconds
Started Jun 11 03:21:13 PM PDT 24
Finished Jun 11 03:21:16 PM PDT 24
Peak memory 203896 kb
Host smart-ddf6abc9-906b-45a6-894f-f86eee3a5b1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464468564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.464468564
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2500833653
Short name T1022
Test name
Test status
Simulation time 40560197 ps
CPU time 0.75 seconds
Started Jun 11 03:21:12 PM PDT 24
Finished Jun 11 03:21:15 PM PDT 24
Peak memory 203868 kb
Host smart-a380cb58-3fe1-42b6-9b59-35997da3d8f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500833653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2500833653
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1649876244
Short name T989
Test name
Test status
Simulation time 16232438 ps
CPU time 0.8 seconds
Started Jun 11 03:21:13 PM PDT 24
Finished Jun 11 03:21:16 PM PDT 24
Peak memory 203964 kb
Host smart-22995bb4-ee27-4e7c-9645-01d335120718
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649876244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1649876244
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1831675654
Short name T1017
Test name
Test status
Simulation time 49562085 ps
CPU time 0.76 seconds
Started Jun 11 03:21:12 PM PDT 24
Finished Jun 11 03:21:14 PM PDT 24
Peak memory 203884 kb
Host smart-123049d7-6cdd-452a-aee5-ae82d2a7256c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831675654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1831675654
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1761335985
Short name T995
Test name
Test status
Simulation time 75456460 ps
CPU time 0.71 seconds
Started Jun 11 03:21:13 PM PDT 24
Finished Jun 11 03:21:15 PM PDT 24
Peak memory 203880 kb
Host smart-5b4bf66c-a16d-4db0-83ea-caf7738923d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761335985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1761335985
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.103252019
Short name T1065
Test name
Test status
Simulation time 47909638 ps
CPU time 0.69 seconds
Started Jun 11 03:21:11 PM PDT 24
Finished Jun 11 03:21:13 PM PDT 24
Peak memory 203868 kb
Host smart-4ae61ac2-8acc-4b27-b7f6-bf39419682a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103252019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.103252019
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1450936848
Short name T1034
Test name
Test status
Simulation time 12689493 ps
CPU time 0.71 seconds
Started Jun 11 03:21:11 PM PDT 24
Finished Jun 11 03:21:14 PM PDT 24
Peak memory 203896 kb
Host smart-3dc1ee70-ea54-42f1-b665-ff79fd23d299
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450936848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1450936848
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.622508298
Short name T983
Test name
Test status
Simulation time 13207173 ps
CPU time 0.75 seconds
Started Jun 11 03:21:16 PM PDT 24
Finished Jun 11 03:21:18 PM PDT 24
Peak memory 203916 kb
Host smart-dcea3569-08a6-4de1-9a99-ee93ec229691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622508298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.622508298
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3294469618
Short name T1050
Test name
Test status
Simulation time 12301815 ps
CPU time 0.71 seconds
Started Jun 11 03:21:11 PM PDT 24
Finished Jun 11 03:21:13 PM PDT 24
Peak memory 204176 kb
Host smart-e7dcf310-1a35-4744-b132-ae911f726146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294469618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3294469618
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3676291767
Short name T1011
Test name
Test status
Simulation time 33751260 ps
CPU time 0.72 seconds
Started Jun 11 03:21:13 PM PDT 24
Finished Jun 11 03:21:16 PM PDT 24
Peak memory 204060 kb
Host smart-fd5b644e-825b-401f-989b-6b7a72375f98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676291767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3676291767
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.863951131
Short name T1101
Test name
Test status
Simulation time 620066243 ps
CPU time 16.04 seconds
Started Jun 11 03:20:38 PM PDT 24
Finished Jun 11 03:20:56 PM PDT 24
Peak memory 207292 kb
Host smart-a6ea0d83-d732-4fa2-9477-78d8d40eabfd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863951131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.863951131
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2616401878
Short name T985
Test name
Test status
Simulation time 8200777426 ps
CPU time 35.11 seconds
Started Jun 11 03:20:39 PM PDT 24
Finished Jun 11 03:21:16 PM PDT 24
Peak memory 207344 kb
Host smart-a276c52f-82fc-4fb1-87d5-a021745eb02c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616401878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2616401878
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.370056315
Short name T83
Test name
Test status
Simulation time 109120036 ps
CPU time 1.17 seconds
Started Jun 11 03:20:42 PM PDT 24
Finished Jun 11 03:20:45 PM PDT 24
Peak memory 216576 kb
Host smart-0c818c38-610a-4610-8dee-6cb059d9d0fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370056315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.370056315
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.114011102
Short name T1096
Test name
Test status
Simulation time 98021142 ps
CPU time 3.55 seconds
Started Jun 11 03:20:39 PM PDT 24
Finished Jun 11 03:20:44 PM PDT 24
Peak memory 217252 kb
Host smart-d9d0bb1a-aeb3-4fa6-b2cd-b0682f211f75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114011102 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.114011102
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2338501321
Short name T1063
Test name
Test status
Simulation time 139664170 ps
CPU time 1.3 seconds
Started Jun 11 03:20:42 PM PDT 24
Finished Jun 11 03:20:45 PM PDT 24
Peak memory 215556 kb
Host smart-1f3365a9-519e-4684-8356-89d19d47c207
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338501321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
338501321
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1388364320
Short name T1016
Test name
Test status
Simulation time 17656494 ps
CPU time 0.76 seconds
Started Jun 11 03:20:40 PM PDT 24
Finished Jun 11 03:20:42 PM PDT 24
Peak memory 203892 kb
Host smart-7a927a69-7a12-4ddc-ad5f-6fc1a16b7c89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388364320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
388364320
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3251374861
Short name T124
Test name
Test status
Simulation time 20343192 ps
CPU time 1.23 seconds
Started Jun 11 03:20:39 PM PDT 24
Finished Jun 11 03:20:42 PM PDT 24
Peak memory 215544 kb
Host smart-f86ed842-df5d-4047-86d2-e8bef36b46ed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251374861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3251374861
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3377204818
Short name T1080
Test name
Test status
Simulation time 12356909 ps
CPU time 0.66 seconds
Started Jun 11 03:20:37 PM PDT 24
Finished Jun 11 03:20:39 PM PDT 24
Peak memory 204192 kb
Host smart-1d1c7070-448b-4639-8f36-42605a1675cf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377204818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3377204818
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3361581610
Short name T1055
Test name
Test status
Simulation time 89876053 ps
CPU time 1.53 seconds
Started Jun 11 03:20:39 PM PDT 24
Finished Jun 11 03:20:42 PM PDT 24
Peak memory 215552 kb
Host smart-14a45910-c8ad-4673-99ab-62564bea37ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361581610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3361581610
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.526011993
Short name T1036
Test name
Test status
Simulation time 212092245 ps
CPU time 1.84 seconds
Started Jun 11 03:20:43 PM PDT 24
Finished Jun 11 03:20:46 PM PDT 24
Peak memory 215624 kb
Host smart-f2b27362-914e-4723-b668-a10173df00b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526011993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.526011993
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2490099171
Short name T1073
Test name
Test status
Simulation time 21279051 ps
CPU time 0.69 seconds
Started Jun 11 03:21:10 PM PDT 24
Finished Jun 11 03:21:12 PM PDT 24
Peak memory 204228 kb
Host smart-9a19e89d-2017-44d5-a23f-365b37a4f25c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490099171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2490099171
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4139348707
Short name T991
Test name
Test status
Simulation time 14792767 ps
CPU time 0.76 seconds
Started Jun 11 03:21:11 PM PDT 24
Finished Jun 11 03:21:13 PM PDT 24
Peak memory 203936 kb
Host smart-444fb8db-782f-4090-9618-fdbd58aa7b35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139348707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4139348707
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.499127453
Short name T1023
Test name
Test status
Simulation time 13448574 ps
CPU time 0.73 seconds
Started Jun 11 03:21:11 PM PDT 24
Finished Jun 11 03:21:13 PM PDT 24
Peak memory 203876 kb
Host smart-5c78f586-1a84-4629-aeca-32d3a7fc8daa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499127453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.499127453
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3105146433
Short name T988
Test name
Test status
Simulation time 15651197 ps
CPU time 0.77 seconds
Started Jun 11 03:21:13 PM PDT 24
Finished Jun 11 03:21:16 PM PDT 24
Peak memory 204228 kb
Host smart-6dbe1a0a-ac04-4d66-afe2-a7e431bcfd13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105146433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3105146433
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.5822305
Short name T1071
Test name
Test status
Simulation time 23680435 ps
CPU time 0.7 seconds
Started Jun 11 03:21:21 PM PDT 24
Finished Jun 11 03:21:23 PM PDT 24
Peak memory 203748 kb
Host smart-c9a78102-84bf-4bd7-8481-8aa0b2dfd783
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5822305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.5822305
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1592497033
Short name T1056
Test name
Test status
Simulation time 13547876 ps
CPU time 0.68 seconds
Started Jun 11 03:21:21 PM PDT 24
Finished Jun 11 03:21:23 PM PDT 24
Peak memory 203864 kb
Host smart-74e94c1a-7ebb-48cc-bf18-54b7abb2608b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592497033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1592497033
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3194864982
Short name T1075
Test name
Test status
Simulation time 24354435 ps
CPU time 0.76 seconds
Started Jun 11 03:21:23 PM PDT 24
Finished Jun 11 03:21:26 PM PDT 24
Peak memory 203944 kb
Host smart-6387b2ee-c963-451e-ae9f-4ec3f3ed441f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194864982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3194864982
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.698537548
Short name T1049
Test name
Test status
Simulation time 23004714 ps
CPU time 0.74 seconds
Started Jun 11 03:21:23 PM PDT 24
Finished Jun 11 03:21:26 PM PDT 24
Peak memory 203888 kb
Host smart-3957e33d-871d-49e4-840e-7f22d2a3826e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698537548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.698537548
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3763175836
Short name T1051
Test name
Test status
Simulation time 14440875 ps
CPU time 0.76 seconds
Started Jun 11 03:21:22 PM PDT 24
Finished Jun 11 03:21:26 PM PDT 24
Peak memory 203908 kb
Host smart-145f18ce-fe5f-4171-93a3-7f6da53f8aec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763175836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3763175836
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2575552359
Short name T997
Test name
Test status
Simulation time 57991809 ps
CPU time 0.71 seconds
Started Jun 11 03:21:20 PM PDT 24
Finished Jun 11 03:21:22 PM PDT 24
Peak memory 203844 kb
Host smart-e1eda227-5b0f-4615-9049-c5be82c1e702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575552359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2575552359
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.866817726
Short name T1030
Test name
Test status
Simulation time 428095775 ps
CPU time 8.23 seconds
Started Jun 11 03:20:38 PM PDT 24
Finished Jun 11 03:20:48 PM PDT 24
Peak memory 215540 kb
Host smart-6dde0be3-d429-4d33-96b0-d414a1639035
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866817726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.866817726
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3940836646
Short name T1053
Test name
Test status
Simulation time 2533183124 ps
CPU time 13.45 seconds
Started Jun 11 03:20:42 PM PDT 24
Finished Jun 11 03:20:57 PM PDT 24
Peak memory 207376 kb
Host smart-e3f20645-7511-4182-9cb5-fd79427f9ae6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940836646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3940836646
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.413518694
Short name T82
Test name
Test status
Simulation time 40123620 ps
CPU time 1.21 seconds
Started Jun 11 03:20:40 PM PDT 24
Finished Jun 11 03:20:42 PM PDT 24
Peak memory 207284 kb
Host smart-16c242a4-4066-42fb-9e02-69a0fce6feb3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413518694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.413518694
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1806521463
Short name T1064
Test name
Test status
Simulation time 48992937 ps
CPU time 1.87 seconds
Started Jun 11 03:20:41 PM PDT 24
Finished Jun 11 03:20:44 PM PDT 24
Peak memory 215764 kb
Host smart-6be8ecdc-724b-46f9-b954-18ff9329086b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806521463 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1806521463
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.895858354
Short name T1081
Test name
Test status
Simulation time 340383648 ps
CPU time 2.83 seconds
Started Jun 11 03:20:42 PM PDT 24
Finished Jun 11 03:20:46 PM PDT 24
Peak memory 215508 kb
Host smart-dc2f8c29-cf82-4b80-84b4-29bde57a1b70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895858354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.895858354
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1447893405
Short name T994
Test name
Test status
Simulation time 45189083 ps
CPU time 0.72 seconds
Started Jun 11 03:20:42 PM PDT 24
Finished Jun 11 03:20:44 PM PDT 24
Peak memory 203884 kb
Host smart-5b56fd16-96d6-47c9-8990-0e8d6a2a4187
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447893405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
447893405
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2078228563
Short name T1095
Test name
Test status
Simulation time 87932248 ps
CPU time 1.61 seconds
Started Jun 11 03:20:38 PM PDT 24
Finished Jun 11 03:20:41 PM PDT 24
Peak memory 215544 kb
Host smart-6d1a55bf-8cab-4a53-9cc7-8c85fc2a829d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078228563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2078228563
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3975201281
Short name T1099
Test name
Test status
Simulation time 29270011 ps
CPU time 0.66 seconds
Started Jun 11 03:20:38 PM PDT 24
Finished Jun 11 03:20:40 PM PDT 24
Peak memory 203740 kb
Host smart-6c7ca69c-f635-46b8-b1ef-23fc5fca99df
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975201281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3975201281
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4000227729
Short name T1003
Test name
Test status
Simulation time 144649580 ps
CPU time 3.9 seconds
Started Jun 11 03:20:40 PM PDT 24
Finished Jun 11 03:20:46 PM PDT 24
Peak memory 215560 kb
Host smart-fd4bd08f-b990-4065-aced-28a1c2b3e011
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000227729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.4000227729
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1998642143
Short name T1072
Test name
Test status
Simulation time 115725860 ps
CPU time 3.71 seconds
Started Jun 11 03:20:40 PM PDT 24
Finished Jun 11 03:20:45 PM PDT 24
Peak memory 215752 kb
Host smart-60d9adb8-da92-41b5-b990-9ceca4bf150d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998642143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
998642143
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2045899341
Short name T1044
Test name
Test status
Simulation time 4491752975 ps
CPU time 7.22 seconds
Started Jun 11 03:20:41 PM PDT 24
Finished Jun 11 03:20:50 PM PDT 24
Peak memory 215844 kb
Host smart-c51e4009-df7d-4560-a07b-79b815c2be74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045899341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2045899341
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1202076132
Short name T1082
Test name
Test status
Simulation time 14131386 ps
CPU time 0.77 seconds
Started Jun 11 03:21:23 PM PDT 24
Finished Jun 11 03:21:26 PM PDT 24
Peak memory 203888 kb
Host smart-0816428d-8fa3-402d-a350-29082bd72861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202076132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1202076132
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4043161313
Short name T1029
Test name
Test status
Simulation time 101658784 ps
CPU time 0.72 seconds
Started Jun 11 03:21:22 PM PDT 24
Finished Jun 11 03:21:25 PM PDT 24
Peak memory 204212 kb
Host smart-b514d4e4-a5e9-4d48-86ae-d834408671f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043161313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
4043161313
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1429803749
Short name T1058
Test name
Test status
Simulation time 16035170 ps
CPU time 0.72 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:21:28 PM PDT 24
Peak memory 203900 kb
Host smart-a0c674ed-beee-49c3-be4d-826950076198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429803749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1429803749
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1208551575
Short name T1018
Test name
Test status
Simulation time 38830765 ps
CPU time 0.72 seconds
Started Jun 11 03:21:24 PM PDT 24
Finished Jun 11 03:21:27 PM PDT 24
Peak memory 203880 kb
Host smart-b0ba127e-2f4a-4ec5-8eec-ee7ff7276f49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208551575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1208551575
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2809727749
Short name T1079
Test name
Test status
Simulation time 36217845 ps
CPU time 0.73 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:21:28 PM PDT 24
Peak memory 203896 kb
Host smart-3dd297c1-ac8f-4ddf-9e3b-39df272ba0d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809727749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2809727749
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2340152105
Short name T1093
Test name
Test status
Simulation time 18945706 ps
CPU time 0.71 seconds
Started Jun 11 03:21:23 PM PDT 24
Finished Jun 11 03:21:27 PM PDT 24
Peak memory 203892 kb
Host smart-7f658ca7-de92-4ff8-858e-da48225bfa30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340152105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2340152105
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1881656148
Short name T1041
Test name
Test status
Simulation time 55764726 ps
CPU time 0.75 seconds
Started Jun 11 03:21:24 PM PDT 24
Finished Jun 11 03:21:28 PM PDT 24
Peak memory 204192 kb
Host smart-f50589fe-f4fd-4c8c-8365-351ed58c9a9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881656148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1881656148
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.79111590
Short name T1020
Test name
Test status
Simulation time 29262349 ps
CPU time 0.76 seconds
Started Jun 11 03:21:24 PM PDT 24
Finished Jun 11 03:21:28 PM PDT 24
Peak memory 203884 kb
Host smart-d327c5e5-a1e7-4c45-baf5-00852627ab7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79111590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.79111590
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.4115989758
Short name T993
Test name
Test status
Simulation time 59689653 ps
CPU time 0.78 seconds
Started Jun 11 03:21:23 PM PDT 24
Finished Jun 11 03:21:26 PM PDT 24
Peak memory 203880 kb
Host smart-68bf3323-e878-4ed6-91c4-3887d6d13af1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115989758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
4115989758
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1448749837
Short name T998
Test name
Test status
Simulation time 45761547 ps
CPU time 0.68 seconds
Started Jun 11 03:21:21 PM PDT 24
Finished Jun 11 03:21:24 PM PDT 24
Peak memory 204196 kb
Host smart-c1beb2c3-ad20-453e-aa89-bb196d5f97ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448749837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1448749837
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1832800017
Short name T1077
Test name
Test status
Simulation time 287552763 ps
CPU time 2.8 seconds
Started Jun 11 03:20:41 PM PDT 24
Finished Jun 11 03:20:46 PM PDT 24
Peak memory 217816 kb
Host smart-74de7339-fad0-4a4f-af12-1ff04809ad3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832800017 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1832800017
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2340570034
Short name T1085
Test name
Test status
Simulation time 102769763 ps
CPU time 1.74 seconds
Started Jun 11 03:20:40 PM PDT 24
Finished Jun 11 03:20:43 PM PDT 24
Peak memory 207336 kb
Host smart-42ae0d42-40fd-407c-90c8-90d8cbf697f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340570034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
340570034
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1352104218
Short name T1042
Test name
Test status
Simulation time 14058782 ps
CPU time 0.7 seconds
Started Jun 11 03:20:39 PM PDT 24
Finished Jun 11 03:20:41 PM PDT 24
Peak memory 203912 kb
Host smart-bca8d4f3-908f-412e-8943-fb46bf8294e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352104218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
352104218
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1957892879
Short name T156
Test name
Test status
Simulation time 74423005 ps
CPU time 1.83 seconds
Started Jun 11 03:20:40 PM PDT 24
Finished Jun 11 03:20:43 PM PDT 24
Peak memory 215552 kb
Host smart-14840752-55b0-41e5-9e26-5293178ad477
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957892879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1957892879
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1388083611
Short name T109
Test name
Test status
Simulation time 124856055 ps
CPU time 3.22 seconds
Started Jun 11 03:20:41 PM PDT 24
Finished Jun 11 03:20:46 PM PDT 24
Peak memory 215752 kb
Host smart-53d72f03-726f-47ab-a8a8-b1587656ec99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388083611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
388083611
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1934625192
Short name T185
Test name
Test status
Simulation time 628914580 ps
CPU time 19.12 seconds
Started Jun 11 03:20:42 PM PDT 24
Finished Jun 11 03:21:03 PM PDT 24
Peak memory 216016 kb
Host smart-061ac17b-66e9-4abf-9c26-800feaf6c188
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934625192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1934625192
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.563868773
Short name T158
Test name
Test status
Simulation time 111855157 ps
CPU time 1.79 seconds
Started Jun 11 03:20:51 PM PDT 24
Finished Jun 11 03:20:54 PM PDT 24
Peak memory 216608 kb
Host smart-9b958491-17b3-499b-bf1e-b190c7dee181
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563868773 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.563868773
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1176649364
Short name T1047
Test name
Test status
Simulation time 266483658 ps
CPU time 2.09 seconds
Started Jun 11 03:20:54 PM PDT 24
Finished Jun 11 03:20:57 PM PDT 24
Peak memory 215432 kb
Host smart-cec1ff47-4569-40b0-b050-5b6cf05d32f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176649364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
176649364
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.38451362
Short name T1010
Test name
Test status
Simulation time 50904796 ps
CPU time 0.7 seconds
Started Jun 11 03:20:48 PM PDT 24
Finished Jun 11 03:20:50 PM PDT 24
Peak memory 203896 kb
Host smart-163d6455-f698-404d-9bad-e28574477c32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38451362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.38451362
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4124243723
Short name T1045
Test name
Test status
Simulation time 30080640 ps
CPU time 1.75 seconds
Started Jun 11 03:20:50 PM PDT 24
Finished Jun 11 03:20:53 PM PDT 24
Peak memory 207312 kb
Host smart-5cc3fb59-70bd-4b4a-b87a-6d4a985fc5ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124243723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.4124243723
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2939308550
Short name T105
Test name
Test status
Simulation time 208123566 ps
CPU time 3.17 seconds
Started Jun 11 03:20:54 PM PDT 24
Finished Jun 11 03:20:59 PM PDT 24
Peak memory 215832 kb
Host smart-9b978ade-824e-4aac-8ccd-9ab7f4a7894b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939308550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
939308550
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.128290359
Short name T1092
Test name
Test status
Simulation time 822042257 ps
CPU time 22.47 seconds
Started Jun 11 03:20:51 PM PDT 24
Finished Jun 11 03:21:15 PM PDT 24
Peak memory 215896 kb
Host smart-bbf76fab-fe40-426a-96a4-ccec4a1421f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128290359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.128290359
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2895200032
Short name T102
Test name
Test status
Simulation time 465480001 ps
CPU time 3.9 seconds
Started Jun 11 03:20:49 PM PDT 24
Finished Jun 11 03:20:54 PM PDT 24
Peak memory 217440 kb
Host smart-b585ef8d-340d-4222-aeaa-3d5fe6f14efc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895200032 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2895200032
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.313525897
Short name T1043
Test name
Test status
Simulation time 255708560 ps
CPU time 1.91 seconds
Started Jun 11 03:20:50 PM PDT 24
Finished Jun 11 03:20:53 PM PDT 24
Peak memory 215388 kb
Host smart-aef0baa3-c93f-4900-8110-f19ef43280b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313525897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.313525897
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.407765553
Short name T1026
Test name
Test status
Simulation time 23004240 ps
CPU time 0.72 seconds
Started Jun 11 03:20:51 PM PDT 24
Finished Jun 11 03:20:53 PM PDT 24
Peak memory 203860 kb
Host smart-42425c78-00b5-4d09-b436-9abd2918d9f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407765553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.407765553
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1557660086
Short name T992
Test name
Test status
Simulation time 617703307 ps
CPU time 3.74 seconds
Started Jun 11 03:20:50 PM PDT 24
Finished Jun 11 03:20:55 PM PDT 24
Peak memory 215568 kb
Host smart-4565325f-6a62-41aa-9575-40df6c4d0ed5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557660086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1557660086
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2575162451
Short name T115
Test name
Test status
Simulation time 39859415 ps
CPU time 1.71 seconds
Started Jun 11 03:20:52 PM PDT 24
Finished Jun 11 03:20:55 PM PDT 24
Peak memory 215720 kb
Host smart-a7bd9dd2-2bf2-49bc-a3db-7cb986c01893
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575162451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
575162451
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.494922430
Short name T1091
Test name
Test status
Simulation time 108091854 ps
CPU time 7.12 seconds
Started Jun 11 03:20:52 PM PDT 24
Finished Jun 11 03:21:00 PM PDT 24
Peak memory 215884 kb
Host smart-07a4b591-3eb3-4308-ab85-a45f019dd67a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494922430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.494922430
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.677797871
Short name T116
Test name
Test status
Simulation time 49289028 ps
CPU time 1.88 seconds
Started Jun 11 03:20:55 PM PDT 24
Finished Jun 11 03:20:58 PM PDT 24
Peak memory 216600 kb
Host smart-f3f2e3d6-7bcc-4b27-889d-7b8f2fbd2820
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677797871 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.677797871
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3024560094
Short name T130
Test name
Test status
Simulation time 294496994 ps
CPU time 2.45 seconds
Started Jun 11 03:20:50 PM PDT 24
Finished Jun 11 03:20:54 PM PDT 24
Peak memory 215556 kb
Host smart-bf18fe24-e089-4d92-926d-4f83ded284b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024560094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
024560094
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1809306934
Short name T1004
Test name
Test status
Simulation time 17893493 ps
CPU time 0.74 seconds
Started Jun 11 03:20:50 PM PDT 24
Finished Jun 11 03:20:52 PM PDT 24
Peak memory 203904 kb
Host smart-b3acf81e-1da7-4189-b974-ac79fef24187
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809306934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
809306934
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.758189596
Short name T155
Test name
Test status
Simulation time 81787061 ps
CPU time 2.12 seconds
Started Jun 11 03:20:54 PM PDT 24
Finished Jun 11 03:20:58 PM PDT 24
Peak memory 215560 kb
Host smart-05c7282f-7e41-4e24-b489-b0f4341e6786
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758189596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.758189596
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.89954436
Short name T1094
Test name
Test status
Simulation time 48325451 ps
CPU time 2.71 seconds
Started Jun 11 03:20:50 PM PDT 24
Finished Jun 11 03:20:54 PM PDT 24
Peak memory 215672 kb
Host smart-3d81cf51-43a2-47f4-8b20-4eb54c9da7be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89954436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.89954436
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.890391392
Short name T183
Test name
Test status
Simulation time 2370264490 ps
CPU time 14.32 seconds
Started Jun 11 03:20:52 PM PDT 24
Finished Jun 11 03:21:08 PM PDT 24
Peak memory 215572 kb
Host smart-9f080a19-600e-4b0d-b974-be6ecded458b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890391392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.890391392
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1554425529
Short name T117
Test name
Test status
Simulation time 215648715 ps
CPU time 3.65 seconds
Started Jun 11 03:20:50 PM PDT 24
Finished Jun 11 03:20:55 PM PDT 24
Peak memory 217204 kb
Host smart-4003a005-2823-4a9b-8b2f-21300dd63114
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554425529 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1554425529
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2159532952
Short name T131
Test name
Test status
Simulation time 201376898 ps
CPU time 2.55 seconds
Started Jun 11 03:20:52 PM PDT 24
Finished Jun 11 03:20:56 PM PDT 24
Peak memory 215576 kb
Host smart-1f8c6498-a76e-4740-825e-ee5bb7fe8bcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159532952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
159532952
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4133246210
Short name T1001
Test name
Test status
Simulation time 47444275 ps
CPU time 0.72 seconds
Started Jun 11 03:20:53 PM PDT 24
Finished Jun 11 03:20:55 PM PDT 24
Peak memory 204040 kb
Host smart-91a9aca9-0b50-4fbc-8cab-7eda7102fb37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133246210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.4
133246210
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4264694438
Short name T1014
Test name
Test status
Simulation time 1133873066 ps
CPU time 4.19 seconds
Started Jun 11 03:20:51 PM PDT 24
Finished Jun 11 03:20:56 PM PDT 24
Peak memory 215560 kb
Host smart-6ddc81ed-64d9-4bc8-a313-021a5944c8b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264694438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4264694438
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2125068630
Short name T96
Test name
Test status
Simulation time 130949791 ps
CPU time 3.07 seconds
Started Jun 11 03:20:53 PM PDT 24
Finished Jun 11 03:20:58 PM PDT 24
Peak memory 215612 kb
Host smart-b895f16f-5e9c-4f7d-a922-2a8fa0cba2f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125068630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
125068630
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3411512396
Short name T189
Test name
Test status
Simulation time 853506895 ps
CPU time 22.79 seconds
Started Jun 11 03:20:52 PM PDT 24
Finished Jun 11 03:21:16 PM PDT 24
Peak memory 216848 kb
Host smart-2849f175-0290-4314-b928-2331d5d479a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411512396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3411512396
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1457950210
Short name T585
Test name
Test status
Simulation time 38711231 ps
CPU time 0.74 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:21:28 PM PDT 24
Peak memory 205336 kb
Host smart-3c867a41-4050-4179-bae9-a4b2ebdbc2a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457950210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
457950210
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3021573597
Short name T824
Test name
Test status
Simulation time 124775494 ps
CPU time 2.51 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:21:30 PM PDT 24
Peak memory 232512 kb
Host smart-21fbc347-e8ff-4b65-8bd0-cf963418f305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021573597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3021573597
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3842953394
Short name T536
Test name
Test status
Simulation time 110805862 ps
CPU time 0.79 seconds
Started Jun 11 03:21:22 PM PDT 24
Finished Jun 11 03:21:26 PM PDT 24
Peak memory 206400 kb
Host smart-954b6668-cf02-4345-9e47-a126e75b825f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842953394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3842953394
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3104760438
Short name T573
Test name
Test status
Simulation time 148338732226 ps
CPU time 120.29 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:23:28 PM PDT 24
Peak memory 249052 kb
Host smart-d8bf4c94-4eec-4ea1-890f-0830c9e56187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104760438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3104760438
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3271846643
Short name T655
Test name
Test status
Simulation time 11971821749 ps
CPU time 45.87 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:22:13 PM PDT 24
Peak memory 240484 kb
Host smart-8ef18012-7066-49e9-b9a0-d367b45479b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271846643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3271846643
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1235331774
Short name T239
Test name
Test status
Simulation time 146155307475 ps
CPU time 328.36 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:26:56 PM PDT 24
Peak memory 255908 kb
Host smart-df69ac18-2e39-4c65-bfda-12e1cea36ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235331774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1235331774
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1459963247
Short name T234
Test name
Test status
Simulation time 12071723996 ps
CPU time 49.64 seconds
Started Jun 11 03:21:24 PM PDT 24
Finished Jun 11 03:22:16 PM PDT 24
Peak memory 249788 kb
Host smart-afff196d-a17e-43da-8c74-f2c8c223c7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459963247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1459963247
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.197764781
Short name T211
Test name
Test status
Simulation time 126966582 ps
CPU time 4.07 seconds
Started Jun 11 03:21:26 PM PDT 24
Finished Jun 11 03:21:34 PM PDT 24
Peak memory 224204 kb
Host smart-26172cf4-64e2-47d1-b571-6087d15e6e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197764781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.197764781
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2492819164
Short name T204
Test name
Test status
Simulation time 1424193338 ps
CPU time 3.68 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:21:31 PM PDT 24
Peak memory 224276 kb
Host smart-1932730e-d26e-4be9-96e8-09aba5b698ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492819164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2492819164
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3597350180
Short name T218
Test name
Test status
Simulation time 1448938695 ps
CPU time 3.77 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:21:31 PM PDT 24
Peak memory 232684 kb
Host smart-084aad5a-f4de-4353-88d5-7e9e6160e446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597350180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3597350180
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2242647316
Short name T272
Test name
Test status
Simulation time 6678633016 ps
CPU time 11.36 seconds
Started Jun 11 03:21:27 PM PDT 24
Finished Jun 11 03:21:42 PM PDT 24
Peak memory 228544 kb
Host smart-3aab3f03-61da-426c-b861-2dfcd32e2533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242647316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2242647316
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1442395925
Short name T980
Test name
Test status
Simulation time 12579029371 ps
CPU time 9.61 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:21:37 PM PDT 24
Peak memory 219976 kb
Host smart-482b6e37-c1a8-493c-a849-f10abdd19d35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1442395925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1442395925
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1350656987
Short name T752
Test name
Test status
Simulation time 52441290511 ps
CPU time 295.86 seconds
Started Jun 11 03:21:29 PM PDT 24
Finished Jun 11 03:26:28 PM PDT 24
Peak memory 255180 kb
Host smart-cd3946a8-ed27-437f-a7ba-7e402f5a2bdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350656987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1350656987
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3323026941
Short name T678
Test name
Test status
Simulation time 373833408 ps
CPU time 3.81 seconds
Started Jun 11 03:21:22 PM PDT 24
Finished Jun 11 03:21:28 PM PDT 24
Peak memory 217508 kb
Host smart-cce34594-4f5f-4f00-828c-5d939bc4e7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323026941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3323026941
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3534677891
Short name T840
Test name
Test status
Simulation time 19798019275 ps
CPU time 13.43 seconds
Started Jun 11 03:21:21 PM PDT 24
Finished Jun 11 03:21:37 PM PDT 24
Peak memory 216172 kb
Host smart-e5f68a9a-5b3a-4137-b24d-741a975b167f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534677891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3534677891
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3544692215
Short name T903
Test name
Test status
Simulation time 110845259 ps
CPU time 1.17 seconds
Started Jun 11 03:21:20 PM PDT 24
Finished Jun 11 03:21:23 PM PDT 24
Peak memory 207768 kb
Host smart-5ebe2425-c5ad-485c-bb6e-3959319fb715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544692215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3544692215
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1264532998
Short name T749
Test name
Test status
Simulation time 142594404 ps
CPU time 0.83 seconds
Started Jun 11 03:21:27 PM PDT 24
Finished Jun 11 03:21:31 PM PDT 24
Peak memory 205912 kb
Host smart-69545ace-016f-4fb5-8747-2cfc6be8ae50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264532998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1264532998
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1057072729
Short name T516
Test name
Test status
Simulation time 93661411 ps
CPU time 3.02 seconds
Started Jun 11 03:21:26 PM PDT 24
Finished Jun 11 03:21:33 PM PDT 24
Peak memory 232504 kb
Host smart-d25f51a5-c949-4af1-b8a7-0aabeb48e715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057072729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1057072729
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3366128188
Short name T65
Test name
Test status
Simulation time 27200719 ps
CPU time 0.7 seconds
Started Jun 11 03:21:29 PM PDT 24
Finished Jun 11 03:21:32 PM PDT 24
Peak memory 204712 kb
Host smart-a28e54a1-6ca4-47f9-bd77-12dda1b553b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366128188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
366128188
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3857508191
Short name T288
Test name
Test status
Simulation time 286964973 ps
CPU time 2.64 seconds
Started Jun 11 03:21:27 PM PDT 24
Finished Jun 11 03:21:32 PM PDT 24
Peak memory 224228 kb
Host smart-a1543516-3577-4d22-b2d1-e0e15af71f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857508191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3857508191
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1830079475
Short name T363
Test name
Test status
Simulation time 15669142 ps
CPU time 0.75 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:21:29 PM PDT 24
Peak memory 206692 kb
Host smart-d6872c85-9893-4691-b3aa-4a7f8013832e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830079475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1830079475
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1138708178
Short name T80
Test name
Test status
Simulation time 42792271984 ps
CPU time 153.76 seconds
Started Jun 11 03:21:26 PM PDT 24
Finished Jun 11 03:24:03 PM PDT 24
Peak memory 265364 kb
Host smart-93eada26-70aa-4452-ade3-f768f5c6b0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138708178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1138708178
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1594445351
Short name T466
Test name
Test status
Simulation time 7130546532 ps
CPU time 62.16 seconds
Started Jun 11 03:21:28 PM PDT 24
Finished Jun 11 03:22:33 PM PDT 24
Peak memory 240608 kb
Host smart-c8e95718-197f-440d-812d-2f7166fe22e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594445351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1594445351
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1799727967
Short name T756
Test name
Test status
Simulation time 132247729819 ps
CPU time 616.66 seconds
Started Jun 11 03:21:27 PM PDT 24
Finished Jun 11 03:31:47 PM PDT 24
Peak memory 249084 kb
Host smart-fa7a2af1-b15b-4897-bd0d-6474ad541c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799727967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1799727967
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1302234451
Short name T153
Test name
Test status
Simulation time 1139034588 ps
CPU time 11.85 seconds
Started Jun 11 03:21:28 PM PDT 24
Finished Jun 11 03:21:43 PM PDT 24
Peak memory 224296 kb
Host smart-7b0f5900-c8a8-4477-934c-6c8a3336705d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302234451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1302234451
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1691141669
Short name T773
Test name
Test status
Simulation time 1258200799 ps
CPU time 6.16 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:21:34 PM PDT 24
Peak memory 224308 kb
Host smart-d8113867-7bc0-472a-a1d5-681f5a9efb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691141669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1691141669
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1967773558
Short name T165
Test name
Test status
Simulation time 17045946279 ps
CPU time 29.87 seconds
Started Jun 11 03:21:24 PM PDT 24
Finished Jun 11 03:21:57 PM PDT 24
Peak memory 224412 kb
Host smart-c86549ae-9624-4f12-bc23-c43f52eab257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967773558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1967773558
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3856804782
Short name T672
Test name
Test status
Simulation time 96342223 ps
CPU time 1.03 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:21:29 PM PDT 24
Peak memory 217712 kb
Host smart-3a140578-ef20-425e-837d-5adcb173bd35
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856804782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3856804782
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2835961968
Short name T534
Test name
Test status
Simulation time 1155892219 ps
CPU time 8.96 seconds
Started Jun 11 03:21:28 PM PDT 24
Finished Jun 11 03:21:40 PM PDT 24
Peak memory 240532 kb
Host smart-41b8fd81-cd08-43a8-8cb1-e094aaaed379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835961968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2835961968
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.965713202
Short name T287
Test name
Test status
Simulation time 28577726765 ps
CPU time 40.84 seconds
Started Jun 11 03:21:28 PM PDT 24
Finished Jun 11 03:22:12 PM PDT 24
Peak memory 249432 kb
Host smart-c6c5e5e2-8b31-4245-a448-b362a596c5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965713202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.965713202
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.832834632
Short name T74
Test name
Test status
Simulation time 339557809 ps
CPU time 1.18 seconds
Started Jun 11 03:21:28 PM PDT 24
Finished Jun 11 03:21:33 PM PDT 24
Peak memory 235428 kb
Host smart-e534a914-65f2-4411-9c43-3e844b7b17db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832834632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.832834632
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3000579794
Short name T256
Test name
Test status
Simulation time 12536754416 ps
CPU time 39.83 seconds
Started Jun 11 03:21:29 PM PDT 24
Finished Jun 11 03:22:12 PM PDT 24
Peak memory 232684 kb
Host smart-d438455e-c392-4338-a280-b626ee271ad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000579794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3000579794
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.4037609455
Short name T41
Test name
Test status
Simulation time 2010807319 ps
CPU time 24.07 seconds
Started Jun 11 03:21:23 PM PDT 24
Finished Jun 11 03:21:50 PM PDT 24
Peak memory 216012 kb
Host smart-bea37a6b-55f8-48c8-9963-1b696c30acb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037609455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.4037609455
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1484809956
Short name T800
Test name
Test status
Simulation time 663943622 ps
CPU time 4.61 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:21:33 PM PDT 24
Peak memory 215976 kb
Host smart-3203606f-de06-4747-a25d-24ea3c67ea98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484809956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1484809956
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1344909693
Short name T682
Test name
Test status
Simulation time 108157586 ps
CPU time 0.9 seconds
Started Jun 11 03:21:27 PM PDT 24
Finished Jun 11 03:21:31 PM PDT 24
Peak memory 207032 kb
Host smart-d144ad7e-1f1c-46bb-81aa-54bcb0af8642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344909693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1344909693
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.62169686
Short name T530
Test name
Test status
Simulation time 20667311 ps
CPU time 0.79 seconds
Started Jun 11 03:21:24 PM PDT 24
Finished Jun 11 03:21:28 PM PDT 24
Peak memory 205680 kb
Host smart-f9635b33-3ca9-4abc-a0ff-ed6d850aa271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62169686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.62169686
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1522525353
Short name T788
Test name
Test status
Simulation time 833805126 ps
CPU time 3.3 seconds
Started Jun 11 03:21:24 PM PDT 24
Finished Jun 11 03:21:30 PM PDT 24
Peak memory 232496 kb
Host smart-65408c00-eaf4-4818-83d1-70e0a09ae165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522525353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1522525353
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3592379325
Short name T863
Test name
Test status
Simulation time 19274494 ps
CPU time 0.74 seconds
Started Jun 11 03:22:01 PM PDT 24
Finished Jun 11 03:22:04 PM PDT 24
Peak memory 205624 kb
Host smart-ead3afd7-5c28-4be6-9230-698bc4810a8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592379325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3592379325
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2332562123
Short name T561
Test name
Test status
Simulation time 96650572 ps
CPU time 2.47 seconds
Started Jun 11 03:21:59 PM PDT 24
Finished Jun 11 03:22:03 PM PDT 24
Peak memory 232460 kb
Host smart-08657976-b409-4386-8e74-ae1e5db7e9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332562123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2332562123
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2737141079
Short name T855
Test name
Test status
Simulation time 18647626 ps
CPU time 0.8 seconds
Started Jun 11 03:22:01 PM PDT 24
Finished Jun 11 03:22:04 PM PDT 24
Peak memory 205368 kb
Host smart-dd294b31-80fc-4efa-aa52-3144d6529157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737141079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2737141079
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.682354081
Short name T463
Test name
Test status
Simulation time 23485527990 ps
CPU time 54.92 seconds
Started Jun 11 03:22:01 PM PDT 24
Finished Jun 11 03:22:58 PM PDT 24
Peak memory 232700 kb
Host smart-0b0e3f9c-d2a6-43e8-98e0-37d26d587ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682354081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.682354081
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.790519908
Short name T837
Test name
Test status
Simulation time 494185778404 ps
CPU time 259.56 seconds
Started Jun 11 03:22:03 PM PDT 24
Finished Jun 11 03:26:24 PM PDT 24
Peak memory 249116 kb
Host smart-f213ee84-568e-473e-ae6b-baec185ff659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790519908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.790519908
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3642503983
Short name T361
Test name
Test status
Simulation time 69159386 ps
CPU time 2.76 seconds
Started Jun 11 03:21:59 PM PDT 24
Finished Jun 11 03:22:04 PM PDT 24
Peak memory 232528 kb
Host smart-47c84e8d-de38-483e-9c60-0e9333fd6d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642503983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3642503983
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1637739892
Short name T500
Test name
Test status
Simulation time 2122026875 ps
CPU time 9.64 seconds
Started Jun 11 03:22:01 PM PDT 24
Finished Jun 11 03:22:13 PM PDT 24
Peak memory 232500 kb
Host smart-a8d90153-b765-4737-b5d7-3bddaaa9033b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637739892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1637739892
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3567220692
Short name T385
Test name
Test status
Simulation time 19100563820 ps
CPU time 40.38 seconds
Started Jun 11 03:22:03 PM PDT 24
Finished Jun 11 03:22:45 PM PDT 24
Peak memory 240600 kb
Host smart-134d0731-75f3-435b-a2ef-653bbd52e304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567220692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3567220692
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3689815443
Short name T853
Test name
Test status
Simulation time 14687193 ps
CPU time 1.05 seconds
Started Jun 11 03:22:00 PM PDT 24
Finished Jun 11 03:22:03 PM PDT 24
Peak memory 217708 kb
Host smart-dc92e446-f40a-4e69-86ef-602d327e65fe
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689815443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3689815443
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.738787679
Short name T279
Test name
Test status
Simulation time 8671323163 ps
CPU time 7.24 seconds
Started Jun 11 03:22:01 PM PDT 24
Finished Jun 11 03:22:10 PM PDT 24
Peak memory 232624 kb
Host smart-9a6c9851-7a45-4070-b495-ae315567dd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738787679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.738787679
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2578671019
Short name T422
Test name
Test status
Simulation time 2842459320 ps
CPU time 12.54 seconds
Started Jun 11 03:21:59 PM PDT 24
Finished Jun 11 03:22:13 PM PDT 24
Peak memory 219192 kb
Host smart-9e86cdf1-a6bd-4b14-85a3-dbe61743395a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2578671019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2578671019
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2596061228
Short name T951
Test name
Test status
Simulation time 11747498455 ps
CPU time 65.12 seconds
Started Jun 11 03:22:03 PM PDT 24
Finished Jun 11 03:23:10 PM PDT 24
Peak memory 249084 kb
Host smart-8848900d-f58a-4811-b318-3a9109012189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596061228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2596061228
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1904114146
Short name T485
Test name
Test status
Simulation time 78195923353 ps
CPU time 25.08 seconds
Started Jun 11 03:22:01 PM PDT 24
Finished Jun 11 03:22:28 PM PDT 24
Peak memory 216156 kb
Host smart-e53a6ea5-240a-4827-bcfd-c1231ac265cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904114146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1904114146
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3543843081
Short name T966
Test name
Test status
Simulation time 2663759704 ps
CPU time 6.06 seconds
Started Jun 11 03:22:00 PM PDT 24
Finished Jun 11 03:22:09 PM PDT 24
Peak memory 216144 kb
Host smart-0038547e-006f-471e-ab33-8893d236011c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543843081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3543843081
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3253483253
Short name T23
Test name
Test status
Simulation time 220905801 ps
CPU time 3.35 seconds
Started Jun 11 03:22:01 PM PDT 24
Finished Jun 11 03:22:07 PM PDT 24
Peak memory 216020 kb
Host smart-99d8e2ec-073b-4030-9861-aa28d1c17f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253483253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3253483253
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.953974130
Short name T743
Test name
Test status
Simulation time 17683546 ps
CPU time 0.72 seconds
Started Jun 11 03:22:04 PM PDT 24
Finished Jun 11 03:22:06 PM PDT 24
Peak memory 205684 kb
Host smart-901bc2a4-93de-4165-931a-70c6ebf42aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953974130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.953974130
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2971475745
Short name T553
Test name
Test status
Simulation time 1113168588 ps
CPU time 4.52 seconds
Started Jun 11 03:21:59 PM PDT 24
Finished Jun 11 03:22:06 PM PDT 24
Peak memory 224356 kb
Host smart-1a7442a6-6533-47d8-88b1-3fad5961816b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971475745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2971475745
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3007734326
Short name T956
Test name
Test status
Simulation time 32178355 ps
CPU time 0.72 seconds
Started Jun 11 03:22:08 PM PDT 24
Finished Jun 11 03:22:10 PM PDT 24
Peak memory 204708 kb
Host smart-21e762db-bf0e-4ab9-a981-1679617fca25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007734326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3007734326
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1280072767
Short name T90
Test name
Test status
Simulation time 8831719294 ps
CPU time 15.29 seconds
Started Jun 11 03:22:04 PM PDT 24
Finished Jun 11 03:22:21 PM PDT 24
Peak memory 224396 kb
Host smart-242e3557-426e-4da6-bc53-9211ae2db974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280072767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1280072767
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2316813852
Short name T748
Test name
Test status
Simulation time 43589502 ps
CPU time 0.79 seconds
Started Jun 11 03:22:00 PM PDT 24
Finished Jun 11 03:22:02 PM PDT 24
Peak memory 206552 kb
Host smart-7837f6e4-2c85-45a1-a8a7-d9f1eb84f11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316813852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2316813852
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3589105657
Short name T77
Test name
Test status
Simulation time 249281695 ps
CPU time 0.81 seconds
Started Jun 11 03:21:59 PM PDT 24
Finished Jun 11 03:22:02 PM PDT 24
Peak memory 215956 kb
Host smart-7053838c-5805-4361-82c2-48484f31b978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589105657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3589105657
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1336689244
Short name T140
Test name
Test status
Simulation time 46315054801 ps
CPU time 304.53 seconds
Started Jun 11 03:22:01 PM PDT 24
Finished Jun 11 03:27:08 PM PDT 24
Peak memory 257288 kb
Host smart-4c214c0b-0463-468a-a3c7-95e060b0fa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336689244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1336689244
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2370444605
Short name T201
Test name
Test status
Simulation time 231301966214 ps
CPU time 385.17 seconds
Started Jun 11 03:21:57 PM PDT 24
Finished Jun 11 03:28:24 PM PDT 24
Peak memory 252308 kb
Host smart-0ae18b58-7f7c-42fb-84b6-50bb15b0ee94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370444605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2370444605
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1568490557
Short name T894
Test name
Test status
Simulation time 11002471590 ps
CPU time 21.14 seconds
Started Jun 11 03:21:58 PM PDT 24
Finished Jun 11 03:22:21 PM PDT 24
Peak memory 232656 kb
Host smart-e29f7a78-2c70-49e6-bf21-db20542c1f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568490557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1568490557
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2680261362
Short name T817
Test name
Test status
Simulation time 8637985856 ps
CPU time 25.48 seconds
Started Jun 11 03:22:00 PM PDT 24
Finished Jun 11 03:22:28 PM PDT 24
Peak memory 232612 kb
Host smart-c1d09782-e865-496b-944f-bb2f019e6390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680261362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2680261362
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.408518764
Short name T383
Test name
Test status
Simulation time 29249134748 ps
CPU time 115.42 seconds
Started Jun 11 03:22:00 PM PDT 24
Finished Jun 11 03:23:58 PM PDT 24
Peak memory 248408 kb
Host smart-af08c946-b7ce-4713-a531-da89fea043b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408518764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.408518764
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3437971278
Short name T771
Test name
Test status
Simulation time 51786253 ps
CPU time 1.07 seconds
Started Jun 11 03:22:00 PM PDT 24
Finished Jun 11 03:22:03 PM PDT 24
Peak memory 216496 kb
Host smart-5054fea1-516c-4d88-8a09-c6f36246d2d7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437971278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3437971278
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2390786539
Short name T411
Test name
Test status
Simulation time 168962231 ps
CPU time 2.6 seconds
Started Jun 11 03:21:58 PM PDT 24
Finished Jun 11 03:22:02 PM PDT 24
Peak memory 224308 kb
Host smart-8fac2390-b27d-448a-93ae-36bf84ae04a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390786539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2390786539
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2776367723
Short name T527
Test name
Test status
Simulation time 1257533605 ps
CPU time 4.48 seconds
Started Jun 11 03:21:59 PM PDT 24
Finished Jun 11 03:22:06 PM PDT 24
Peak memory 224268 kb
Host smart-c890e1c9-e417-43d2-b8d0-a112a80a7e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776367723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2776367723
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3837557424
Short name T367
Test name
Test status
Simulation time 4493223639 ps
CPU time 14.67 seconds
Started Jun 11 03:21:57 PM PDT 24
Finished Jun 11 03:22:14 PM PDT 24
Peak memory 222920 kb
Host smart-50d90408-923a-4f85-bbd8-a208c60e278e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3837557424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3837557424
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.792714167
Short name T312
Test name
Test status
Simulation time 32795788057 ps
CPU time 72.8 seconds
Started Jun 11 03:22:08 PM PDT 24
Finished Jun 11 03:23:22 PM PDT 24
Peak memory 251036 kb
Host smart-43399de5-2642-49bd-bf61-6f4ea1f5d00d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792714167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.792714167
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1952474287
Short name T570
Test name
Test status
Simulation time 25422465727 ps
CPU time 29.38 seconds
Started Jun 11 03:22:02 PM PDT 24
Finished Jun 11 03:22:33 PM PDT 24
Peak memory 216380 kb
Host smart-35b58ad8-ceb4-4bcd-a69f-e5d9079ac04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952474287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1952474287
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1388861775
Short name T708
Test name
Test status
Simulation time 28466985 ps
CPU time 0.72 seconds
Started Jun 11 03:21:59 PM PDT 24
Finished Jun 11 03:22:02 PM PDT 24
Peak memory 205480 kb
Host smart-952535e8-74c8-4756-8cec-f74089b2ede8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388861775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1388861775
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3295183335
Short name T584
Test name
Test status
Simulation time 134686449 ps
CPU time 2.55 seconds
Started Jun 11 03:21:57 PM PDT 24
Finished Jun 11 03:22:01 PM PDT 24
Peak memory 216100 kb
Host smart-fbe156bb-bf04-45f1-94b4-065cdb11a89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295183335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3295183335
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3391731483
Short name T772
Test name
Test status
Simulation time 33267297 ps
CPU time 0.77 seconds
Started Jun 11 03:21:57 PM PDT 24
Finished Jun 11 03:22:00 PM PDT 24
Peak memory 205688 kb
Host smart-984e9332-0678-40fb-9543-42f56ae35caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391731483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3391731483
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.874468178
Short name T526
Test name
Test status
Simulation time 18260326120 ps
CPU time 16.75 seconds
Started Jun 11 03:21:58 PM PDT 24
Finished Jun 11 03:22:17 PM PDT 24
Peak memory 224640 kb
Host smart-51d192ae-0e2f-469f-8875-5657ac6fc213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874468178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.874468178
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2569133164
Short name T704
Test name
Test status
Simulation time 1468493880 ps
CPU time 8.82 seconds
Started Jun 11 03:22:06 PM PDT 24
Finished Jun 11 03:22:17 PM PDT 24
Peak memory 232500 kb
Host smart-3fbbacb3-8980-4674-8f82-35b36088472e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569133164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2569133164
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2784458700
Short name T900
Test name
Test status
Simulation time 25606477 ps
CPU time 0.82 seconds
Started Jun 11 03:22:06 PM PDT 24
Finished Jun 11 03:22:07 PM PDT 24
Peak memory 206388 kb
Host smart-fa5177cd-d6a1-4b3a-98b2-426acefc810a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784458700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2784458700
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1234726609
Short name T49
Test name
Test status
Simulation time 5574423996 ps
CPU time 29.11 seconds
Started Jun 11 03:22:08 PM PDT 24
Finished Jun 11 03:22:39 PM PDT 24
Peak memory 240560 kb
Host smart-e6419148-d74a-44a5-855a-a6457210ae48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234726609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1234726609
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3455990531
Short name T60
Test name
Test status
Simulation time 684457092069 ps
CPU time 410.44 seconds
Started Jun 11 03:22:09 PM PDT 24
Finished Jun 11 03:29:01 PM PDT 24
Peak memory 257268 kb
Host smart-2c6d2ee7-1544-41fb-9515-8ce7f91ca05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455990531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3455990531
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.683680098
Short name T221
Test name
Test status
Simulation time 64248790370 ps
CPU time 617.74 seconds
Started Jun 11 03:22:07 PM PDT 24
Finished Jun 11 03:32:26 PM PDT 24
Peak memory 256584 kb
Host smart-57ead93c-2b1e-4315-9444-5e79e687a548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683680098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.683680098
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1372622156
Short name T575
Test name
Test status
Simulation time 13952620843 ps
CPU time 31.21 seconds
Started Jun 11 03:22:07 PM PDT 24
Finished Jun 11 03:22:40 PM PDT 24
Peak memory 231948 kb
Host smart-e0d89de5-0d92-49ba-9dfc-7676da8b998f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372622156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1372622156
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.629337779
Short name T644
Test name
Test status
Simulation time 341974977 ps
CPU time 6.18 seconds
Started Jun 11 03:22:06 PM PDT 24
Finished Jun 11 03:22:13 PM PDT 24
Peak memory 224248 kb
Host smart-4b41a8ec-6ecb-4a66-86b7-c4bf72f965c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629337779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.629337779
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1134903453
Short name T650
Test name
Test status
Simulation time 1739294609 ps
CPU time 11.47 seconds
Started Jun 11 03:22:06 PM PDT 24
Finished Jun 11 03:22:18 PM PDT 24
Peak memory 224296 kb
Host smart-131d7dcf-bb46-4b8e-b291-91199c7c2f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134903453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1134903453
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3550281559
Short name T891
Test name
Test status
Simulation time 181296381 ps
CPU time 1.01 seconds
Started Jun 11 03:22:08 PM PDT 24
Finished Jun 11 03:22:10 PM PDT 24
Peak memory 216488 kb
Host smart-8e10a6b2-9d9c-4a92-a8c9-919f874f5fca
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550281559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3550281559
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1370536453
Short name T203
Test name
Test status
Simulation time 13481714056 ps
CPU time 12.71 seconds
Started Jun 11 03:22:06 PM PDT 24
Finished Jun 11 03:22:20 PM PDT 24
Peak memory 232664 kb
Host smart-f96d1b89-1ebd-4e0d-81ac-3d14438487b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370536453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1370536453
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2577302975
Short name T706
Test name
Test status
Simulation time 4600757492 ps
CPU time 14.1 seconds
Started Jun 11 03:22:08 PM PDT 24
Finished Jun 11 03:22:24 PM PDT 24
Peak memory 232496 kb
Host smart-00528a5a-9948-4961-9801-5be9594118c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577302975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2577302975
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2481140949
Short name T488
Test name
Test status
Simulation time 749045248 ps
CPU time 3.81 seconds
Started Jun 11 03:22:07 PM PDT 24
Finished Jun 11 03:22:12 PM PDT 24
Peak memory 220208 kb
Host smart-27e65637-7978-4b36-8835-b410f148b9a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2481140949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2481140949
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2486184469
Short name T161
Test name
Test status
Simulation time 36641340147 ps
CPU time 337.59 seconds
Started Jun 11 03:22:07 PM PDT 24
Finished Jun 11 03:27:46 PM PDT 24
Peak memory 266728 kb
Host smart-ba477b72-583d-4765-a71a-e42816ef285f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486184469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2486184469
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1742218299
Short name T525
Test name
Test status
Simulation time 11363688533 ps
CPU time 16.59 seconds
Started Jun 11 03:22:08 PM PDT 24
Finished Jun 11 03:22:26 PM PDT 24
Peak memory 216180 kb
Host smart-f4005185-e94b-40ff-b968-8b4a0a8e46ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742218299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1742218299
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.373842794
Short name T884
Test name
Test status
Simulation time 4304745520 ps
CPU time 4.2 seconds
Started Jun 11 03:22:07 PM PDT 24
Finished Jun 11 03:22:13 PM PDT 24
Peak memory 216184 kb
Host smart-913f27b7-b004-4143-9a91-294b09620844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373842794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.373842794
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2734292185
Short name T619
Test name
Test status
Simulation time 193567985 ps
CPU time 1.26 seconds
Started Jun 11 03:22:08 PM PDT 24
Finished Jun 11 03:22:11 PM PDT 24
Peak memory 215952 kb
Host smart-d7698ae7-9e0e-4b52-b225-1b99b8578827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734292185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2734292185
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.877312328
Short name T893
Test name
Test status
Simulation time 38648171 ps
CPU time 0.81 seconds
Started Jun 11 03:22:07 PM PDT 24
Finished Jun 11 03:22:09 PM PDT 24
Peak memory 205676 kb
Host smart-50bdda2b-253c-4bc7-bc1b-5eabf6a938a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877312328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.877312328
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1325043420
Short name T236
Test name
Test status
Simulation time 594518954 ps
CPU time 6.64 seconds
Started Jun 11 03:22:08 PM PDT 24
Finished Jun 11 03:22:16 PM PDT 24
Peak memory 232500 kb
Host smart-c9897c9d-82bf-4dcc-9a4d-59c23b9cb08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325043420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1325043420
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3284085176
Short name T427
Test name
Test status
Simulation time 23798402 ps
CPU time 0.77 seconds
Started Jun 11 03:22:19 PM PDT 24
Finished Jun 11 03:22:22 PM PDT 24
Peak memory 205300 kb
Host smart-cb8e2a92-4ae8-4dd4-a40d-db4946dfe043
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284085176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3284085176
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1131980639
Short name T380
Test name
Test status
Simulation time 265924551 ps
CPU time 2.55 seconds
Started Jun 11 03:22:13 PM PDT 24
Finished Jun 11 03:22:17 PM PDT 24
Peak memory 232260 kb
Host smart-5a0b7166-5724-4b87-98bb-d824bf891964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131980639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1131980639
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3799802779
Short name T766
Test name
Test status
Simulation time 30513459 ps
CPU time 0.8 seconds
Started Jun 11 03:22:06 PM PDT 24
Finished Jun 11 03:22:08 PM PDT 24
Peak memory 206372 kb
Host smart-a5188b0d-0228-440d-9fad-a5909ba3b9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799802779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3799802779
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2649115325
Short name T546
Test name
Test status
Simulation time 6179148540 ps
CPU time 35.51 seconds
Started Jun 11 03:22:13 PM PDT 24
Finished Jun 11 03:22:50 PM PDT 24
Peak memory 249100 kb
Host smart-393021db-8c0e-4947-a1ee-d2d3d619a537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649115325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2649115325
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3431139858
Short name T629
Test name
Test status
Simulation time 18344957167 ps
CPU time 101.72 seconds
Started Jun 11 03:22:18 PM PDT 24
Finished Jun 11 03:24:02 PM PDT 24
Peak memory 249812 kb
Host smart-5165128a-21da-428a-8fe2-c01659cbc9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431139858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3431139858
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2511035130
Short name T250
Test name
Test status
Simulation time 99321597320 ps
CPU time 271.03 seconds
Started Jun 11 03:22:14 PM PDT 24
Finished Jun 11 03:26:46 PM PDT 24
Peak memory 256748 kb
Host smart-37d981c0-504e-4aa3-8de0-dafe4fca53a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511035130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2511035130
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.685666895
Short name T598
Test name
Test status
Simulation time 403942780 ps
CPU time 4.4 seconds
Started Jun 11 03:22:19 PM PDT 24
Finished Jun 11 03:22:26 PM PDT 24
Peak memory 224332 kb
Host smart-d290a401-f116-4a58-9a81-056e677e8e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685666895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.685666895
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.246560802
Short name T166
Test name
Test status
Simulation time 621476786 ps
CPU time 7.81 seconds
Started Jun 11 03:22:06 PM PDT 24
Finished Jun 11 03:22:15 PM PDT 24
Peak memory 232460 kb
Host smart-d738ad37-cb7b-4169-8a60-4d025c338ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246560802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.246560802
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2451039096
Short name T400
Test name
Test status
Simulation time 600597099 ps
CPU time 3.48 seconds
Started Jun 11 03:22:06 PM PDT 24
Finished Jun 11 03:22:11 PM PDT 24
Peak memory 224216 kb
Host smart-d63f69cd-b415-4420-b202-6d2fd05c88bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451039096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2451039096
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.4207322009
Short name T926
Test name
Test status
Simulation time 25976091 ps
CPU time 1.1 seconds
Started Jun 11 03:22:07 PM PDT 24
Finished Jun 11 03:22:10 PM PDT 24
Peak memory 216512 kb
Host smart-8db4d6fe-aa19-48eb-a1df-cb6d5d505d38
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207322009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.4207322009
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.986185410
Short name T133
Test name
Test status
Simulation time 117246003 ps
CPU time 2.56 seconds
Started Jun 11 03:22:06 PM PDT 24
Finished Jun 11 03:22:10 PM PDT 24
Peak memory 224280 kb
Host smart-95fd23b7-c16b-4430-b707-78ef3be5e48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986185410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.986185410
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3543122828
Short name T396
Test name
Test status
Simulation time 1529775829 ps
CPU time 10.38 seconds
Started Jun 11 03:22:06 PM PDT 24
Finished Jun 11 03:22:18 PM PDT 24
Peak memory 232504 kb
Host smart-568377e2-e5cd-469f-adef-fabc224f4044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543122828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3543122828
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1613807759
Short name T596
Test name
Test status
Simulation time 2659967318 ps
CPU time 9.18 seconds
Started Jun 11 03:22:21 PM PDT 24
Finished Jun 11 03:22:32 PM PDT 24
Peak memory 218828 kb
Host smart-5d94361f-bcac-48a3-9814-cdadcff94eea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1613807759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1613807759
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2525066234
Short name T885
Test name
Test status
Simulation time 13102068610 ps
CPU time 124.14 seconds
Started Jun 11 03:22:16 PM PDT 24
Finished Jun 11 03:24:22 PM PDT 24
Peak memory 257356 kb
Host smart-a90f7a55-b176-4a90-981c-89846f0a891c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525066234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2525066234
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1887057103
Short name T826
Test name
Test status
Simulation time 2299421883 ps
CPU time 18.13 seconds
Started Jun 11 03:22:09 PM PDT 24
Finished Jun 11 03:22:28 PM PDT 24
Peak memory 216160 kb
Host smart-6f152c45-501b-41a5-9443-1c77c0af1af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887057103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1887057103
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.436291741
Short name T769
Test name
Test status
Simulation time 115008012485 ps
CPU time 16.14 seconds
Started Jun 11 03:22:07 PM PDT 24
Finished Jun 11 03:22:25 PM PDT 24
Peak memory 216140 kb
Host smart-689e92c9-a922-4c80-9ee8-a73eac5a4393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436291741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.436291741
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2431142479
Short name T694
Test name
Test status
Simulation time 43714670 ps
CPU time 1.29 seconds
Started Jun 11 03:22:07 PM PDT 24
Finished Jun 11 03:22:11 PM PDT 24
Peak memory 207772 kb
Host smart-6f6ad800-4637-404c-add1-d46d57898e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431142479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2431142479
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1527270712
Short name T414
Test name
Test status
Simulation time 80197821 ps
CPU time 0.9 seconds
Started Jun 11 03:22:07 PM PDT 24
Finished Jun 11 03:22:09 PM PDT 24
Peak memory 205680 kb
Host smart-d8449f99-7dcd-4489-85f0-74845cadb872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527270712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1527270712
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3981125426
Short name T389
Test name
Test status
Simulation time 1545435562 ps
CPU time 7.49 seconds
Started Jun 11 03:22:19 PM PDT 24
Finished Jun 11 03:22:29 PM PDT 24
Peak memory 224320 kb
Host smart-13e9367f-609c-4ef1-bfb9-dfac03543d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981125426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3981125426
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.654942808
Short name T876
Test name
Test status
Simulation time 14094449 ps
CPU time 0.75 seconds
Started Jun 11 03:22:17 PM PDT 24
Finished Jun 11 03:22:20 PM PDT 24
Peak memory 205336 kb
Host smart-94b57cd2-2a27-478d-806d-8c4c0876838d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654942808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.654942808
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.565706348
Short name T802
Test name
Test status
Simulation time 193919506 ps
CPU time 2.55 seconds
Started Jun 11 03:22:15 PM PDT 24
Finished Jun 11 03:22:18 PM PDT 24
Peak memory 232456 kb
Host smart-79ff2880-f0c4-428d-a0c6-f377dfe5ff41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565706348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.565706348
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.842026869
Short name T961
Test name
Test status
Simulation time 44531984 ps
CPU time 0.74 seconds
Started Jun 11 03:22:14 PM PDT 24
Finished Jun 11 03:22:16 PM PDT 24
Peak memory 205312 kb
Host smart-e76cf0b8-2d7c-4c71-9672-3bc28308a468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842026869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.842026869
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2358483144
Short name T309
Test name
Test status
Simulation time 4248994794 ps
CPU time 90.78 seconds
Started Jun 11 03:22:16 PM PDT 24
Finished Jun 11 03:23:50 PM PDT 24
Peak memory 265424 kb
Host smart-839e16d3-6f34-4da0-a919-6ad644dd08ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358483144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2358483144
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3255999242
Short name T785
Test name
Test status
Simulation time 2427601358 ps
CPU time 24.57 seconds
Started Jun 11 03:22:18 PM PDT 24
Finished Jun 11 03:22:45 PM PDT 24
Peak memory 238088 kb
Host smart-60a97b69-9a6b-474d-965f-761036f475e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255999242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3255999242
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.729818738
Short name T79
Test name
Test status
Simulation time 3753687435 ps
CPU time 30.85 seconds
Started Jun 11 03:22:18 PM PDT 24
Finished Jun 11 03:22:51 PM PDT 24
Peak memory 234672 kb
Host smart-e18dabdf-34fa-4d2d-9f8b-f2b8e6df0d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729818738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.729818738
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3881650556
Short name T917
Test name
Test status
Simulation time 1472485798 ps
CPU time 15.42 seconds
Started Jun 11 03:22:19 PM PDT 24
Finished Jun 11 03:22:37 PM PDT 24
Peak memory 224488 kb
Host smart-f8f83736-b9f0-42d1-ac9e-1041c5e301dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881650556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3881650556
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2643884702
Short name T267
Test name
Test status
Simulation time 2159530911 ps
CPU time 13.87 seconds
Started Jun 11 03:22:16 PM PDT 24
Finished Jun 11 03:22:31 PM PDT 24
Peak memory 240352 kb
Host smart-65598707-e51d-4394-858b-8ebbeba5c90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643884702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2643884702
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1778185667
Short name T920
Test name
Test status
Simulation time 188661140 ps
CPU time 1.03 seconds
Started Jun 11 03:22:14 PM PDT 24
Finished Jun 11 03:22:17 PM PDT 24
Peak memory 216484 kb
Host smart-d211f3c3-3b92-43a4-9edf-5b554042a2e5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778185667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1778185667
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.487201953
Short name T820
Test name
Test status
Simulation time 10429867391 ps
CPU time 16.71 seconds
Started Jun 11 03:22:16 PM PDT 24
Finished Jun 11 03:22:34 PM PDT 24
Peak memory 232632 kb
Host smart-aa83e1e3-2f8f-4c59-8bf5-20031e9ea6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487201953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.487201953
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3198091252
Short name T275
Test name
Test status
Simulation time 6180731567 ps
CPU time 5.57 seconds
Started Jun 11 03:22:18 PM PDT 24
Finished Jun 11 03:22:26 PM PDT 24
Peak memory 232676 kb
Host smart-0b3c454c-c861-4da0-89c8-78c08586fc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198091252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3198091252
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.56120784
Short name T433
Test name
Test status
Simulation time 972018769 ps
CPU time 4.23 seconds
Started Jun 11 03:22:17 PM PDT 24
Finished Jun 11 03:22:23 PM PDT 24
Peak memory 220136 kb
Host smart-57e9c97b-4c1b-46fd-8705-2e57f66f2931
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=56120784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direc
t.56120784
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.610473006
Short name T436
Test name
Test status
Simulation time 28207389356 ps
CPU time 28.94 seconds
Started Jun 11 03:22:14 PM PDT 24
Finished Jun 11 03:22:44 PM PDT 24
Peak memory 216208 kb
Host smart-e4a5f559-2f52-4709-bdc1-4c1bc6596360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610473006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.610473006
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1349988323
Short name T368
Test name
Test status
Simulation time 882950356 ps
CPU time 2.47 seconds
Started Jun 11 03:22:14 PM PDT 24
Finished Jun 11 03:22:18 PM PDT 24
Peak memory 216024 kb
Host smart-63c42363-aa25-47d1-b712-af73639ee21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349988323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1349988323
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3437528067
Short name T470
Test name
Test status
Simulation time 327307367 ps
CPU time 6.98 seconds
Started Jun 11 03:22:14 PM PDT 24
Finished Jun 11 03:22:22 PM PDT 24
Peak memory 215964 kb
Host smart-a442a722-550b-4008-8a8f-e970fc485f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437528067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3437528067
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1491584699
Short name T714
Test name
Test status
Simulation time 150219002 ps
CPU time 1.02 seconds
Started Jun 11 03:22:18 PM PDT 24
Finished Jun 11 03:22:22 PM PDT 24
Peak memory 205708 kb
Host smart-41718378-f1fb-474e-bad5-fa1506d61de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491584699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1491584699
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1821952270
Short name T26
Test name
Test status
Simulation time 34108747 ps
CPU time 2.07 seconds
Started Jun 11 03:22:15 PM PDT 24
Finished Jun 11 03:22:18 PM PDT 24
Peak memory 222680 kb
Host smart-597cf49c-e323-4bd7-9ae8-2d2faeea84ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821952270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1821952270
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2839625642
Short name T503
Test name
Test status
Simulation time 26900467 ps
CPU time 0.69 seconds
Started Jun 11 03:22:18 PM PDT 24
Finished Jun 11 03:22:21 PM PDT 24
Peak memory 204764 kb
Host smart-d295da4d-0717-47e5-8d99-5a8b5c1686c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839625642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2839625642
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.825571688
Short name T661
Test name
Test status
Simulation time 590790221 ps
CPU time 10.29 seconds
Started Jun 11 03:22:19 PM PDT 24
Finished Jun 11 03:22:32 PM PDT 24
Peak memory 224180 kb
Host smart-dc06f0d8-6bb7-46cc-a1e2-3146b0630bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825571688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.825571688
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1530545170
Short name T604
Test name
Test status
Simulation time 16856517 ps
CPU time 0.78 seconds
Started Jun 11 03:22:16 PM PDT 24
Finished Jun 11 03:22:18 PM PDT 24
Peak memory 206684 kb
Host smart-169bc161-91a4-4cf9-ba59-afdb13667f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530545170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1530545170
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2991737721
Short name T739
Test name
Test status
Simulation time 6228050046 ps
CPU time 51.95 seconds
Started Jun 11 03:22:21 PM PDT 24
Finished Jun 11 03:23:16 PM PDT 24
Peak memory 240844 kb
Host smart-8618d09c-f560-40bf-af00-818491e5d856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991737721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2991737721
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2377418245
Short name T474
Test name
Test status
Simulation time 7366164545 ps
CPU time 54.05 seconds
Started Jun 11 03:22:19 PM PDT 24
Finished Jun 11 03:23:15 PM PDT 24
Peak memory 250136 kb
Host smart-59d0b347-2d64-4869-bb61-2a9e01b39e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377418245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2377418245
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2585831268
Short name T529
Test name
Test status
Simulation time 21959395199 ps
CPU time 33.52 seconds
Started Jun 11 03:22:21 PM PDT 24
Finished Jun 11 03:22:57 PM PDT 24
Peak memory 249112 kb
Host smart-6c8b8cef-659e-40a7-828d-7c6d5dea6da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585831268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2585831268
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3096560300
Short name T601
Test name
Test status
Simulation time 782396371 ps
CPU time 7.37 seconds
Started Jun 11 03:22:16 PM PDT 24
Finished Jun 11 03:22:25 PM PDT 24
Peak memory 240552 kb
Host smart-c7095c00-b723-4172-9af0-08310871f343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096560300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3096560300
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.522793107
Short name T637
Test name
Test status
Simulation time 704104004 ps
CPU time 10.96 seconds
Started Jun 11 03:22:18 PM PDT 24
Finished Jun 11 03:22:32 PM PDT 24
Peak memory 232528 kb
Host smart-8b764d78-8964-4c70-a713-4dc4ac62361f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522793107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.522793107
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.648087924
Short name T972
Test name
Test status
Simulation time 1333049552 ps
CPU time 15.59 seconds
Started Jun 11 03:22:20 PM PDT 24
Finished Jun 11 03:22:38 PM PDT 24
Peak memory 235792 kb
Host smart-210ec0c5-70b6-467c-9e65-e440d16c8483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648087924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.648087924
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3695459537
Short name T851
Test name
Test status
Simulation time 18315037 ps
CPU time 1.02 seconds
Started Jun 11 03:22:16 PM PDT 24
Finished Jun 11 03:22:19 PM PDT 24
Peak memory 216508 kb
Host smart-2e53b408-2413-43ee-97f3-6be4619caaf5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695459537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3695459537
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1906143618
Short name T277
Test name
Test status
Simulation time 13018791204 ps
CPU time 8.82 seconds
Started Jun 11 03:22:22 PM PDT 24
Finished Jun 11 03:22:34 PM PDT 24
Peak memory 218484 kb
Host smart-527cb8ce-b741-4bc6-9121-f90591bbe4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906143618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1906143618
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3326534102
Short name T482
Test name
Test status
Simulation time 3794927696 ps
CPU time 14.47 seconds
Started Jun 11 03:22:16 PM PDT 24
Finished Jun 11 03:22:32 PM PDT 24
Peak memory 240544 kb
Host smart-1d185093-1a76-4f58-9be1-efc6920763c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326534102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3326534102
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1707013079
Short name T555
Test name
Test status
Simulation time 553891738 ps
CPU time 7.97 seconds
Started Jun 11 03:22:15 PM PDT 24
Finished Jun 11 03:22:25 PM PDT 24
Peak memory 220236 kb
Host smart-cf1f061f-0168-4c7f-b2dc-c9a2b640aeb9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1707013079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1707013079
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1769605461
Short name T21
Test name
Test status
Simulation time 107522847 ps
CPU time 1.08 seconds
Started Jun 11 03:22:18 PM PDT 24
Finished Jun 11 03:22:22 PM PDT 24
Peak memory 206596 kb
Host smart-da44d99f-900c-4a41-a0da-340b33c0df27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769605461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1769605461
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.460795170
Short name T135
Test name
Test status
Simulation time 6659487199 ps
CPU time 6.37 seconds
Started Jun 11 03:22:14 PM PDT 24
Finished Jun 11 03:22:21 PM PDT 24
Peak memory 216140 kb
Host smart-7f561acd-4a90-4066-b548-c3e219af6228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460795170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.460795170
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.299881967
Short name T724
Test name
Test status
Simulation time 996886399 ps
CPU time 5.64 seconds
Started Jun 11 03:22:20 PM PDT 24
Finished Jun 11 03:22:28 PM PDT 24
Peak memory 215992 kb
Host smart-2327098c-46bb-4f92-bb08-688872cb7f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299881967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.299881967
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3282959334
Short name T3
Test name
Test status
Simulation time 46793119 ps
CPU time 0.76 seconds
Started Jun 11 03:22:19 PM PDT 24
Finished Jun 11 03:22:22 PM PDT 24
Peak memory 205916 kb
Host smart-e0ce78e5-4def-4260-b0fd-7d0c26bbed08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282959334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3282959334
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2806111952
Short name T538
Test name
Test status
Simulation time 55223481 ps
CPU time 0.8 seconds
Started Jun 11 03:22:15 PM PDT 24
Finished Jun 11 03:22:18 PM PDT 24
Peak memory 205700 kb
Host smart-5b962322-e66e-41f3-8ff8-ef397f66361d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806111952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2806111952
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.565454538
Short name T908
Test name
Test status
Simulation time 13539770707 ps
CPU time 39.36 seconds
Started Jun 11 03:22:20 PM PDT 24
Finished Jun 11 03:23:01 PM PDT 24
Peak memory 236964 kb
Host smart-37e97193-1cb1-456f-ae57-7e733a282fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565454538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.565454538
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.440870824
Short name T512
Test name
Test status
Simulation time 11292086 ps
CPU time 0.69 seconds
Started Jun 11 03:22:22 PM PDT 24
Finished Jun 11 03:22:25 PM PDT 24
Peak memory 205244 kb
Host smart-66ed70c6-8643-437a-b9d2-91544bf95ee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440870824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.440870824
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2088682120
Short name T344
Test name
Test status
Simulation time 7615144208 ps
CPU time 7.35 seconds
Started Jun 11 03:22:23 PM PDT 24
Finished Jun 11 03:22:33 PM PDT 24
Peak memory 232620 kb
Host smart-f6dc52a3-a8d3-4922-a192-17f48f1e11af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088682120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2088682120
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.837496145
Short name T579
Test name
Test status
Simulation time 33516459 ps
CPU time 0.75 seconds
Started Jun 11 03:22:23 PM PDT 24
Finished Jun 11 03:22:26 PM PDT 24
Peak memory 205324 kb
Host smart-60d0f186-da59-43b9-89e7-ab092e71b98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837496145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.837496145
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.691240089
Short name T806
Test name
Test status
Simulation time 234727257542 ps
CPU time 495.18 seconds
Started Jun 11 03:22:24 PM PDT 24
Finished Jun 11 03:30:42 PM PDT 24
Peak memory 264132 kb
Host smart-7b901601-dc13-4e77-9120-63a0a1959b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691240089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.691240089
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1940487957
Short name T178
Test name
Test status
Simulation time 287955742037 ps
CPU time 375.6 seconds
Started Jun 11 03:22:22 PM PDT 24
Finished Jun 11 03:28:40 PM PDT 24
Peak memory 269076 kb
Host smart-3821ee82-9d53-4fb2-b3a0-0e2ed2cf66dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940487957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1940487957
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.658541055
Short name T982
Test name
Test status
Simulation time 3914774634 ps
CPU time 34.09 seconds
Started Jun 11 03:22:24 PM PDT 24
Finished Jun 11 03:23:01 PM PDT 24
Peak memory 232600 kb
Host smart-354c4ab9-d0c9-41ee-acfa-e14b90f350f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658541055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.658541055
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3625040450
Short name T883
Test name
Test status
Simulation time 1679571804 ps
CPU time 5.55 seconds
Started Jun 11 03:22:24 PM PDT 24
Finished Jun 11 03:22:32 PM PDT 24
Peak memory 232416 kb
Host smart-6a38aa7a-de4c-492f-89ae-a708bff2d653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625040450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3625040450
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3551225762
Short name T364
Test name
Test status
Simulation time 467916259 ps
CPU time 10.87 seconds
Started Jun 11 03:22:23 PM PDT 24
Finished Jun 11 03:22:36 PM PDT 24
Peak memory 240524 kb
Host smart-70fea6d0-d20a-46f3-a81a-4e24e3adef0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551225762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3551225762
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.103934606
Short name T630
Test name
Test status
Simulation time 29696009 ps
CPU time 1.05 seconds
Started Jun 11 03:22:21 PM PDT 24
Finished Jun 11 03:22:25 PM PDT 24
Peak memory 216480 kb
Host smart-7e32f771-634d-413f-9a30-801bc4b87210
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103934606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.103934606
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3625808001
Short name T753
Test name
Test status
Simulation time 1679666461 ps
CPU time 8.58 seconds
Started Jun 11 03:22:23 PM PDT 24
Finished Jun 11 03:22:35 PM PDT 24
Peak memory 224272 kb
Host smart-2be627d8-fe6a-460c-84da-9c4a88843069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625808001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3625808001
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3814340717
Short name T285
Test name
Test status
Simulation time 1240765371 ps
CPU time 9.16 seconds
Started Jun 11 03:22:23 PM PDT 24
Finished Jun 11 03:22:35 PM PDT 24
Peak memory 232516 kb
Host smart-9b6eeea5-79dc-4b22-b634-a61830133d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814340717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3814340717
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.135586544
Short name T795
Test name
Test status
Simulation time 79471194 ps
CPU time 3.97 seconds
Started Jun 11 03:22:25 PM PDT 24
Finished Jun 11 03:22:32 PM PDT 24
Peak memory 220184 kb
Host smart-2f26e3fc-e33a-4a9c-90e2-1d1ae4ac7047
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=135586544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.135586544
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.96158449
Short name T159
Test name
Test status
Simulation time 128563468375 ps
CPU time 323.81 seconds
Started Jun 11 03:22:22 PM PDT 24
Finished Jun 11 03:27:48 PM PDT 24
Peak memory 252428 kb
Host smart-e7eb950e-c93b-460c-a7fd-690f06b8fc11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96158449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress
_all.96158449
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1171096770
Short name T332
Test name
Test status
Simulation time 2747434058 ps
CPU time 18.76 seconds
Started Jun 11 03:22:22 PM PDT 24
Finished Jun 11 03:22:43 PM PDT 24
Peak memory 216184 kb
Host smart-45d44142-ac1b-4cbc-b846-733facbbb47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171096770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1171096770
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1318208615
Short name T828
Test name
Test status
Simulation time 4348347014 ps
CPU time 6.51 seconds
Started Jun 11 03:22:26 PM PDT 24
Finished Jun 11 03:22:35 PM PDT 24
Peak memory 216128 kb
Host smart-f802fe68-d81c-4f65-b34c-f855d44d67d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318208615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1318208615
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1748852512
Short name T168
Test name
Test status
Simulation time 64062884 ps
CPU time 1.07 seconds
Started Jun 11 03:22:25 PM PDT 24
Finished Jun 11 03:22:28 PM PDT 24
Peak memory 207360 kb
Host smart-922a64d3-ed91-4f39-b16f-8197dd7c3f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748852512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1748852512
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.87880584
Short name T455
Test name
Test status
Simulation time 15724829 ps
CPU time 0.69 seconds
Started Jun 11 03:22:21 PM PDT 24
Finished Jun 11 03:22:24 PM PDT 24
Peak memory 205416 kb
Host smart-66ae3413-997d-4b50-911b-b199546a51bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87880584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.87880584
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2855482153
Short name T237
Test name
Test status
Simulation time 5950279582 ps
CPU time 9.31 seconds
Started Jun 11 03:22:22 PM PDT 24
Finished Jun 11 03:22:34 PM PDT 24
Peak memory 232620 kb
Host smart-03a7bf89-45c5-4abc-8a04-28c8b8a91c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855482153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2855482153
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1164720614
Short name T384
Test name
Test status
Simulation time 110378992 ps
CPU time 0.69 seconds
Started Jun 11 03:22:33 PM PDT 24
Finished Jun 11 03:22:36 PM PDT 24
Peak memory 204748 kb
Host smart-d9c30c6b-ba2c-4f7c-9e67-349ea94e137d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164720614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1164720614
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3913452940
Short name T872
Test name
Test status
Simulation time 630869711 ps
CPU time 2.29 seconds
Started Jun 11 03:22:24 PM PDT 24
Finished Jun 11 03:22:29 PM PDT 24
Peak memory 223012 kb
Host smart-1be47087-2ebb-48c9-9ae8-8f9db702d30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913452940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3913452940
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3090742771
Short name T552
Test name
Test status
Simulation time 20775349 ps
CPU time 0.78 seconds
Started Jun 11 03:22:25 PM PDT 24
Finished Jun 11 03:22:29 PM PDT 24
Peak memory 205664 kb
Host smart-9a719f16-6a4d-41ef-b654-3dce89c07414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090742771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3090742771
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2112847744
Short name T889
Test name
Test status
Simulation time 7754804656 ps
CPU time 60.24 seconds
Started Jun 11 03:22:36 PM PDT 24
Finished Jun 11 03:23:38 PM PDT 24
Peak memory 249068 kb
Host smart-3e88ea7a-c221-4ca0-8ae6-224fd735a9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112847744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2112847744
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2130860863
Short name T862
Test name
Test status
Simulation time 102379334522 ps
CPU time 308.77 seconds
Started Jun 11 03:22:32 PM PDT 24
Finished Jun 11 03:27:43 PM PDT 24
Peak memory 250144 kb
Host smart-9bff9ebe-b9d3-446f-acd3-f93786b7ee82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130860863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2130860863
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.4041900272
Short name T191
Test name
Test status
Simulation time 1248532256 ps
CPU time 32.43 seconds
Started Jun 11 03:22:31 PM PDT 24
Finished Jun 11 03:23:06 PM PDT 24
Peak memory 240892 kb
Host smart-06c9d823-03cc-4249-b4cf-5fe5a7c7c0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041900272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.4041900272
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1926594648
Short name T324
Test name
Test status
Simulation time 460724631 ps
CPU time 5.74 seconds
Started Jun 11 03:22:31 PM PDT 24
Finished Jun 11 03:22:38 PM PDT 24
Peak memory 232512 kb
Host smart-c42886f1-fc13-4c24-9031-d80f6b21ac94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926594648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1926594648
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2489453167
Short name T846
Test name
Test status
Simulation time 652414034 ps
CPU time 3.39 seconds
Started Jun 11 03:22:23 PM PDT 24
Finished Jun 11 03:22:29 PM PDT 24
Peak memory 232516 kb
Host smart-fed26dc7-1049-4649-88dc-644b4263c26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489453167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2489453167
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.4077286204
Short name T442
Test name
Test status
Simulation time 139553644 ps
CPU time 4.97 seconds
Started Jun 11 03:22:22 PM PDT 24
Finished Jun 11 03:22:30 PM PDT 24
Peak memory 232560 kb
Host smart-2205dc0e-b1b9-41e3-9f7c-a815a526fa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077286204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.4077286204
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.144830147
Short name T703
Test name
Test status
Simulation time 15029008 ps
CPU time 1.07 seconds
Started Jun 11 03:22:27 PM PDT 24
Finished Jun 11 03:22:30 PM PDT 24
Peak memory 217704 kb
Host smart-fa7ea435-81d7-46d7-a966-d4267056ddfc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144830147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.144830147
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1008281437
Short name T391
Test name
Test status
Simulation time 122007772 ps
CPU time 3.34 seconds
Started Jun 11 03:22:24 PM PDT 24
Finished Jun 11 03:22:30 PM PDT 24
Peak memory 224316 kb
Host smart-d91cc7bb-0fd8-4cc8-8d40-5c556a08f483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008281437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1008281437
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2324118428
Short name T948
Test name
Test status
Simulation time 1341850580 ps
CPU time 6.02 seconds
Started Jun 11 03:22:22 PM PDT 24
Finished Jun 11 03:22:31 PM PDT 24
Peak memory 238044 kb
Host smart-bbe12f96-31cd-4b8f-a31e-5dada0887067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324118428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2324118428
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1988182341
Short name T633
Test name
Test status
Simulation time 101989493 ps
CPU time 3.98 seconds
Started Jun 11 03:22:35 PM PDT 24
Finished Jun 11 03:22:41 PM PDT 24
Peak memory 222688 kb
Host smart-13f620b8-6d65-4e00-bd80-f884ac5fd9b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1988182341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1988182341
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1208895317
Short name T638
Test name
Test status
Simulation time 5222217341 ps
CPU time 33.4 seconds
Started Jun 11 03:22:27 PM PDT 24
Finished Jun 11 03:23:02 PM PDT 24
Peak memory 216148 kb
Host smart-351e3a31-3802-4804-a373-8ed10ce4f744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208895317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1208895317
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.847987187
Short name T497
Test name
Test status
Simulation time 143245863 ps
CPU time 1.33 seconds
Started Jun 11 03:22:21 PM PDT 24
Finished Jun 11 03:22:25 PM PDT 24
Peak memory 215948 kb
Host smart-56e6c845-708d-453b-a1a9-6296e9998ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847987187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.847987187
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.566152663
Short name T866
Test name
Test status
Simulation time 29477980 ps
CPU time 0.72 seconds
Started Jun 11 03:22:24 PM PDT 24
Finished Jun 11 03:22:28 PM PDT 24
Peak memory 205620 kb
Host smart-33873673-0aff-4c65-9dea-765ba9d17093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566152663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.566152663
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.4145195193
Short name T610
Test name
Test status
Simulation time 380953775 ps
CPU time 3.55 seconds
Started Jun 11 03:22:24 PM PDT 24
Finished Jun 11 03:22:31 PM PDT 24
Peak memory 224336 kb
Host smart-f90a7594-d760-45af-9a5b-735a4040c95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145195193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.4145195193
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3051657336
Short name T430
Test name
Test status
Simulation time 36611711 ps
CPU time 0.72 seconds
Started Jun 11 03:22:33 PM PDT 24
Finished Jun 11 03:22:36 PM PDT 24
Peak memory 205292 kb
Host smart-5e9a1b69-6d57-4a2f-b1a6-4e22e103680c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051657336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3051657336
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.626800076
Short name T945
Test name
Test status
Simulation time 662523510 ps
CPU time 5.29 seconds
Started Jun 11 03:22:32 PM PDT 24
Finished Jun 11 03:22:40 PM PDT 24
Peak memory 224316 kb
Host smart-663282f5-322f-4552-8be5-d31ba52445b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626800076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.626800076
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.808538085
Short name T346
Test name
Test status
Simulation time 52540135 ps
CPU time 0.78 seconds
Started Jun 11 03:22:33 PM PDT 24
Finished Jun 11 03:22:36 PM PDT 24
Peak memory 205356 kb
Host smart-90cd3b0f-e9f3-4346-bbdc-6e939f175a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808538085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.808538085
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2203122348
Short name T767
Test name
Test status
Simulation time 28472757102 ps
CPU time 76.98 seconds
Started Jun 11 03:22:33 PM PDT 24
Finished Jun 11 03:23:53 PM PDT 24
Peak memory 240008 kb
Host smart-68e1b383-322e-4ac5-92fe-555d17728dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203122348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2203122348
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2535051575
Short name T460
Test name
Test status
Simulation time 23534922658 ps
CPU time 202.34 seconds
Started Jun 11 03:22:30 PM PDT 24
Finished Jun 11 03:25:54 PM PDT 24
Peak memory 253712 kb
Host smart-eb8f8c9b-31a6-466e-9022-9e8f375bd265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535051575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2535051575
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2002186571
Short name T292
Test name
Test status
Simulation time 163870623 ps
CPU time 4.13 seconds
Started Jun 11 03:22:32 PM PDT 24
Finished Jun 11 03:22:38 PM PDT 24
Peak memory 232532 kb
Host smart-32db6d16-b5dc-4d0d-9c96-cf9607864672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002186571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2002186571
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3270794761
Short name T258
Test name
Test status
Simulation time 221324273 ps
CPU time 4.14 seconds
Started Jun 11 03:22:31 PM PDT 24
Finished Jun 11 03:22:38 PM PDT 24
Peak memory 224260 kb
Host smart-da985773-6733-46c7-85c1-9d60cec41f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270794761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3270794761
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.22404546
Short name T811
Test name
Test status
Simulation time 14472775 ps
CPU time 1.02 seconds
Started Jun 11 03:22:33 PM PDT 24
Finished Jun 11 03:22:36 PM PDT 24
Peak memory 217748 kb
Host smart-2da08089-9bc4-45fe-bb40-4f01d3c35f00
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22404546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.22404546
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3180774952
Short name T311
Test name
Test status
Simulation time 287555500 ps
CPU time 4.64 seconds
Started Jun 11 03:22:31 PM PDT 24
Finished Jun 11 03:22:38 PM PDT 24
Peak memory 232572 kb
Host smart-06c46f41-6a62-4129-b91b-dd685dbd888a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180774952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3180774952
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.736886841
Short name T734
Test name
Test status
Simulation time 3288429060 ps
CPU time 10.11 seconds
Started Jun 11 03:22:34 PM PDT 24
Finished Jun 11 03:22:46 PM PDT 24
Peak memory 224600 kb
Host smart-4ec3fbe6-4637-4b15-a643-975db3387a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736886841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.736886841
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2889565150
Short name T764
Test name
Test status
Simulation time 3728386945 ps
CPU time 7.67 seconds
Started Jun 11 03:22:32 PM PDT 24
Finished Jun 11 03:22:41 PM PDT 24
Peak memory 219792 kb
Host smart-3d119825-989d-4e2b-b47b-1cb34a4cfd5b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2889565150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2889565150
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1105148580
Short name T137
Test name
Test status
Simulation time 2460706796 ps
CPU time 13.35 seconds
Started Jun 11 03:22:31 PM PDT 24
Finished Jun 11 03:22:46 PM PDT 24
Peak memory 216184 kb
Host smart-8ffc5c98-9450-40c9-a869-d03a5b9c0427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105148580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1105148580
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1061374450
Short name T746
Test name
Test status
Simulation time 356169986 ps
CPU time 1.72 seconds
Started Jun 11 03:22:34 PM PDT 24
Finished Jun 11 03:22:38 PM PDT 24
Peak memory 206792 kb
Host smart-858e6902-2581-4e3f-91d1-601f6d77d244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061374450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1061374450
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2259748901
Short name T388
Test name
Test status
Simulation time 153206043 ps
CPU time 3.9 seconds
Started Jun 11 03:22:33 PM PDT 24
Finished Jun 11 03:22:40 PM PDT 24
Peak memory 216012 kb
Host smart-d070bae7-143d-4c19-a3de-af877d481a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259748901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2259748901
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1811678626
Short name T408
Test name
Test status
Simulation time 310990575 ps
CPU time 0.81 seconds
Started Jun 11 03:22:30 PM PDT 24
Finished Jun 11 03:22:33 PM PDT 24
Peak memory 205644 kb
Host smart-f6636ee0-2a3b-46b7-ad7e-53b7394b269d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811678626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1811678626
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.4077113415
Short name T827
Test name
Test status
Simulation time 5907570913 ps
CPU time 12.38 seconds
Started Jun 11 03:22:31 PM PDT 24
Finished Jun 11 03:22:46 PM PDT 24
Peak memory 232692 kb
Host smart-32c68657-e3a4-4f62-a595-6cde45aa0532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077113415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.4077113415
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2553110025
Short name T72
Test name
Test status
Simulation time 16726121 ps
CPU time 0.73 seconds
Started Jun 11 03:22:42 PM PDT 24
Finished Jun 11 03:22:45 PM PDT 24
Peak memory 204752 kb
Host smart-23c87e5c-89d1-4777-a455-66ed8a7a010e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553110025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2553110025
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1255241327
Short name T599
Test name
Test status
Simulation time 896129248 ps
CPU time 10.6 seconds
Started Jun 11 03:22:42 PM PDT 24
Finished Jun 11 03:22:55 PM PDT 24
Peak memory 232504 kb
Host smart-31344da9-9d4b-4291-92b8-a5afc1027915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255241327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1255241327
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2712843555
Short name T6
Test name
Test status
Simulation time 16519577 ps
CPU time 0.8 seconds
Started Jun 11 03:22:36 PM PDT 24
Finished Jun 11 03:22:38 PM PDT 24
Peak memory 206716 kb
Host smart-e218c2a9-e2ee-44df-80cd-06a41ba6849b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712843555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2712843555
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.4096392743
Short name T207
Test name
Test status
Simulation time 174414615666 ps
CPU time 233.74 seconds
Started Jun 11 03:22:41 PM PDT 24
Finished Jun 11 03:26:36 PM PDT 24
Peak memory 256964 kb
Host smart-439b709b-ba7a-4299-a405-e033a867a30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096392743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.4096392743
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2896208013
Short name T68
Test name
Test status
Simulation time 686880804 ps
CPU time 15.87 seconds
Started Jun 11 03:22:48 PM PDT 24
Finished Jun 11 03:23:06 PM PDT 24
Peak memory 240760 kb
Host smart-3619f8da-32ae-4e73-b3ff-2e68a35fbe82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896208013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2896208013
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3037114007
Short name T423
Test name
Test status
Simulation time 27532103683 ps
CPU time 51.91 seconds
Started Jun 11 03:22:48 PM PDT 24
Finished Jun 11 03:23:43 PM PDT 24
Peak memory 229188 kb
Host smart-ec0eeeb1-d5b8-4c86-a5c3-163801d5bea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037114007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3037114007
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.4289770766
Short name T152
Test name
Test status
Simulation time 3056741771 ps
CPU time 24.55 seconds
Started Jun 11 03:22:42 PM PDT 24
Finished Jun 11 03:23:08 PM PDT 24
Peak memory 240864 kb
Host smart-5ee21030-1db0-49e4-b5fc-3248452e327b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289770766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.4289770766
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.868098197
Short name T228
Test name
Test status
Simulation time 367165977 ps
CPU time 4.82 seconds
Started Jun 11 03:22:36 PM PDT 24
Finished Jun 11 03:22:42 PM PDT 24
Peak memory 224280 kb
Host smart-93325298-e217-493c-bd0b-ca3f7cb941f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868098197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.868098197
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3714131061
Short name T91
Test name
Test status
Simulation time 7202643675 ps
CPU time 39.58 seconds
Started Jun 11 03:22:35 PM PDT 24
Finished Jun 11 03:23:17 PM PDT 24
Peak memory 240652 kb
Host smart-74db89ee-3edf-4f97-a3c8-fb8d1881d912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714131061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3714131061
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2873529229
Short name T669
Test name
Test status
Simulation time 199436453 ps
CPU time 1.12 seconds
Started Jun 11 03:22:33 PM PDT 24
Finished Jun 11 03:22:36 PM PDT 24
Peak memory 216512 kb
Host smart-df0105f7-134b-4aa3-9e71-b03b4c5b58eb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873529229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2873529229
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3607860340
Short name T280
Test name
Test status
Simulation time 2424436080 ps
CPU time 5.54 seconds
Started Jun 11 03:22:31 PM PDT 24
Finished Jun 11 03:22:38 PM PDT 24
Peak memory 232656 kb
Host smart-8b2dcbd3-384a-4997-b65c-f592012cbcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607860340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3607860340
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.423014808
Short name T781
Test name
Test status
Simulation time 1015759041 ps
CPU time 5.28 seconds
Started Jun 11 03:22:31 PM PDT 24
Finished Jun 11 03:22:38 PM PDT 24
Peak memory 232548 kb
Host smart-4bbae33c-49fd-412f-bfbb-95c1c3f940c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423014808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.423014808
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3303653062
Short name T657
Test name
Test status
Simulation time 57627595 ps
CPU time 3.32 seconds
Started Jun 11 03:22:45 PM PDT 24
Finished Jun 11 03:22:50 PM PDT 24
Peak memory 222764 kb
Host smart-7bbb64ad-4512-4874-a0de-c6ddcafa1d30
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3303653062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3303653062
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3091781350
Short name T929
Test name
Test status
Simulation time 1440886746 ps
CPU time 10.02 seconds
Started Jun 11 03:22:31 PM PDT 24
Finished Jun 11 03:22:43 PM PDT 24
Peak memory 216208 kb
Host smart-ae786578-e9e4-4333-b56a-8a8830640c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091781350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3091781350
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1897988160
Short name T399
Test name
Test status
Simulation time 2776723750 ps
CPU time 10.97 seconds
Started Jun 11 03:22:33 PM PDT 24
Finished Jun 11 03:22:46 PM PDT 24
Peak memory 216172 kb
Host smart-16028052-485a-4c52-acdf-94085accf644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897988160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1897988160
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2015276832
Short name T397
Test name
Test status
Simulation time 103235617 ps
CPU time 1.67 seconds
Started Jun 11 03:22:33 PM PDT 24
Finished Jun 11 03:22:37 PM PDT 24
Peak memory 216072 kb
Host smart-a4d000db-a038-4079-ae9d-59336fa9596d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015276832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2015276832
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1043299162
Short name T370
Test name
Test status
Simulation time 47202140 ps
CPU time 0.89 seconds
Started Jun 11 03:22:32 PM PDT 24
Finished Jun 11 03:22:36 PM PDT 24
Peak memory 205700 kb
Host smart-920623f5-1f27-4b4c-b4f4-825c2dcaee04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043299162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1043299162
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2579596500
Short name T841
Test name
Test status
Simulation time 1487141076 ps
CPU time 9.35 seconds
Started Jun 11 03:22:46 PM PDT 24
Finished Jun 11 03:22:58 PM PDT 24
Peak memory 232580 kb
Host smart-9800a2e5-1ad7-4d8a-bddc-a2cff880d1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579596500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2579596500
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1805743912
Short name T541
Test name
Test status
Simulation time 37098306 ps
CPU time 0.7 seconds
Started Jun 11 03:21:32 PM PDT 24
Finished Jun 11 03:21:35 PM PDT 24
Peak memory 205296 kb
Host smart-6cb8391e-5e9d-4b36-aa0f-662c732ce28d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805743912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
805743912
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.224019819
Short name T565
Test name
Test status
Simulation time 389350416 ps
CPU time 5.27 seconds
Started Jun 11 03:21:22 PM PDT 24
Finished Jun 11 03:21:30 PM PDT 24
Peak memory 232516 kb
Host smart-c0780b3e-eb5d-4c56-9dee-6d7aaa7280d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224019819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.224019819
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.713245420
Short name T874
Test name
Test status
Simulation time 37404374 ps
CPU time 0.79 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:21:29 PM PDT 24
Peak memory 206672 kb
Host smart-4d983142-bcbe-4c8a-9a28-0c1717e44396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713245420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.713245420
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.52287913
Short name T468
Test name
Test status
Simulation time 880739048 ps
CPU time 22.11 seconds
Started Jun 11 03:21:34 PM PDT 24
Finished Jun 11 03:21:58 PM PDT 24
Peak memory 248536 kb
Host smart-ef2063a8-b784-4e7d-91af-e2243b7cb4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52287913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.52287913
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3288925537
Short name T282
Test name
Test status
Simulation time 39737550957 ps
CPU time 100.33 seconds
Started Jun 11 03:21:32 PM PDT 24
Finished Jun 11 03:23:15 PM PDT 24
Peak memory 237832 kb
Host smart-e9577f75-c96e-4c41-9111-22bd4db26374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288925537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3288925537
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1651058828
Short name T146
Test name
Test status
Simulation time 1005613057 ps
CPU time 6.92 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:21:35 PM PDT 24
Peak memory 232572 kb
Host smart-abf34ffa-3bf3-4d1f-82ba-4b96e74b2e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651058828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1651058828
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.4048413272
Short name T373
Test name
Test status
Simulation time 17210092131 ps
CPU time 44.46 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:22:12 PM PDT 24
Peak memory 232632 kb
Host smart-59d81c8e-466a-4550-b800-fa594909f57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048413272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.4048413272
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3677869825
Short name T654
Test name
Test status
Simulation time 98926176 ps
CPU time 0.98 seconds
Started Jun 11 03:21:28 PM PDT 24
Finished Jun 11 03:21:32 PM PDT 24
Peak memory 217708 kb
Host smart-5929b3ce-d4df-4fdf-a932-8c8cedd38d3c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677869825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3677869825
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1935127792
Short name T699
Test name
Test status
Simulation time 4009472188 ps
CPU time 6.34 seconds
Started Jun 11 03:21:23 PM PDT 24
Finished Jun 11 03:21:32 PM PDT 24
Peak memory 224316 kb
Host smart-4084edf5-0da3-47d9-887d-16c34865e391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935127792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1935127792
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1349853364
Short name T150
Test name
Test status
Simulation time 4283431252 ps
CPU time 8.83 seconds
Started Jun 11 03:21:26 PM PDT 24
Finished Jun 11 03:21:39 PM PDT 24
Peak memory 221868 kb
Host smart-ab542540-f7a3-433b-80f9-1e3e0ec33928
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1349853364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1349853364
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.632872050
Short name T20
Test name
Test status
Simulation time 65543602 ps
CPU time 1.04 seconds
Started Jun 11 03:21:30 PM PDT 24
Finished Jun 11 03:21:34 PM PDT 24
Peak memory 235516 kb
Host smart-6446abcc-d16f-4ae1-b1b1-8ac7a244c413
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632872050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.632872050
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3212761770
Short name T302
Test name
Test status
Simulation time 27513444745 ps
CPU time 168.76 seconds
Started Jun 11 03:21:33 PM PDT 24
Finished Jun 11 03:24:24 PM PDT 24
Peak memory 254912 kb
Host smart-7bdcdfc0-998a-4bce-b3e5-1e463e3546f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212761770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3212761770
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.650653436
Short name T636
Test name
Test status
Simulation time 1719754003 ps
CPU time 9.97 seconds
Started Jun 11 03:21:25 PM PDT 24
Finished Jun 11 03:21:38 PM PDT 24
Peak memory 216092 kb
Host smart-b6c0058f-91d9-4135-8f33-bffb8fb64294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650653436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.650653436
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3604821959
Short name T24
Test name
Test status
Simulation time 2144289501 ps
CPU time 6.24 seconds
Started Jun 11 03:21:26 PM PDT 24
Finished Jun 11 03:21:35 PM PDT 24
Peak memory 216036 kb
Host smart-9f258371-db5a-4def-8f69-5a851257cbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604821959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3604821959
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2635943078
Short name T406
Test name
Test status
Simulation time 19943264 ps
CPU time 0.85 seconds
Started Jun 11 03:21:22 PM PDT 24
Finished Jun 11 03:21:25 PM PDT 24
Peak memory 206196 kb
Host smart-5eef6eb6-61a3-4f50-9fbe-26bfaedff4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635943078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2635943078
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2491278501
Short name T447
Test name
Test status
Simulation time 34718458 ps
CPU time 0.89 seconds
Started Jun 11 03:21:24 PM PDT 24
Finished Jun 11 03:21:28 PM PDT 24
Peak memory 205692 kb
Host smart-810ca352-2ce7-46b1-ab3b-1f33be0b9504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491278501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2491278501
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3723439755
Short name T274
Test name
Test status
Simulation time 131950495 ps
CPU time 2.64 seconds
Started Jun 11 03:21:24 PM PDT 24
Finished Jun 11 03:21:29 PM PDT 24
Peak memory 232556 kb
Host smart-5082067c-f4e1-4a47-a8f7-f1617caa664c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723439755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3723439755
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2569489445
Short name T506
Test name
Test status
Simulation time 34314203 ps
CPU time 0.72 seconds
Started Jun 11 03:22:45 PM PDT 24
Finished Jun 11 03:22:48 PM PDT 24
Peak memory 205312 kb
Host smart-21640c96-b168-41f5-a8bd-7a1f57d517f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569489445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2569489445
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2039423668
Short name T640
Test name
Test status
Simulation time 69257714 ps
CPU time 3.06 seconds
Started Jun 11 03:22:46 PM PDT 24
Finished Jun 11 03:22:51 PM PDT 24
Peak memory 232564 kb
Host smart-02334d62-3be7-4e42-8465-30f16611e767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039423668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2039423668
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.66130250
Short name T483
Test name
Test status
Simulation time 15313175 ps
CPU time 0.74 seconds
Started Jun 11 03:22:46 PM PDT 24
Finished Jun 11 03:22:50 PM PDT 24
Peak memory 205660 kb
Host smart-c3e28f5d-7844-4d03-8958-3204ea10b49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66130250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.66130250
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3014585142
Short name T323
Test name
Test status
Simulation time 32256593884 ps
CPU time 23.38 seconds
Started Jun 11 03:22:47 PM PDT 24
Finished Jun 11 03:23:13 PM PDT 24
Peak memory 249268 kb
Host smart-94df3b5e-80a8-4980-829d-34158d16eca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014585142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3014585142
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2802772086
Short name T740
Test name
Test status
Simulation time 11156511114 ps
CPU time 90.93 seconds
Started Jun 11 03:22:41 PM PDT 24
Finished Jun 11 03:24:13 PM PDT 24
Peak memory 255516 kb
Host smart-654b000b-b291-4622-841d-e30323682124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802772086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2802772086
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.594609688
Short name T783
Test name
Test status
Simulation time 460004924 ps
CPU time 11.57 seconds
Started Jun 11 03:22:44 PM PDT 24
Finished Jun 11 03:22:58 PM PDT 24
Peak memory 237760 kb
Host smart-f9158f92-e699-46e3-8605-ddfe55c41893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594609688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.594609688
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.202497137
Short name T219
Test name
Test status
Simulation time 168988405 ps
CPU time 2.61 seconds
Started Jun 11 03:22:43 PM PDT 24
Finished Jun 11 03:22:48 PM PDT 24
Peak memory 224264 kb
Host smart-aef5c12f-f384-4a35-ad25-7599afaf6aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202497137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.202497137
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2469946395
Short name T892
Test name
Test status
Simulation time 130346140 ps
CPU time 3.43 seconds
Started Jun 11 03:23:17 PM PDT 24
Finished Jun 11 03:23:23 PM PDT 24
Peak memory 232504 kb
Host smart-759f5d0c-fec7-4958-9904-b72e700a7f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469946395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2469946395
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1604279999
Short name T374
Test name
Test status
Simulation time 100594724 ps
CPU time 2.02 seconds
Started Jun 11 03:22:43 PM PDT 24
Finished Jun 11 03:22:48 PM PDT 24
Peak memory 222732 kb
Host smart-1ef6d352-2c8f-4098-b83d-3e8e0394f93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604279999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1604279999
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3389595583
Short name T420
Test name
Test status
Simulation time 197740012 ps
CPU time 2.25 seconds
Started Jun 11 03:22:44 PM PDT 24
Finished Jun 11 03:22:48 PM PDT 24
Peak memory 222716 kb
Host smart-d94b21d8-f5be-4780-8920-a03f63488377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389595583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3389595583
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.755512144
Short name T902
Test name
Test status
Simulation time 297346758 ps
CPU time 3.8 seconds
Started Jun 11 03:22:42 PM PDT 24
Finished Jun 11 03:22:48 PM PDT 24
Peak memory 218964 kb
Host smart-e9e58429-73b3-4b6e-863d-e61fe38366d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=755512144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.755512144
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.907754596
Short name T144
Test name
Test status
Simulation time 52655402933 ps
CPU time 578.53 seconds
Started Jun 11 03:22:46 PM PDT 24
Finished Jun 11 03:32:27 PM PDT 24
Peak memory 272324 kb
Host smart-374f1785-e596-4efa-a008-547f74b61e8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907754596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.907754596
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1658696879
Short name T758
Test name
Test status
Simulation time 59908636762 ps
CPU time 25.73 seconds
Started Jun 11 03:22:46 PM PDT 24
Finished Jun 11 03:23:14 PM PDT 24
Peak memory 216176 kb
Host smart-41b6a1ff-58cd-4e8f-a18c-23f1657e7380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658696879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1658696879
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1040142144
Short name T167
Test name
Test status
Simulation time 4969698785 ps
CPU time 4.33 seconds
Started Jun 11 03:22:44 PM PDT 24
Finished Jun 11 03:22:51 PM PDT 24
Peak memory 216144 kb
Host smart-bb60d87d-ef89-49e0-8eed-235bd0f0b9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040142144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1040142144
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2830872466
Short name T649
Test name
Test status
Simulation time 28110379 ps
CPU time 0.68 seconds
Started Jun 11 03:22:46 PM PDT 24
Finished Jun 11 03:22:49 PM PDT 24
Peak memory 205416 kb
Host smart-99831c4c-86b3-4338-a4f1-6de48a4598aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830872466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2830872466
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3900613605
Short name T64
Test name
Test status
Simulation time 24844290 ps
CPU time 0.76 seconds
Started Jun 11 03:22:44 PM PDT 24
Finished Jun 11 03:22:47 PM PDT 24
Peak memory 205704 kb
Host smart-3f301c28-7f5e-4250-bb83-cc5f5800dc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900613605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3900613605
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.114301361
Short name T857
Test name
Test status
Simulation time 200979742 ps
CPU time 2.45 seconds
Started Jun 11 03:22:50 PM PDT 24
Finished Jun 11 03:22:54 PM PDT 24
Peak memory 224100 kb
Host smart-d5e8680d-bf6b-4bfe-be01-509eb3292696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114301361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.114301361
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2816897948
Short name T405
Test name
Test status
Simulation time 21335423 ps
CPU time 0.76 seconds
Started Jun 11 03:22:42 PM PDT 24
Finished Jun 11 03:22:44 PM PDT 24
Peak memory 204720 kb
Host smart-6e95d496-a77a-4d33-a4af-a92944f187ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816897948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2816897948
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.656943048
Short name T271
Test name
Test status
Simulation time 4264609577 ps
CPU time 13.66 seconds
Started Jun 11 03:22:47 PM PDT 24
Finished Jun 11 03:23:03 PM PDT 24
Peak memory 224476 kb
Host smart-65f3505e-9cff-4696-a057-bb275e2deb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656943048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.656943048
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.602261476
Short name T797
Test name
Test status
Simulation time 28894265 ps
CPU time 0.75 seconds
Started Jun 11 03:22:43 PM PDT 24
Finished Jun 11 03:22:46 PM PDT 24
Peak memory 206380 kb
Host smart-8a48ca86-01f8-45d7-b39e-5c435cc5b68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602261476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.602261476
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1178771510
Short name T794
Test name
Test status
Simulation time 152573734851 ps
CPU time 223.39 seconds
Started Jun 11 03:22:48 PM PDT 24
Finished Jun 11 03:26:34 PM PDT 24
Peak memory 249096 kb
Host smart-e2d626d2-d8b9-42a6-9138-3597147b66f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178771510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1178771510
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2237476397
Short name T174
Test name
Test status
Simulation time 6970307696 ps
CPU time 95.91 seconds
Started Jun 11 03:22:46 PM PDT 24
Finished Jun 11 03:24:25 PM PDT 24
Peak memory 251660 kb
Host smart-35c58f06-7ae0-4bc9-865a-b6d20a036b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237476397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2237476397
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.4173617363
Short name T645
Test name
Test status
Simulation time 298993994 ps
CPU time 4.06 seconds
Started Jun 11 03:22:45 PM PDT 24
Finished Jun 11 03:22:51 PM PDT 24
Peak memory 233556 kb
Host smart-a6072572-f0c3-48b1-8740-a6e3c6faeec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173617363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.4173617363
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1323663180
Short name T517
Test name
Test status
Simulation time 11561412861 ps
CPU time 21.17 seconds
Started Jun 11 03:22:42 PM PDT 24
Finished Jun 11 03:23:05 PM PDT 24
Peak memory 224404 kb
Host smart-83cbb0ed-e89b-4248-9c02-bdc7fb3509e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323663180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1323663180
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3945095293
Short name T686
Test name
Test status
Simulation time 90697412 ps
CPU time 2.06 seconds
Started Jun 11 03:22:45 PM PDT 24
Finished Jun 11 03:22:49 PM PDT 24
Peak memory 222884 kb
Host smart-69cf7d82-59f7-4693-aee5-f8d0309b94ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945095293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3945095293
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1549838085
Short name T667
Test name
Test status
Simulation time 532614459 ps
CPU time 4.86 seconds
Started Jun 11 03:22:47 PM PDT 24
Finished Jun 11 03:22:54 PM PDT 24
Peak memory 232500 kb
Host smart-58ea31e0-1ef1-450b-abee-039c2633498c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549838085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1549838085
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1931155556
Short name T264
Test name
Test status
Simulation time 119925936 ps
CPU time 1.99 seconds
Started Jun 11 03:22:48 PM PDT 24
Finished Jun 11 03:22:52 PM PDT 24
Peak memory 224340 kb
Host smart-3933f59d-0b6b-4be7-abeb-3f7911645499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931155556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1931155556
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2414531682
Short name T622
Test name
Test status
Simulation time 4346632338 ps
CPU time 8.47 seconds
Started Jun 11 03:22:42 PM PDT 24
Finished Jun 11 03:22:53 PM PDT 24
Peak memory 222856 kb
Host smart-1bc8a769-86ab-4f5e-8918-9e2a3307c04e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2414531682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2414531682
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.4230630420
Short name T4
Test name
Test status
Simulation time 317443710 ps
CPU time 2.25 seconds
Started Jun 11 03:22:46 PM PDT 24
Finished Jun 11 03:22:50 PM PDT 24
Peak memory 216184 kb
Host smart-30c97400-a6c9-4504-abba-4b83a51f2ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230630420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.4230630420
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1728698460
Short name T358
Test name
Test status
Simulation time 17418719783 ps
CPU time 13.07 seconds
Started Jun 11 03:22:47 PM PDT 24
Finished Jun 11 03:23:03 PM PDT 24
Peak memory 216140 kb
Host smart-fd897381-3a39-4e8f-be67-8665c0f45da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728698460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1728698460
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2548137567
Short name T359
Test name
Test status
Simulation time 62777329 ps
CPU time 1.61 seconds
Started Jun 11 03:22:46 PM PDT 24
Finished Jun 11 03:22:49 PM PDT 24
Peak memory 216020 kb
Host smart-f1ca4156-d726-4250-92ea-888ca0f86429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548137567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2548137567
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1668456180
Short name T491
Test name
Test status
Simulation time 86542567 ps
CPU time 0.78 seconds
Started Jun 11 03:22:42 PM PDT 24
Finished Jun 11 03:22:44 PM PDT 24
Peak memory 205644 kb
Host smart-a19629b9-e905-458e-9820-75715b16253e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668456180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1668456180
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.783031776
Short name T398
Test name
Test status
Simulation time 7606873722 ps
CPU time 9.83 seconds
Started Jun 11 03:22:47 PM PDT 24
Finished Jun 11 03:22:59 PM PDT 24
Peak memory 232592 kb
Host smart-25c16106-0a80-4eaa-91b6-479b55fae148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783031776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.783031776
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1216248990
Short name T737
Test name
Test status
Simulation time 31317072 ps
CPU time 0.71 seconds
Started Jun 11 03:22:52 PM PDT 24
Finished Jun 11 03:22:55 PM PDT 24
Peak memory 204668 kb
Host smart-614d4fb1-4d56-4f73-8679-0729aab117b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216248990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1216248990
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.954997735
Short name T261
Test name
Test status
Simulation time 4569297916 ps
CPU time 7.5 seconds
Started Jun 11 03:22:57 PM PDT 24
Finished Jun 11 03:23:05 PM PDT 24
Peak memory 224460 kb
Host smart-7f8467bc-5168-4aad-be55-ff74ce80078e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954997735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.954997735
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1520130412
Short name T450
Test name
Test status
Simulation time 19560234 ps
CPU time 0.8 seconds
Started Jun 11 03:22:47 PM PDT 24
Finished Jun 11 03:22:50 PM PDT 24
Peak memory 206364 kb
Host smart-274f87ed-a9a8-468c-b84e-5b8c707ae6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520130412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1520130412
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3201403789
Short name T720
Test name
Test status
Simulation time 7944145266 ps
CPU time 30.26 seconds
Started Jun 11 03:22:52 PM PDT 24
Finished Jun 11 03:23:24 PM PDT 24
Peak memory 240380 kb
Host smart-70199439-4c13-4d15-a8f8-90a4d870a85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201403789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3201403789
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3645697081
Short name T310
Test name
Test status
Simulation time 62984624139 ps
CPU time 518.95 seconds
Started Jun 11 03:22:51 PM PDT 24
Finished Jun 11 03:31:32 PM PDT 24
Peak memory 265960 kb
Host smart-f52937d8-e663-4da0-84cb-d5a29ae19039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645697081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3645697081
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.550521783
Short name T233
Test name
Test status
Simulation time 430718508 ps
CPU time 15.06 seconds
Started Jun 11 03:23:00 PM PDT 24
Finished Jun 11 03:23:16 PM PDT 24
Peak memory 232512 kb
Host smart-e24dc2ec-8cb7-4af3-9108-bce51eaa770b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550521783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.550521783
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.238833982
Short name T392
Test name
Test status
Simulation time 102565725 ps
CPU time 2.73 seconds
Started Jun 11 03:22:53 PM PDT 24
Finished Jun 11 03:22:58 PM PDT 24
Peak memory 232544 kb
Host smart-5d07e450-433d-4c9c-9528-532ffcac4005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238833982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.238833982
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.4261128393
Short name T700
Test name
Test status
Simulation time 444982525 ps
CPU time 7.49 seconds
Started Jun 11 03:22:54 PM PDT 24
Finished Jun 11 03:23:04 PM PDT 24
Peak memory 232524 kb
Host smart-e7308788-d085-4c47-952a-e6e7d14a4c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261128393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.4261128393
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3411611073
Short name T362
Test name
Test status
Simulation time 471799485 ps
CPU time 2.93 seconds
Started Jun 11 03:22:53 PM PDT 24
Finished Jun 11 03:22:58 PM PDT 24
Peak memory 224324 kb
Host smart-86acb3ae-fcff-4c68-855e-42ef4c23fd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411611073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3411611073
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1113829357
Short name T664
Test name
Test status
Simulation time 13588505327 ps
CPU time 13.42 seconds
Started Jun 11 03:22:52 PM PDT 24
Finished Jun 11 03:23:08 PM PDT 24
Peak memory 240760 kb
Host smart-c8546da5-1a42-4c18-ab12-2c07fc010efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113829357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1113829357
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.654809597
Short name T149
Test name
Test status
Simulation time 2215149059 ps
CPU time 7.07 seconds
Started Jun 11 03:22:52 PM PDT 24
Finished Jun 11 03:23:01 PM PDT 24
Peak memory 222688 kb
Host smart-baba2e26-e593-440c-bedc-23b845b1ac16
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=654809597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.654809597
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2036557689
Short name T762
Test name
Test status
Simulation time 18224542 ps
CPU time 0.8 seconds
Started Jun 11 03:22:47 PM PDT 24
Finished Jun 11 03:22:50 PM PDT 24
Peak memory 205536 kb
Host smart-ff756e31-526e-4b29-b798-f3dc964f6792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036557689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2036557689
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1480889528
Short name T426
Test name
Test status
Simulation time 5022753036 ps
CPU time 5.76 seconds
Started Jun 11 03:22:43 PM PDT 24
Finished Jun 11 03:22:52 PM PDT 24
Peak memory 216108 kb
Host smart-4885ad6a-ea37-4dd4-8c12-cf23a548792f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480889528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1480889528
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2596288187
Short name T27
Test name
Test status
Simulation time 102394198 ps
CPU time 1.06 seconds
Started Jun 11 03:22:52 PM PDT 24
Finished Jun 11 03:22:55 PM PDT 24
Peak memory 206400 kb
Host smart-630e834f-4128-4c5b-97ae-0f3e86fe1c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596288187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2596288187
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.116335572
Short name T942
Test name
Test status
Simulation time 46825501 ps
CPU time 0.84 seconds
Started Jun 11 03:22:53 PM PDT 24
Finished Jun 11 03:22:56 PM PDT 24
Peak memory 205676 kb
Host smart-9caed8aa-c0d1-4338-b6d2-28f6a293d8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116335572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.116335572
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3451435565
Short name T293
Test name
Test status
Simulation time 134649844 ps
CPU time 2.18 seconds
Started Jun 11 03:22:52 PM PDT 24
Finished Jun 11 03:22:56 PM PDT 24
Peak memory 224296 kb
Host smart-54f9973b-fbcb-4088-b2d9-c10ad2c09899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451435565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3451435565
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3547871847
Short name T504
Test name
Test status
Simulation time 12214192 ps
CPU time 0.74 seconds
Started Jun 11 03:22:50 PM PDT 24
Finished Jun 11 03:22:53 PM PDT 24
Peak memory 204720 kb
Host smart-4a5df588-08d2-477a-9dfe-5ac95ad594b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547871847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3547871847
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1084128447
Short name T779
Test name
Test status
Simulation time 2069208926 ps
CPU time 7.35 seconds
Started Jun 11 03:22:59 PM PDT 24
Finished Jun 11 03:23:07 PM PDT 24
Peak memory 224276 kb
Host smart-b2ce8026-e5a6-49f5-85a6-9c4fb984e9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084128447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1084128447
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2643949143
Short name T822
Test name
Test status
Simulation time 18566243 ps
CPU time 0.76 seconds
Started Jun 11 03:22:55 PM PDT 24
Finished Jun 11 03:22:57 PM PDT 24
Peak memory 205316 kb
Host smart-e74867f3-22fd-4a5e-92c3-34bbc824e9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643949143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2643949143
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1317768539
Short name T69
Test name
Test status
Simulation time 48616498055 ps
CPU time 140.48 seconds
Started Jun 11 03:22:52 PM PDT 24
Finished Jun 11 03:25:15 PM PDT 24
Peak memory 253376 kb
Host smart-2d9666ba-56cc-4781-8ca9-f474043f71a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317768539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1317768539
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1196071805
Short name T821
Test name
Test status
Simulation time 31811875366 ps
CPU time 74.97 seconds
Started Jun 11 03:22:54 PM PDT 24
Finished Jun 11 03:24:11 PM PDT 24
Peak memory 253612 kb
Host smart-7280c8f2-38ca-4b8a-bace-07c7103b3779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196071805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1196071805
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1145079819
Short name T327
Test name
Test status
Simulation time 3330607836 ps
CPU time 9.58 seconds
Started Jun 11 03:22:51 PM PDT 24
Finished Jun 11 03:23:03 PM PDT 24
Peak memory 248968 kb
Host smart-f6fb34e6-c522-4fca-bb05-5f660eb41a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145079819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1145079819
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2145961954
Short name T716
Test name
Test status
Simulation time 945716713 ps
CPU time 10.64 seconds
Started Jun 11 03:22:54 PM PDT 24
Finished Jun 11 03:23:07 PM PDT 24
Peak memory 228764 kb
Host smart-5fa8ed68-6ae2-4371-851d-ecdf24fd4c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145961954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2145961954
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.641324578
Short name T848
Test name
Test status
Simulation time 7805844449 ps
CPU time 26.15 seconds
Started Jun 11 03:22:57 PM PDT 24
Finished Jun 11 03:23:24 PM PDT 24
Peak memory 233660 kb
Host smart-ce36ec21-fad2-4e29-bcda-6ebcdd5245fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641324578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.641324578
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1096121134
Short name T489
Test name
Test status
Simulation time 6539157945 ps
CPU time 13.52 seconds
Started Jun 11 03:22:52 PM PDT 24
Finished Jun 11 03:23:08 PM PDT 24
Peak memory 240644 kb
Host smart-58fd1159-504a-414b-b1f7-70a353d3f8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096121134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1096121134
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.71011525
Short name T810
Test name
Test status
Simulation time 1372278260 ps
CPU time 3.43 seconds
Started Jun 11 03:22:51 PM PDT 24
Finished Jun 11 03:22:57 PM PDT 24
Peak memory 232520 kb
Host smart-327c08e8-dc58-4e01-9ad7-4b3914930be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71011525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.71011525
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2363276649
Short name T528
Test name
Test status
Simulation time 2036017960 ps
CPU time 26.63 seconds
Started Jun 11 03:22:51 PM PDT 24
Finished Jun 11 03:23:20 PM PDT 24
Peak memory 219512 kb
Host smart-0016de82-c480-4127-b602-8c6eea0bb661
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2363276649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2363276649
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1430306218
Short name T329
Test name
Test status
Simulation time 4104781006 ps
CPU time 21.43 seconds
Started Jun 11 03:22:55 PM PDT 24
Finished Jun 11 03:23:18 PM PDT 24
Peak memory 219904 kb
Host smart-dfeaca29-53ac-4973-a24b-97468b7c6eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430306218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1430306218
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1364822686
Short name T930
Test name
Test status
Simulation time 1031151931 ps
CPU time 3.99 seconds
Started Jun 11 03:22:55 PM PDT 24
Finished Jun 11 03:23:01 PM PDT 24
Peak memory 216116 kb
Host smart-52424b97-d71e-4897-b430-5998208df666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364822686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1364822686
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1602939897
Short name T582
Test name
Test status
Simulation time 10777577 ps
CPU time 0.7 seconds
Started Jun 11 03:22:52 PM PDT 24
Finished Jun 11 03:22:55 PM PDT 24
Peak memory 205388 kb
Host smart-e18eb95c-82ac-4657-9949-abb9590195ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602939897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1602939897
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2259941354
Short name T898
Test name
Test status
Simulation time 184095636 ps
CPU time 0.85 seconds
Started Jun 11 03:22:57 PM PDT 24
Finished Jun 11 03:22:59 PM PDT 24
Peak memory 205704 kb
Host smart-30a2700f-8a87-4946-857f-0b96186d3375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259941354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2259941354
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.223729061
Short name T887
Test name
Test status
Simulation time 103161307 ps
CPU time 2.21 seconds
Started Jun 11 03:22:53 PM PDT 24
Finished Jun 11 03:22:57 PM PDT 24
Peak memory 216492 kb
Host smart-ee01d352-1147-4a6d-845b-728cad8ed8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223729061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.223729061
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.585183342
Short name T386
Test name
Test status
Simulation time 24630951 ps
CPU time 0.73 seconds
Started Jun 11 03:23:03 PM PDT 24
Finished Jun 11 03:23:06 PM PDT 24
Peak memory 205320 kb
Host smart-d31042fa-920e-402f-83fb-cb3c6244b456
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585183342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.585183342
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.244052643
Short name T833
Test name
Test status
Simulation time 88570689 ps
CPU time 2.61 seconds
Started Jun 11 03:22:55 PM PDT 24
Finished Jun 11 03:22:59 PM PDT 24
Peak memory 232492 kb
Host smart-615d9c86-e109-4020-be1d-35305f3f2b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244052643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.244052643
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2914999890
Short name T496
Test name
Test status
Simulation time 29804774 ps
CPU time 0.81 seconds
Started Jun 11 03:22:54 PM PDT 24
Finished Jun 11 03:22:57 PM PDT 24
Peak memory 206712 kb
Host smart-241f51b6-9e7d-4e63-ab1e-1db790c7ff1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914999890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2914999890
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1955422631
Short name T949
Test name
Test status
Simulation time 9672605142 ps
CPU time 89.38 seconds
Started Jun 11 03:22:57 PM PDT 24
Finished Jun 11 03:24:27 PM PDT 24
Peak memory 238668 kb
Host smart-11815534-3827-4946-9009-ea39b0137647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955422631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1955422631
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3710949463
Short name T33
Test name
Test status
Simulation time 57422013197 ps
CPU time 178.32 seconds
Started Jun 11 03:22:57 PM PDT 24
Finished Jun 11 03:25:57 PM PDT 24
Peak memory 251440 kb
Host smart-88322aec-a628-4b59-9a7d-bfefe3531203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710949463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3710949463
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.626381156
Short name T458
Test name
Test status
Simulation time 8756302334 ps
CPU time 46.71 seconds
Started Jun 11 03:23:01 PM PDT 24
Finished Jun 11 03:23:49 PM PDT 24
Peak memory 217196 kb
Host smart-09bb7983-dcb7-491d-9d2f-da1e7aa2b08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626381156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.626381156
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2478648142
Short name T606
Test name
Test status
Simulation time 5855567982 ps
CPU time 7.89 seconds
Started Jun 11 03:22:57 PM PDT 24
Finished Jun 11 03:23:06 PM PDT 24
Peak memory 232680 kb
Host smart-c2753a3c-326e-415b-b2d1-4f59a0f9867c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478648142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2478648142
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2642025620
Short name T200
Test name
Test status
Simulation time 1216755741 ps
CPU time 9.05 seconds
Started Jun 11 03:22:55 PM PDT 24
Finished Jun 11 03:23:06 PM PDT 24
Peak memory 232736 kb
Host smart-f7a9a4c1-8303-42a1-ae24-d72f52a50916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642025620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2642025620
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.4180153578
Short name T801
Test name
Test status
Simulation time 8290180964 ps
CPU time 96.12 seconds
Started Jun 11 03:22:54 PM PDT 24
Finished Jun 11 03:24:32 PM PDT 24
Peak memory 232796 kb
Host smart-13682581-4bb0-4f3d-970d-0d868381b465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180153578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.4180153578
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.275753602
Short name T563
Test name
Test status
Simulation time 10423123038 ps
CPU time 18.6 seconds
Started Jun 11 03:22:55 PM PDT 24
Finished Jun 11 03:23:16 PM PDT 24
Peak memory 232636 kb
Host smart-f472a916-43cf-42c6-ad9f-25476b4b6809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275753602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.275753602
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.334431441
Short name T269
Test name
Test status
Simulation time 447640911 ps
CPU time 8.49 seconds
Started Jun 11 03:22:55 PM PDT 24
Finished Jun 11 03:23:06 PM PDT 24
Peak memory 240704 kb
Host smart-76d47833-7dc4-46d3-9ef2-f15be776da25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334431441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.334431441
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2341415155
Short name T441
Test name
Test status
Simulation time 4429826243 ps
CPU time 5.53 seconds
Started Jun 11 03:22:57 PM PDT 24
Finished Jun 11 03:23:04 PM PDT 24
Peak memory 220060 kb
Host smart-c90ceece-aa6e-4557-932b-ecedf637c3f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2341415155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2341415155
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.4208157270
Short name T725
Test name
Test status
Simulation time 12271398688 ps
CPU time 82.33 seconds
Started Jun 11 03:23:06 PM PDT 24
Finished Jun 11 03:24:30 PM PDT 24
Peak memory 237120 kb
Host smart-21c2fd8a-723f-467b-9c82-456be8083bc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208157270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.4208157270
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.779960411
Short name T583
Test name
Test status
Simulation time 9669639696 ps
CPU time 55.81 seconds
Started Jun 11 03:22:59 PM PDT 24
Finished Jun 11 03:23:56 PM PDT 24
Peak memory 216160 kb
Host smart-42a47f4b-1188-414b-96e9-d6f3ec36bed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779960411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.779960411
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4121271834
Short name T556
Test name
Test status
Simulation time 2198494436 ps
CPU time 5.07 seconds
Started Jun 11 03:22:52 PM PDT 24
Finished Jun 11 03:23:00 PM PDT 24
Peak memory 216152 kb
Host smart-75ca55de-c147-45d3-96a2-05c65bd02c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121271834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4121271834
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1540693068
Short name T343
Test name
Test status
Simulation time 31373713 ps
CPU time 0.96 seconds
Started Jun 11 03:22:54 PM PDT 24
Finished Jun 11 03:22:57 PM PDT 24
Peak memory 206756 kb
Host smart-b8995716-de87-4354-b5d5-6f0ae1a2bd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540693068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1540693068
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.950152942
Short name T499
Test name
Test status
Simulation time 34508249 ps
CPU time 0.72 seconds
Started Jun 11 03:22:52 PM PDT 24
Finished Jun 11 03:22:55 PM PDT 24
Peak memory 205368 kb
Host smart-8e4fc9ed-b05f-42f3-acc3-8540165aaa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950152942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.950152942
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3297287479
Short name T508
Test name
Test status
Simulation time 1602467535 ps
CPU time 9.02 seconds
Started Jun 11 03:22:55 PM PDT 24
Finished Jun 11 03:23:06 PM PDT 24
Peak memory 224540 kb
Host smart-02d17df4-a637-4180-88f9-5e62e4b75d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297287479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3297287479
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3626847146
Short name T352
Test name
Test status
Simulation time 37953579 ps
CPU time 0.71 seconds
Started Jun 11 03:23:04 PM PDT 24
Finished Jun 11 03:23:07 PM PDT 24
Peak memory 204704 kb
Host smart-a0f6e763-5cc7-4661-b3a4-44fb66d068ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626847146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3626847146
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3918872620
Short name T845
Test name
Test status
Simulation time 3655151310 ps
CPU time 14.47 seconds
Started Jun 11 03:23:04 PM PDT 24
Finished Jun 11 03:23:21 PM PDT 24
Peak memory 224384 kb
Host smart-6350c3ab-1234-4949-90e5-b9c03422f220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918872620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3918872620
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1890301095
Short name T366
Test name
Test status
Simulation time 45384209 ps
CPU time 0.75 seconds
Started Jun 11 03:23:05 PM PDT 24
Finished Jun 11 03:23:07 PM PDT 24
Peak memory 206696 kb
Host smart-d5fb7882-8358-4fe6-b6c3-141edec5fc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890301095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1890301095
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1040622855
Short name T600
Test name
Test status
Simulation time 2820610435 ps
CPU time 35.87 seconds
Started Jun 11 03:23:04 PM PDT 24
Finished Jun 11 03:23:41 PM PDT 24
Peak memory 249000 kb
Host smart-eb537517-01cf-4812-9d04-75c5192a1349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040622855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1040622855
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2309084828
Short name T938
Test name
Test status
Simulation time 175394580292 ps
CPU time 75.86 seconds
Started Jun 11 03:23:11 PM PDT 24
Finished Jun 11 03:24:28 PM PDT 24
Peak memory 224452 kb
Host smart-7c00dd23-d5be-4493-bc6a-af494db00254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309084828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2309084828
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.885540541
Short name T751
Test name
Test status
Simulation time 677031890 ps
CPU time 10.38 seconds
Started Jun 11 03:23:03 PM PDT 24
Finished Jun 11 03:23:15 PM PDT 24
Peak memory 232528 kb
Host smart-a79084a1-a1e3-4bc9-9716-5574c0ff356c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885540541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.885540541
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.189447310
Short name T213
Test name
Test status
Simulation time 1307972131 ps
CPU time 10.19 seconds
Started Jun 11 03:23:11 PM PDT 24
Finished Jun 11 03:23:21 PM PDT 24
Peak memory 224252 kb
Host smart-2cff65ec-9154-405e-b6bd-da003d3ce106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189447310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.189447310
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2349501836
Short name T169
Test name
Test status
Simulation time 23415584415 ps
CPU time 50.43 seconds
Started Jun 11 03:23:05 PM PDT 24
Finished Jun 11 03:23:57 PM PDT 24
Peak memory 232688 kb
Host smart-a75a9bbd-0639-4bbe-82c9-4a3c9e51f39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349501836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2349501836
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2463456782
Short name T278
Test name
Test status
Simulation time 11663149841 ps
CPU time 14.62 seconds
Started Jun 11 03:23:05 PM PDT 24
Finished Jun 11 03:23:21 PM PDT 24
Peak memory 240508 kb
Host smart-c1dc69ec-5ca1-4905-accb-215a0345c783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463456782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2463456782
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3082806272
Short name T416
Test name
Test status
Simulation time 52886974 ps
CPU time 2.15 seconds
Started Jun 11 03:23:02 PM PDT 24
Finished Jun 11 03:23:06 PM PDT 24
Peak memory 232348 kb
Host smart-faacf3f0-cfae-4ea4-b002-a5bd79b309ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082806272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3082806272
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3939377742
Short name T784
Test name
Test status
Simulation time 697077830 ps
CPU time 4.12 seconds
Started Jun 11 03:23:04 PM PDT 24
Finished Jun 11 03:23:10 PM PDT 24
Peak memory 221544 kb
Host smart-9a4491a3-725f-454f-86f4-7092175070d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3939377742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3939377742
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3651924263
Short name T838
Test name
Test status
Simulation time 39277545246 ps
CPU time 82.52 seconds
Started Jun 11 03:23:05 PM PDT 24
Finished Jun 11 03:24:29 PM PDT 24
Peak memory 240496 kb
Host smart-700567ed-8b57-466a-b0ac-1f9725e3d764
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651924263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3651924263
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1794501390
Short name T456
Test name
Test status
Simulation time 1629702460 ps
CPU time 16.95 seconds
Started Jun 11 03:23:03 PM PDT 24
Finished Jun 11 03:23:22 PM PDT 24
Peak memory 216260 kb
Host smart-e1c362d9-65a6-49c2-81af-6a2560c2b96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794501390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1794501390
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.589611252
Short name T605
Test name
Test status
Simulation time 2684444991 ps
CPU time 9.86 seconds
Started Jun 11 03:23:06 PM PDT 24
Finished Jun 11 03:23:18 PM PDT 24
Peak memory 216208 kb
Host smart-3ca57fb1-a40a-4492-9360-8a14a9029030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589611252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.589611252
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3128196373
Short name T778
Test name
Test status
Simulation time 36238848 ps
CPU time 1.18 seconds
Started Jun 11 03:23:01 PM PDT 24
Finished Jun 11 03:23:04 PM PDT 24
Peak memory 207784 kb
Host smart-dca5e211-3b86-454b-8d14-92628c4be7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128196373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3128196373
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1701056250
Short name T819
Test name
Test status
Simulation time 43342296 ps
CPU time 0.69 seconds
Started Jun 11 03:23:03 PM PDT 24
Finished Jun 11 03:23:06 PM PDT 24
Peak memory 205348 kb
Host smart-78158313-0494-4222-8e55-44cf121ee086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701056250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1701056250
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.898233719
Short name T960
Test name
Test status
Simulation time 7415146293 ps
CPU time 23.56 seconds
Started Jun 11 03:23:02 PM PDT 24
Finished Jun 11 03:23:27 PM PDT 24
Peak memory 232632 kb
Host smart-4ba0816f-b343-42df-a33a-93ffa9eca90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898233719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.898233719
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1853782695
Short name T922
Test name
Test status
Simulation time 17112344 ps
CPU time 0.77 seconds
Started Jun 11 03:23:07 PM PDT 24
Finished Jun 11 03:23:09 PM PDT 24
Peak memory 204688 kb
Host smart-3f4c3cbd-a4bc-426b-b186-435a91109967
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853782695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1853782695
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3139226116
Short name T911
Test name
Test status
Simulation time 197601850 ps
CPU time 4.64 seconds
Started Jun 11 03:23:09 PM PDT 24
Finished Jun 11 03:23:14 PM PDT 24
Peak memory 232664 kb
Host smart-ec955c66-6bd7-4cd3-bcbf-beca43b06b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139226116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3139226116
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2398114233
Short name T830
Test name
Test status
Simulation time 55565359 ps
CPU time 0.79 seconds
Started Jun 11 03:23:08 PM PDT 24
Finished Jun 11 03:23:09 PM PDT 24
Peak memory 206352 kb
Host smart-03385b93-7db7-4b7b-ab49-993ff24ce03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398114233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2398114233
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1155865154
Short name T216
Test name
Test status
Simulation time 8530449202 ps
CPU time 20.77 seconds
Started Jun 11 03:23:04 PM PDT 24
Finished Jun 11 03:23:26 PM PDT 24
Peak memory 240784 kb
Host smart-2ba97e4e-eab9-48d8-b45b-0afed599e332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155865154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1155865154
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1662597436
Short name T680
Test name
Test status
Simulation time 143895444320 ps
CPU time 323.86 seconds
Started Jun 11 03:23:02 PM PDT 24
Finished Jun 11 03:28:28 PM PDT 24
Peak memory 250392 kb
Host smart-4c7fe2c8-2b50-4415-aad1-7068b277ec08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662597436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1662597436
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3960097328
Short name T750
Test name
Test status
Simulation time 32600043282 ps
CPU time 93.13 seconds
Started Jun 11 03:23:03 PM PDT 24
Finished Jun 11 03:24:38 PM PDT 24
Peak memory 253592 kb
Host smart-d86366a0-a1a9-456b-8b2f-103b6c210a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960097328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3960097328
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.4191152565
Short name T586
Test name
Test status
Simulation time 680098348 ps
CPU time 15.17 seconds
Started Jun 11 03:23:01 PM PDT 24
Finished Jun 11 03:23:18 PM PDT 24
Peak memory 224328 kb
Host smart-53340151-5383-443d-a794-29b2994c71d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191152565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4191152565
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1461474818
Short name T787
Test name
Test status
Simulation time 376088756 ps
CPU time 4.89 seconds
Started Jun 11 03:23:06 PM PDT 24
Finished Jun 11 03:23:13 PM PDT 24
Peak memory 224264 kb
Host smart-2dd95aa9-1dc1-4119-8d8e-9ce1eaada732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461474818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1461474818
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.849499366
Short name T590
Test name
Test status
Simulation time 26592168425 ps
CPU time 68.67 seconds
Started Jun 11 03:23:01 PM PDT 24
Finished Jun 11 03:24:11 PM PDT 24
Peak memory 232640 kb
Host smart-58fabc00-a7fc-4716-8858-bc93be3a5277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849499366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.849499366
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.4123917493
Short name T759
Test name
Test status
Simulation time 6224250344 ps
CPU time 19.46 seconds
Started Jun 11 03:23:03 PM PDT 24
Finished Jun 11 03:23:25 PM PDT 24
Peak memory 232656 kb
Host smart-677a69d1-b901-43d5-a57d-7505d5d60f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123917493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.4123917493
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2727958588
Short name T286
Test name
Test status
Simulation time 412461798 ps
CPU time 2.97 seconds
Started Jun 11 03:23:06 PM PDT 24
Finished Jun 11 03:23:10 PM PDT 24
Peak memory 232548 kb
Host smart-190ac0dd-f574-474f-a03e-e393c2e164de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727958588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2727958588
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.4020790166
Short name T564
Test name
Test status
Simulation time 206097375 ps
CPU time 4.59 seconds
Started Jun 11 03:23:03 PM PDT 24
Finished Jun 11 03:23:10 PM PDT 24
Peak memory 222772 kb
Host smart-308140be-0fdd-4c2f-a510-450cab826c18
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4020790166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.4020790166
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2504812422
Short name T921
Test name
Test status
Simulation time 93093363870 ps
CPU time 487.01 seconds
Started Jun 11 03:23:05 PM PDT 24
Finished Jun 11 03:31:14 PM PDT 24
Peak memory 252396 kb
Host smart-992bc5d5-c42f-47d3-ab78-91dfecb717a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504812422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2504812422
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2659316278
Short name T632
Test name
Test status
Simulation time 5261771970 ps
CPU time 17.33 seconds
Started Jun 11 03:23:11 PM PDT 24
Finished Jun 11 03:23:29 PM PDT 24
Peak memory 216312 kb
Host smart-bcf02069-e451-43f1-8614-a03b2d64975a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659316278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2659316278
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2134556031
Short name T428
Test name
Test status
Simulation time 1222478355 ps
CPU time 3.48 seconds
Started Jun 11 03:23:09 PM PDT 24
Finished Jun 11 03:23:13 PM PDT 24
Peak memory 216228 kb
Host smart-ccac1763-9d1f-46ce-9a78-e3e5314eeb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134556031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2134556031
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2593225581
Short name T341
Test name
Test status
Simulation time 239053207 ps
CPU time 9.77 seconds
Started Jun 11 03:23:04 PM PDT 24
Finished Jun 11 03:23:15 PM PDT 24
Peak memory 215996 kb
Host smart-b9dd3bac-d478-404f-8714-6024cf143273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593225581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2593225581
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1858349438
Short name T448
Test name
Test status
Simulation time 70557157 ps
CPU time 0.75 seconds
Started Jun 11 03:23:04 PM PDT 24
Finished Jun 11 03:23:07 PM PDT 24
Peak memory 205668 kb
Host smart-061230d2-cd8c-41fb-9637-91b9aa93a5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858349438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1858349438
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.961408636
Short name T209
Test name
Test status
Simulation time 2740364736 ps
CPU time 11.68 seconds
Started Jun 11 03:23:04 PM PDT 24
Finished Jun 11 03:23:17 PM PDT 24
Peak memory 232628 kb
Host smart-b43cede0-d94b-41b2-b075-b8eefeaed512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961408636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.961408636
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3827124299
Short name T542
Test name
Test status
Simulation time 12516397 ps
CPU time 0.69 seconds
Started Jun 11 03:23:15 PM PDT 24
Finished Jun 11 03:23:17 PM PDT 24
Peak memory 204668 kb
Host smart-c0e05ea4-1eba-4fda-978e-6e6f9011867a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827124299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3827124299
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1406153
Short name T132
Test name
Test status
Simulation time 2760537489 ps
CPU time 7.47 seconds
Started Jun 11 03:23:19 PM PDT 24
Finished Jun 11 03:23:28 PM PDT 24
Peak memory 232572 kb
Host smart-04eeb36d-850e-40f8-8f3f-ee073d1116bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1406153
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.946577465
Short name T963
Test name
Test status
Simulation time 120498035 ps
CPU time 0.75 seconds
Started Jun 11 03:23:07 PM PDT 24
Finished Jun 11 03:23:09 PM PDT 24
Peak memory 205652 kb
Host smart-b0b5897c-4eb6-4bf2-b0d9-784cc0bd1c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946577465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.946577465
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3309453823
Short name T88
Test name
Test status
Simulation time 45492148234 ps
CPU time 97.13 seconds
Started Jun 11 03:23:15 PM PDT 24
Finished Jun 11 03:24:54 PM PDT 24
Peak memory 232644 kb
Host smart-7eb1d4d5-eb53-44b5-8400-2b04553ac077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309453823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3309453823
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2106970998
Short name T434
Test name
Test status
Simulation time 2241039049 ps
CPU time 41.52 seconds
Started Jun 11 03:23:17 PM PDT 24
Finished Jun 11 03:24:00 PM PDT 24
Peak memory 249316 kb
Host smart-13762e6f-c712-450f-a367-720dccb6f9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106970998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2106970998
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2920184405
Short name T51
Test name
Test status
Simulation time 1790485676 ps
CPU time 8.77 seconds
Started Jun 11 03:23:17 PM PDT 24
Finished Jun 11 03:23:28 PM PDT 24
Peak memory 232536 kb
Host smart-fadfc183-2ab9-4fd2-a837-ff7ece0f9f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920184405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2920184405
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3744546173
Short name T705
Test name
Test status
Simulation time 1082104063 ps
CPU time 3.67 seconds
Started Jun 11 03:23:15 PM PDT 24
Finished Jun 11 03:23:20 PM PDT 24
Peak memory 224296 kb
Host smart-d6882cc7-134d-4604-89da-d903a6315d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744546173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3744546173
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.391307417
Short name T689
Test name
Test status
Simulation time 5528370326 ps
CPU time 62.88 seconds
Started Jun 11 03:23:16 PM PDT 24
Finished Jun 11 03:24:21 PM PDT 24
Peak memory 224352 kb
Host smart-b1d867a2-8d41-406b-94a9-c5ebde02d860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391307417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.391307417
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3461812872
Short name T656
Test name
Test status
Simulation time 1595377372 ps
CPU time 6.59 seconds
Started Jun 11 03:23:17 PM PDT 24
Finished Jun 11 03:23:25 PM PDT 24
Peak memory 226600 kb
Host smart-2892b89c-ecc5-482c-9643-8c04b17d94c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461812872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3461812872
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2058393443
Short name T793
Test name
Test status
Simulation time 13867403508 ps
CPU time 10.33 seconds
Started Jun 11 03:23:14 PM PDT 24
Finished Jun 11 03:23:26 PM PDT 24
Peak memory 224456 kb
Host smart-3256060e-7d27-485e-9b12-c94041e6ebac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058393443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2058393443
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1882526315
Short name T531
Test name
Test status
Simulation time 778322657 ps
CPU time 9.3 seconds
Started Jun 11 03:23:18 PM PDT 24
Finished Jun 11 03:23:29 PM PDT 24
Peak memory 222732 kb
Host smart-0dbb5d4f-51f4-4f41-8ddf-6268a93a39a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1882526315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1882526315
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3373279604
Short name T415
Test name
Test status
Simulation time 49172016 ps
CPU time 1.01 seconds
Started Jun 11 03:23:19 PM PDT 24
Finished Jun 11 03:23:22 PM PDT 24
Peak memory 206768 kb
Host smart-37e731d6-af17-4afa-8409-7e104b01cb03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373279604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3373279604
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3563161860
Short name T417
Test name
Test status
Simulation time 2840569815 ps
CPU time 4.76 seconds
Started Jun 11 03:23:05 PM PDT 24
Finished Jun 11 03:23:11 PM PDT 24
Peak memory 219484 kb
Host smart-a93ccbee-e633-4001-8d04-a31c59060e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563161860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3563161860
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2287412108
Short name T690
Test name
Test status
Simulation time 578085421 ps
CPU time 3.5 seconds
Started Jun 11 03:23:08 PM PDT 24
Finished Jun 11 03:23:13 PM PDT 24
Peak memory 215960 kb
Host smart-b5621b2c-3638-4bc9-8799-877b32a711f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287412108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2287412108
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3202774448
Short name T544
Test name
Test status
Simulation time 240913332 ps
CPU time 3.02 seconds
Started Jun 11 03:23:15 PM PDT 24
Finished Jun 11 03:23:20 PM PDT 24
Peak memory 216076 kb
Host smart-c0bd8ef1-2d22-444a-a960-09ed7848dbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202774448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3202774448
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3516856290
Short name T540
Test name
Test status
Simulation time 39380515 ps
CPU time 0.82 seconds
Started Jun 11 03:23:04 PM PDT 24
Finished Jun 11 03:23:07 PM PDT 24
Peak memory 205608 kb
Host smart-9f582148-7242-4535-a9d1-fd4eef0b4a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516856290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3516856290
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.4003189489
Short name T660
Test name
Test status
Simulation time 439466552 ps
CPU time 2.7 seconds
Started Jun 11 03:23:18 PM PDT 24
Finished Jun 11 03:23:23 PM PDT 24
Peak memory 224336 kb
Host smart-2484d1ea-7413-43ad-940d-b7accc252b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003189489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.4003189489
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1730991697
Short name T351
Test name
Test status
Simulation time 20117719 ps
CPU time 0.71 seconds
Started Jun 11 03:23:16 PM PDT 24
Finished Jun 11 03:23:18 PM PDT 24
Peak memory 205284 kb
Host smart-3275ffe7-0d79-4759-8727-19753d1ce4d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730991697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1730991697
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3477950833
Short name T263
Test name
Test status
Simulation time 902835829 ps
CPU time 5.18 seconds
Started Jun 11 03:23:16 PM PDT 24
Finished Jun 11 03:23:23 PM PDT 24
Peak memory 232576 kb
Host smart-ad8e767d-5ecf-4616-8f33-82b620a6523e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477950833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3477950833
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1610424686
Short name T515
Test name
Test status
Simulation time 15096444 ps
CPU time 0.76 seconds
Started Jun 11 03:23:17 PM PDT 24
Finished Jun 11 03:23:20 PM PDT 24
Peak memory 205672 kb
Host smart-71b681fa-0012-45b3-96c5-78f443c1750c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610424686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1610424686
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3091475619
Short name T647
Test name
Test status
Simulation time 22243996655 ps
CPU time 61.26 seconds
Started Jun 11 03:23:16 PM PDT 24
Finished Jun 11 03:24:19 PM PDT 24
Peak memory 249536 kb
Host smart-f8a7ced1-84e2-445a-9d50-7da9cff28b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091475619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3091475619
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2097948739
Short name T247
Test name
Test status
Simulation time 5087057420 ps
CPU time 65.45 seconds
Started Jun 11 03:23:17 PM PDT 24
Finished Jun 11 03:24:24 PM PDT 24
Peak memory 249016 kb
Host smart-d6726932-0dbd-42eb-97ad-771a2a74fb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097948739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2097948739
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.4240583617
Short name T326
Test name
Test status
Simulation time 1803753239 ps
CPU time 9.14 seconds
Started Jun 11 03:23:20 PM PDT 24
Finished Jun 11 03:23:32 PM PDT 24
Peak memory 240752 kb
Host smart-4f3e0c88-58ff-41b3-addd-f8bfba253766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240583617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4240583617
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3178407839
Short name T663
Test name
Test status
Simulation time 2003326663 ps
CPU time 16.39 seconds
Started Jun 11 03:23:17 PM PDT 24
Finished Jun 11 03:23:35 PM PDT 24
Peak memory 224296 kb
Host smart-57b057fb-4a01-42cd-81f2-60af824ac4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178407839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3178407839
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2812269347
Short name T284
Test name
Test status
Simulation time 452088182 ps
CPU time 13.31 seconds
Started Jun 11 03:23:16 PM PDT 24
Finished Jun 11 03:23:30 PM PDT 24
Peak memory 248496 kb
Host smart-3de39bbc-0a08-4eda-ac6f-c97aa06ab961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812269347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2812269347
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2554653886
Short name T257
Test name
Test status
Simulation time 689099880 ps
CPU time 3.01 seconds
Started Jun 11 03:23:18 PM PDT 24
Finished Jun 11 03:23:23 PM PDT 24
Peak memory 224356 kb
Host smart-6e8f043a-3db0-423c-8af7-5f8084b8dfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554653886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2554653886
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.923803543
Short name T968
Test name
Test status
Simulation time 382794891 ps
CPU time 2.57 seconds
Started Jun 11 03:23:19 PM PDT 24
Finished Jun 11 03:23:24 PM PDT 24
Peak memory 224332 kb
Host smart-cdd0acf8-ebf4-4504-a108-74a0f6655c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923803543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.923803543
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3835887119
Short name T621
Test name
Test status
Simulation time 12067734275 ps
CPU time 14.17 seconds
Started Jun 11 03:23:17 PM PDT 24
Finished Jun 11 03:23:33 PM PDT 24
Peak memory 223040 kb
Host smart-a99d5b5a-0622-4fe1-a3a5-232349cacd12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3835887119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3835887119
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3535733242
Short name T895
Test name
Test status
Simulation time 23984811840 ps
CPU time 39.49 seconds
Started Jun 11 03:23:17 PM PDT 24
Finished Jun 11 03:23:58 PM PDT 24
Peak memory 216216 kb
Host smart-9c9161c5-4e66-46b9-9119-2844ef853cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535733242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3535733242
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3260227377
Short name T163
Test name
Test status
Simulation time 3010213277 ps
CPU time 4.48 seconds
Started Jun 11 03:23:15 PM PDT 24
Finished Jun 11 03:23:21 PM PDT 24
Peak memory 216172 kb
Host smart-601e496d-734d-4430-bf06-36cf61e540e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260227377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3260227377
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2763162937
Short name T646
Test name
Test status
Simulation time 120084456 ps
CPU time 0.82 seconds
Started Jun 11 03:23:18 PM PDT 24
Finished Jun 11 03:23:21 PM PDT 24
Peak memory 205696 kb
Host smart-6371a3c4-df4c-40dc-9886-3f0586e45c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763162937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2763162937
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.775284727
Short name T429
Test name
Test status
Simulation time 228486415 ps
CPU time 0.92 seconds
Started Jun 11 03:23:19 PM PDT 24
Finished Jun 11 03:23:22 PM PDT 24
Peak memory 206720 kb
Host smart-ab77c0a9-34cd-4176-b003-7537cdaa28a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775284727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.775284727
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3840396701
Short name T978
Test name
Test status
Simulation time 576778975 ps
CPU time 8.46 seconds
Started Jun 11 03:23:15 PM PDT 24
Finished Jun 11 03:23:25 PM PDT 24
Peak memory 232516 kb
Host smart-d55bb92b-7dce-470e-a448-7b4ec5e84822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840396701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3840396701
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3604414908
Short name T977
Test name
Test status
Simulation time 13550335 ps
CPU time 0.76 seconds
Started Jun 11 03:23:29 PM PDT 24
Finished Jun 11 03:23:31 PM PDT 24
Peak memory 204748 kb
Host smart-4a36e3d7-caa5-4af5-8dc3-376f8edfb623
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604414908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3604414908
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1276553133
Short name T939
Test name
Test status
Simulation time 61531625 ps
CPU time 2.6 seconds
Started Jun 11 03:23:16 PM PDT 24
Finished Jun 11 03:23:20 PM PDT 24
Peak memory 232336 kb
Host smart-dd432ff2-38bf-4ac9-8b52-2bfa6eec0332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276553133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1276553133
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.191869424
Short name T437
Test name
Test status
Simulation time 12812320 ps
CPU time 0.78 seconds
Started Jun 11 03:23:18 PM PDT 24
Finished Jun 11 03:23:21 PM PDT 24
Peak memory 205336 kb
Host smart-c68300fc-a277-41c7-8754-32f2d44974a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191869424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.191869424
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3708050975
Short name T814
Test name
Test status
Simulation time 285758319814 ps
CPU time 359.25 seconds
Started Jun 11 03:23:19 PM PDT 24
Finished Jun 11 03:29:21 PM PDT 24
Peak memory 263040 kb
Host smart-7fb95a6d-37ed-40cc-8ed3-62f8893092fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708050975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3708050975
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2437179669
Short name T421
Test name
Test status
Simulation time 2904009626 ps
CPU time 6.89 seconds
Started Jun 11 03:23:15 PM PDT 24
Finished Jun 11 03:23:23 PM PDT 24
Peak memory 232660 kb
Host smart-ba42574b-0310-48ca-a062-3f1547554b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437179669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2437179669
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3461960160
Short name T611
Test name
Test status
Simulation time 8188951567 ps
CPU time 20.35 seconds
Started Jun 11 03:23:16 PM PDT 24
Finished Jun 11 03:23:39 PM PDT 24
Peak memory 232672 kb
Host smart-2989fb5f-15e5-4f67-bafb-a7d59f1133f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461960160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3461960160
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3759845227
Short name T2
Test name
Test status
Simulation time 56586636 ps
CPU time 2.45 seconds
Started Jun 11 03:23:20 PM PDT 24
Finished Jun 11 03:23:24 PM PDT 24
Peak memory 232380 kb
Host smart-ad88d0f0-ceb0-4162-a700-9cb6e1c32902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759845227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3759845227
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2826542655
Short name T320
Test name
Test status
Simulation time 7763524167 ps
CPU time 19.02 seconds
Started Jun 11 03:23:17 PM PDT 24
Finished Jun 11 03:23:39 PM PDT 24
Peak memory 224388 kb
Host smart-0b69078d-ce10-4daa-a875-452cd9c93843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826542655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2826542655
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.4287993190
Short name T574
Test name
Test status
Simulation time 11733534511 ps
CPU time 11.7 seconds
Started Jun 11 03:23:17 PM PDT 24
Finished Jun 11 03:23:30 PM PDT 24
Peak memory 240600 kb
Host smart-534be354-3420-4b24-8a85-49e7a0491cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287993190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.4287993190
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3032501512
Short name T401
Test name
Test status
Simulation time 233435322 ps
CPU time 5.55 seconds
Started Jun 11 03:23:17 PM PDT 24
Finished Jun 11 03:23:25 PM PDT 24
Peak memory 221996 kb
Host smart-f45bee77-c205-4f5b-b7a6-366767093ccf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3032501512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3032501512
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2921729523
Short name T867
Test name
Test status
Simulation time 18235476028 ps
CPU time 42.16 seconds
Started Jun 11 03:23:16 PM PDT 24
Finished Jun 11 03:24:00 PM PDT 24
Peak memory 216128 kb
Host smart-1b7baf7d-a3c7-40e3-926d-27739217be67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921729523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2921729523
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3870159043
Short name T860
Test name
Test status
Simulation time 3100830046 ps
CPU time 9.53 seconds
Started Jun 11 03:23:15 PM PDT 24
Finished Jun 11 03:23:26 PM PDT 24
Peak memory 216248 kb
Host smart-ca885fa5-5078-4fb2-ac5e-23c2e35ff65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870159043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3870159043
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2388842672
Short name T462
Test name
Test status
Simulation time 25015538 ps
CPU time 0.71 seconds
Started Jun 11 03:23:17 PM PDT 24
Finished Jun 11 03:23:20 PM PDT 24
Peak memory 205336 kb
Host smart-5d2fb05e-8354-44ba-91b7-ee78d77448dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388842672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2388842672
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1609563820
Short name T87
Test name
Test status
Simulation time 55103683 ps
CPU time 0.72 seconds
Started Jun 11 03:23:15 PM PDT 24
Finished Jun 11 03:23:17 PM PDT 24
Peak memory 205700 kb
Host smart-14fbd407-1cdc-41c1-a7ac-ce3ead1e6738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609563820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1609563820
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2915533954
Short name T514
Test name
Test status
Simulation time 294605138 ps
CPU time 5.68 seconds
Started Jun 11 03:23:17 PM PDT 24
Finished Jun 11 03:23:25 PM PDT 24
Peak memory 232576 kb
Host smart-e2c81188-94b3-4ba9-9a4d-01f790c865d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915533954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2915533954
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.498785283
Short name T832
Test name
Test status
Simulation time 11410070 ps
CPU time 0.71 seconds
Started Jun 11 03:21:33 PM PDT 24
Finished Jun 11 03:21:36 PM PDT 24
Peak memory 204704 kb
Host smart-b53dd34d-978e-4df3-bab9-b261200700ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498785283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.498785283
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2065830048
Short name T757
Test name
Test status
Simulation time 120350716 ps
CPU time 2.68 seconds
Started Jun 11 03:21:33 PM PDT 24
Finished Jun 11 03:21:38 PM PDT 24
Peak memory 224288 kb
Host smart-5c0c74a1-0ac2-48be-971a-d4176397d81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065830048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2065830048
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2287448124
Short name T443
Test name
Test status
Simulation time 15550157 ps
CPU time 0.79 seconds
Started Jun 11 03:21:30 PM PDT 24
Finished Jun 11 03:21:33 PM PDT 24
Peak memory 205644 kb
Host smart-d336efac-80b4-422e-89e9-e824e8d84608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287448124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2287448124
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.583205993
Short name T899
Test name
Test status
Simulation time 3262213349 ps
CPU time 55.82 seconds
Started Jun 11 03:21:33 PM PDT 24
Finished Jun 11 03:22:31 PM PDT 24
Peak memory 249008 kb
Host smart-a69a32f0-ddd8-42af-80b0-ae90675d096d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583205993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.583205993
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2307670061
Short name T490
Test name
Test status
Simulation time 5898323769 ps
CPU time 36.49 seconds
Started Jun 11 03:21:32 PM PDT 24
Finished Jun 11 03:22:11 PM PDT 24
Peak memory 233672 kb
Host smart-2b502321-7449-4b7d-a187-b02f3968ffc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307670061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2307670061
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.489977563
Short name T333
Test name
Test status
Simulation time 2559206330 ps
CPU time 27.14 seconds
Started Jun 11 03:21:33 PM PDT 24
Finished Jun 11 03:22:03 PM PDT 24
Peak memory 217224 kb
Host smart-5f1ab332-35d8-4c37-bd58-64738fd32702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489977563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
489977563
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3290732124
Short name T834
Test name
Test status
Simulation time 64752490 ps
CPU time 3.33 seconds
Started Jun 11 03:21:32 PM PDT 24
Finished Jun 11 03:21:37 PM PDT 24
Peak memory 232524 kb
Host smart-81a55f13-c2c0-4ca7-8275-a9ef0f5cfc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290732124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3290732124
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.661921853
Short name T844
Test name
Test status
Simulation time 174481231 ps
CPU time 5.01 seconds
Started Jun 11 03:21:32 PM PDT 24
Finished Jun 11 03:21:39 PM PDT 24
Peak memory 232456 kb
Host smart-2876e1ef-c7fe-4f92-9278-e9761fe0ed2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661921853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.661921853
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2881273455
Short name T912
Test name
Test status
Simulation time 1691715910 ps
CPU time 16.95 seconds
Started Jun 11 03:21:31 PM PDT 24
Finished Jun 11 03:21:50 PM PDT 24
Peak memory 232472 kb
Host smart-8add5b84-f885-4079-8a4e-d85eccfe7339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881273455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2881273455
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3754306787
Short name T965
Test name
Test status
Simulation time 21525077 ps
CPU time 1.08 seconds
Started Jun 11 03:21:30 PM PDT 24
Finished Jun 11 03:21:34 PM PDT 24
Peak memory 216488 kb
Host smart-22a5f193-35d7-43f0-9f3b-a457cb1b2324
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754306787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3754306787
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1866491357
Short name T547
Test name
Test status
Simulation time 367768277 ps
CPU time 2.17 seconds
Started Jun 11 03:21:32 PM PDT 24
Finished Jun 11 03:21:37 PM PDT 24
Peak memory 223896 kb
Host smart-a0c94f8f-10f4-4e43-8d72-207d4b66c090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866491357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1866491357
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1565375249
Short name T9
Test name
Test status
Simulation time 4749112346 ps
CPU time 6.19 seconds
Started Jun 11 03:21:31 PM PDT 24
Finished Jun 11 03:21:39 PM PDT 24
Peak memory 232612 kb
Host smart-e33efe1d-98c4-449e-a0bc-f9c9da1e99a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565375249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1565375249
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2929530004
Short name T702
Test name
Test status
Simulation time 4627994998 ps
CPU time 7.55 seconds
Started Jun 11 03:21:32 PM PDT 24
Finished Jun 11 03:21:42 PM PDT 24
Peak memory 223188 kb
Host smart-4f1fd25a-a7f8-4373-80eb-300b3d6b15ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2929530004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2929530004
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.43611931
Short name T75
Test name
Test status
Simulation time 37938325 ps
CPU time 1 seconds
Started Jun 11 03:21:32 PM PDT 24
Finished Jun 11 03:21:35 PM PDT 24
Peak memory 235468 kb
Host smart-7d05a665-7deb-432c-90ea-b8534802a3d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43611931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.43611931
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3768145336
Short name T17
Test name
Test status
Simulation time 3345435871 ps
CPU time 68.43 seconds
Started Jun 11 03:21:36 PM PDT 24
Finished Jun 11 03:22:46 PM PDT 24
Peak memory 252316 kb
Host smart-e1add474-7aed-4a86-9ade-a80e2e860cf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768145336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3768145336
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.4181292277
Short name T338
Test name
Test status
Simulation time 20020088204 ps
CPU time 15.33 seconds
Started Jun 11 03:21:29 PM PDT 24
Finished Jun 11 03:21:47 PM PDT 24
Peak memory 217344 kb
Host smart-af5e3c5f-c90d-4da3-ba32-3060e7cbf798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181292277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.4181292277
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.396607138
Short name T713
Test name
Test status
Simulation time 2610385153 ps
CPU time 8.97 seconds
Started Jun 11 03:21:30 PM PDT 24
Finished Jun 11 03:21:42 PM PDT 24
Peak memory 216128 kb
Host smart-2802f684-6a08-422d-adb8-aa95728eb085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396607138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.396607138
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3286878698
Short name T875
Test name
Test status
Simulation time 282774649 ps
CPU time 2.9 seconds
Started Jun 11 03:21:33 PM PDT 24
Finished Jun 11 03:21:38 PM PDT 24
Peak memory 215992 kb
Host smart-e661deeb-c3d6-477a-b398-c9c737ff2b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286878698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3286878698
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.18336653
Short name T511
Test name
Test status
Simulation time 348533346 ps
CPU time 0.89 seconds
Started Jun 11 03:21:33 PM PDT 24
Finished Jun 11 03:21:36 PM PDT 24
Peak memory 205672 kb
Host smart-4026250b-fa76-4a4e-931f-ecd4a506a120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18336653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.18336653
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3016551139
Short name T289
Test name
Test status
Simulation time 341516261 ps
CPU time 3.87 seconds
Started Jun 11 03:21:31 PM PDT 24
Finished Jun 11 03:21:37 PM PDT 24
Peak memory 232564 kb
Host smart-7cda4e95-03f9-4ce1-b2db-fc89c22f8611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016551139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3016551139
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2087789516
Short name T897
Test name
Test status
Simulation time 41127848 ps
CPU time 0.69 seconds
Started Jun 11 03:23:27 PM PDT 24
Finished Jun 11 03:23:29 PM PDT 24
Peak memory 204672 kb
Host smart-d45ccd9e-1de7-40ea-98cd-3c65b8a296e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087789516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2087789516
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.4245345835
Short name T484
Test name
Test status
Simulation time 223482658 ps
CPU time 3.25 seconds
Started Jun 11 03:23:26 PM PDT 24
Finished Jun 11 03:23:30 PM PDT 24
Peak memory 224320 kb
Host smart-92481eef-0eec-464c-884a-80c0828b26e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245345835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.4245345835
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2446265632
Short name T959
Test name
Test status
Simulation time 58418199 ps
CPU time 0.78 seconds
Started Jun 11 03:23:25 PM PDT 24
Finished Jun 11 03:23:28 PM PDT 24
Peak memory 206376 kb
Host smart-e384096b-7178-4e05-8474-a778b9804e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446265632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2446265632
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.935361119
Short name T842
Test name
Test status
Simulation time 72428335294 ps
CPU time 160.34 seconds
Started Jun 11 03:23:35 PM PDT 24
Finished Jun 11 03:26:17 PM PDT 24
Peak memory 252208 kb
Host smart-d70a68c5-8a35-4c77-b00f-283ebf6f514a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935361119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.935361119
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.526223934
Short name T14
Test name
Test status
Simulation time 14495099502 ps
CPU time 113.63 seconds
Started Jun 11 03:23:25 PM PDT 24
Finished Jun 11 03:25:20 PM PDT 24
Peak memory 240888 kb
Host smart-ff9f2822-c0ae-4fa6-9e7e-32b6b44f8bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526223934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.526223934
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1373202216
Short name T297
Test name
Test status
Simulation time 74563632968 ps
CPU time 195.59 seconds
Started Jun 11 03:23:26 PM PDT 24
Finished Jun 11 03:26:43 PM PDT 24
Peak memory 254380 kb
Host smart-34a1d65b-5d36-436b-b597-4f371af141d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373202216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1373202216
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2169986036
Short name T403
Test name
Test status
Simulation time 2473745916 ps
CPU time 23.49 seconds
Started Jun 11 03:23:26 PM PDT 24
Finished Jun 11 03:23:51 PM PDT 24
Peak memory 240812 kb
Host smart-59feae8e-7015-47a0-af2d-d86162b195c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169986036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2169986036
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1147821838
Short name T454
Test name
Test status
Simulation time 1029995566 ps
CPU time 14.71 seconds
Started Jun 11 03:23:25 PM PDT 24
Finished Jun 11 03:23:42 PM PDT 24
Peak memory 224316 kb
Host smart-aee6bedf-1285-4f65-94db-71e0d67fd506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147821838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1147821838
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3938673157
Short name T231
Test name
Test status
Simulation time 268678139 ps
CPU time 2.71 seconds
Started Jun 11 03:23:24 PM PDT 24
Finished Jun 11 03:23:29 PM PDT 24
Peak memory 232540 kb
Host smart-8526a419-5d51-4082-9612-636d95968a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938673157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3938673157
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.581365093
Short name T67
Test name
Test status
Simulation time 162138174816 ps
CPU time 27.78 seconds
Started Jun 11 03:23:27 PM PDT 24
Finished Jun 11 03:23:56 PM PDT 24
Peak memory 224416 kb
Host smart-27e2b930-80dc-4bbc-b575-1e044bfc246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581365093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.581365093
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.4235249387
Short name T760
Test name
Test status
Simulation time 361810053 ps
CPU time 3.2 seconds
Started Jun 11 03:23:26 PM PDT 24
Finished Jun 11 03:23:31 PM PDT 24
Peak memory 232728 kb
Host smart-9b01e514-d92b-40c6-b2fe-900d27b699b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235249387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.4235249387
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1740942108
Short name T776
Test name
Test status
Simulation time 241095057 ps
CPU time 4.14 seconds
Started Jun 11 03:23:26 PM PDT 24
Finished Jun 11 03:23:31 PM PDT 24
Peak memory 218684 kb
Host smart-1a06345b-3621-4735-9ab0-28485f4d3cf2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1740942108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1740942108
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3900137900
Short name T321
Test name
Test status
Simulation time 50239072291 ps
CPU time 345.51 seconds
Started Jun 11 03:23:29 PM PDT 24
Finished Jun 11 03:29:16 PM PDT 24
Peak memory 266940 kb
Host smart-164304c5-7364-488f-af35-749f61b8e24b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900137900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3900137900
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.583101230
Short name T336
Test name
Test status
Simulation time 9284368231 ps
CPU time 49.67 seconds
Started Jun 11 03:23:26 PM PDT 24
Finished Jun 11 03:24:17 PM PDT 24
Peak memory 216120 kb
Host smart-7b84e6ee-dc86-43fc-8e5c-1369ab111c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583101230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.583101230
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.632847063
Short name T375
Test name
Test status
Simulation time 7433678711 ps
CPU time 17.47 seconds
Started Jun 11 03:23:23 PM PDT 24
Finished Jun 11 03:23:42 PM PDT 24
Peak memory 216120 kb
Host smart-d0ef455d-d4ab-4194-a61e-243d66089ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632847063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.632847063
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1619653650
Short name T852
Test name
Test status
Simulation time 241441648 ps
CPU time 2.55 seconds
Started Jun 11 03:23:31 PM PDT 24
Finished Jun 11 03:23:35 PM PDT 24
Peak memory 216092 kb
Host smart-9be2f3c2-1e2e-4357-9f8c-acff1671d8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619653650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1619653650
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.917582175
Short name T955
Test name
Test status
Simulation time 64018750 ps
CPU time 0.88 seconds
Started Jun 11 03:23:24 PM PDT 24
Finished Jun 11 03:23:27 PM PDT 24
Peak memory 205692 kb
Host smart-6fdca895-8641-49d9-8599-c5e5d5ad78e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917582175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.917582175
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.957923147
Short name T290
Test name
Test status
Simulation time 269462140 ps
CPU time 4.9 seconds
Started Jun 11 03:23:30 PM PDT 24
Finished Jun 11 03:23:36 PM PDT 24
Peak memory 224352 kb
Host smart-8664c431-55a3-43fe-baf6-85e38153b8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957923147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.957923147
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.830943139
Short name T790
Test name
Test status
Simulation time 13783293 ps
CPU time 0.79 seconds
Started Jun 11 03:23:23 PM PDT 24
Finished Jun 11 03:23:26 PM PDT 24
Peak memory 205312 kb
Host smart-8eea65d6-931d-469f-b2da-5bfbffe446f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830943139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.830943139
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3407504782
Short name T879
Test name
Test status
Simulation time 293975454 ps
CPU time 2.73 seconds
Started Jun 11 03:23:32 PM PDT 24
Finished Jun 11 03:23:36 PM PDT 24
Peak memory 224364 kb
Host smart-e4788b45-5e67-4d61-9014-c3bf8e5fa722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407504782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3407504782
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2920105389
Short name T923
Test name
Test status
Simulation time 15596260 ps
CPU time 0.71 seconds
Started Jun 11 03:23:24 PM PDT 24
Finished Jun 11 03:23:26 PM PDT 24
Peak memory 205316 kb
Host smart-79fbbdc6-201c-4a19-a27e-8179698fc9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920105389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2920105389
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.237968136
Short name T641
Test name
Test status
Simulation time 17242615196 ps
CPU time 85.01 seconds
Started Jun 11 03:23:35 PM PDT 24
Finished Jun 11 03:25:02 PM PDT 24
Peak memory 249432 kb
Host smart-d87cb5b4-1680-44f2-8c3f-039f5a05b74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237968136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.237968136
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.4282582821
Short name T177
Test name
Test status
Simulation time 9270191386 ps
CPU time 40.86 seconds
Started Jun 11 03:23:26 PM PDT 24
Finished Jun 11 03:24:09 PM PDT 24
Peak memory 239948 kb
Host smart-2f21c1cd-c36f-4d78-84fd-8ad2f0377a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282582821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.4282582821
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.658191239
Short name T652
Test name
Test status
Simulation time 729508954 ps
CPU time 13.04 seconds
Started Jun 11 03:23:26 PM PDT 24
Finished Jun 11 03:23:40 PM PDT 24
Peak memory 232504 kb
Host smart-a65a3516-45a5-4dd8-a715-a250ec08ace4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658191239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.658191239
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2117049947
Short name T532
Test name
Test status
Simulation time 427948780 ps
CPU time 3.09 seconds
Started Jun 11 03:23:31 PM PDT 24
Finished Jun 11 03:23:36 PM PDT 24
Peak memory 224316 kb
Host smart-c275e0e0-f053-4473-977e-eb44e483dbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117049947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2117049947
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3677907977
Short name T243
Test name
Test status
Simulation time 1827520187 ps
CPU time 19.58 seconds
Started Jun 11 03:23:25 PM PDT 24
Finished Jun 11 03:23:46 PM PDT 24
Peak memory 232460 kb
Host smart-17c383cd-4200-4a17-a4d8-569e1242b82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677907977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3677907977
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3925100198
Short name T10
Test name
Test status
Simulation time 1288155005 ps
CPU time 4.78 seconds
Started Jun 11 03:23:29 PM PDT 24
Finished Jun 11 03:23:36 PM PDT 24
Peak memory 232516 kb
Host smart-5b5e3149-c1b0-403e-9223-cb115cd02723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925100198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3925100198
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3593918687
Short name T524
Test name
Test status
Simulation time 2558828530 ps
CPU time 10.8 seconds
Started Jun 11 03:23:31 PM PDT 24
Finished Jun 11 03:23:43 PM PDT 24
Peak memory 240156 kb
Host smart-1708f90a-21f6-4721-85b3-8bd8f5dd9fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593918687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3593918687
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2271174398
Short name T931
Test name
Test status
Simulation time 792631223 ps
CPU time 4.21 seconds
Started Jun 11 03:23:28 PM PDT 24
Finished Jun 11 03:23:33 PM PDT 24
Peak memory 219124 kb
Host smart-91023367-03f7-4289-aebe-27e43e972fea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2271174398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2271174398
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2229928975
Short name T141
Test name
Test status
Simulation time 39208543475 ps
CPU time 135.99 seconds
Started Jun 11 03:23:27 PM PDT 24
Finished Jun 11 03:25:44 PM PDT 24
Peak memory 257116 kb
Host smart-825f63fc-8777-4f67-87fb-02ab58124ceb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229928975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2229928975
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3713404551
Short name T815
Test name
Test status
Simulation time 7252911818 ps
CPU time 27.34 seconds
Started Jun 11 03:23:25 PM PDT 24
Finished Jun 11 03:23:54 PM PDT 24
Peak memory 216236 kb
Host smart-07b70eb4-9222-4d02-a66c-c5c6e5ef6bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713404551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3713404551
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2576050435
Short name T742
Test name
Test status
Simulation time 43598479531 ps
CPU time 19.32 seconds
Started Jun 11 03:23:25 PM PDT 24
Finished Jun 11 03:23:46 PM PDT 24
Peak memory 216148 kb
Host smart-748e9c5c-ad83-48cc-8f1f-93dbd076655f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576050435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2576050435
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3128588098
Short name T835
Test name
Test status
Simulation time 10414128 ps
CPU time 0.69 seconds
Started Jun 11 03:23:34 PM PDT 24
Finished Jun 11 03:23:37 PM PDT 24
Peak memory 205416 kb
Host smart-c28791b0-8028-4c27-9f9c-7d4d9189508f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128588098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3128588098
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2448918203
Short name T618
Test name
Test status
Simulation time 157905413 ps
CPU time 0.81 seconds
Started Jun 11 03:23:28 PM PDT 24
Finished Jun 11 03:23:30 PM PDT 24
Peak memory 205676 kb
Host smart-533aef1f-3f34-4b13-83da-3b85c1613152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448918203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2448918203
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3401054109
Short name T856
Test name
Test status
Simulation time 30142750495 ps
CPU time 9.86 seconds
Started Jun 11 03:23:23 PM PDT 24
Finished Jun 11 03:23:35 PM PDT 24
Peak memory 224448 kb
Host smart-36aa63e3-6bfa-4b95-a67f-66f1d72e76c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401054109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3401054109
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2037985359
Short name T445
Test name
Test status
Simulation time 14137056 ps
CPU time 0.74 seconds
Started Jun 11 03:23:35 PM PDT 24
Finished Jun 11 03:23:38 PM PDT 24
Peak memory 204728 kb
Host smart-c35e014c-6fe3-40f8-b79f-a6a5af989c3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037985359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2037985359
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1772387038
Short name T628
Test name
Test status
Simulation time 982684156 ps
CPU time 4.82 seconds
Started Jun 11 03:23:34 PM PDT 24
Finished Jun 11 03:23:40 PM PDT 24
Peak memory 232496 kb
Host smart-986eda94-d9af-448d-9d18-005a6a17ac9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772387038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1772387038
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2758289620
Short name T913
Test name
Test status
Simulation time 38562910 ps
CPU time 0.84 seconds
Started Jun 11 03:23:26 PM PDT 24
Finished Jun 11 03:23:28 PM PDT 24
Peak memory 206428 kb
Host smart-de966086-f293-487d-9a47-ad25b45e3d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758289620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2758289620
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1898400064
Short name T44
Test name
Test status
Simulation time 8343547515 ps
CPU time 38.32 seconds
Started Jun 11 03:23:36 PM PDT 24
Finished Jun 11 03:24:16 PM PDT 24
Peak memory 249272 kb
Host smart-b78651ed-8c45-47e4-91c7-2054364ac1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898400064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1898400064
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3600691334
Short name T242
Test name
Test status
Simulation time 2971920718 ps
CPU time 61.25 seconds
Started Jun 11 03:23:33 PM PDT 24
Finished Jun 11 03:24:36 PM PDT 24
Peak memory 252196 kb
Host smart-f8b71f58-52c0-449b-b376-f6cb382082c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600691334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3600691334
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3903834493
Short name T245
Test name
Test status
Simulation time 4338732470 ps
CPU time 62.07 seconds
Started Jun 11 03:23:34 PM PDT 24
Finished Jun 11 03:24:38 PM PDT 24
Peak memory 255376 kb
Host smart-a60982a7-688b-4761-b86e-d1f86d4741c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903834493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3903834493
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2093738018
Short name T620
Test name
Test status
Simulation time 251005141 ps
CPU time 3.81 seconds
Started Jun 11 03:23:33 PM PDT 24
Finished Jun 11 03:23:38 PM PDT 24
Peak memory 237448 kb
Host smart-d76b69da-422b-41ab-9074-e295828ef6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093738018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2093738018
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3836939626
Short name T901
Test name
Test status
Simulation time 124920939 ps
CPU time 3.57 seconds
Started Jun 11 03:23:24 PM PDT 24
Finished Jun 11 03:23:29 PM PDT 24
Peak memory 232544 kb
Host smart-112484ec-dce4-4f3b-9afa-f51e8bb19c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836939626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3836939626
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3978515620
Short name T770
Test name
Test status
Simulation time 30663689563 ps
CPU time 63.42 seconds
Started Jun 11 03:23:36 PM PDT 24
Finished Jun 11 03:24:41 PM PDT 24
Peak memory 240772 kb
Host smart-3c1d7c87-f35b-47c0-96b0-ca2d10ce4e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978515620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3978515620
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3874908602
Short name T322
Test name
Test status
Simulation time 16517477118 ps
CPU time 17.11 seconds
Started Jun 11 03:23:35 PM PDT 24
Finished Jun 11 03:23:54 PM PDT 24
Peak memory 232668 kb
Host smart-85659a56-5d7d-4594-9027-78c13467d669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874908602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3874908602
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.80538025
Short name T681
Test name
Test status
Simulation time 1805590881 ps
CPU time 10.5 seconds
Started Jun 11 03:23:30 PM PDT 24
Finished Jun 11 03:23:41 PM PDT 24
Peak memory 239240 kb
Host smart-eb320781-465f-4441-a1c5-a199dc361125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80538025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.80538025
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.103591202
Short name T712
Test name
Test status
Simulation time 6399933165 ps
CPU time 13.68 seconds
Started Jun 11 03:23:35 PM PDT 24
Finished Jun 11 03:23:50 PM PDT 24
Peak memory 218748 kb
Host smart-86106764-3043-44db-afde-d60ca45d3456
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=103591202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.103591202
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1598218531
Short name T212
Test name
Test status
Simulation time 9234934522 ps
CPU time 103.84 seconds
Started Jun 11 03:23:34 PM PDT 24
Finished Jun 11 03:25:20 PM PDT 24
Peak memory 261644 kb
Host smart-99a00b83-e82a-4e98-9b47-23b63e3c7711
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598218531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1598218531
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2133014974
Short name T904
Test name
Test status
Simulation time 4719496127 ps
CPU time 31.56 seconds
Started Jun 11 03:23:26 PM PDT 24
Finished Jun 11 03:23:59 PM PDT 24
Peak memory 216148 kb
Host smart-b053afd8-bbbc-468c-8e2f-171cbdd2b5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133014974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2133014974
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3783236042
Short name T932
Test name
Test status
Simulation time 572862315 ps
CPU time 2.03 seconds
Started Jun 11 03:23:35 PM PDT 24
Finished Jun 11 03:23:39 PM PDT 24
Peak memory 206760 kb
Host smart-c7905000-c39f-4259-a88e-8d0b896519c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783236042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3783236042
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3107965285
Short name T451
Test name
Test status
Simulation time 46007783 ps
CPU time 0.79 seconds
Started Jun 11 03:23:35 PM PDT 24
Finished Jun 11 03:23:38 PM PDT 24
Peak memory 205696 kb
Host smart-a617f7b6-e844-4d21-8afc-f6b67021c913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107965285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3107965285
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3866936499
Short name T854
Test name
Test status
Simulation time 284757752 ps
CPU time 0.9 seconds
Started Jun 11 03:23:30 PM PDT 24
Finished Jun 11 03:23:32 PM PDT 24
Peak memory 205684 kb
Host smart-4086104f-8312-4ca4-a770-bf908a3c147f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866936499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3866936499
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3992698196
Short name T459
Test name
Test status
Simulation time 908057456 ps
CPU time 3.84 seconds
Started Jun 11 03:23:35 PM PDT 24
Finished Jun 11 03:23:41 PM PDT 24
Peak memory 224308 kb
Host smart-8d79839d-7c0b-42bd-9efe-561cb3cd7e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992698196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3992698196
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.4089137583
Short name T662
Test name
Test status
Simulation time 13719435 ps
CPU time 0.76 seconds
Started Jun 11 03:23:34 PM PDT 24
Finished Jun 11 03:23:36 PM PDT 24
Peak memory 205312 kb
Host smart-72ae4266-3609-4939-95e5-0ea7d182cff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089137583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
4089137583
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3401556383
Short name T940
Test name
Test status
Simulation time 5097209166 ps
CPU time 20.03 seconds
Started Jun 11 03:23:37 PM PDT 24
Finished Jun 11 03:23:59 PM PDT 24
Peak memory 232604 kb
Host smart-71f0af57-1e94-481f-8ed7-11c176a5d693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401556383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3401556383
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2069072675
Short name T478
Test name
Test status
Simulation time 26154747 ps
CPU time 0.76 seconds
Started Jun 11 03:23:34 PM PDT 24
Finished Jun 11 03:23:37 PM PDT 24
Peak memory 205652 kb
Host smart-d088c244-6e85-4248-9e44-675c2592df97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069072675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2069072675
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2317869984
Short name T971
Test name
Test status
Simulation time 20941965 ps
CPU time 0.8 seconds
Started Jun 11 03:23:34 PM PDT 24
Finished Jun 11 03:23:36 PM PDT 24
Peak memory 215860 kb
Host smart-eb55375e-eb3b-48d1-b523-9f3598c0294f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317869984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2317869984
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.650332060
Short name T59
Test name
Test status
Simulation time 75515169299 ps
CPU time 211.49 seconds
Started Jun 11 03:23:33 PM PDT 24
Finished Jun 11 03:27:06 PM PDT 24
Peak memory 256168 kb
Host smart-ab7da867-d149-4bbd-995a-9a3d40b2e484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650332060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.650332060
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.4274377564
Short name T719
Test name
Test status
Simulation time 5506824888 ps
CPU time 109.11 seconds
Started Jun 11 03:23:33 PM PDT 24
Finished Jun 11 03:25:23 PM PDT 24
Peak memory 250076 kb
Host smart-64253daf-dd2a-4bca-8d7e-1211857a0fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274377564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.4274377564
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3467234950
Short name T612
Test name
Test status
Simulation time 1529385335 ps
CPU time 7.34 seconds
Started Jun 11 03:23:37 PM PDT 24
Finished Jun 11 03:23:46 PM PDT 24
Peak memory 224324 kb
Host smart-74bf911c-f541-4474-a21f-67a6a8d232d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467234950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3467234950
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.69524682
Short name T353
Test name
Test status
Simulation time 289323571 ps
CPU time 4.27 seconds
Started Jun 11 03:23:34 PM PDT 24
Finished Jun 11 03:23:40 PM PDT 24
Peak memory 227408 kb
Host smart-f01c112a-d6d7-4467-89e2-e89e755664b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69524682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.69524682
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3744187768
Short name T597
Test name
Test status
Simulation time 57197852 ps
CPU time 2.44 seconds
Started Jun 11 03:23:33 PM PDT 24
Finished Jun 11 03:23:37 PM PDT 24
Peak memory 232356 kb
Host smart-3db17adb-0571-456c-b695-54341d3f5b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744187768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3744187768
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.545328672
Short name T843
Test name
Test status
Simulation time 6489955770 ps
CPU time 19.76 seconds
Started Jun 11 03:23:35 PM PDT 24
Finished Jun 11 03:23:57 PM PDT 24
Peak memory 232612 kb
Host smart-9b33e4ef-a712-437f-90ac-3df15452b550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545328672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.545328672
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3346427076
Short name T95
Test name
Test status
Simulation time 1229858313 ps
CPU time 6.23 seconds
Started Jun 11 03:23:34 PM PDT 24
Finished Jun 11 03:23:43 PM PDT 24
Peak memory 232500 kb
Host smart-6ab2924b-9111-47f0-bc4c-1498fa243a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346427076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3346427076
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3304803910
Short name T882
Test name
Test status
Simulation time 707769446 ps
CPU time 12.8 seconds
Started Jun 11 03:23:36 PM PDT 24
Finished Jun 11 03:23:50 PM PDT 24
Peak memory 219032 kb
Host smart-20fbf995-44a2-4ae7-b8da-762b8597fb82
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3304803910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3304803910
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1388816525
Short name T479
Test name
Test status
Simulation time 51838945 ps
CPU time 1.05 seconds
Started Jun 11 03:23:33 PM PDT 24
Finished Jun 11 03:23:35 PM PDT 24
Peak memory 206476 kb
Host smart-b9b94dce-0ad6-48eb-8d33-ec1647bb6332
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388816525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1388816525
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2373458548
Short name T580
Test name
Test status
Simulation time 13241405213 ps
CPU time 29.84 seconds
Started Jun 11 03:23:34 PM PDT 24
Finished Jun 11 03:24:06 PM PDT 24
Peak memory 216248 kb
Host smart-822a8fe7-8d34-4555-8a8d-d93f72d370e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373458548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2373458548
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.789632245
Short name T726
Test name
Test status
Simulation time 1444078089 ps
CPU time 5.83 seconds
Started Jun 11 03:23:35 PM PDT 24
Finished Jun 11 03:23:43 PM PDT 24
Peak memory 216048 kb
Host smart-d83931fa-33f7-4511-bd81-c286490583e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789632245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.789632245
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.180525932
Short name T786
Test name
Test status
Simulation time 194443839 ps
CPU time 3.01 seconds
Started Jun 11 03:23:34 PM PDT 24
Finished Jun 11 03:23:39 PM PDT 24
Peak memory 216148 kb
Host smart-e619988d-b8c6-4241-bf86-abf44771c979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180525932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.180525932
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2541043618
Short name T829
Test name
Test status
Simulation time 66420806 ps
CPU time 0.91 seconds
Started Jun 11 03:23:33 PM PDT 24
Finished Jun 11 03:23:35 PM PDT 24
Peak memory 205680 kb
Host smart-270a1e5b-ae5b-41a7-a0fb-622a8cfd349b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541043618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2541043618
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3325577701
Short name T276
Test name
Test status
Simulation time 17701164652 ps
CPU time 17.56 seconds
Started Jun 11 03:23:36 PM PDT 24
Finished Jun 11 03:23:55 PM PDT 24
Peak memory 238440 kb
Host smart-7cef2702-4348-4966-b373-391cab2550e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325577701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3325577701
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4136618989
Short name T796
Test name
Test status
Simulation time 14551251 ps
CPU time 0.78 seconds
Started Jun 11 03:23:41 PM PDT 24
Finished Jun 11 03:23:44 PM PDT 24
Peak memory 204756 kb
Host smart-02ae2f59-85c1-4539-8329-926fdc53df88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136618989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4136618989
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.576343889
Short name T268
Test name
Test status
Simulation time 227660809 ps
CPU time 2.85 seconds
Started Jun 11 03:23:33 PM PDT 24
Finished Jun 11 03:23:37 PM PDT 24
Peak memory 232528 kb
Host smart-bc35d3ed-d15e-4e98-b39c-ad235e1a3797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576343889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.576343889
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3395217703
Short name T639
Test name
Test status
Simulation time 45013901 ps
CPU time 0.77 seconds
Started Jun 11 03:23:33 PM PDT 24
Finished Jun 11 03:23:35 PM PDT 24
Peak memory 206364 kb
Host smart-0706a326-5bda-4ef2-81b0-464057391168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395217703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3395217703
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3533630247
Short name T251
Test name
Test status
Simulation time 951412791 ps
CPU time 15.78 seconds
Started Jun 11 03:23:41 PM PDT 24
Finished Jun 11 03:23:58 PM PDT 24
Peak memory 240536 kb
Host smart-36e236f5-b0cf-4212-8672-d131469a3353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533630247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3533630247
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.4115222382
Short name T306
Test name
Test status
Simulation time 3244353371 ps
CPU time 82.94 seconds
Started Jun 11 03:23:44 PM PDT 24
Finished Jun 11 03:25:09 PM PDT 24
Peak memory 255732 kb
Host smart-c7a8eb7d-94bb-4da5-a9cb-e3ae3f84b9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115222382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.4115222382
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.652051000
Short name T635
Test name
Test status
Simulation time 35340652102 ps
CPU time 82.81 seconds
Started Jun 11 03:23:44 PM PDT 24
Finished Jun 11 03:25:08 PM PDT 24
Peak memory 256280 kb
Host smart-64ee20d5-c68f-42a6-9a03-a523362ba0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652051000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.652051000
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1359870171
Short name T472
Test name
Test status
Simulation time 1253421872 ps
CPU time 8.94 seconds
Started Jun 11 03:23:34 PM PDT 24
Finished Jun 11 03:23:45 PM PDT 24
Peak memory 232572 kb
Host smart-76089e4f-60af-48a4-bdf2-dbf801be7940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359870171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1359870171
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.243511638
Short name T505
Test name
Test status
Simulation time 828732005 ps
CPU time 5.02 seconds
Started Jun 11 03:23:35 PM PDT 24
Finished Jun 11 03:23:42 PM PDT 24
Peak memory 232492 kb
Host smart-59e35c93-1120-41a6-bbcd-1ce290b863ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243511638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.243511638
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3264089112
Short name T659
Test name
Test status
Simulation time 4847826267 ps
CPU time 18.41 seconds
Started Jun 11 03:23:37 PM PDT 24
Finished Jun 11 03:23:57 PM PDT 24
Peak memory 232612 kb
Host smart-23e7b608-37a6-4666-bbfb-6914eee05594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264089112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3264089112
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3511793107
Short name T42
Test name
Test status
Simulation time 3272495991 ps
CPU time 8.64 seconds
Started Jun 11 03:23:32 PM PDT 24
Finished Jun 11 03:23:42 PM PDT 24
Peak memory 224364 kb
Host smart-44a47793-5fec-4f4d-9058-253742ce2606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511793107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3511793107
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.385352285
Short name T537
Test name
Test status
Simulation time 5248988353 ps
CPU time 4.56 seconds
Started Jun 11 03:23:34 PM PDT 24
Finished Jun 11 03:23:40 PM PDT 24
Peak memory 232628 kb
Host smart-6351054b-411c-4163-8d3f-1c01e449eaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385352285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.385352285
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.4155117884
Short name T518
Test name
Test status
Simulation time 2473581776 ps
CPU time 13.13 seconds
Started Jun 11 03:23:42 PM PDT 24
Finished Jun 11 03:23:58 PM PDT 24
Peak memory 219128 kb
Host smart-60963844-966f-4713-9ea5-66bc2a740f55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4155117884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.4155117884
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2762838794
Short name T196
Test name
Test status
Simulation time 240565750187 ps
CPU time 1161.97 seconds
Started Jun 11 03:23:43 PM PDT 24
Finished Jun 11 03:43:07 PM PDT 24
Peak memory 273644 kb
Host smart-e9addf63-caa3-4758-8d13-4e7d7faa72d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762838794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2762838794
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3845790771
Short name T916
Test name
Test status
Simulation time 1601398944 ps
CPU time 15.78 seconds
Started Jun 11 03:23:38 PM PDT 24
Finished Jun 11 03:23:55 PM PDT 24
Peak memory 216144 kb
Host smart-182564c1-b43a-49a1-a42e-90ca3e96ed86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845790771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3845790771
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1418554027
Short name T623
Test name
Test status
Simulation time 32978508 ps
CPU time 0.7 seconds
Started Jun 11 03:23:33 PM PDT 24
Finished Jun 11 03:23:35 PM PDT 24
Peak memory 205456 kb
Host smart-fde3e9ac-6a5f-43a3-a888-a45dac497291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418554027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1418554027
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.741657461
Short name T387
Test name
Test status
Simulation time 17668517 ps
CPU time 0.77 seconds
Started Jun 11 03:23:37 PM PDT 24
Finished Jun 11 03:23:39 PM PDT 24
Peak memory 205696 kb
Host smart-3eae330a-83e0-4a22-9557-0bcf9b3f4138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741657461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.741657461
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3513128327
Short name T371
Test name
Test status
Simulation time 162814307 ps
CPU time 0.87 seconds
Started Jun 11 03:23:34 PM PDT 24
Finished Jun 11 03:23:37 PM PDT 24
Peak memory 205652 kb
Host smart-17967e12-c9ab-40e3-923d-7604c941b928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513128327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3513128327
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2112508491
Short name T927
Test name
Test status
Simulation time 947314247 ps
CPU time 8.09 seconds
Started Jun 11 03:23:35 PM PDT 24
Finished Jun 11 03:23:46 PM PDT 24
Peak memory 240668 kb
Host smart-ddd1f535-5b09-4b4f-9156-414208c22b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112508491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2112508491
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.613275474
Short name T464
Test name
Test status
Simulation time 13721174 ps
CPU time 0.74 seconds
Started Jun 11 03:23:48 PM PDT 24
Finished Jun 11 03:23:50 PM PDT 24
Peak memory 204728 kb
Host smart-fcd9f9ec-e204-4a57-bcd0-221a4da9674c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613275474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.613275474
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3895691034
Short name T905
Test name
Test status
Simulation time 1180604946 ps
CPU time 5.03 seconds
Started Jun 11 03:23:44 PM PDT 24
Finished Jun 11 03:23:51 PM PDT 24
Peak memory 232532 kb
Host smart-e4531b61-aaa8-4d81-8f2c-fff5beaa6b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895691034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3895691034
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3338335947
Short name T707
Test name
Test status
Simulation time 56329017 ps
CPU time 0.82 seconds
Started Jun 11 03:23:43 PM PDT 24
Finished Jun 11 03:23:45 PM PDT 24
Peak memory 206376 kb
Host smart-0cd51eb7-586d-4246-b3bf-382be7966e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338335947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3338335947
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1040050481
Short name T94
Test name
Test status
Simulation time 8896545832 ps
CPU time 20.19 seconds
Started Jun 11 03:23:43 PM PDT 24
Finished Jun 11 03:24:05 PM PDT 24
Peak memory 224456 kb
Host smart-e28f614d-be6e-4e0c-9154-1da4c79da3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040050481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1040050481
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3930528255
Short name T671
Test name
Test status
Simulation time 6024889456 ps
CPU time 14.95 seconds
Started Jun 11 03:23:42 PM PDT 24
Finished Jun 11 03:23:59 PM PDT 24
Peak memory 240932 kb
Host smart-b3303edb-1aec-4ac1-a8f1-8704c7c0290c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930528255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3930528255
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3515314351
Short name T763
Test name
Test status
Simulation time 2145060758 ps
CPU time 43.09 seconds
Started Jun 11 03:23:46 PM PDT 24
Finished Jun 11 03:24:31 PM PDT 24
Peak memory 248712 kb
Host smart-3d13bc0b-784f-4fce-93dc-2415acf021f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515314351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3515314351
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1723773408
Short name T325
Test name
Test status
Simulation time 12686813501 ps
CPU time 16.43 seconds
Started Jun 11 03:23:44 PM PDT 24
Finished Jun 11 03:24:02 PM PDT 24
Peak memory 240948 kb
Host smart-9cdde83e-2198-4147-b3ed-9e1de7ed50f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723773408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1723773408
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2447741491
Short name T475
Test name
Test status
Simulation time 59671485 ps
CPU time 2.59 seconds
Started Jun 11 03:23:45 PM PDT 24
Finished Jun 11 03:23:49 PM PDT 24
Peak memory 232532 kb
Host smart-4467f2ab-39df-4572-8a5f-30cd58ad4668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447741491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2447741491
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3533286444
Short name T775
Test name
Test status
Simulation time 539756727 ps
CPU time 2.52 seconds
Started Jun 11 03:23:46 PM PDT 24
Finished Jun 11 03:23:50 PM PDT 24
Peak memory 232308 kb
Host smart-dca5dd33-96a2-4b46-b61c-1c999617ee25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533286444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3533286444
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2488866643
Short name T594
Test name
Test status
Simulation time 138677242 ps
CPU time 4.03 seconds
Started Jun 11 03:23:42 PM PDT 24
Finished Jun 11 03:23:48 PM PDT 24
Peak memory 232500 kb
Host smart-3d9d97f5-9025-47d8-aed4-2b1c9a5c1251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488866643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2488866643
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.709815725
Short name T648
Test name
Test status
Simulation time 6104279759 ps
CPU time 16.63 seconds
Started Jun 11 03:23:44 PM PDT 24
Finished Jun 11 03:24:03 PM PDT 24
Peak memory 232612 kb
Host smart-ce254ea7-06ab-4581-834b-d4de1b436460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709815725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.709815725
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.273271108
Short name T698
Test name
Test status
Simulation time 1242170946 ps
CPU time 8.61 seconds
Started Jun 11 03:23:42 PM PDT 24
Finished Jun 11 03:23:53 PM PDT 24
Peak memory 222728 kb
Host smart-33b7c1e4-cd26-4f7a-9388-ce6b8fbc4831
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=273271108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.273271108
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2084938840
Short name T139
Test name
Test status
Simulation time 205009938318 ps
CPU time 227.23 seconds
Started Jun 11 03:23:43 PM PDT 24
Finished Jun 11 03:27:32 PM PDT 24
Peak memory 252828 kb
Host smart-56463ddb-9df2-4a7d-acb4-d66d3fc0308f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084938840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2084938840
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2715374674
Short name T692
Test name
Test status
Simulation time 9977138368 ps
CPU time 29.5 seconds
Started Jun 11 03:23:42 PM PDT 24
Finished Jun 11 03:24:14 PM PDT 24
Peak memory 216148 kb
Host smart-69148965-e8af-47b8-b1e1-4321cdfd8c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715374674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2715374674
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.4076056577
Short name T469
Test name
Test status
Simulation time 1422579270 ps
CPU time 8.24 seconds
Started Jun 11 03:23:42 PM PDT 24
Finished Jun 11 03:23:52 PM PDT 24
Peak memory 215992 kb
Host smart-676342b9-bf2a-4cce-b6f4-1a3df9955620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076056577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.4076056577
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1848173294
Short name T78
Test name
Test status
Simulation time 108360335 ps
CPU time 1.18 seconds
Started Jun 11 03:23:47 PM PDT 24
Finished Jun 11 03:23:50 PM PDT 24
Peak memory 216036 kb
Host smart-65b7e694-3c78-48f1-a6fe-411f0bbf97ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848173294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1848173294
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.902649076
Short name T934
Test name
Test status
Simulation time 59330773 ps
CPU time 0.88 seconds
Started Jun 11 03:23:43 PM PDT 24
Finished Jun 11 03:23:46 PM PDT 24
Peak memory 205672 kb
Host smart-ebc07e6f-ce38-437a-af08-394c28a43b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902649076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.902649076
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.991094555
Short name T858
Test name
Test status
Simulation time 1209077365 ps
CPU time 5.62 seconds
Started Jun 11 03:23:43 PM PDT 24
Finished Jun 11 03:23:51 PM PDT 24
Peak memory 232496 kb
Host smart-ae2dc22c-6a6a-4615-8594-4f2e458882e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991094555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.991094555
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1500542123
Short name T727
Test name
Test status
Simulation time 117065435 ps
CPU time 0.68 seconds
Started Jun 11 03:23:54 PM PDT 24
Finished Jun 11 03:23:58 PM PDT 24
Peak memory 205244 kb
Host smart-2ee313b1-ad52-4b2c-8b61-d17edcd80cbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500542123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1500542123
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.4257652201
Short name T914
Test name
Test status
Simulation time 286578586 ps
CPU time 4.2 seconds
Started Jun 11 03:23:44 PM PDT 24
Finished Jun 11 03:23:51 PM PDT 24
Peak memory 224300 kb
Host smart-c00ee36a-7dc9-4731-8c86-a47e6b7924e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257652201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.4257652201
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.798813694
Short name T651
Test name
Test status
Simulation time 16983566 ps
CPU time 0.82 seconds
Started Jun 11 03:23:45 PM PDT 24
Finished Jun 11 03:23:48 PM PDT 24
Peak memory 206688 kb
Host smart-f7370465-cb7f-4cd6-9d28-09f321d6640c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798813694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.798813694
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3547318045
Short name T208
Test name
Test status
Simulation time 42583062016 ps
CPU time 307.58 seconds
Started Jun 11 03:23:54 PM PDT 24
Finished Jun 11 03:29:04 PM PDT 24
Peak memory 254132 kb
Host smart-068fc163-f643-4348-9c53-d0b7479a4784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547318045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3547318045
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1860149299
Short name T227
Test name
Test status
Simulation time 50084370935 ps
CPU time 77.04 seconds
Started Jun 11 03:23:54 PM PDT 24
Finished Jun 11 03:25:14 PM PDT 24
Peak memory 249124 kb
Host smart-5e29a656-1e49-4eff-95bd-d3d73140d7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860149299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1860149299
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1521996918
Short name T53
Test name
Test status
Simulation time 727152293 ps
CPU time 15.57 seconds
Started Jun 11 03:23:45 PM PDT 24
Finished Jun 11 03:24:02 PM PDT 24
Peak memory 224320 kb
Host smart-394fd6d0-8b15-4b79-a7d2-7f4ff016ee7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521996918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1521996918
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3610826098
Short name T230
Test name
Test status
Simulation time 1899375214 ps
CPU time 20.29 seconds
Started Jun 11 03:23:45 PM PDT 24
Finished Jun 11 03:24:07 PM PDT 24
Peak memory 224288 kb
Host smart-77a95e36-6917-4a8c-ab13-5d4c0534c21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610826098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3610826098
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2756039964
Short name T440
Test name
Test status
Simulation time 5792246281 ps
CPU time 53.18 seconds
Started Jun 11 03:23:46 PM PDT 24
Finished Jun 11 03:24:41 PM PDT 24
Peak memory 252104 kb
Host smart-2ea934f0-064a-4dcf-a95a-8fd7499bdd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756039964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2756039964
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3302604911
Short name T675
Test name
Test status
Simulation time 36364042239 ps
CPU time 34.53 seconds
Started Jun 11 03:23:43 PM PDT 24
Finished Jun 11 03:24:19 PM PDT 24
Peak memory 234252 kb
Host smart-f922d27a-a7ee-4ee0-a5b3-54172a33698c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302604911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3302604911
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2280399956
Short name T591
Test name
Test status
Simulation time 368593335 ps
CPU time 3.52 seconds
Started Jun 11 03:23:46 PM PDT 24
Finished Jun 11 03:23:51 PM PDT 24
Peak memory 224328 kb
Host smart-2f15ce19-6458-4d6f-9873-4048def31da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280399956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2280399956
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2518128550
Short name T5
Test name
Test status
Simulation time 101246283 ps
CPU time 4.22 seconds
Started Jun 11 03:23:41 PM PDT 24
Finished Jun 11 03:23:47 PM PDT 24
Peak memory 221668 kb
Host smart-c6483b41-95e3-418d-a9d0-ad22d9473780
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2518128550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2518128550
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.239319394
Short name T782
Test name
Test status
Simulation time 3132693908 ps
CPU time 23.93 seconds
Started Jun 11 03:23:41 PM PDT 24
Finished Jun 11 03:24:07 PM PDT 24
Peak memory 216188 kb
Host smart-565a4e75-b576-46ba-b54e-d84bf41c610d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239319394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.239319394
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3577409746
Short name T449
Test name
Test status
Simulation time 2627133739 ps
CPU time 8.23 seconds
Started Jun 11 03:23:42 PM PDT 24
Finished Jun 11 03:23:53 PM PDT 24
Peak memory 216144 kb
Host smart-4887032f-c0fb-44a1-a365-eca0e8d735cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577409746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3577409746
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.574049720
Short name T390
Test name
Test status
Simulation time 524950606 ps
CPU time 2.22 seconds
Started Jun 11 03:23:43 PM PDT 24
Finished Jun 11 03:23:47 PM PDT 24
Peak memory 216072 kb
Host smart-5d1d7c3d-3186-434c-a188-8e1ef3eebc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574049720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.574049720
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.4185562165
Short name T907
Test name
Test status
Simulation time 13879226 ps
CPU time 0.73 seconds
Started Jun 11 03:23:42 PM PDT 24
Finished Jun 11 03:23:45 PM PDT 24
Peak memory 205660 kb
Host smart-f3ea7ea2-bbd6-4f63-ae0e-00a885c28560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185562165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.4185562165
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1803102298
Short name T492
Test name
Test status
Simulation time 125382083 ps
CPU time 2.57 seconds
Started Jun 11 03:23:46 PM PDT 24
Finished Jun 11 03:23:51 PM PDT 24
Peak memory 232364 kb
Host smart-93e0a457-c694-4db8-b496-ed489bc88dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803102298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1803102298
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2261061594
Short name T733
Test name
Test status
Simulation time 13687057 ps
CPU time 0.77 seconds
Started Jun 11 03:23:54 PM PDT 24
Finished Jun 11 03:23:57 PM PDT 24
Peak memory 205324 kb
Host smart-9a6eefd1-9760-4c75-80b2-275d1867fe72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261061594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2261061594
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1574611138
Short name T877
Test name
Test status
Simulation time 1396572629 ps
CPU time 5.98 seconds
Started Jun 11 03:23:54 PM PDT 24
Finished Jun 11 03:24:02 PM PDT 24
Peak memory 228308 kb
Host smart-42422574-1cd0-47c5-82c4-dc624f1fe23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574611138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1574611138
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.287876877
Short name T446
Test name
Test status
Simulation time 16588920 ps
CPU time 0.76 seconds
Started Jun 11 03:23:54 PM PDT 24
Finished Jun 11 03:23:58 PM PDT 24
Peak memory 205364 kb
Host smart-7a6c852b-e9c3-45db-815f-be27de712fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287876877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.287876877
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1957922236
Short name T348
Test name
Test status
Simulation time 453681219 ps
CPU time 3.05 seconds
Started Jun 11 03:23:53 PM PDT 24
Finished Jun 11 03:23:59 PM PDT 24
Peak memory 224332 kb
Host smart-eca73186-e234-4c5a-867d-037be2dcabe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957922236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1957922236
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1065489500
Short name T205
Test name
Test status
Simulation time 176196427 ps
CPU time 4.67 seconds
Started Jun 11 03:23:56 PM PDT 24
Finished Jun 11 03:24:04 PM PDT 24
Peak memory 232528 kb
Host smart-a0818676-2761-4286-9553-776ef150825c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065489500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1065489500
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.968693339
Short name T805
Test name
Test status
Simulation time 3345751233 ps
CPU time 33.94 seconds
Started Jun 11 03:23:54 PM PDT 24
Finished Jun 11 03:24:30 PM PDT 24
Peak memory 240584 kb
Host smart-dfc8abd1-a1d1-45a3-863f-ab5fb2cb7782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968693339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.968693339
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2376852776
Short name T252
Test name
Test status
Simulation time 4492300286 ps
CPU time 14.58 seconds
Started Jun 11 03:23:53 PM PDT 24
Finished Jun 11 03:24:09 PM PDT 24
Peak memory 232660 kb
Host smart-335c9085-6a15-4152-ae3f-19f6be324b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376852776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2376852776
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2360625884
Short name T730
Test name
Test status
Simulation time 29509841061 ps
CPU time 19.18 seconds
Started Jun 11 03:23:57 PM PDT 24
Finished Jun 11 03:24:18 PM PDT 24
Peak memory 240764 kb
Host smart-5a99ea9a-e59e-4ca3-8f5d-9748ff9e9f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360625884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2360625884
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2123660936
Short name T979
Test name
Test status
Simulation time 1004151604 ps
CPU time 6.45 seconds
Started Jun 11 03:23:56 PM PDT 24
Finished Jun 11 03:24:05 PM PDT 24
Peak memory 218692 kb
Host smart-dc5ec175-b728-4547-a648-6f07b3b81768
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2123660936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2123660936
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.4227570794
Short name T545
Test name
Test status
Simulation time 33007452705 ps
CPU time 44.93 seconds
Started Jun 11 03:23:57 PM PDT 24
Finished Jun 11 03:24:45 PM PDT 24
Peak memory 224468 kb
Host smart-a80b5d3f-8c21-405c-bf96-a544db242c00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227570794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.4227570794
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.4040412745
Short name T668
Test name
Test status
Simulation time 2662976994 ps
CPU time 7.82 seconds
Started Jun 11 03:23:53 PM PDT 24
Finished Jun 11 03:24:03 PM PDT 24
Peak memory 216512 kb
Host smart-b75b1cf9-7a14-4776-b640-c6cada5f8eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040412745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.4040412745
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.4275920407
Short name T768
Test name
Test status
Simulation time 4223912800 ps
CPU time 4.61 seconds
Started Jun 11 03:23:53 PM PDT 24
Finished Jun 11 03:23:59 PM PDT 24
Peak memory 216156 kb
Host smart-b9da59c5-9db7-4293-b295-84a96ec05e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275920407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.4275920407
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.14902952
Short name T476
Test name
Test status
Simulation time 32744025 ps
CPU time 1.2 seconds
Started Jun 11 03:23:52 PM PDT 24
Finished Jun 11 03:23:55 PM PDT 24
Peak memory 215940 kb
Host smart-cfa254c0-2466-4a9c-9eb6-dc557ea5d87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14902952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.14902952
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3429220344
Short name T376
Test name
Test status
Simulation time 26966404 ps
CPU time 0.84 seconds
Started Jun 11 03:23:54 PM PDT 24
Finished Jun 11 03:23:58 PM PDT 24
Peak memory 205672 kb
Host smart-b18bca9d-ca42-402a-8788-45d23e0b4a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429220344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3429220344
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1495554434
Short name T676
Test name
Test status
Simulation time 191047148 ps
CPU time 2.62 seconds
Started Jun 11 03:23:57 PM PDT 24
Finished Jun 11 03:24:02 PM PDT 24
Peak memory 224280 kb
Host smart-11cae98b-2b01-46a2-83ec-e0e34049edd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495554434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1495554434
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.503986370
Short name T409
Test name
Test status
Simulation time 19081944 ps
CPU time 0.7 seconds
Started Jun 11 03:24:08 PM PDT 24
Finished Jun 11 03:24:11 PM PDT 24
Peak memory 205296 kb
Host smart-e11dc7c0-7494-42d4-a293-654670e81cb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503986370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.503986370
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2331311906
Short name T658
Test name
Test status
Simulation time 1349915719 ps
CPU time 8.61 seconds
Started Jun 11 03:23:58 PM PDT 24
Finished Jun 11 03:24:09 PM PDT 24
Peak memory 224260 kb
Host smart-10695f37-1fa0-4781-94cd-4f45f824ba85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331311906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2331311906
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3278206530
Short name T576
Test name
Test status
Simulation time 40019318 ps
CPU time 0.81 seconds
Started Jun 11 03:23:53 PM PDT 24
Finished Jun 11 03:23:56 PM PDT 24
Peak memory 206376 kb
Host smart-cd24e588-ac4d-4028-95d3-b3c025a31204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278206530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3278206530
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3506716466
Short name T717
Test name
Test status
Simulation time 51284551248 ps
CPU time 89.66 seconds
Started Jun 11 03:23:55 PM PDT 24
Finished Jun 11 03:25:28 PM PDT 24
Peak memory 255144 kb
Host smart-7a8f5df1-9303-4331-831a-9c1a1b433bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506716466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3506716466
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.997445986
Short name T194
Test name
Test status
Simulation time 26085732634 ps
CPU time 228.06 seconds
Started Jun 11 03:23:53 PM PDT 24
Finished Jun 11 03:27:44 PM PDT 24
Peak memory 249076 kb
Host smart-a07df2ea-3d2c-4989-90a7-4f6f3d50251c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997445986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.997445986
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3844448653
Short name T39
Test name
Test status
Simulation time 2800735814 ps
CPU time 26.51 seconds
Started Jun 11 03:24:09 PM PDT 24
Finished Jun 11 03:24:37 PM PDT 24
Peak memory 217256 kb
Host smart-c6802596-3db8-4687-ae69-63cfba737cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844448653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3844448653
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2144115674
Short name T571
Test name
Test status
Simulation time 396430479 ps
CPU time 8.45 seconds
Started Jun 11 03:23:52 PM PDT 24
Finished Jun 11 03:24:03 PM PDT 24
Peak memory 224340 kb
Host smart-f4b1fb5a-6287-44c1-b142-6f628565a64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144115674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2144115674
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.827365569
Short name T566
Test name
Test status
Simulation time 1087512703 ps
CPU time 5.97 seconds
Started Jun 11 03:23:55 PM PDT 24
Finished Jun 11 03:24:04 PM PDT 24
Peak memory 224124 kb
Host smart-3a1e7c21-fd1f-4e48-8214-57c61e3d1eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827365569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.827365569
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3215780014
Short name T62
Test name
Test status
Simulation time 1186431136 ps
CPU time 6.69 seconds
Started Jun 11 03:23:55 PM PDT 24
Finished Jun 11 03:24:04 PM PDT 24
Peak memory 224304 kb
Host smart-e4e940d2-5196-4abe-a4ed-7127597bd981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215780014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3215780014
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2042949833
Short name T974
Test name
Test status
Simulation time 6380733280 ps
CPU time 11.18 seconds
Started Jun 11 03:24:00 PM PDT 24
Finished Jun 11 03:24:13 PM PDT 24
Peak memory 232616 kb
Host smart-d019c430-23ef-493a-9c43-6ac073fe18a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042949833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2042949833
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1370679138
Short name T609
Test name
Test status
Simulation time 1319784170 ps
CPU time 8.58 seconds
Started Jun 11 03:23:55 PM PDT 24
Finished Jun 11 03:24:06 PM PDT 24
Peak memory 240656 kb
Host smart-934e4fc4-7297-4523-869c-478e79159f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370679138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1370679138
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.931408071
Short name T494
Test name
Test status
Simulation time 1927756097 ps
CPU time 5.58 seconds
Started Jun 11 03:23:54 PM PDT 24
Finished Jun 11 03:24:02 PM PDT 24
Peak memory 218572 kb
Host smart-2001ab91-1642-4e99-90d4-45df19c5fa34
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=931408071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.931408071
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2567984578
Short name T171
Test name
Test status
Simulation time 3516562206 ps
CPU time 5.81 seconds
Started Jun 11 03:24:06 PM PDT 24
Finished Jun 11 03:24:14 PM PDT 24
Peak memory 224512 kb
Host smart-85e73dd0-cc6a-49f9-bd5c-bab017ac0ce4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567984578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2567984578
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4141539786
Short name T687
Test name
Test status
Simulation time 2735096685 ps
CPU time 13.58 seconds
Started Jun 11 03:23:55 PM PDT 24
Finished Jun 11 03:24:12 PM PDT 24
Peak memory 216156 kb
Host smart-766dab37-0a17-4e03-801c-28397b6b6918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141539786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4141539786
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1691656041
Short name T345
Test name
Test status
Simulation time 562920429 ps
CPU time 3.02 seconds
Started Jun 11 03:23:55 PM PDT 24
Finished Jun 11 03:24:01 PM PDT 24
Peak memory 216032 kb
Host smart-2b1913d6-6c4b-46c6-8b49-196f4ba4fd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691656041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1691656041
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.565956219
Short name T685
Test name
Test status
Simulation time 126898423 ps
CPU time 2.05 seconds
Started Jun 11 03:23:57 PM PDT 24
Finished Jun 11 03:24:02 PM PDT 24
Peak memory 216004 kb
Host smart-bfa1f5e8-724e-4305-a516-c8de1933ea80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565956219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.565956219
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1160141249
Short name T355
Test name
Test status
Simulation time 10894981 ps
CPU time 0.69 seconds
Started Jun 11 03:23:54 PM PDT 24
Finished Jun 11 03:23:58 PM PDT 24
Peak memory 205408 kb
Host smart-4e37e25b-1ac3-4d18-b520-310bbcebaacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160141249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1160141249
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1378876671
Short name T577
Test name
Test status
Simulation time 262019676 ps
CPU time 3.82 seconds
Started Jun 11 03:23:55 PM PDT 24
Finished Jun 11 03:24:01 PM PDT 24
Peak memory 224348 kb
Host smart-e2b800a2-a47d-48e8-a849-4e4ce51f004c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378876671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1378876671
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3006619142
Short name T549
Test name
Test status
Simulation time 35328570 ps
CPU time 0.77 seconds
Started Jun 11 03:24:04 PM PDT 24
Finished Jun 11 03:24:06 PM PDT 24
Peak memory 205344 kb
Host smart-586d6fd9-1425-404c-a19a-3991d2ebfee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006619142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3006619142
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.236532818
Short name T850
Test name
Test status
Simulation time 379946267 ps
CPU time 3.87 seconds
Started Jun 11 03:24:06 PM PDT 24
Finished Jun 11 03:24:11 PM PDT 24
Peak memory 232392 kb
Host smart-72ea08fc-2825-42f6-a51c-15ec7fea2477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236532818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.236532818
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1450437000
Short name T507
Test name
Test status
Simulation time 102789718 ps
CPU time 0.8 seconds
Started Jun 11 03:24:07 PM PDT 24
Finished Jun 11 03:24:09 PM PDT 24
Peak memory 206368 kb
Host smart-1a320d04-b16b-4cd2-9d60-485da1eca52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450437000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1450437000
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.810701942
Short name T240
Test name
Test status
Simulation time 488696553 ps
CPU time 11.04 seconds
Started Jun 11 03:24:07 PM PDT 24
Finished Jun 11 03:24:20 PM PDT 24
Peak memory 234304 kb
Host smart-8a93ddc9-444b-48fd-a5fb-bbabde80f400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810701942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.810701942
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3276346267
Short name T58
Test name
Test status
Simulation time 6524443629 ps
CPU time 119.65 seconds
Started Jun 11 03:24:08 PM PDT 24
Finished Jun 11 03:26:09 PM PDT 24
Peak memory 257308 kb
Host smart-701035e9-b6f6-4a25-8b71-c00e612cc067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276346267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3276346267
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2753367643
Short name T941
Test name
Test status
Simulation time 71681869 ps
CPU time 3.14 seconds
Started Jun 11 03:24:05 PM PDT 24
Finished Jun 11 03:24:10 PM PDT 24
Peak memory 232540 kb
Host smart-8f840469-f8e4-415b-b07b-bb3c332c277e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753367643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2753367643
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3545123606
Short name T521
Test name
Test status
Simulation time 3002371741 ps
CPU time 6.78 seconds
Started Jun 11 03:24:07 PM PDT 24
Finished Jun 11 03:24:16 PM PDT 24
Peak memory 224372 kb
Host smart-e5749eaf-b6ee-43a6-95b2-e8a806466b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545123606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3545123606
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3597806138
Short name T865
Test name
Test status
Simulation time 471002817 ps
CPU time 2.52 seconds
Started Jun 11 03:24:08 PM PDT 24
Finished Jun 11 03:24:12 PM PDT 24
Peak memory 224224 kb
Host smart-65a296c9-a31f-4dbf-b3d0-c7f5b888ca43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597806138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3597806138
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2819558217
Short name T465
Test name
Test status
Simulation time 11465152124 ps
CPU time 14.8 seconds
Started Jun 11 03:24:13 PM PDT 24
Finished Jun 11 03:24:30 PM PDT 24
Peak memory 224444 kb
Host smart-abc762e4-f05a-44cc-a3a0-357ca2ba2494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819558217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2819558217
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3125203927
Short name T625
Test name
Test status
Simulation time 8512260427 ps
CPU time 5.54 seconds
Started Jun 11 03:24:07 PM PDT 24
Finished Jun 11 03:24:14 PM PDT 24
Peak memory 222472 kb
Host smart-eedbe6de-2a89-424c-adc5-d022b85de1a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3125203927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3125203927
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3127466733
Short name T172
Test name
Test status
Simulation time 13550765206 ps
CPU time 77.63 seconds
Started Jun 11 03:24:06 PM PDT 24
Finished Jun 11 03:25:26 PM PDT 24
Peak memory 251480 kb
Host smart-036da741-832e-4cdc-abd7-2fd6c1f49ad9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127466733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3127466733
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.798352667
Short name T634
Test name
Test status
Simulation time 4215409635 ps
CPU time 18.64 seconds
Started Jun 11 03:24:05 PM PDT 24
Finished Jun 11 03:24:25 PM PDT 24
Peak memory 216496 kb
Host smart-f160d62c-a926-42af-a15b-f2ab4aea0feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798352667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.798352667
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2666640669
Short name T425
Test name
Test status
Simulation time 1821231842 ps
CPU time 9.85 seconds
Started Jun 11 03:24:03 PM PDT 24
Finished Jun 11 03:24:14 PM PDT 24
Peak memory 215988 kb
Host smart-977e2687-f7cb-4b04-9332-49a81ceb48eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666640669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2666640669
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.536212099
Short name T696
Test name
Test status
Simulation time 239228820 ps
CPU time 2.27 seconds
Started Jun 11 03:24:05 PM PDT 24
Finished Jun 11 03:24:09 PM PDT 24
Peak memory 216064 kb
Host smart-31b568ca-ffbd-4dc2-92ec-fe53b8f634e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536212099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.536212099
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.589671693
Short name T61
Test name
Test status
Simulation time 133694667 ps
CPU time 0.74 seconds
Started Jun 11 03:24:06 PM PDT 24
Finished Jun 11 03:24:08 PM PDT 24
Peak memory 205684 kb
Host smart-ab013136-3349-4db7-8159-04665724ec98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589671693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.589671693
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2733437942
Short name T266
Test name
Test status
Simulation time 1725104492 ps
CPU time 6.33 seconds
Started Jun 11 03:24:07 PM PDT 24
Finished Jun 11 03:24:15 PM PDT 24
Peak memory 238808 kb
Host smart-0aa4d79f-c0ad-4a05-9891-11b8208f0267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733437942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2733437942
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2660813310
Short name T356
Test name
Test status
Simulation time 76212847 ps
CPU time 0.72 seconds
Started Jun 11 03:21:42 PM PDT 24
Finished Jun 11 03:21:44 PM PDT 24
Peak memory 205596 kb
Host smart-991a334a-af87-4f3f-9158-fdd4d4846b51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660813310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
660813310
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.417801009
Short name T92
Test name
Test status
Simulation time 486465344 ps
CPU time 3.09 seconds
Started Jun 11 03:21:35 PM PDT 24
Finished Jun 11 03:21:39 PM PDT 24
Peak memory 224280 kb
Host smart-ec56e03c-6b2e-43bb-a590-45dce52dcb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417801009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.417801009
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.4156228123
Short name T347
Test name
Test status
Simulation time 37432725 ps
CPU time 0.77 seconds
Started Jun 11 03:21:32 PM PDT 24
Finished Jun 11 03:21:35 PM PDT 24
Peak memory 206356 kb
Host smart-f5861ecc-1d5b-4aa2-a4fc-35acb742caf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156228123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.4156228123
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1639049956
Short name T318
Test name
Test status
Simulation time 17399535027 ps
CPU time 119.17 seconds
Started Jun 11 03:21:42 PM PDT 24
Finished Jun 11 03:23:43 PM PDT 24
Peak memory 240820 kb
Host smart-6b105323-cf58-48d8-8b7d-2f3802fd484c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639049956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1639049956
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2740492688
Short name T870
Test name
Test status
Simulation time 33804320095 ps
CPU time 342.69 seconds
Started Jun 11 03:21:40 PM PDT 24
Finished Jun 11 03:27:24 PM PDT 24
Peak memory 250636 kb
Host smart-f41d9df4-d889-433e-86e8-c88291263540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740492688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2740492688
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.4181979405
Short name T607
Test name
Test status
Simulation time 23939686958 ps
CPU time 46.43 seconds
Started Jun 11 03:21:41 PM PDT 24
Finished Jun 11 03:22:29 PM PDT 24
Peak memory 249132 kb
Host smart-6bb51ab2-4fc8-4cd1-9e76-b0639cbadc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181979405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.4181979405
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2353383549
Short name T798
Test name
Test status
Simulation time 15707295020 ps
CPU time 46.55 seconds
Started Jun 11 03:21:36 PM PDT 24
Finished Jun 11 03:22:24 PM PDT 24
Peak memory 232564 kb
Host smart-d755ab0b-50df-43b7-a778-bc6666969e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353383549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2353383549
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1273937945
Short name T944
Test name
Test status
Simulation time 2232415695 ps
CPU time 23.25 seconds
Started Jun 11 03:21:32 PM PDT 24
Finished Jun 11 03:21:58 PM PDT 24
Peak memory 224300 kb
Host smart-ccfce99c-938c-4828-b1fd-2f32f1049358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273937945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1273937945
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2433679692
Short name T869
Test name
Test status
Simulation time 4032349592 ps
CPU time 37.29 seconds
Started Jun 11 03:21:35 PM PDT 24
Finished Jun 11 03:22:14 PM PDT 24
Peak memory 232556 kb
Host smart-31023e47-8f7b-495f-a745-cb1e1acd26c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433679692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2433679692
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1513914409
Short name T513
Test name
Test status
Simulation time 49781830 ps
CPU time 1.06 seconds
Started Jun 11 03:21:31 PM PDT 24
Finished Jun 11 03:21:34 PM PDT 24
Peak memory 217740 kb
Host smart-f7ffcc25-602d-402c-8d89-d8244392c53e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513914409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1513914409
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1516597013
Short name T896
Test name
Test status
Simulation time 11365286892 ps
CPU time 29.15 seconds
Started Jun 11 03:21:33 PM PDT 24
Finished Jun 11 03:22:04 PM PDT 24
Peak memory 224432 kb
Host smart-792d4566-c0d1-4d81-8e79-ee776e6880aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516597013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1516597013
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3987951220
Short name T273
Test name
Test status
Simulation time 1286700860 ps
CPU time 4.4 seconds
Started Jun 11 03:21:32 PM PDT 24
Finished Jun 11 03:21:39 PM PDT 24
Peak memory 224256 kb
Host smart-c63f5820-1cae-41dc-952d-ee7053bc7024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987951220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3987951220
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3041504465
Short name T691
Test name
Test status
Simulation time 990782860 ps
CPU time 3.67 seconds
Started Jun 11 03:21:41 PM PDT 24
Finished Jun 11 03:21:46 PM PDT 24
Peak memory 219692 kb
Host smart-7f0318d9-2206-4ad7-96de-c3901ee46c4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3041504465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3041504465
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2948498294
Short name T16
Test name
Test status
Simulation time 306458289 ps
CPU time 1.09 seconds
Started Jun 11 03:21:45 PM PDT 24
Finished Jun 11 03:21:47 PM PDT 24
Peak memory 235356 kb
Host smart-a6fb30da-d82d-464c-8b58-8af8387d2fc3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948498294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2948498294
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.17340105
Short name T589
Test name
Test status
Simulation time 24190723102 ps
CPU time 28.4 seconds
Started Jun 11 03:21:32 PM PDT 24
Finished Jun 11 03:22:03 PM PDT 24
Peak memory 216148 kb
Host smart-f3b5b46f-a21b-4305-b8d9-00fb7daeaba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17340105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.17340105
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.4022598909
Short name T381
Test name
Test status
Simulation time 5088948682 ps
CPU time 5.12 seconds
Started Jun 11 03:21:35 PM PDT 24
Finished Jun 11 03:21:42 PM PDT 24
Peak memory 216148 kb
Host smart-49555cce-2330-4663-affa-8efba3d1de14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022598909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.4022598909
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1652321149
Short name T502
Test name
Test status
Simulation time 248518305 ps
CPU time 4.62 seconds
Started Jun 11 03:21:36 PM PDT 24
Finished Jun 11 03:21:42 PM PDT 24
Peak memory 215932 kb
Host smart-9aa19bac-eb66-42a3-a222-8762b36722c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652321149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1652321149
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2538433195
Short name T558
Test name
Test status
Simulation time 124439717 ps
CPU time 1.03 seconds
Started Jun 11 03:21:32 PM PDT 24
Finished Jun 11 03:21:35 PM PDT 24
Peak memory 205676 kb
Host smart-1d3076c1-28d6-453a-be26-968d93f339af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538433195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2538433195
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.254899480
Short name T721
Test name
Test status
Simulation time 40082305 ps
CPU time 2.13 seconds
Started Jun 11 03:21:35 PM PDT 24
Finished Jun 11 03:21:38 PM PDT 24
Peak memory 222548 kb
Host smart-f18a522a-cc2d-42f5-af6d-6c27c0cf797a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254899480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.254899480
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1847102952
Short name T967
Test name
Test status
Simulation time 178400359 ps
CPU time 0.77 seconds
Started Jun 11 03:24:03 PM PDT 24
Finished Jun 11 03:24:05 PM PDT 24
Peak memory 205684 kb
Host smart-f854c6c8-e221-4aa1-a40f-980f6ebfb9e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847102952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1847102952
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1072598802
Short name T864
Test name
Test status
Simulation time 751880978 ps
CPU time 3.56 seconds
Started Jun 11 03:24:07 PM PDT 24
Finished Jun 11 03:24:12 PM PDT 24
Peak memory 224364 kb
Host smart-965ad104-13f2-4c2e-96f6-0d11e12be0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072598802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1072598802
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3018054733
Short name T888
Test name
Test status
Simulation time 20143017 ps
CPU time 0.84 seconds
Started Jun 11 03:24:07 PM PDT 24
Finished Jun 11 03:24:10 PM PDT 24
Peak memory 205700 kb
Host smart-04abaf0f-f95a-4d6d-acfa-b01f53282a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018054733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3018054733
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.722697379
Short name T179
Test name
Test status
Simulation time 12164772660 ps
CPU time 93.25 seconds
Started Jun 11 03:24:04 PM PDT 24
Finished Jun 11 03:25:39 PM PDT 24
Peak memory 249048 kb
Host smart-ae847422-c23b-489b-a790-079e7d925830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722697379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.722697379
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.130409726
Short name T937
Test name
Test status
Simulation time 51619191642 ps
CPU time 184.24 seconds
Started Jun 11 03:24:10 PM PDT 24
Finished Jun 11 03:27:16 PM PDT 24
Peak memory 249312 kb
Host smart-999b47de-7e64-4fa9-bc39-ee5259d40a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130409726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.130409726
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1413355695
Short name T342
Test name
Test status
Simulation time 37891616734 ps
CPU time 95.01 seconds
Started Jun 11 03:24:06 PM PDT 24
Finished Jun 11 03:25:43 PM PDT 24
Peak memory 249352 kb
Host smart-49251895-3abe-4811-a2ae-5629ff06c081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413355695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1413355695
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2963891646
Short name T418
Test name
Test status
Simulation time 142533295 ps
CPU time 3.43 seconds
Started Jun 11 03:24:11 PM PDT 24
Finished Jun 11 03:24:16 PM PDT 24
Peak memory 224316 kb
Host smart-84b2804c-c7f5-407b-b645-92955eaf4e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963891646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2963891646
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1958270580
Short name T509
Test name
Test status
Simulation time 130300280 ps
CPU time 3.25 seconds
Started Jun 11 03:24:05 PM PDT 24
Finished Jun 11 03:24:10 PM PDT 24
Peak memory 224248 kb
Host smart-6bf07b99-fd8f-474c-b19d-9413323aed67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958270580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1958270580
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3083633414
Short name T225
Test name
Test status
Simulation time 6724768838 ps
CPU time 69.01 seconds
Started Jun 11 03:24:08 PM PDT 24
Finished Jun 11 03:25:19 PM PDT 24
Peak memory 232620 kb
Host smart-83eafb81-ce13-4329-9745-4ccb792802ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083633414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3083633414
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3037955792
Short name T958
Test name
Test status
Simulation time 556304486 ps
CPU time 7.88 seconds
Started Jun 11 03:24:09 PM PDT 24
Finished Jun 11 03:24:19 PM PDT 24
Peak memory 224344 kb
Host smart-c120f0b7-1108-4fd0-9c2c-cc9bdb512644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037955792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3037955792
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1551464342
Short name T559
Test name
Test status
Simulation time 5353306713 ps
CPU time 9.41 seconds
Started Jun 11 03:24:07 PM PDT 24
Finished Jun 11 03:24:18 PM PDT 24
Peak memory 232648 kb
Host smart-de364ef2-677e-4f6e-ad1f-a4ffa39ee450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551464342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1551464342
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3571714066
Short name T602
Test name
Test status
Simulation time 674397365 ps
CPU time 5.27 seconds
Started Jun 11 03:24:05 PM PDT 24
Finished Jun 11 03:24:12 PM PDT 24
Peak memory 220200 kb
Host smart-d6189455-6dc2-4638-b551-8c11c726c103
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3571714066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3571714066
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.151311661
Short name T741
Test name
Test status
Simulation time 11710181944 ps
CPU time 80.23 seconds
Started Jun 11 03:24:05 PM PDT 24
Finished Jun 11 03:25:27 PM PDT 24
Peak memory 264604 kb
Host smart-92782330-734a-47a7-957f-4ee5b82280c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151311661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.151311661
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2684751017
Short name T335
Test name
Test status
Simulation time 12804000808 ps
CPU time 15.32 seconds
Started Jun 11 03:24:04 PM PDT 24
Finished Jun 11 03:24:21 PM PDT 24
Peak memory 216184 kb
Host smart-c9cd0b8a-c50e-43df-9fd8-280bd507409d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684751017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2684751017
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2557843788
Short name T578
Test name
Test status
Simulation time 1018311972 ps
CPU time 6.92 seconds
Started Jun 11 03:24:07 PM PDT 24
Finished Jun 11 03:24:15 PM PDT 24
Peak memory 216000 kb
Host smart-991fa909-2254-4027-b1ef-52657add319a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557843788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2557843788
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1715867745
Short name T523
Test name
Test status
Simulation time 501416985 ps
CPU time 4.59 seconds
Started Jun 11 03:24:07 PM PDT 24
Finished Jun 11 03:24:13 PM PDT 24
Peak memory 216104 kb
Host smart-01f37b89-76c9-423e-bf48-081642cbb835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715867745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1715867745
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2524372544
Short name T804
Test name
Test status
Simulation time 213276449 ps
CPU time 0.81 seconds
Started Jun 11 03:24:09 PM PDT 24
Finished Jun 11 03:24:12 PM PDT 24
Peak memory 205708 kb
Host smart-274a9c29-f55b-46e8-8e5f-7a86806d0137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524372544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2524372544
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3428206064
Short name T809
Test name
Test status
Simulation time 50688460 ps
CPU time 2.15 seconds
Started Jun 11 03:24:05 PM PDT 24
Finished Jun 11 03:24:09 PM PDT 24
Peak memory 223736 kb
Host smart-e0dc9fe7-16b8-4422-86e6-b34a0e5accc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428206064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3428206064
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2556597796
Short name T831
Test name
Test status
Simulation time 112857582 ps
CPU time 0.72 seconds
Started Jun 11 03:24:15 PM PDT 24
Finished Jun 11 03:24:17 PM PDT 24
Peak memory 205632 kb
Host smart-369da414-d2d1-4020-961c-06e5c501bee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556597796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2556597796
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.312699001
Short name T924
Test name
Test status
Simulation time 2993846655 ps
CPU time 10.16 seconds
Started Jun 11 03:24:12 PM PDT 24
Finished Jun 11 03:24:24 PM PDT 24
Peak memory 232644 kb
Host smart-810e503c-ccfc-4361-9a61-623b61af78ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312699001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.312699001
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3301485075
Short name T715
Test name
Test status
Simulation time 68850860 ps
CPU time 0.81 seconds
Started Jun 11 03:24:03 PM PDT 24
Finished Jun 11 03:24:05 PM PDT 24
Peak memory 206684 kb
Host smart-52c507f5-1146-4e97-ba87-62142133b366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301485075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3301485075
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3497541630
Short name T709
Test name
Test status
Simulation time 49811190974 ps
CPU time 137.54 seconds
Started Jun 11 03:24:11 PM PDT 24
Finished Jun 11 03:26:30 PM PDT 24
Peak memory 254832 kb
Host smart-5afe6194-51d8-419c-bf76-be225f23b6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497541630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3497541630
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1064813453
Short name T933
Test name
Test status
Simulation time 276308091814 ps
CPU time 621.01 seconds
Started Jun 11 03:24:11 PM PDT 24
Finished Jun 11 03:34:34 PM PDT 24
Peak memory 257280 kb
Host smart-fd2776bf-5e79-46a6-adc5-6082a5d789ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064813453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1064813453
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2573433288
Short name T151
Test name
Test status
Simulation time 1328921421 ps
CPU time 16.89 seconds
Started Jun 11 03:24:13 PM PDT 24
Finished Jun 11 03:24:32 PM PDT 24
Peak memory 236492 kb
Host smart-fa2613e2-8a09-452a-8226-ce7fa3f48be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573433288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2573433288
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3043590308
Short name T780
Test name
Test status
Simulation time 921207502 ps
CPU time 9.23 seconds
Started Jun 11 03:24:05 PM PDT 24
Finished Jun 11 03:24:16 PM PDT 24
Peak memory 232480 kb
Host smart-eaf5fb77-c05f-426f-a4cf-bbceddfa707f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043590308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3043590308
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2566999576
Short name T533
Test name
Test status
Simulation time 26975172334 ps
CPU time 54.88 seconds
Started Jun 11 03:24:17 PM PDT 24
Finished Jun 11 03:25:13 PM PDT 24
Peak memory 240604 kb
Host smart-e8a260a0-da84-4fc6-83ac-3bb8249e8d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566999576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2566999576
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1538524172
Short name T946
Test name
Test status
Simulation time 564762231 ps
CPU time 4.64 seconds
Started Jun 11 03:24:07 PM PDT 24
Finished Jun 11 03:24:13 PM PDT 24
Peak memory 224200 kb
Host smart-959bf8af-28a0-4581-9616-1b2bc0079f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538524172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1538524172
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3745943056
Short name T859
Test name
Test status
Simulation time 12042060927 ps
CPU time 18.33 seconds
Started Jun 11 03:24:05 PM PDT 24
Finished Jun 11 03:24:25 PM PDT 24
Peak memory 228372 kb
Host smart-579cd120-ace5-4395-87f4-8fb011b15af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745943056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3745943056
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1021272167
Short name T878
Test name
Test status
Simulation time 140508075 ps
CPU time 3.79 seconds
Started Jun 11 03:24:12 PM PDT 24
Finished Jun 11 03:24:17 PM PDT 24
Peak memory 222244 kb
Host smart-0cea5a7f-5052-4439-8b05-b989172615d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1021272167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1021272167
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1843225187
Short name T162
Test name
Test status
Simulation time 469761016 ps
CPU time 0.87 seconds
Started Jun 11 03:24:15 PM PDT 24
Finished Jun 11 03:24:18 PM PDT 24
Peak memory 206708 kb
Host smart-86761f15-78de-4437-a0de-6aa45486440c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843225187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1843225187
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3980198145
Short name T360
Test name
Test status
Simulation time 484392078 ps
CPU time 3.42 seconds
Started Jun 11 03:24:11 PM PDT 24
Finished Jun 11 03:24:16 PM PDT 24
Peak memory 216120 kb
Host smart-029a70b8-0a1a-454a-bb83-93de3648d1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980198145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3980198145
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.4039461939
Short name T413
Test name
Test status
Simulation time 16434441937 ps
CPU time 13.14 seconds
Started Jun 11 03:24:08 PM PDT 24
Finished Jun 11 03:24:23 PM PDT 24
Peak memory 216148 kb
Host smart-34a9c12e-46a3-41cb-8caa-227f4c1dad59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039461939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.4039461939
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3246161761
Short name T481
Test name
Test status
Simulation time 173121005 ps
CPU time 0.88 seconds
Started Jun 11 03:24:06 PM PDT 24
Finished Jun 11 03:24:09 PM PDT 24
Peak memory 206824 kb
Host smart-565532d1-4759-4ee3-a0af-1294ba7eee67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246161761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3246161761
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.461559269
Short name T825
Test name
Test status
Simulation time 32162287 ps
CPU time 0.72 seconds
Started Jun 11 03:24:07 PM PDT 24
Finished Jun 11 03:24:09 PM PDT 24
Peak memory 205420 kb
Host smart-45f96333-88bf-4d96-ae6e-f8f3023142cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461559269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.461559269
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2668441629
Short name T777
Test name
Test status
Simulation time 2038067850 ps
CPU time 7.68 seconds
Started Jun 11 03:24:15 PM PDT 24
Finished Jun 11 03:24:24 PM PDT 24
Peak memory 224348 kb
Host smart-84ec2f1e-4451-4faf-8e95-2da8ecc71fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668441629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2668441629
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.695037460
Short name T735
Test name
Test status
Simulation time 12767750 ps
CPU time 0.72 seconds
Started Jun 11 03:24:14 PM PDT 24
Finished Jun 11 03:24:17 PM PDT 24
Peak memory 204648 kb
Host smart-5208565c-04a7-42c0-a1a9-c437d7d1075d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695037460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.695037460
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1306263297
Short name T969
Test name
Test status
Simulation time 4950501131 ps
CPU time 6.44 seconds
Started Jun 11 03:24:15 PM PDT 24
Finished Jun 11 03:24:23 PM PDT 24
Peak memory 232620 kb
Host smart-b357f85e-7989-42b9-ab01-402ab8bf4ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306263297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1306263297
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2715079316
Short name T962
Test name
Test status
Simulation time 30590266 ps
CPU time 0.79 seconds
Started Jun 11 03:24:14 PM PDT 24
Finished Jun 11 03:24:16 PM PDT 24
Peak memory 205328 kb
Host smart-78f57fac-3284-4988-b989-445cf140bf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715079316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2715079316
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2373731003
Short name T305
Test name
Test status
Simulation time 1962316273 ps
CPU time 49.07 seconds
Started Jun 11 03:24:14 PM PDT 24
Finished Jun 11 03:25:05 PM PDT 24
Peak memory 253032 kb
Host smart-8740956f-cefa-4e84-8e1d-dd2ca085d6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373731003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2373731003
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1909814995
Short name T304
Test name
Test status
Simulation time 241702255537 ps
CPU time 576.86 seconds
Started Jun 11 03:24:10 PM PDT 24
Finished Jun 11 03:33:49 PM PDT 24
Peak memory 257232 kb
Host smart-d2ca7ed8-c3e8-4f11-9458-54371019fb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909814995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1909814995
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3526271904
Short name T562
Test name
Test status
Simulation time 17616296086 ps
CPU time 70.37 seconds
Started Jun 11 03:24:13 PM PDT 24
Finished Jun 11 03:25:25 PM PDT 24
Peak memory 249136 kb
Host smart-53b1a275-23f3-4e87-9c6f-b349630f0cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526271904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3526271904
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1113301920
Short name T354
Test name
Test status
Simulation time 420953102 ps
CPU time 8.84 seconds
Started Jun 11 03:24:14 PM PDT 24
Finished Jun 11 03:24:25 PM PDT 24
Peak memory 232556 kb
Host smart-01293a21-7dc9-4b3f-9752-dc606b2594f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113301920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1113301920
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1349798169
Short name T791
Test name
Test status
Simulation time 901297760 ps
CPU time 9.08 seconds
Started Jun 11 03:24:15 PM PDT 24
Finished Jun 11 03:24:26 PM PDT 24
Peak memory 229508 kb
Host smart-c6c10633-f982-49cf-a738-332181b97e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349798169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1349798169
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3886583601
Short name T812
Test name
Test status
Simulation time 35586972 ps
CPU time 2.52 seconds
Started Jun 11 03:24:10 PM PDT 24
Finished Jun 11 03:24:15 PM PDT 24
Peak memory 232360 kb
Host smart-0127ba5a-f31d-4a2a-9e77-547116beded2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886583601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3886583601
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.861211101
Short name T928
Test name
Test status
Simulation time 391072483 ps
CPU time 3.01 seconds
Started Jun 11 03:24:12 PM PDT 24
Finished Jun 11 03:24:17 PM PDT 24
Peak memory 232728 kb
Host smart-a056b213-c40b-4ebc-a8b5-4a5d2a8889fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861211101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.861211101
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3599154839
Short name T43
Test name
Test status
Simulation time 20072285708 ps
CPU time 12.21 seconds
Started Jun 11 03:24:13 PM PDT 24
Finished Jun 11 03:24:27 PM PDT 24
Peak memory 232660 kb
Host smart-9f08c3ee-3670-4110-9115-795b0c3236fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599154839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3599154839
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3715850313
Short name T868
Test name
Test status
Simulation time 9873443856 ps
CPU time 11.67 seconds
Started Jun 11 03:24:12 PM PDT 24
Finished Jun 11 03:24:26 PM PDT 24
Peak memory 218788 kb
Host smart-f2de3e49-501b-4417-af47-6fac384547d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3715850313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3715850313
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2772914918
Short name T22
Test name
Test status
Simulation time 200197171 ps
CPU time 1.07 seconds
Started Jun 11 03:24:13 PM PDT 24
Finished Jun 11 03:24:16 PM PDT 24
Peak memory 206816 kb
Host smart-6e94aeed-8ed6-43ae-95d2-ed7fd4e585cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772914918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2772914918
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3592073777
Short name T339
Test name
Test status
Simulation time 3440457482 ps
CPU time 7.99 seconds
Started Jun 11 03:24:14 PM PDT 24
Finished Jun 11 03:24:24 PM PDT 24
Peak memory 218028 kb
Host smart-43089739-024a-4f08-ba30-e8b5cff9ffb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592073777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3592073777
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.4048565210
Short name T624
Test name
Test status
Simulation time 9584872268 ps
CPU time 15.24 seconds
Started Jun 11 03:24:12 PM PDT 24
Finished Jun 11 03:24:29 PM PDT 24
Peak memory 216164 kb
Host smart-e6ef0af0-0ce7-47d7-94a6-66a6770f8d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048565210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.4048565210
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1138618576
Short name T693
Test name
Test status
Simulation time 79929361 ps
CPU time 1.95 seconds
Started Jun 11 03:24:12 PM PDT 24
Finished Jun 11 03:24:16 PM PDT 24
Peak memory 216020 kb
Host smart-e453253b-df2b-4796-bd8c-a26e0aeb09c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138618576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1138618576
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1490300335
Short name T723
Test name
Test status
Simulation time 83365723 ps
CPU time 0.84 seconds
Started Jun 11 03:24:15 PM PDT 24
Finished Jun 11 03:24:18 PM PDT 24
Peak memory 205660 kb
Host smart-e7e05e8f-8b99-4e0a-9e28-2c799008c3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490300335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1490300335
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3207872461
Short name T981
Test name
Test status
Simulation time 219063311 ps
CPU time 3.89 seconds
Started Jun 11 03:24:13 PM PDT 24
Finished Jun 11 03:24:18 PM PDT 24
Peak memory 232468 kb
Host smart-a54aa636-553b-4ba1-94db-9c16fa059220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207872461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3207872461
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1343374620
Short name T954
Test name
Test status
Simulation time 22979779 ps
CPU time 0.72 seconds
Started Jun 11 03:24:18 PM PDT 24
Finished Jun 11 03:24:20 PM PDT 24
Peak memory 205652 kb
Host smart-3ade97db-f781-4c70-a75b-6e0e60f035fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343374620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1343374620
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.870054103
Short name T718
Test name
Test status
Simulation time 143872898 ps
CPU time 2.26 seconds
Started Jun 11 03:24:12 PM PDT 24
Finished Jun 11 03:24:16 PM PDT 24
Peak memory 224288 kb
Host smart-6fae5bdc-4298-42bd-a153-a76dcf329720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870054103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.870054103
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2737361150
Short name T28
Test name
Test status
Simulation time 75156814 ps
CPU time 0.8 seconds
Started Jun 11 03:24:14 PM PDT 24
Finished Jun 11 03:24:16 PM PDT 24
Peak memory 206376 kb
Host smart-b308d369-e997-43d4-9f4c-954b39b0dd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737361150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2737361150
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.4100216902
Short name T222
Test name
Test status
Simulation time 8885062012 ps
CPU time 60.41 seconds
Started Jun 11 03:24:23 PM PDT 24
Finished Jun 11 03:25:25 PM PDT 24
Peak memory 250144 kb
Host smart-5b0e155d-f819-4b7f-9d4b-54a9b4eaae07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100216902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.4100216902
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2750816708
Short name T461
Test name
Test status
Simulation time 11726378059 ps
CPU time 132.14 seconds
Started Jun 11 03:24:22 PM PDT 24
Finished Jun 11 03:26:36 PM PDT 24
Peak memory 264820 kb
Host smart-f5b0f645-e552-4d0e-ba66-3f2e0c7a200a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750816708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2750816708
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.541999454
Short name T847
Test name
Test status
Simulation time 964116853 ps
CPU time 5.7 seconds
Started Jun 11 03:24:22 PM PDT 24
Finished Jun 11 03:24:30 PM PDT 24
Peak memory 218488 kb
Host smart-3890a73e-d330-4826-b12c-313f14be1d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541999454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.541999454
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.4191257911
Short name T198
Test name
Test status
Simulation time 197693493 ps
CPU time 2.38 seconds
Started Jun 11 03:24:13 PM PDT 24
Finished Jun 11 03:24:17 PM PDT 24
Peak memory 224280 kb
Host smart-cb82e4e1-2831-47e7-9e53-70be2f96d3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191257911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.4191257911
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2096023796
Short name T543
Test name
Test status
Simulation time 24594475625 ps
CPU time 82.41 seconds
Started Jun 11 03:24:11 PM PDT 24
Finished Jun 11 03:25:35 PM PDT 24
Peak memory 240632 kb
Host smart-189167e8-3a86-4ecd-a15f-b201c3321804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096023796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2096023796
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1771083940
Short name T55
Test name
Test status
Simulation time 512019279 ps
CPU time 5.61 seconds
Started Jun 11 03:24:15 PM PDT 24
Finished Jun 11 03:24:23 PM PDT 24
Peak memory 232448 kb
Host smart-ef14d8b5-0748-4449-a35c-5b9295d2e47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771083940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1771083940
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2463779844
Short name T254
Test name
Test status
Simulation time 32866160671 ps
CPU time 16.71 seconds
Started Jun 11 03:24:11 PM PDT 24
Finished Jun 11 03:24:30 PM PDT 24
Peak memory 224380 kb
Host smart-2f061893-4cb0-4a98-b351-8546e461bb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463779844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2463779844
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.35133855
Short name T823
Test name
Test status
Simulation time 539343022 ps
CPU time 5.05 seconds
Started Jun 11 03:24:20 PM PDT 24
Finished Jun 11 03:24:27 PM PDT 24
Peak memory 222408 kb
Host smart-75bddd27-bbbb-46d1-8639-3b3159b57290
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=35133855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direc
t.35133855
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2759919480
Short name T249
Test name
Test status
Simulation time 216099722673 ps
CPU time 487.31 seconds
Started Jun 11 03:24:25 PM PDT 24
Finished Jun 11 03:32:34 PM PDT 24
Peak memory 257244 kb
Host smart-cc69bcd8-5b49-4ee5-a51e-13ccfba9b0e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759919480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2759919480
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.941205095
Short name T551
Test name
Test status
Simulation time 2031947240 ps
CPU time 15.63 seconds
Started Jun 11 03:24:14 PM PDT 24
Finished Jun 11 03:24:31 PM PDT 24
Peak memory 216072 kb
Host smart-e3fcf285-fa02-4357-89d2-5bc89f1d02a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941205095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.941205095
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3256967321
Short name T670
Test name
Test status
Simulation time 14010480695 ps
CPU time 22.09 seconds
Started Jun 11 03:24:12 PM PDT 24
Finished Jun 11 03:24:36 PM PDT 24
Peak memory 216164 kb
Host smart-425fad6d-759a-4710-92ea-2533e3a532f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256967321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3256967321
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1981319168
Short name T424
Test name
Test status
Simulation time 115131590 ps
CPU time 1.37 seconds
Started Jun 11 03:24:16 PM PDT 24
Finished Jun 11 03:24:19 PM PDT 24
Peak memory 216108 kb
Host smart-80f4f8cc-955d-4625-8865-279b4e7c42cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981319168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1981319168
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3282209557
Short name T480
Test name
Test status
Simulation time 62141507 ps
CPU time 0.86 seconds
Started Jun 11 03:24:12 PM PDT 24
Finished Jun 11 03:24:15 PM PDT 24
Peak memory 205700 kb
Host smart-ac3319a7-4860-48ae-9d9b-cae230e98d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282209557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3282209557
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.751251878
Short name T457
Test name
Test status
Simulation time 2299683766 ps
CPU time 5.32 seconds
Started Jun 11 03:24:14 PM PDT 24
Finished Jun 11 03:24:21 PM PDT 24
Peak memory 224416 kb
Host smart-b154353f-c714-4f95-9ddc-334db07b7b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751251878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.751251878
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3761163648
Short name T71
Test name
Test status
Simulation time 23933492 ps
CPU time 0.75 seconds
Started Jun 11 03:24:20 PM PDT 24
Finished Jun 11 03:24:23 PM PDT 24
Peak memory 205260 kb
Host smart-f2f1e33b-97cd-439c-9d73-a8d3fabbf0b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761163648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3761163648
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3120849751
Short name T193
Test name
Test status
Simulation time 190608403 ps
CPU time 2.56 seconds
Started Jun 11 03:24:22 PM PDT 24
Finished Jun 11 03:24:27 PM PDT 24
Peak memory 232548 kb
Host smart-5ccb8269-63f5-4e98-af2c-cbe2dbdfd300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120849751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3120849751
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3818651756
Short name T890
Test name
Test status
Simulation time 21214887 ps
CPU time 0.81 seconds
Started Jun 11 03:24:22 PM PDT 24
Finished Jun 11 03:24:25 PM PDT 24
Peak memory 206396 kb
Host smart-8de9bc08-c872-4558-bab1-90a34b9a2680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818651756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3818651756
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3613587595
Short name T487
Test name
Test status
Simulation time 2318228077 ps
CPU time 5.86 seconds
Started Jun 11 03:24:20 PM PDT 24
Finished Jun 11 03:24:28 PM PDT 24
Peak memory 224460 kb
Host smart-ebab61eb-2c8a-4fed-baae-5bf9395b15df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613587595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3613587595
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1739633843
Short name T316
Test name
Test status
Simulation time 25514057142 ps
CPU time 85.31 seconds
Started Jun 11 03:24:20 PM PDT 24
Finished Jun 11 03:25:47 PM PDT 24
Peak memory 252140 kb
Host smart-e197dbf5-0dfe-4dab-9865-5daa48122f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739633843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1739633843
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2302787224
Short name T871
Test name
Test status
Simulation time 949174003 ps
CPU time 13.97 seconds
Started Jun 11 03:24:22 PM PDT 24
Finished Jun 11 03:24:38 PM PDT 24
Peak memory 224396 kb
Host smart-58be8aae-a84d-49bf-a68d-81056b5dd707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302787224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2302787224
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1031881888
Short name T711
Test name
Test status
Simulation time 851895484 ps
CPU time 16.22 seconds
Started Jun 11 03:24:24 PM PDT 24
Finished Jun 11 03:24:42 PM PDT 24
Peak memory 240712 kb
Host smart-225c80ba-dc05-4612-9735-a66f15dead28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031881888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1031881888
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.388430537
Short name T229
Test name
Test status
Simulation time 236317138 ps
CPU time 4.53 seconds
Started Jun 11 03:24:22 PM PDT 24
Finished Jun 11 03:24:29 PM PDT 24
Peak memory 232568 kb
Host smart-4198dd7a-579f-47c9-a966-9542d97647e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388430537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.388430537
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2697825485
Short name T548
Test name
Test status
Simulation time 4000985589 ps
CPU time 23.29 seconds
Started Jun 11 03:24:22 PM PDT 24
Finished Jun 11 03:24:47 PM PDT 24
Peak memory 218644 kb
Host smart-a0938e61-c78d-4ffb-9b5d-e768d1a16520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697825485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2697825485
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.81700441
Short name T774
Test name
Test status
Simulation time 1023881133 ps
CPU time 5.56 seconds
Started Jun 11 03:24:26 PM PDT 24
Finished Jun 11 03:24:33 PM PDT 24
Peak memory 218392 kb
Host smart-7c849b11-7742-4612-9b92-64feb0ca27af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81700441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.81700441
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.728661863
Short name T134
Test name
Test status
Simulation time 88657130364 ps
CPU time 13.59 seconds
Started Jun 11 03:24:23 PM PDT 24
Finished Jun 11 03:24:38 PM PDT 24
Peak memory 240692 kb
Host smart-dcb51f9f-d2aa-4f4e-a974-e406b00b1b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728661863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.728661863
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.4156557126
Short name T93
Test name
Test status
Simulation time 6756971783 ps
CPU time 9.96 seconds
Started Jun 11 03:24:19 PM PDT 24
Finished Jun 11 03:24:30 PM PDT 24
Peak memory 222160 kb
Host smart-dc4d7d16-8bec-46eb-9322-f95571514ddc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4156557126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.4156557126
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3897362601
Short name T142
Test name
Test status
Simulation time 101278874600 ps
CPU time 193.55 seconds
Started Jun 11 03:24:24 PM PDT 24
Finished Jun 11 03:27:40 PM PDT 24
Peak memory 264520 kb
Host smart-0201ef0e-6557-4c52-a4b7-7600f33e710d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897362601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3897362601
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1208616512
Short name T909
Test name
Test status
Simulation time 3754252183 ps
CPU time 21.91 seconds
Started Jun 11 03:24:20 PM PDT 24
Finished Jun 11 03:24:44 PM PDT 24
Peak memory 216220 kb
Host smart-7def847c-8f9d-4b85-899c-024e54dd8d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208616512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1208616512
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.411245339
Short name T697
Test name
Test status
Simulation time 2788055691 ps
CPU time 4.9 seconds
Started Jun 11 03:24:22 PM PDT 24
Finished Jun 11 03:24:29 PM PDT 24
Peak memory 216096 kb
Host smart-9dc30997-180c-4af6-bf13-ac2524f5abea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411245339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.411245339
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.605714645
Short name T378
Test name
Test status
Simulation time 278710151 ps
CPU time 1.39 seconds
Started Jun 11 03:24:19 PM PDT 24
Finished Jun 11 03:24:22 PM PDT 24
Peak memory 216104 kb
Host smart-6af3bfdf-b4cc-414c-a855-addf99de1be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605714645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.605714645
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2658773803
Short name T572
Test name
Test status
Simulation time 187693942 ps
CPU time 0.9 seconds
Started Jun 11 03:24:19 PM PDT 24
Finished Jun 11 03:24:21 PM PDT 24
Peak memory 206748 kb
Host smart-fedc73fc-b31e-4ff3-b29c-1d8f4c962150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658773803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2658773803
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3672916151
Short name T906
Test name
Test status
Simulation time 28141518368 ps
CPU time 23.52 seconds
Started Jun 11 03:24:22 PM PDT 24
Finished Jun 11 03:24:48 PM PDT 24
Peak memory 224488 kb
Host smart-2ad1fc54-90fc-4af7-874c-31b028f6b0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672916151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3672916151
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.4223869465
Short name T435
Test name
Test status
Simulation time 20635809 ps
CPU time 0.74 seconds
Started Jun 11 03:24:25 PM PDT 24
Finished Jun 11 03:24:27 PM PDT 24
Peak memory 205620 kb
Host smart-657fe306-bbb6-4574-a2ab-90ff0eb8ba77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223869465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4223869465
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.333472692
Short name T404
Test name
Test status
Simulation time 972054968 ps
CPU time 4.76 seconds
Started Jun 11 03:24:22 PM PDT 24
Finished Jun 11 03:24:29 PM PDT 24
Peak memory 224340 kb
Host smart-fad81a96-eb65-40d0-950d-7fa5bfd1f3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333472692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.333472692
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.4268707894
Short name T593
Test name
Test status
Simulation time 52341072 ps
CPU time 0.77 seconds
Started Jun 11 03:24:20 PM PDT 24
Finished Jun 11 03:24:22 PM PDT 24
Peak memory 206356 kb
Host smart-0def64cd-8552-4c7f-89a6-1dc27278a376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268707894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.4268707894
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2364134449
Short name T881
Test name
Test status
Simulation time 39212282 ps
CPU time 0.77 seconds
Started Jun 11 03:24:23 PM PDT 24
Finished Jun 11 03:24:26 PM PDT 24
Peak memory 215808 kb
Host smart-d83f62e5-0d78-4967-82c1-cd5d06c7a3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364134449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2364134449
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1421373544
Short name T34
Test name
Test status
Simulation time 53218651565 ps
CPU time 542.82 seconds
Started Jun 11 03:24:24 PM PDT 24
Finished Jun 11 03:33:29 PM PDT 24
Peak memory 266104 kb
Host smart-9b00cb6f-5afc-49e4-b474-29b91bf4d506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421373544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1421373544
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2235036784
Short name T950
Test name
Test status
Simulation time 235553121843 ps
CPU time 224.55 seconds
Started Jun 11 03:24:20 PM PDT 24
Finished Jun 11 03:28:07 PM PDT 24
Peak memory 251096 kb
Host smart-fc1cc021-1f87-4030-a77a-4196889a36b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235036784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2235036784
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1733572679
Short name T148
Test name
Test status
Simulation time 552130270 ps
CPU time 5.03 seconds
Started Jun 11 03:24:27 PM PDT 24
Finished Jun 11 03:24:34 PM PDT 24
Peak memory 224312 kb
Host smart-922d003f-4c13-4ac8-bafa-d913886e2c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733572679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1733572679
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2770977800
Short name T975
Test name
Test status
Simulation time 315972684 ps
CPU time 6.78 seconds
Started Jun 11 03:24:20 PM PDT 24
Finished Jun 11 03:24:28 PM PDT 24
Peak memory 224260 kb
Host smart-e3659519-c8f5-4da1-a7e9-a971b24fda7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770977800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2770977800
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.612941732
Short name T616
Test name
Test status
Simulation time 805544611 ps
CPU time 3.29 seconds
Started Jun 11 03:24:20 PM PDT 24
Finished Jun 11 03:24:25 PM PDT 24
Peak memory 224280 kb
Host smart-5d7ab473-aef3-4801-b329-af84cff8f6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612941732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.612941732
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1493665138
Short name T603
Test name
Test status
Simulation time 536514522 ps
CPU time 4.14 seconds
Started Jun 11 03:24:24 PM PDT 24
Finished Jun 11 03:24:30 PM PDT 24
Peak memory 232516 kb
Host smart-d94319ec-45bf-4f2a-9630-e78e19144170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493665138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1493665138
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1034647533
Short name T170
Test name
Test status
Simulation time 2299040025 ps
CPU time 11.74 seconds
Started Jun 11 03:24:20 PM PDT 24
Finished Jun 11 03:24:34 PM PDT 24
Peak memory 232588 kb
Host smart-d4b37fab-57c1-4696-bd91-c65d84a055fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034647533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1034647533
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3618155216
Short name T554
Test name
Test status
Simulation time 162551635 ps
CPU time 3.72 seconds
Started Jun 11 03:24:23 PM PDT 24
Finished Jun 11 03:24:29 PM PDT 24
Peak memory 222672 kb
Host smart-5cf7daba-02ae-4cae-8889-c217898f5603
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3618155216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3618155216
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3344002878
Short name T495
Test name
Test status
Simulation time 179803959 ps
CPU time 1.01 seconds
Started Jun 11 03:24:20 PM PDT 24
Finished Jun 11 03:24:23 PM PDT 24
Peak memory 206720 kb
Host smart-70b24ead-3c06-4ced-bfab-f3eb08c7eb3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344002878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3344002878
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.546648499
Short name T683
Test name
Test status
Simulation time 3808797284 ps
CPU time 30.35 seconds
Started Jun 11 03:24:20 PM PDT 24
Finished Jun 11 03:24:52 PM PDT 24
Peak memory 220020 kb
Host smart-9e752ebf-f6f3-41d5-b9c8-29fc6456ca31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546648499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.546648499
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2405030153
Short name T357
Test name
Test status
Simulation time 3373271261 ps
CPU time 7.52 seconds
Started Jun 11 03:24:21 PM PDT 24
Finished Jun 11 03:24:30 PM PDT 24
Peak memory 216204 kb
Host smart-5b215201-25cb-4bce-949f-9a8093b69ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405030153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2405030153
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3976872888
Short name T477
Test name
Test status
Simulation time 44224237 ps
CPU time 2 seconds
Started Jun 11 03:24:23 PM PDT 24
Finished Jun 11 03:24:27 PM PDT 24
Peak memory 215984 kb
Host smart-ee2ecd67-d223-4d47-9610-9edcc18a57bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976872888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3976872888
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.42603653
Short name T976
Test name
Test status
Simulation time 141699007 ps
CPU time 1.12 seconds
Started Jun 11 03:24:25 PM PDT 24
Finished Jun 11 03:24:28 PM PDT 24
Peak memory 205664 kb
Host smart-aa3fe586-53c3-457b-ab82-5c89fac678d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42603653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.42603653
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1038063856
Short name T522
Test name
Test status
Simulation time 2855161935 ps
CPU time 13.24 seconds
Started Jun 11 03:24:20 PM PDT 24
Finished Jun 11 03:24:35 PM PDT 24
Peak memory 232632 kb
Host smart-40b7a6e0-5359-4334-b450-dbb61f8ec9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038063856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1038063856
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.14865292
Short name T66
Test name
Test status
Simulation time 13282930 ps
CPU time 0.74 seconds
Started Jun 11 03:24:28 PM PDT 24
Finished Jun 11 03:24:30 PM PDT 24
Peak memory 205264 kb
Host smart-8770a230-0682-4beb-8f82-a47870d5d659
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14865292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.14865292
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.175134494
Short name T744
Test name
Test status
Simulation time 10949869205 ps
CPU time 12.6 seconds
Started Jun 11 03:24:37 PM PDT 24
Finished Jun 11 03:24:51 PM PDT 24
Peak memory 224484 kb
Host smart-199d292f-9992-47e7-8cce-93bb43229f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175134494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.175134494
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.4287359375
Short name T587
Test name
Test status
Simulation time 18370089 ps
CPU time 0.79 seconds
Started Jun 11 03:24:21 PM PDT 24
Finished Jun 11 03:24:24 PM PDT 24
Peak memory 205372 kb
Host smart-e23ee421-2ca4-46e3-acc0-a987a69283ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287359375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.4287359375
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2040370766
Short name T679
Test name
Test status
Simulation time 2417018746 ps
CPU time 32.91 seconds
Started Jun 11 03:24:32 PM PDT 24
Finished Jun 11 03:25:06 PM PDT 24
Peak memory 240860 kb
Host smart-f62ef5f9-7dbc-45d6-a480-1ef09f102b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040370766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2040370766
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1456212141
Short name T50
Test name
Test status
Simulation time 31081985825 ps
CPU time 173.37 seconds
Started Jun 11 03:24:28 PM PDT 24
Finished Jun 11 03:27:23 PM PDT 24
Peak memory 249088 kb
Host smart-8c1e5e90-4826-46dd-82d0-e2023086aba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456212141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1456212141
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1513671588
Short name T915
Test name
Test status
Simulation time 57620502555 ps
CPU time 291.61 seconds
Started Jun 11 03:24:32 PM PDT 24
Finished Jun 11 03:29:24 PM PDT 24
Peak memory 256612 kb
Host smart-b3702bb9-924a-4965-b014-e3464be37c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513671588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1513671588
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4126721687
Short name T147
Test name
Test status
Simulation time 4593794785 ps
CPU time 23.43 seconds
Started Jun 11 03:24:27 PM PDT 24
Finished Jun 11 03:24:52 PM PDT 24
Peak memory 232656 kb
Host smart-771605c9-672a-4c6a-a500-a38a4f4b6516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126721687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4126721687
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2311277407
Short name T138
Test name
Test status
Simulation time 116841667 ps
CPU time 2.73 seconds
Started Jun 11 03:24:33 PM PDT 24
Finished Jun 11 03:24:37 PM PDT 24
Peak memory 224220 kb
Host smart-6e721fca-8b0d-478c-ab70-64647670210b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311277407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2311277407
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2698818149
Short name T755
Test name
Test status
Simulation time 2286826073 ps
CPU time 16.7 seconds
Started Jun 11 03:24:37 PM PDT 24
Finished Jun 11 03:24:55 PM PDT 24
Peak memory 232608 kb
Host smart-65e65b83-a216-4e7e-b866-072c895036b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698818149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2698818149
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.406740771
Short name T232
Test name
Test status
Simulation time 860411661 ps
CPU time 7.11 seconds
Started Jun 11 03:24:30 PM PDT 24
Finished Jun 11 03:24:38 PM PDT 24
Peak memory 224304 kb
Host smart-6140f576-4235-451c-9ac1-1003117313f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406740771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.406740771
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3314459017
Short name T673
Test name
Test status
Simulation time 198688141 ps
CPU time 2.68 seconds
Started Jun 11 03:24:28 PM PDT 24
Finished Jun 11 03:24:32 PM PDT 24
Peak memory 232452 kb
Host smart-73b04843-7ad3-49d3-86fa-70252bf2fabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314459017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3314459017
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.4018731704
Short name T626
Test name
Test status
Simulation time 2025037745 ps
CPU time 5.05 seconds
Started Jun 11 03:24:31 PM PDT 24
Finished Jun 11 03:24:37 PM PDT 24
Peak memory 219696 kb
Host smart-18d77b1d-4850-49a4-8682-f169707842b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4018731704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.4018731704
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3099768899
Short name T642
Test name
Test status
Simulation time 47254881 ps
CPU time 0.92 seconds
Started Jun 11 03:24:30 PM PDT 24
Finished Jun 11 03:24:32 PM PDT 24
Peak memory 206716 kb
Host smart-56490b0a-58e1-4853-98ec-6ea6e68c075e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099768899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3099768899
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.4243430895
Short name T402
Test name
Test status
Simulation time 92634744 ps
CPU time 0.71 seconds
Started Jun 11 03:24:26 PM PDT 24
Finished Jun 11 03:24:29 PM PDT 24
Peak memory 205512 kb
Host smart-d0d42a4e-46d6-4539-8f88-0b87457cccc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243430895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4243430895
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3080083875
Short name T394
Test name
Test status
Simulation time 1686688172 ps
CPU time 3.46 seconds
Started Jun 11 03:24:29 PM PDT 24
Finished Jun 11 03:24:34 PM PDT 24
Peak memory 216016 kb
Host smart-ed1c4c78-de34-47f5-981c-7b7504f8eb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080083875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3080083875
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3469638092
Short name T666
Test name
Test status
Simulation time 39074498 ps
CPU time 0.78 seconds
Started Jun 11 03:24:27 PM PDT 24
Finished Jun 11 03:24:30 PM PDT 24
Peak memory 205708 kb
Host smart-5a9cc925-5f34-4688-928a-026f491e0e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469638092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3469638092
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3954301866
Short name T684
Test name
Test status
Simulation time 122663288 ps
CPU time 0.92 seconds
Started Jun 11 03:24:27 PM PDT 24
Finished Jun 11 03:24:30 PM PDT 24
Peak memory 206044 kb
Host smart-5d60b9f0-7a4b-4a67-a6b2-2fad6e9366e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954301866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3954301866
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.738738841
Short name T849
Test name
Test status
Simulation time 13087458291 ps
CPU time 19.79 seconds
Started Jun 11 03:24:30 PM PDT 24
Finished Jun 11 03:24:51 PM PDT 24
Peak memory 224400 kb
Host smart-8d0e7ff0-0b0e-4336-a791-6a413db39642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738738841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.738738841
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2521544945
Short name T439
Test name
Test status
Simulation time 26044792 ps
CPU time 0.73 seconds
Started Jun 11 03:24:36 PM PDT 24
Finished Jun 11 03:24:38 PM PDT 24
Peak memory 205660 kb
Host smart-2c836b5c-6f60-435e-a07a-4d7f50ff0ed8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521544945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2521544945
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1455144157
Short name T557
Test name
Test status
Simulation time 448966721 ps
CPU time 6.26 seconds
Started Jun 11 03:24:28 PM PDT 24
Finished Jun 11 03:24:36 PM PDT 24
Peak memory 232512 kb
Host smart-f6ca5c40-edba-4ecc-b346-514531747a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455144157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1455144157
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3783293041
Short name T761
Test name
Test status
Simulation time 22395966 ps
CPU time 0.79 seconds
Started Jun 11 03:24:33 PM PDT 24
Finished Jun 11 03:24:35 PM PDT 24
Peak memory 206328 kb
Host smart-34903899-4a8a-42c9-be5c-ddeb75d76a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783293041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3783293041
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3447996137
Short name T315
Test name
Test status
Simulation time 9692746634 ps
CPU time 45.84 seconds
Started Jun 11 03:24:37 PM PDT 24
Finished Jun 11 03:25:24 PM PDT 24
Peak memory 240848 kb
Host smart-ad3a674a-5545-48a2-a1e4-5bb80e9d9413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447996137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3447996137
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3430488142
Short name T301
Test name
Test status
Simulation time 6456905771 ps
CPU time 41.23 seconds
Started Jun 11 03:24:38 PM PDT 24
Finished Jun 11 03:25:21 PM PDT 24
Peak memory 249100 kb
Host smart-f31491d6-9377-46c5-a542-1fd9b368ebf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430488142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3430488142
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3056043420
Short name T677
Test name
Test status
Simulation time 7861454755 ps
CPU time 66.51 seconds
Started Jun 11 03:24:28 PM PDT 24
Finished Jun 11 03:25:36 PM PDT 24
Peak memory 238112 kb
Host smart-bcda65d9-a5ca-491f-ae6c-26efcdeb9e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056043420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3056043420
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.4002581447
Short name T328
Test name
Test status
Simulation time 1042644512 ps
CPU time 11.31 seconds
Started Jun 11 03:24:27 PM PDT 24
Finished Jun 11 03:24:40 PM PDT 24
Peak memory 240744 kb
Host smart-6c0f5d61-6a1c-4384-98b3-3342c91dd25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002581447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.4002581447
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3961574669
Short name T223
Test name
Test status
Simulation time 254669407 ps
CPU time 4.27 seconds
Started Jun 11 03:24:45 PM PDT 24
Finished Jun 11 03:24:51 PM PDT 24
Peak memory 232424 kb
Host smart-22cb9af8-ee9a-4400-a772-d39f1b77d339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961574669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3961574669
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1126543115
Short name T283
Test name
Test status
Simulation time 59856445185 ps
CPU time 127.64 seconds
Started Jun 11 03:24:31 PM PDT 24
Finished Jun 11 03:26:39 PM PDT 24
Peak memory 233684 kb
Host smart-dc9e5606-cc8e-48ae-9b56-ff6ccee00bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126543115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1126543115
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1874962359
Short name T281
Test name
Test status
Simulation time 12644425080 ps
CPU time 20.46 seconds
Started Jun 11 03:24:30 PM PDT 24
Finished Jun 11 03:24:52 PM PDT 24
Peak memory 248656 kb
Host smart-51444357-a973-4e53-adae-a02e7d1e7cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874962359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1874962359
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2187049504
Short name T947
Test name
Test status
Simulation time 3382123509 ps
CPU time 8.98 seconds
Started Jun 11 03:24:29 PM PDT 24
Finished Jun 11 03:24:39 PM PDT 24
Peak memory 240704 kb
Host smart-097d12fd-206d-4ff2-8661-926352960811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187049504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2187049504
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3461735257
Short name T627
Test name
Test status
Simulation time 4554875990 ps
CPU time 4.69 seconds
Started Jun 11 03:24:37 PM PDT 24
Finished Jun 11 03:24:44 PM PDT 24
Peak memory 220608 kb
Host smart-de261169-878c-497c-9b03-7aaaf240eb72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3461735257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3461735257
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3938413800
Short name T419
Test name
Test status
Simulation time 1721837659 ps
CPU time 17.57 seconds
Started Jun 11 03:24:36 PM PDT 24
Finished Jun 11 03:24:55 PM PDT 24
Peak memory 216088 kb
Host smart-9d4469ab-6ebc-4204-9678-40340daadd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938413800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3938413800
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1811221760
Short name T438
Test name
Test status
Simulation time 3518949421 ps
CPU time 13.66 seconds
Started Jun 11 03:24:31 PM PDT 24
Finished Jun 11 03:24:46 PM PDT 24
Peak memory 216236 kb
Host smart-15af6c31-7a5c-47fa-a4b2-3138cea00621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811221760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1811221760
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3806506501
Short name T617
Test name
Test status
Simulation time 229826451 ps
CPU time 2.42 seconds
Started Jun 11 03:24:27 PM PDT 24
Finished Jun 11 03:24:31 PM PDT 24
Peak memory 215980 kb
Host smart-cf339de9-48e9-43c4-afbb-08c6deb629dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806506501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3806506501
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2338606461
Short name T765
Test name
Test status
Simulation time 88617082 ps
CPU time 1.04 seconds
Started Jun 11 03:24:33 PM PDT 24
Finished Jun 11 03:24:35 PM PDT 24
Peak memory 206072 kb
Host smart-87c87b8d-824c-4a40-a71e-925520231918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338606461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2338606461
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.320227372
Short name T226
Test name
Test status
Simulation time 2813440280 ps
CPU time 6.63 seconds
Started Jun 11 03:24:31 PM PDT 24
Finished Jun 11 03:24:39 PM PDT 24
Peak memory 224400 kb
Host smart-3d999668-dc9a-4f1d-8595-ba0cdb760882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320227372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.320227372
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.512614841
Short name T803
Test name
Test status
Simulation time 10833054 ps
CPU time 0.72 seconds
Started Jun 11 03:24:38 PM PDT 24
Finished Jun 11 03:24:40 PM PDT 24
Peak memory 204656 kb
Host smart-383406ef-0970-482c-b646-1f4d70d4a14d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512614841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.512614841
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.359556011
Short name T393
Test name
Test status
Simulation time 1744371783 ps
CPU time 2.58 seconds
Started Jun 11 03:24:38 PM PDT 24
Finished Jun 11 03:24:42 PM PDT 24
Peak memory 224276 kb
Host smart-9604e60d-753e-4040-91e6-3e5f73567376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359556011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.359556011
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.259928689
Short name T886
Test name
Test status
Simulation time 16408605 ps
CPU time 0.8 seconds
Started Jun 11 03:24:37 PM PDT 24
Finished Jun 11 03:24:39 PM PDT 24
Peak memory 205376 kb
Host smart-32e87752-29a9-42db-a7de-22bac58ee35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259928689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.259928689
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1276278229
Short name T176
Test name
Test status
Simulation time 1259997533 ps
CPU time 16.45 seconds
Started Jun 11 03:24:37 PM PDT 24
Finished Jun 11 03:24:55 PM PDT 24
Peak memory 248988 kb
Host smart-e6047a16-bd50-4f88-9491-0192aeeb1a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276278229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1276278229
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.855997295
Short name T175
Test name
Test status
Simulation time 37030753697 ps
CPU time 158.29 seconds
Started Jun 11 03:24:37 PM PDT 24
Finished Jun 11 03:27:16 PM PDT 24
Peak memory 251032 kb
Host smart-e0ecf476-651c-4258-88d9-c88139aa0572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855997295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.855997295
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3728896694
Short name T220
Test name
Test status
Simulation time 83675754231 ps
CPU time 489.29 seconds
Started Jun 11 03:24:36 PM PDT 24
Finished Jun 11 03:32:47 PM PDT 24
Peak memory 263304 kb
Host smart-6b9ee1fc-8ba6-42e0-bed8-34f4e79f00b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728896694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3728896694
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1911560601
Short name T925
Test name
Test status
Simulation time 9028859079 ps
CPU time 34.16 seconds
Started Jun 11 03:24:36 PM PDT 24
Finished Jun 11 03:25:11 PM PDT 24
Peak memory 240884 kb
Host smart-6ea0dedb-df53-46cf-bb4d-155b997c6840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911560601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1911560601
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1083286662
Short name T732
Test name
Test status
Simulation time 171806910 ps
CPU time 4.39 seconds
Started Jun 11 03:24:38 PM PDT 24
Finished Jun 11 03:24:44 PM PDT 24
Peak memory 224276 kb
Host smart-547d1f78-6009-40c1-bde5-9644db644101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083286662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1083286662
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.4282000946
Short name T467
Test name
Test status
Simulation time 145407406 ps
CPU time 3.35 seconds
Started Jun 11 03:24:38 PM PDT 24
Finished Jun 11 03:24:43 PM PDT 24
Peak memory 232544 kb
Host smart-1c1f0384-37ca-4bcd-bc6a-b21654210a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282000946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4282000946
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2994444626
Short name T674
Test name
Test status
Simulation time 17729512609 ps
CPU time 15.12 seconds
Started Jun 11 03:24:37 PM PDT 24
Finished Jun 11 03:24:54 PM PDT 24
Peak memory 240728 kb
Host smart-758545db-be92-4ac9-9150-f8d2c9df3675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994444626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2994444626
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1825592481
Short name T206
Test name
Test status
Simulation time 538578671 ps
CPU time 5.46 seconds
Started Jun 11 03:24:39 PM PDT 24
Finished Jun 11 03:24:46 PM PDT 24
Peak memory 232484 kb
Host smart-9dba971e-0ef2-4b33-9671-ada3a3bc9048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825592481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1825592481
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2209471396
Short name T377
Test name
Test status
Simulation time 1115009721 ps
CPU time 9.78 seconds
Started Jun 11 03:24:40 PM PDT 24
Finished Jun 11 03:24:51 PM PDT 24
Peak memory 222020 kb
Host smart-a3577014-0930-4823-b8c7-634563ef1853
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2209471396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2209471396
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.506054147
Short name T160
Test name
Test status
Simulation time 10820566070 ps
CPU time 48.67 seconds
Started Jun 11 03:24:38 PM PDT 24
Finished Jun 11 03:25:29 PM PDT 24
Peak memory 251864 kb
Host smart-64c29f3d-a455-4ef9-9d67-b83598bc2fbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506054147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.506054147
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2731435580
Short name T653
Test name
Test status
Simulation time 7081516319 ps
CPU time 42.14 seconds
Started Jun 11 03:24:40 PM PDT 24
Finished Jun 11 03:25:24 PM PDT 24
Peak memory 216168 kb
Host smart-f1e99d44-45e3-4b3a-89dd-e56c447c6314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731435580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2731435580
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.96719568
Short name T608
Test name
Test status
Simulation time 2657769885 ps
CPU time 2.57 seconds
Started Jun 11 03:24:40 PM PDT 24
Finished Jun 11 03:24:44 PM PDT 24
Peak memory 207832 kb
Host smart-55a28372-3d9d-4666-a4d2-0a252666cdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96719568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.96719568
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.341226406
Short name T340
Test name
Test status
Simulation time 85271012 ps
CPU time 0.87 seconds
Started Jun 11 03:24:36 PM PDT 24
Finished Jun 11 03:24:39 PM PDT 24
Peak memory 205668 kb
Host smart-e5237f39-fa16-476a-b64f-87771551d4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341226406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.341226406
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.672730034
Short name T695
Test name
Test status
Simulation time 83757038 ps
CPU time 0.79 seconds
Started Jun 11 03:24:39 PM PDT 24
Finished Jun 11 03:24:41 PM PDT 24
Peak memory 205668 kb
Host smart-1b80004f-a4e1-4d9b-a4c7-5129bdd18fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672730034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.672730034
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2442200340
Short name T550
Test name
Test status
Simulation time 665916470 ps
CPU time 3.15 seconds
Started Jun 11 03:24:38 PM PDT 24
Finished Jun 11 03:24:43 PM PDT 24
Peak memory 224316 kb
Host smart-c7af3dc0-dcd2-4aac-8947-2aea8003e832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442200340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2442200340
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.897309442
Short name T350
Test name
Test status
Simulation time 30925574 ps
CPU time 0.65 seconds
Started Jun 11 03:24:46 PM PDT 24
Finished Jun 11 03:24:49 PM PDT 24
Peak memory 205204 kb
Host smart-1c950955-2b20-42d3-8dfa-dad3576a4cbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897309442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.897309442
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1359203843
Short name T471
Test name
Test status
Simulation time 903971940 ps
CPU time 10.47 seconds
Started Jun 11 03:24:35 PM PDT 24
Finished Jun 11 03:24:46 PM PDT 24
Peak memory 224332 kb
Host smart-9b2e2481-3df3-4062-96a1-75943418a86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359203843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1359203843
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3576859741
Short name T919
Test name
Test status
Simulation time 14864440 ps
CPU time 0.8 seconds
Started Jun 11 03:24:37 PM PDT 24
Finished Jun 11 03:24:39 PM PDT 24
Peak memory 205336 kb
Host smart-50e55253-5998-48fc-bf0a-004c2524038a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576859741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3576859741
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3360695801
Short name T799
Test name
Test status
Simulation time 35822216 ps
CPU time 0.78 seconds
Started Jun 11 03:24:47 PM PDT 24
Finished Jun 11 03:24:50 PM PDT 24
Peak memory 215832 kb
Host smart-85a470b2-d5a9-4b0c-92f8-d3d651814741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360695801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3360695801
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3869805175
Short name T38
Test name
Test status
Simulation time 18257585097 ps
CPU time 194.32 seconds
Started Jun 11 03:24:47 PM PDT 24
Finished Jun 11 03:28:03 PM PDT 24
Peak memory 249136 kb
Host smart-b52a7c2d-e8ed-4287-8aa3-8b135aafaeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869805175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3869805175
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3531733214
Short name T957
Test name
Test status
Simulation time 1065697694 ps
CPU time 3.75 seconds
Started Jun 11 03:24:46 PM PDT 24
Finished Jun 11 03:24:52 PM PDT 24
Peak memory 219276 kb
Host smart-73b72799-f6bd-4fc6-907f-b35e921eb370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531733214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3531733214
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.503026969
Short name T13
Test name
Test status
Simulation time 132357119 ps
CPU time 3.43 seconds
Started Jun 11 03:24:38 PM PDT 24
Finished Jun 11 03:24:43 PM PDT 24
Peak memory 224324 kb
Host smart-8f93689b-6853-4e66-aa86-ec89c1097ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503026969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.503026969
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.272172922
Short name T164
Test name
Test status
Simulation time 251271275 ps
CPU time 5.03 seconds
Started Jun 11 03:24:37 PM PDT 24
Finished Jun 11 03:24:44 PM PDT 24
Peak memory 232532 kb
Host smart-7c26e9ea-350a-4c67-86f3-20e0075bfd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272172922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.272172922
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1175934529
Short name T588
Test name
Test status
Simulation time 5060176673 ps
CPU time 46.58 seconds
Started Jun 11 03:24:36 PM PDT 24
Finished Jun 11 03:25:25 PM PDT 24
Peak memory 248680 kb
Host smart-330233ab-429f-4128-9b1f-529ba9f2c23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175934529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1175934529
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.366685806
Short name T255
Test name
Test status
Simulation time 388306468 ps
CPU time 3.64 seconds
Started Jun 11 03:24:38 PM PDT 24
Finished Jun 11 03:24:43 PM PDT 24
Peak memory 224336 kb
Host smart-c03a0cb3-ef3f-4de7-8ace-f71ddbf96123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366685806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.366685806
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.4009071325
Short name T568
Test name
Test status
Simulation time 55160439701 ps
CPU time 31.23 seconds
Started Jun 11 03:24:40 PM PDT 24
Finished Jun 11 03:25:12 PM PDT 24
Peak memory 238060 kb
Host smart-a96fdc96-773b-4156-bac6-5d0476636dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009071325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.4009071325
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.824064864
Short name T382
Test name
Test status
Simulation time 959921177 ps
CPU time 4.38 seconds
Started Jun 11 03:24:38 PM PDT 24
Finished Jun 11 03:24:44 PM PDT 24
Peak memory 219912 kb
Host smart-8350fb68-1a58-41bd-94ee-07b477d31e20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=824064864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.824064864
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1102688668
Short name T331
Test name
Test status
Simulation time 9764384906 ps
CPU time 17.93 seconds
Started Jun 11 03:24:40 PM PDT 24
Finished Jun 11 03:25:00 PM PDT 24
Peak memory 216212 kb
Host smart-ef655196-9951-47e2-8d42-9cafbd874036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102688668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1102688668
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2925117945
Short name T722
Test name
Test status
Simulation time 888528118 ps
CPU time 3.94 seconds
Started Jun 11 03:24:40 PM PDT 24
Finished Jun 11 03:24:45 PM PDT 24
Peak memory 216084 kb
Host smart-10cb9a07-4be6-4814-b378-ce336f79638b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925117945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2925117945
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.737968102
Short name T970
Test name
Test status
Simulation time 49775367 ps
CPU time 0.88 seconds
Started Jun 11 03:24:38 PM PDT 24
Finished Jun 11 03:24:41 PM PDT 24
Peak memory 206756 kb
Host smart-e08b822e-0ce1-4a30-affc-27d9fd4b94b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737968102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.737968102
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.926900928
Short name T86
Test name
Test status
Simulation time 26452957 ps
CPU time 0.89 seconds
Started Jun 11 03:24:39 PM PDT 24
Finished Jun 11 03:24:41 PM PDT 24
Peak memory 205704 kb
Host smart-a22f0494-f1d6-4e5d-86e9-dd6783a599d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926900928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.926900928
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3475123009
Short name T453
Test name
Test status
Simulation time 94883224 ps
CPU time 2.47 seconds
Started Jun 11 03:24:40 PM PDT 24
Finished Jun 11 03:24:44 PM PDT 24
Peak memory 224132 kb
Host smart-44326059-d1e0-4391-ab29-e89aa2ebaea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475123009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3475123009
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3092298123
Short name T369
Test name
Test status
Simulation time 12835246 ps
CPU time 0.72 seconds
Started Jun 11 03:21:43 PM PDT 24
Finished Jun 11 03:21:44 PM PDT 24
Peak memory 205652 kb
Host smart-dba37fa1-1404-42ca-8fc9-b99a94f3ce40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092298123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
092298123
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3876518920
Short name T754
Test name
Test status
Simulation time 140509088 ps
CPU time 3.32 seconds
Started Jun 11 03:21:43 PM PDT 24
Finished Jun 11 03:21:48 PM PDT 24
Peak memory 232516 kb
Host smart-4aac98b6-1c8b-4211-b75b-f4509465b2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876518920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3876518920
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.4236436077
Short name T839
Test name
Test status
Simulation time 54230344 ps
CPU time 0.8 seconds
Started Jun 11 03:21:41 PM PDT 24
Finished Jun 11 03:21:43 PM PDT 24
Peak memory 206372 kb
Host smart-20fe78af-2d65-4cad-a41e-7ae91fd4c782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236436077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.4236436077
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2464562385
Short name T45
Test name
Test status
Simulation time 94333299773 ps
CPU time 166.13 seconds
Started Jun 11 03:21:44 PM PDT 24
Finished Jun 11 03:24:32 PM PDT 24
Peak memory 256912 kb
Host smart-22f24a96-fed2-498b-bfc1-dd1345f19929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464562385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2464562385
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.664209942
Short name T303
Test name
Test status
Simulation time 10581995026 ps
CPU time 95.82 seconds
Started Jun 11 03:21:44 PM PDT 24
Finished Jun 11 03:23:21 PM PDT 24
Peak memory 253816 kb
Host smart-aca1844f-7356-4fe1-b0d3-a2892331b1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664209942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.664209942
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2590620085
Short name T510
Test name
Test status
Simulation time 59195240856 ps
CPU time 167.47 seconds
Started Jun 11 03:21:42 PM PDT 24
Finished Jun 11 03:24:31 PM PDT 24
Peak memory 257316 kb
Host smart-b6b889ad-b0e7-420b-9eb5-fc77c09132bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590620085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2590620085
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1113015489
Short name T953
Test name
Test status
Simulation time 1832790004 ps
CPU time 31.06 seconds
Started Jun 11 03:21:41 PM PDT 24
Finished Jun 11 03:22:13 PM PDT 24
Peak memory 224356 kb
Host smart-24f3123d-a8e2-4949-a1d9-3f5bcb13d1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113015489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1113015489
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3529988012
Short name T729
Test name
Test status
Simulation time 972777733 ps
CPU time 8.87 seconds
Started Jun 11 03:21:41 PM PDT 24
Finished Jun 11 03:21:51 PM PDT 24
Peak memory 227556 kb
Host smart-25c22790-09f7-4ea7-afc6-435833a473ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529988012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3529988012
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.716459598
Short name T407
Test name
Test status
Simulation time 30849213399 ps
CPU time 151.7 seconds
Started Jun 11 03:21:42 PM PDT 24
Finished Jun 11 03:24:15 PM PDT 24
Peak memory 240036 kb
Host smart-f0d5d04e-1947-497c-8201-8c3ccab9dfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716459598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.716459598
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2081177941
Short name T36
Test name
Test status
Simulation time 45635315 ps
CPU time 1.11 seconds
Started Jun 11 03:21:41 PM PDT 24
Finished Jun 11 03:21:43 PM PDT 24
Peak memory 216512 kb
Host smart-2a13813f-44a4-4389-ae9e-f2141ddd16ff
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081177941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2081177941
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2138118025
Short name T295
Test name
Test status
Simulation time 9032721066 ps
CPU time 21.96 seconds
Started Jun 11 03:21:42 PM PDT 24
Finished Jun 11 03:22:05 PM PDT 24
Peak memory 232868 kb
Host smart-c859a738-a4de-4c26-80df-1f70d940fa4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138118025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2138118025
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2137085897
Short name T136
Test name
Test status
Simulation time 368714652 ps
CPU time 4.75 seconds
Started Jun 11 03:21:44 PM PDT 24
Finished Jun 11 03:21:50 PM PDT 24
Peak memory 224316 kb
Host smart-cee3f308-8863-43bf-b591-0e204c373ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137085897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2137085897
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3548157134
Short name T789
Test name
Test status
Simulation time 748316106 ps
CPU time 4.58 seconds
Started Jun 11 03:21:43 PM PDT 24
Finished Jun 11 03:21:49 PM PDT 24
Peak memory 222820 kb
Host smart-561a3e8f-7e0f-4d26-8a92-525c28ac1507
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3548157134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3548157134
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3953231506
Short name T592
Test name
Test status
Simulation time 126753400 ps
CPU time 0.96 seconds
Started Jun 11 03:21:40 PM PDT 24
Finished Jun 11 03:21:42 PM PDT 24
Peak memory 206844 kb
Host smart-23b6f8f8-0f4a-4095-b8c6-2662d9ebfe05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953231506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3953231506
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.4115690215
Short name T738
Test name
Test status
Simulation time 608934317 ps
CPU time 3.83 seconds
Started Jun 11 03:21:41 PM PDT 24
Finished Jun 11 03:21:46 PM PDT 24
Peak memory 216012 kb
Host smart-7b5296ad-cf86-4399-9a09-8cc9b44675a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115690215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.4115690215
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3005118165
Short name T25
Test name
Test status
Simulation time 1227389477 ps
CPU time 4.32 seconds
Started Jun 11 03:21:44 PM PDT 24
Finished Jun 11 03:21:49 PM PDT 24
Peak memory 215672 kb
Host smart-bd950f50-ae4a-43e3-9ca2-885d69fd5f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005118165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3005118165
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3503554035
Short name T444
Test name
Test status
Simulation time 13909101 ps
CPU time 0.71 seconds
Started Jun 11 03:21:41 PM PDT 24
Finished Jun 11 03:21:43 PM PDT 24
Peak memory 205428 kb
Host smart-7ef06a10-1c2e-4381-8839-14c9d7064330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503554035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3503554035
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1612751282
Short name T535
Test name
Test status
Simulation time 136661517 ps
CPU time 0.87 seconds
Started Jun 11 03:21:46 PM PDT 24
Finished Jun 11 03:21:48 PM PDT 24
Peak memory 205680 kb
Host smart-a4a6bdc3-d39f-48ba-9d7a-fcf12d97b9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612751282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1612751282
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.4189096519
Short name T291
Test name
Test status
Simulation time 3950233861 ps
CPU time 14.61 seconds
Started Jun 11 03:21:40 PM PDT 24
Finished Jun 11 03:21:55 PM PDT 24
Peak memory 232632 kb
Host smart-66682218-bb15-4772-b18e-15d9ce1fce2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189096519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.4189096519
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2547403462
Short name T70
Test name
Test status
Simulation time 58769439 ps
CPU time 0.73 seconds
Started Jun 11 03:21:44 PM PDT 24
Finished Jun 11 03:21:46 PM PDT 24
Peak memory 205304 kb
Host smart-9e0b75b1-3a44-453e-8f13-b9a78b6dfdae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547403462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
547403462
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1146707736
Short name T688
Test name
Test status
Simulation time 301122648 ps
CPU time 7.54 seconds
Started Jun 11 03:21:44 PM PDT 24
Finished Jun 11 03:21:53 PM PDT 24
Peak memory 232492 kb
Host smart-772b2886-d7d3-439a-86ea-e04ace5ac68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146707736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1146707736
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1299351966
Short name T973
Test name
Test status
Simulation time 20283125 ps
CPU time 0.83 seconds
Started Jun 11 03:21:42 PM PDT 24
Finished Jun 11 03:21:44 PM PDT 24
Peak memory 206392 kb
Host smart-8f1a8351-20a4-459b-b5dd-3f7cdfeee49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299351966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1299351966
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.463905783
Short name T818
Test name
Test status
Simulation time 5547516041 ps
CPU time 38.71 seconds
Started Jun 11 03:21:44 PM PDT 24
Finished Jun 11 03:22:24 PM PDT 24
Peak memory 239184 kb
Host smart-08079d26-b940-41f6-bb47-5472b54bd985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463905783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.463905783
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.850940498
Short name T452
Test name
Test status
Simulation time 7733043439 ps
CPU time 25.69 seconds
Started Jun 11 03:21:41 PM PDT 24
Finished Jun 11 03:22:08 PM PDT 24
Peak memory 240820 kb
Host smart-ad27c095-edce-435d-aa32-689c1231e457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850940498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.850940498
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3018646077
Short name T12
Test name
Test status
Simulation time 8025374172 ps
CPU time 58.67 seconds
Started Jun 11 03:21:43 PM PDT 24
Finished Jun 11 03:22:43 PM PDT 24
Peak memory 256080 kb
Host smart-e43aabdf-bf9d-4189-aba7-21d4dd80794c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018646077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3018646077
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3747119025
Short name T880
Test name
Test status
Simulation time 2274324986 ps
CPU time 30.65 seconds
Started Jun 11 03:21:45 PM PDT 24
Finished Jun 11 03:22:16 PM PDT 24
Peak memory 238376 kb
Host smart-4e8e0022-33b7-459d-b255-13e8cffb1a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747119025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3747119025
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3472173551
Short name T265
Test name
Test status
Simulation time 1628159864 ps
CPU time 7.31 seconds
Started Jun 11 03:21:39 PM PDT 24
Finished Jun 11 03:21:48 PM PDT 24
Peak memory 224304 kb
Host smart-397a8c52-785b-461f-ba49-47083f0ed3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472173551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3472173551
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.323183247
Short name T235
Test name
Test status
Simulation time 2127443593 ps
CPU time 10.66 seconds
Started Jun 11 03:21:45 PM PDT 24
Finished Jun 11 03:21:57 PM PDT 24
Peak memory 232484 kb
Host smart-2c265d27-786b-45d2-96ce-07d2ed98515f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323183247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.323183247
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.768698868
Short name T35
Test name
Test status
Simulation time 30710540 ps
CPU time 1.09 seconds
Started Jun 11 03:21:40 PM PDT 24
Finished Jun 11 03:21:43 PM PDT 24
Peak memory 216488 kb
Host smart-476c1fd6-696f-4b9a-83f3-c034e5d7820d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768698868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.768698868
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2029292965
Short name T260
Test name
Test status
Simulation time 120905709 ps
CPU time 2.31 seconds
Started Jun 11 03:21:39 PM PDT 24
Finished Jun 11 03:21:43 PM PDT 24
Peak memory 224272 kb
Host smart-b59415e8-00b3-40be-8bfa-3346f5094aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029292965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2029292965
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3586402567
Short name T701
Test name
Test status
Simulation time 115204675 ps
CPU time 2.66 seconds
Started Jun 11 03:21:45 PM PDT 24
Finished Jun 11 03:21:49 PM PDT 24
Peak memory 232324 kb
Host smart-10a85286-6410-4e7b-abe8-1e4ca2c32070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586402567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3586402567
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.4139453016
Short name T432
Test name
Test status
Simulation time 777008075 ps
CPU time 5.13 seconds
Started Jun 11 03:21:46 PM PDT 24
Finished Jun 11 03:21:52 PM PDT 24
Peak memory 222760 kb
Host smart-447f1e53-a875-4062-80ef-38a30ce5912d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4139453016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.4139453016
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1834873116
Short name T736
Test name
Test status
Simulation time 34978213 ps
CPU time 0.89 seconds
Started Jun 11 03:21:43 PM PDT 24
Finished Jun 11 03:21:45 PM PDT 24
Peak memory 205364 kb
Host smart-cfd770e8-7f27-4bbb-b638-266db16a7f36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834873116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1834873116
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1873655062
Short name T943
Test name
Test status
Simulation time 2737068482 ps
CPU time 22.54 seconds
Started Jun 11 03:21:44 PM PDT 24
Finished Jun 11 03:22:08 PM PDT 24
Peak memory 216484 kb
Host smart-39fab484-1d88-44a0-80e4-c4fcb5ca273b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873655062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1873655062
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4174717328
Short name T30
Test name
Test status
Simulation time 6828189475 ps
CPU time 19.67 seconds
Started Jun 11 03:21:40 PM PDT 24
Finished Jun 11 03:22:01 PM PDT 24
Peak memory 216244 kb
Host smart-7bd05848-c689-440c-868e-7a01de237522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174717328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4174717328
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.945675763
Short name T486
Test name
Test status
Simulation time 45911098 ps
CPU time 0.99 seconds
Started Jun 11 03:21:43 PM PDT 24
Finished Jun 11 03:21:45 PM PDT 24
Peak memory 206860 kb
Host smart-98ace2f7-06b6-4307-b81e-b06698e50e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945675763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.945675763
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1138149003
Short name T710
Test name
Test status
Simulation time 25914534 ps
CPU time 0.81 seconds
Started Jun 11 03:21:41 PM PDT 24
Finished Jun 11 03:21:43 PM PDT 24
Peak memory 205672 kb
Host smart-ba82af47-6c01-499f-8e79-2b3b797fdef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138149003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1138149003
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3755441182
Short name T262
Test name
Test status
Simulation time 849386685 ps
CPU time 5.03 seconds
Started Jun 11 03:21:43 PM PDT 24
Finished Jun 11 03:21:49 PM PDT 24
Peak memory 224352 kb
Host smart-146ccfce-740d-4d9e-8500-61c061913e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755441182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3755441182
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.798207984
Short name T581
Test name
Test status
Simulation time 39504246 ps
CPU time 0.73 seconds
Started Jun 11 03:21:53 PM PDT 24
Finished Jun 11 03:21:55 PM PDT 24
Peak memory 205664 kb
Host smart-54254175-c594-4f8d-b2cd-c2445ba8d6d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798207984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.798207984
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1411497578
Short name T813
Test name
Test status
Simulation time 433893182 ps
CPU time 3.31 seconds
Started Jun 11 03:21:52 PM PDT 24
Finished Jun 11 03:21:57 PM PDT 24
Peak memory 232492 kb
Host smart-1db36452-2667-482d-bcdb-c9713d61ffaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411497578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1411497578
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3411030887
Short name T412
Test name
Test status
Simulation time 41493062 ps
CPU time 0.84 seconds
Started Jun 11 03:21:46 PM PDT 24
Finished Jun 11 03:21:48 PM PDT 24
Peak memory 206376 kb
Host smart-65bdc8a0-e386-4811-b85a-ed4391c3365a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411030887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3411030887
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.664855512
Short name T567
Test name
Test status
Simulation time 8692625580 ps
CPU time 67.69 seconds
Started Jun 11 03:21:49 PM PDT 24
Finished Jun 11 03:22:58 PM PDT 24
Peak memory 240828 kb
Host smart-c3b7f67b-8992-450f-a627-58ff88a9ec15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664855512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.664855512
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.754614892
Short name T244
Test name
Test status
Simulation time 127865309111 ps
CPU time 300.16 seconds
Started Jun 11 03:21:50 PM PDT 24
Finished Jun 11 03:26:52 PM PDT 24
Peak memory 249104 kb
Host smart-ff21f8f9-5096-4a0f-bc5d-2a2f8db6b04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754614892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.754614892
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1939256876
Short name T330
Test name
Test status
Simulation time 12598696549 ps
CPU time 19.97 seconds
Started Jun 11 03:21:50 PM PDT 24
Finished Jun 11 03:22:11 PM PDT 24
Peak memory 217280 kb
Host smart-0cb6763e-4eb0-494f-bf2c-6b9b8e5fdf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939256876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1939256876
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1831052708
Short name T519
Test name
Test status
Simulation time 1229756090 ps
CPU time 16.38 seconds
Started Jun 11 03:21:52 PM PDT 24
Finished Jun 11 03:22:10 PM PDT 24
Peak memory 240692 kb
Host smart-ab66285a-15a0-4d74-a42f-eedd591ec7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831052708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1831052708
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.41758347
Short name T241
Test name
Test status
Simulation time 527192371 ps
CPU time 5.89 seconds
Started Jun 11 03:21:52 PM PDT 24
Finished Jun 11 03:21:59 PM PDT 24
Peak memory 232500 kb
Host smart-4d0c35a9-4456-48ad-9097-6cf6aba436ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41758347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.41758347
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2574652165
Short name T861
Test name
Test status
Simulation time 333130753 ps
CPU time 2.23 seconds
Started Jun 11 03:21:48 PM PDT 24
Finished Jun 11 03:21:52 PM PDT 24
Peak memory 224328 kb
Host smart-c4204601-7cfd-44a3-aa6a-51469a43acf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574652165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2574652165
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3692232105
Short name T37
Test name
Test status
Simulation time 27822295 ps
CPU time 1.14 seconds
Started Jun 11 03:21:46 PM PDT 24
Finished Jun 11 03:21:48 PM PDT 24
Peak memory 216492 kb
Host smart-4ff2f4f5-6d5c-4455-8e8a-c62df68c8029
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692232105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3692232105
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.986849691
Short name T910
Test name
Test status
Simulation time 161773723 ps
CPU time 2.73 seconds
Started Jun 11 03:21:51 PM PDT 24
Finished Jun 11 03:21:56 PM PDT 24
Peak memory 224308 kb
Host smart-77a56773-bc16-4238-98b6-13c91c214bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986849691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
986849691
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.103186969
Short name T615
Test name
Test status
Simulation time 1619518976 ps
CPU time 12.09 seconds
Started Jun 11 03:21:50 PM PDT 24
Finished Jun 11 03:22:04 PM PDT 24
Peak memory 221648 kb
Host smart-ba31f43d-0d9f-49a0-b260-e292ef98b1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103186969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.103186969
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.994381573
Short name T745
Test name
Test status
Simulation time 10519062062 ps
CPU time 8.39 seconds
Started Jun 11 03:21:51 PM PDT 24
Finished Jun 11 03:22:01 PM PDT 24
Peak memory 222900 kb
Host smart-55cd2df1-a6fe-49bb-93a9-4d27019f1445
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=994381573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.994381573
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2817020588
Short name T298
Test name
Test status
Simulation time 525607780030 ps
CPU time 976.43 seconds
Started Jun 11 03:21:50 PM PDT 24
Finished Jun 11 03:38:08 PM PDT 24
Peak memory 280932 kb
Host smart-401ded97-7c1d-4547-8934-86899802d014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817020588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2817020588
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.851231684
Short name T372
Test name
Test status
Simulation time 489463289 ps
CPU time 8.01 seconds
Started Jun 11 03:21:48 PM PDT 24
Finished Jun 11 03:21:56 PM PDT 24
Peak memory 218844 kb
Host smart-fc299824-7f7e-45dd-94be-5ad8a3bd1129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851231684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.851231684
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.4082116119
Short name T520
Test name
Test status
Simulation time 778806161 ps
CPU time 2.63 seconds
Started Jun 11 03:21:43 PM PDT 24
Finished Jun 11 03:21:46 PM PDT 24
Peak memory 216088 kb
Host smart-8f666441-ad17-48b7-ab04-1efc77b6decd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082116119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.4082116119
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3414965965
Short name T498
Test name
Test status
Simulation time 109427956 ps
CPU time 3.65 seconds
Started Jun 11 03:21:50 PM PDT 24
Finished Jun 11 03:21:54 PM PDT 24
Peak memory 216028 kb
Host smart-24025669-0859-40eb-baea-a164bb4e96de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414965965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3414965965
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3270211830
Short name T935
Test name
Test status
Simulation time 82385466 ps
CPU time 0.77 seconds
Started Jun 11 03:21:50 PM PDT 24
Finished Jun 11 03:21:53 PM PDT 24
Peak memory 205660 kb
Host smart-c72075aa-3b9c-4699-95bc-3051f686a4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270211830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3270211830
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.792046153
Short name T365
Test name
Test status
Simulation time 285288149 ps
CPU time 2.23 seconds
Started Jun 11 03:21:50 PM PDT 24
Finished Jun 11 03:21:54 PM PDT 24
Peak memory 223096 kb
Host smart-5e520423-4cc1-43c5-9c85-585c0fd8dacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792046153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.792046153
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1746039930
Short name T595
Test name
Test status
Simulation time 33730341 ps
CPU time 0.7 seconds
Started Jun 11 03:21:55 PM PDT 24
Finished Jun 11 03:21:58 PM PDT 24
Peak memory 204756 kb
Host smart-63e025fa-4376-411e-b8a5-7e3226ccc8f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746039930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
746039930
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3098633237
Short name T493
Test name
Test status
Simulation time 37732899 ps
CPU time 2.69 seconds
Started Jun 11 03:21:52 PM PDT 24
Finished Jun 11 03:21:57 PM PDT 24
Peak memory 232492 kb
Host smart-ea1228c0-e48a-41d4-85a2-ddd13ab968a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098633237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3098633237
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3600809687
Short name T395
Test name
Test status
Simulation time 30145033 ps
CPU time 0.82 seconds
Started Jun 11 03:21:51 PM PDT 24
Finished Jun 11 03:21:53 PM PDT 24
Peak memory 206384 kb
Host smart-bea686b7-4826-406a-878a-a6555f22c0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600809687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3600809687
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2953201762
Short name T792
Test name
Test status
Simulation time 19510757453 ps
CPU time 102.06 seconds
Started Jun 11 03:21:51 PM PDT 24
Finished Jun 11 03:23:35 PM PDT 24
Peak memory 257140 kb
Host smart-81b98b5e-2e65-428c-8735-e5db1abd95d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953201762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2953201762
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.478812256
Short name T747
Test name
Test status
Simulation time 23478899761 ps
CPU time 57.35 seconds
Started Jun 11 03:21:55 PM PDT 24
Finished Jun 11 03:22:54 PM PDT 24
Peak memory 237716 kb
Host smart-db32c369-ec5d-43fe-b9ce-b519962c315f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478812256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.478812256
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3867959756
Short name T337
Test name
Test status
Simulation time 3832874832 ps
CPU time 28.87 seconds
Started Jun 11 03:21:50 PM PDT 24
Finished Jun 11 03:22:20 PM PDT 24
Peak memory 235796 kb
Host smart-9e0b4f94-463d-4dcb-9d3a-db33202acab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867959756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3867959756
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2136711128
Short name T731
Test name
Test status
Simulation time 3192775485 ps
CPU time 24.96 seconds
Started Jun 11 03:21:50 PM PDT 24
Finished Jun 11 03:22:16 PM PDT 24
Peak memory 249032 kb
Host smart-cccb6a56-6932-4f1a-8266-1f1e13167bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136711128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2136711128
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2871386409
Short name T936
Test name
Test status
Simulation time 2025553728 ps
CPU time 11.5 seconds
Started Jun 11 03:21:51 PM PDT 24
Finished Jun 11 03:22:05 PM PDT 24
Peak memory 218396 kb
Host smart-55ac9e40-6fe3-4535-9e95-dcd2d5c78474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871386409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2871386409
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.526033880
Short name T1
Test name
Test status
Simulation time 5613571541 ps
CPU time 12.34 seconds
Started Jun 11 03:21:51 PM PDT 24
Finished Jun 11 03:22:05 PM PDT 24
Peak memory 224388 kb
Host smart-22900923-cf61-4791-b1bb-ddd082570bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526033880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.526033880
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.2853542756
Short name T873
Test name
Test status
Simulation time 45536400 ps
CPU time 1.03 seconds
Started Jun 11 03:21:51 PM PDT 24
Finished Jun 11 03:21:53 PM PDT 24
Peak memory 217648 kb
Host smart-6ab9f269-4f19-4fc4-a1ff-64b9d253443b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853542756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.2853542756
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2373854117
Short name T473
Test name
Test status
Simulation time 1612930682 ps
CPU time 4 seconds
Started Jun 11 03:21:51 PM PDT 24
Finished Jun 11 03:21:57 PM PDT 24
Peak memory 228444 kb
Host smart-63475c92-f370-4e98-a198-3a22a7322dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373854117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2373854117
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2220473093
Short name T173
Test name
Test status
Simulation time 1426496327 ps
CPU time 4.14 seconds
Started Jun 11 03:21:51 PM PDT 24
Finished Jun 11 03:21:56 PM PDT 24
Peak memory 232536 kb
Host smart-e36dc957-dcc2-4cc6-b8b6-48d41b266833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220473093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2220473093
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.129432006
Short name T410
Test name
Test status
Simulation time 4172430800 ps
CPU time 8.57 seconds
Started Jun 11 03:21:51 PM PDT 24
Finished Jun 11 03:22:01 PM PDT 24
Peak memory 219056 kb
Host smart-68aaf8a2-e549-4935-880b-5a8f9d8d167d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=129432006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.129432006
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1238228091
Short name T31
Test name
Test status
Simulation time 7038097559 ps
CPU time 72.22 seconds
Started Jun 11 03:21:49 PM PDT 24
Finished Jun 11 03:23:03 PM PDT 24
Peak memory 256512 kb
Host smart-a390d9f6-03ad-4230-8d28-c05c4829cfcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238228091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1238228091
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.318646612
Short name T539
Test name
Test status
Simulation time 13055126002 ps
CPU time 21.11 seconds
Started Jun 11 03:21:49 PM PDT 24
Finished Jun 11 03:22:11 PM PDT 24
Peak memory 219764 kb
Host smart-7c249d41-8a44-48aa-9ecd-92b6fa4dac63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318646612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.318646612
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2812847485
Short name T63
Test name
Test status
Simulation time 8908076928 ps
CPU time 10.9 seconds
Started Jun 11 03:21:50 PM PDT 24
Finished Jun 11 03:22:03 PM PDT 24
Peak memory 216164 kb
Host smart-cb020c1c-6fe2-4289-bba0-c44779a1dc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812847485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2812847485
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.196068774
Short name T501
Test name
Test status
Simulation time 196246866 ps
CPU time 1.18 seconds
Started Jun 11 03:21:49 PM PDT 24
Finished Jun 11 03:21:52 PM PDT 24
Peak memory 207792 kb
Host smart-7b2b7f6b-28fe-4f5a-ac54-f45f9bc2bf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196068774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.196068774
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3584931379
Short name T643
Test name
Test status
Simulation time 204147270 ps
CPU time 0.8 seconds
Started Jun 11 03:21:50 PM PDT 24
Finished Jun 11 03:21:52 PM PDT 24
Peak memory 205692 kb
Host smart-4a6000de-08ec-4111-bd6d-e3163e704c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584931379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3584931379
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1511048578
Short name T807
Test name
Test status
Simulation time 1672510214 ps
CPU time 7.27 seconds
Started Jun 11 03:21:48 PM PDT 24
Finished Jun 11 03:21:56 PM PDT 24
Peak memory 224320 kb
Host smart-30927040-ad4b-472f-a6be-fbf1456504c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511048578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1511048578
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2515045443
Short name T560
Test name
Test status
Simulation time 40270870 ps
CPU time 0.73 seconds
Started Jun 11 03:21:59 PM PDT 24
Finished Jun 11 03:22:01 PM PDT 24
Peak memory 205312 kb
Host smart-d28708d0-2d38-4e2f-86fb-a0d255b7e1d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515045443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
515045443
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3023712511
Short name T952
Test name
Test status
Simulation time 290192870 ps
CPU time 2.36 seconds
Started Jun 11 03:21:53 PM PDT 24
Finished Jun 11 03:21:57 PM PDT 24
Peak memory 224276 kb
Host smart-93da3a4b-1366-422e-95ea-09d4e715d6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023712511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3023712511
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.742075875
Short name T431
Test name
Test status
Simulation time 48123426 ps
CPU time 0.77 seconds
Started Jun 11 03:21:56 PM PDT 24
Finished Jun 11 03:21:58 PM PDT 24
Peak memory 205376 kb
Host smart-d7697dfc-0578-47fc-b749-f4b4149c6ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742075875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.742075875
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3690061459
Short name T964
Test name
Test status
Simulation time 57783816183 ps
CPU time 97.11 seconds
Started Jun 11 03:21:58 PM PDT 24
Finished Jun 11 03:23:37 PM PDT 24
Peak memory 249000 kb
Host smart-87d719c0-e809-48e3-b69c-e6735bd1d1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690061459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3690061459
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3815676845
Short name T57
Test name
Test status
Simulation time 45009900543 ps
CPU time 441.8 seconds
Started Jun 11 03:22:01 PM PDT 24
Finished Jun 11 03:29:26 PM PDT 24
Peak memory 267388 kb
Host smart-a97ec919-598b-4cbd-9e82-43cb3c840a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815676845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3815676845
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1776026005
Short name T816
Test name
Test status
Simulation time 4632873896 ps
CPU time 45.91 seconds
Started Jun 11 03:21:56 PM PDT 24
Finished Jun 11 03:22:44 PM PDT 24
Peak memory 252740 kb
Host smart-3a68dc43-11b7-49e2-a9fe-327d49a10201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776026005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1776026005
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.234865852
Short name T808
Test name
Test status
Simulation time 412927074 ps
CPU time 4.63 seconds
Started Jun 11 03:21:54 PM PDT 24
Finished Jun 11 03:22:00 PM PDT 24
Peak memory 232468 kb
Host smart-ab65b28a-f396-4d20-824b-1a62b50de4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234865852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.234865852
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1753418137
Short name T214
Test name
Test status
Simulation time 10558613859 ps
CPU time 33.13 seconds
Started Jun 11 03:21:52 PM PDT 24
Finished Jun 11 03:22:27 PM PDT 24
Peak memory 224364 kb
Host smart-d86b38f3-dd48-475b-8219-632bf3c98bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753418137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1753418137
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.422682348
Short name T76
Test name
Test status
Simulation time 1711966725 ps
CPU time 25.58 seconds
Started Jun 11 03:21:49 PM PDT 24
Finished Jun 11 03:22:16 PM PDT 24
Peak memory 248888 kb
Host smart-93360bf0-89ad-4a5c-af3e-ed6860445e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422682348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.422682348
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1639087867
Short name T631
Test name
Test status
Simulation time 101645798 ps
CPU time 1.06 seconds
Started Jun 11 03:21:50 PM PDT 24
Finished Jun 11 03:21:53 PM PDT 24
Peak memory 217748 kb
Host smart-e40017b2-b829-45ba-ad10-d3ea5be1e788
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639087867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1639087867
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3855732494
Short name T259
Test name
Test status
Simulation time 1631251585 ps
CPU time 4.73 seconds
Started Jun 11 03:21:53 PM PDT 24
Finished Jun 11 03:21:59 PM PDT 24
Peak memory 232708 kb
Host smart-8d6b2bf8-0dd4-403e-8ac7-940d44f228ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855732494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3855732494
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2710945445
Short name T270
Test name
Test status
Simulation time 4573828275 ps
CPU time 14.83 seconds
Started Jun 11 03:21:52 PM PDT 24
Finished Jun 11 03:22:09 PM PDT 24
Peak memory 240152 kb
Host smart-4ad4b792-dc02-4a65-bbab-2c4ffb5cb091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710945445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2710945445
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.735684096
Short name T379
Test name
Test status
Simulation time 1014859179 ps
CPU time 12.76 seconds
Started Jun 11 03:22:02 PM PDT 24
Finished Jun 11 03:22:17 PM PDT 24
Peak memory 222852 kb
Host smart-6919bc2b-b0d2-4b99-85db-7ad78b566c28
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=735684096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.735684096
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2392734914
Short name T334
Test name
Test status
Simulation time 7012856875 ps
CPU time 18.58 seconds
Started Jun 11 03:21:51 PM PDT 24
Finished Jun 11 03:22:11 PM PDT 24
Peak memory 216164 kb
Host smart-1f322df1-c10a-43e9-91a5-c52526c2480d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392734914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2392734914
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1923470868
Short name T569
Test name
Test status
Simulation time 8285636649 ps
CPU time 10.55 seconds
Started Jun 11 03:21:51 PM PDT 24
Finished Jun 11 03:22:04 PM PDT 24
Peak memory 216124 kb
Host smart-f0d70b89-d57a-43fb-b49c-5565dd34b6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923470868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1923470868
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1849926233
Short name T918
Test name
Test status
Simulation time 60523829 ps
CPU time 0.99 seconds
Started Jun 11 03:21:51 PM PDT 24
Finished Jun 11 03:21:54 PM PDT 24
Peak memory 206348 kb
Host smart-ad3a9977-d0da-4f62-8683-d500abc60b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849926233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1849926233
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1238253729
Short name T613
Test name
Test status
Simulation time 89791688 ps
CPU time 0.97 seconds
Started Jun 11 03:21:53 PM PDT 24
Finished Jun 11 03:21:55 PM PDT 24
Peak memory 205880 kb
Host smart-23c76793-2d63-4c20-9cca-d45f7b60764a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238253729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1238253729
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3591982463
Short name T238
Test name
Test status
Simulation time 1548094802 ps
CPU time 5.08 seconds
Started Jun 11 03:21:52 PM PDT 24
Finished Jun 11 03:21:59 PM PDT 24
Peak memory 224280 kb
Host smart-6ab23ff4-9ae9-4e13-8e20-be7aa3b64c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591982463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3591982463
Directory /workspace/9.spi_device_upload/latest
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