Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2539745	1			T1	1865		T2	49803		T3	1
all_values[1]	2539745	1			T1	1865		T2	49803		T3	1
all_values[2]	2539745	1			T1	1865		T2	49803		T3	1
all_values[3]	2539745	1			T1	1865		T2	49803		T3	1
all_values[4]	2539745	1			T1	1865		T2	49803		T3	1
all_values[5]	2539745	1			T1	1865		T2	49803		T3	1
all_values[6]	2539745	1			T1	1865		T2	49803		T3	1
all_values[7]	2539745	1			T1	1865		T2	49803		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19550454

1

T1

14920

T2

398424

T3

8

auto[1]

767506

1

T13

26897

T14

41

T15

41

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20293858

1

T1

14920

T2

398250

T3

8

auto[1]

24102

1

T2

174

T5

180

T8

103

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2514771	1			T1	1865		T2	49726		T3	1
all_values[0]	auto[0]	auto[1]	11151	1			T2	77		T5	116		T8	64
all_values[0]	auto[1]	auto[0]	13471	1			T13	8862		T14	1		T15	1
all_values[0]	auto[1]	auto[1]	352	1			T13	101		T14	6		T56	3
all_values[1]	auto[0]	auto[0]	2459963	1			T1	1865		T2	49741		T3	1
all_values[1]	auto[0]	auto[1]	7315	1			T2	62		T5	62		T8	38
all_values[1]	auto[1]	auto[0]	71997	1			T13	1		T14	1		T15	4
all_values[1]	auto[1]	auto[1]	470	1			T13	1		T14	5		T15	3
all_values[2]	auto[0]	auto[0]	2414951	1			T1	1865		T2	49768		T3	1
all_values[2]	auto[0]	auto[1]	2578	1			T2	35		T5	2		T8	1
all_values[2]	auto[1]	auto[0]	121746	1			T13	1		T14	6		T15	8
all_values[2]	auto[1]	auto[1]	470	1			T14	1		T56	20		T154	57
all_values[3]	auto[0]	auto[0]	2491151	1			T1	1865		T2	49803		T3	1
all_values[3]	auto[0]	auto[1]	171	1			T13	3		T14	1		T15	2
all_values[3]	auto[1]	auto[0]	48252	1			T14	3		T15	2		T56	22216
all_values[3]	auto[1]	auto[1]	171	1			T13	2		T14	1		T56	1
all_values[4]	auto[0]	auto[0]	2410122	1			T1	1865		T2	49803		T3	1
all_values[4]	auto[0]	auto[1]	188	1			T13	1		T14	4		T15	2
all_values[4]	auto[1]	auto[0]	129255	1			T13	8961		T15	1		T56	3
all_values[4]	auto[1]	auto[1]	180	1			T15	4		T56	3		T17	2
all_values[5]	auto[0]	auto[0]	2419580	1			T1	1865		T2	49803		T3	1
all_values[5]	auto[0]	auto[1]	173	1			T13	2		T14	2		T15	1
all_values[5]	auto[1]	auto[0]	119847	1			T13	8961		T14	5		T15	6
all_values[5]	auto[1]	auto[1]	145	1			T13	2		T14	3		T56	2
all_values[6]	auto[0]	auto[0]	2404945	1			T1	1865		T2	49803		T3	1
all_values[6]	auto[0]	auto[1]	167	1			T14	5		T15	1		T56	2
all_values[6]	auto[1]	auto[0]	134465	1			T13	2		T14	1		T15	6
all_values[6]	auto[1]	auto[1]	168	1			T13	2		T14	1		T15	1
all_values[7]	auto[0]	auto[0]	2413021	1			T1	1865		T2	49803		T3	1
all_values[7]	auto[0]	auto[1]	207	1			T13	4		T14	3		T56	7
all_values[7]	auto[1]	auto[0]	126321	1			T13	1		T14	3		T15	5
all_values[7]	auto[1]	auto[1]	196	1			T14	4		T56	3		T17	3