Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34166	1			T2	100		T3	2		T4	206
auto[SpiFlashAddrCfg]	6563	1			T2	35		T3	6		T4	37
auto[SpiFlashAddr3b]	8218	1			T2	64		T3	2		T4	57
auto[SpiFlashAddr4b]	6813	1			T2	49		T3	4		T4	35

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31322

1

T2

143

T3

14

T4

185

auto[1]

24438

1

T2

105

T4

150

T5

121

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29142

1

T2

116

T3

4

T4

174

auto[1]

26618

1

T2

132

T3

10

T4

161

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38345	1			T2	128		T3	4		T4	236
values[1]	986	1			T2	3		T4	4		T5	8
values[2]	1225	1			T2	8		T4	3		T5	2
values[3]	1244	1			T2	3		T4	5		T5	8
values[4]	1328	1			T2	13		T4	6		T5	15
values[5]	1312	1			T2	7		T3	4		T4	7
values[6]	1267	1			T2	14		T4	11		T5	11
values[7]	1333	1			T2	11		T3	2		T4	7
values[8]	8720	1			T2	61		T3	4		T4	56

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28005

1

T2

248

T3

14

T5

188

auto[1]

27755

1

T4

335

T5

67

T7

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

52860

1

T2

236

T3

14

T4

315

write

2900

1

T2

12

T4

20

T5

21

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16879

1

T2

103

T3

10

T4

103

valids[0x1]

38881

1

T2

145

T3

4

T4

232

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1403	1			T2	10		T3	2		T4	12
internal_process_ops[0x5a]	1316	1			T2	8		T3	2		T4	12
internal_process_ops[0x05]	22254	1			T2	36		T4	126		T5	44
internal_process_ops[0x35]	1315	1			T2	13		T4	7		T5	7
internal_process_ops[0x15]	1372	1			T2	6		T4	12		T5	10
internal_process_ops[0x03]	954	1			T2	6		T3	2		T4	1
internal_process_ops[0x0b]	970	1			T2	11		T4	3		T5	5
internal_process_ops[0x3b]	949	1			T2	7		T3	2		T4	1
internal_process_ops[0x6b]	941	1			T2	5		T3	2		T4	2
internal_process_ops[0xbb]	929	1			T2	10		T4	4		T5	5
internal_process_ops[0xeb]	945	1			T2	8		T3	4		T5	7

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54342

1

T2

245

T3

14

T4

325

auto[1]

1418

1

T2

3

T4

10

T5

5

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53746

1

T2

238

T3

14

T4

319

auto[1]

2014

1

T2

10

T4

16

T5

13

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9202

1

T2

74

T3

2

T5

53

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6412

1

T2

23

T5

35

T6

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1845

1

T2

13

T3

6

T5

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1505

1

T2

18

T5

17

T8

19

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2278

1

T2

25

T3

2

T5

13

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1887

1

T2

36

T5

16

T6

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1879

1

T2

22

T3

4

T5

16

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1556

1

T2

25

T5

16

T6

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

113

1

T2

2

T5

2

T27

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

91

1

T13

1

T36

2

T14

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

75

1

T27

1

T13

1

T36

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

77

1

T2

1

T5

1

T8

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

101

1

T13

8

T14

1

T67

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

86

1

T2

2

T5

2

T27

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

73

1

T2

2

T5

1

T8

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

72

1

T8

1

T36

1

T33

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

100

1

T2

3

T5

1

T14

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

70

1

T14

3

T15

2

T67

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

88

1

T8

2

T13

1

T14

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

118

1

T8

2

T14

3

T15

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

105

1

T2

2

T5

2

T27

5

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

90

1

T8

1

T36

1

T14

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

89

1

T5

2

T27

1

T13

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

93

1

T5

1

T14

1

T15

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10401

1

T4

128

T5

21

T9

92

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7453

1

T4

78

T5

14

T9

29

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1259

1

T4

15

T5

4

T9

14

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1300

1

T4

13

T5

1

T9

18

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1612

1

T4

17

T5

5

T9

19

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1661

1

T4

34

T5

5

T9

17

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1365

1

T4

14

T5

4

T7

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1245

1

T4

16

T5

4

T9

16

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

81

1

T5

1

T9

2

T26

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

90

1

T9

1

T156

4

T157

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

94

1

T5

5

T9

1

T26

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

77

1

T40

2

T13

1

T114

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

94

1

T66

1

T158

1

T156

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

68

1

T4

5

T114

2

T17

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

73

1

T4

3

T26

1

T40

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

87

1

T4

1

T9

2

T40

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

97

1

T4

1

T9

1

T26

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

84

1

T9

1

T17

4

T158

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

113

1

T4

3

T9

3

T26

5

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

110

1

T4

2

T5

1

T9

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

93

1

T4

3

T9

2

T26

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

118

1

T4

2

T26

4

T40

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

93

1

T5

2

T13

1

T159

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

87

1

T26

4

T13

1

T66

6

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3253	1			T2	32		T3	2		T5	29
auto[0]	values[0]	valids[0x1]	15035	1			T2	96		T3	2		T5	79
auto[0]	values[1]	valids[0x1]	511	1			T2	3		T5	6		T6	4
auto[0]	values[2]	valids[0x0]	478	1			T2	7		T8	8		T27	5
auto[0]	values[2]	valids[0x1]	245	1			T2	1		T8	4		T27	3
auto[0]	values[3]	valids[0x0]	460	1			T2	3		T5	4		T8	1
auto[0]	values[3]	valids[0x1]	230	1			T5	2		T27	7		T13	3
auto[0]	values[4]	valids[0x0]	476	1			T2	8		T5	5		T8	8
auto[0]	values[4]	valids[0x1]	285	1			T2	5		T5	10		T8	1
auto[0]	values[5]	valids[0x0]	498	1			T2	4		T3	4		T5	1
auto[0]	values[5]	valids[0x1]	239	1			T2	3		T5	2		T8	1
auto[0]	values[6]	valids[0x0]	473	1			T2	4		T5	5		T6	2
auto[0]	values[6]	valids[0x1]	250	1			T2	10		T5	4		T27	2
auto[0]	values[7]	valids[0x0]	484	1			T2	9		T5	2		T6	2
auto[0]	values[7]	valids[0x1]	269	1			T2	2		T3	2		T5	5
auto[0]	values[8]	valids[0x0]	3066	1			T2	36		T3	4		T5	23
auto[0]	values[8]	valids[0x1]	1753	1			T2	25		T5	11		T8	22
auto[1]	values[0]	valids[0x0]	3395	1			T4	45		T5	15		T9	42
auto[1]	values[0]	valids[0x1]	16662	1			T4	191		T5	31		T9	92
auto[1]	values[1]	valids[0x1]	475	1			T4	4		T5	2		T9	4
auto[1]	values[2]	valids[0x0]	311	1			T4	3		T5	2		T9	4
auto[1]	values[2]	valids[0x1]	191	1			T9	2		T26	4		T40	1
auto[1]	values[3]	valids[0x0]	351	1			T4	5		T5	2		T9	1
auto[1]	values[3]	valids[0x1]	203	1			T9	2		T26	6		T40	3
auto[1]	values[4]	valids[0x0]	341	1			T4	2		T9	5		T26	2
auto[1]	values[4]	valids[0x1]	226	1			T4	4		T9	6		T26	3
auto[1]	values[5]	valids[0x0]	340	1			T4	6		T9	5		T26	7
auto[1]	values[5]	valids[0x1]	235	1			T4	1		T5	1		T9	2
auto[1]	values[6]	valids[0x0]	321	1			T4	7		T5	1		T9	1
auto[1]	values[6]	valids[0x1]	223	1			T4	4		T5	1		T9	8
auto[1]	values[7]	valids[0x0]	321	1			T4	2		T7	2		T9	9
auto[1]	values[7]	valids[0x1]	259	1			T4	5		T5	1		T9	1
auto[1]	values[8]	valids[0x0]	2311	1			T4	33		T5	6		T9	34
auto[1]	values[8]	valids[0x1]	1590	1			T4	23		T5	5		T9	15