Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2774642

1

T2

21504

T3

1504

T4

13032

auto[1]

20927

1

T2

28

T4

115

T5

35

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

794860

1

T2

60

T3

1504

T4

74

auto[1]

2000709

1

T2

21472

T4

13073

T5

20753

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	541214	1			T2	2129		T3	504		T4	688
auto[524288:1048575]	343467	1			T2	3534		T3	28		T4	1036
auto[1048576:1572863]	304709	1			T2	2078		T3	216		T4	22
auto[1572864:2097151]	315234	1			T2	523		T4	1362		T5	269
auto[2097152:2621439]	292864	1			T2	1678		T3	521		T4	267
auto[2621440:3145727]	315321	1			T2	779		T4	2351		T5	400
auto[3145728:3670015]	379726	1			T2	7693		T3	142		T4	3040
auto[3670016:4194303]	303034	1			T2	3118		T3	93		T4	4381

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2019263

1

T2

21532

T3

25

T4

13132

auto[1]

776306

1

T3

1479

T4

15

T7

235

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2424005

1

T2

19841

T3

1504

T4

10687

auto[1]

371564

1

T2

1691

T4

2460

T5

3171

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	168489	1			T2	9		T3	504		T4	6
auto[0]	auto[0]	auto[0:524287]	auto[1]	302060	1			T2	2116		T4	575		T5	5689
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	89684	1			T2	5		T3	28		T4	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	205323	1			T2	3003		T4	256		T5	2253
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	109427	1			T2	1		T3	216		T4	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	156053	1			T2	2071		T4	3		T8	896
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	112535	1			T2	4		T4	2		T5	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	165757	1			T2	513		T5	257		T8	3999
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	76635	1			T2	3		T3	521		T4	9
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	161785	1			T2	1281		T4	5		T5	5752
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	71669	1			T2	1		T4	11		T5	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	199820	1			T4	2319		T5	388		T8	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	84373	1			T2	6		T3	142		T4	8
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	246953	1			T2	7687		T4	2994		T5	3095
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	72152	1			T2	6		T3	93		T4	5
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	184826	1			T2	3112		T4	4376		T5	140
auto[0]	auto[1]	auto[0:524287]	auto[0]	907	1			T4	3		T9	2		T26	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	66755	1			T4	99		T8	1924		T9	129
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1286	1			T2	2		T4	6		T5	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	44034	1			T2	513		T4	769		T5	410
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	407	1			T2	3		T8	1		T26	5
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	36093	1			T2	1		T26	3		T27	2387
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	401	1			T2	1		T4	1		T5	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	34588	1			T2	4		T4	1359		T5	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	2399	1			T2	1		T8	1		T9	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	49735	1			T2	384		T4	219		T9	1607
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	278	1			T2	8		T9	2		T26	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	40529	1			T2	769		T8	2234		T9	129
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	876	1			T5	4		T8	1		T40	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	44780	1			T5	2746		T8	1		T9	512
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1325	1			T9	12		T27	7		T13	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	42708	1			T9	5543		T27	2003		T13	2
auto[1]	auto[0]	auto[0:524287]	auto[0]	234	1			T2	2		T4	1		T5	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	1984	1			T2	2		T4	3		T5	8
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	201	1			T2	3		T8	1		T26	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2166	1			T2	6		T8	1		T26	68
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	202	1			T4	3		T26	5		T40	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1974	1			T4	11		T26	23		T40	10
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	201	1			T2	1		T5	1		T8	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1463	1			T5	2		T8	7		T40	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	177	1			T2	1		T4	5		T5	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1686	1			T2	8		T4	29		T9	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	197	1			T4	2		T5	2		T9	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2151	1			T4	19		T5	4		T27	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	202	1			T4	3		T5	1		T8	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1945	1			T4	35		T5	3		T8	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	173	1			T5	3		T8	1		T40	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1508	1			T5	3		T8	2		T13	15
auto[1]	auto[1]	auto[0:524287]	auto[0]	65	1			T4	1		T9	1		T66	4
auto[1]	auto[1]	auto[0:524287]	auto[1]	720	1			T9	1		T66	3		T17	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	70	1			T2	1		T4	1		T9	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	703	1			T2	1		T4	2		T9	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	57	1			T2	1		T26	3		T14	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	496	1			T2	1		T26	16		T33	82
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	42	1			T5	1		T67	2		T249	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	247	1			T5	2		T67	4		T249	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	39	1			T9	1		T159	3		T33	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	408	1			T9	3		T159	9		T33	74
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	59	1			T2	1		T9	1		T26	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	618	1			T9	5		T26	6		T27	9
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	54	1			T5	1		T8	1		T13	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	543	1			T15	5		T67	4		T176	18
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	44	1			T9	4		T27	3		T13	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	298	1			T9	7		T27	2		T13	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1637228	1			T2	19818		T3	25		T4	10572
auto[0]	auto[0]	auto[1]	770313	1			T3	1479		T4	4		T7	235
auto[0]	auto[1]	auto[0]	361514	1			T2	1686		T4	2455		T5	3167
auto[0]	auto[1]	auto[1]	5587	1			T4	1		T27	2		T159	1
auto[1]	auto[0]	auto[0]	16151	1			T2	23		T4	102		T5	31
auto[1]	auto[0]	auto[1]	313	1			T4	9		T27	2		T13	2
auto[1]	auto[1]	auto[0]	4370	1			T2	5		T4	3		T5	4
auto[1]	auto[1]	auto[1]	93	1			T4	1		T27	2		T159	1