Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15960

1

T2

143

T3

14

T5

99

auto[1]

12045

1

T2

105

T5

89

T6

10

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3601	1			T2	20		T8	27		T14	20
values[1]	4343	1			T2	49		T5	25		T39	10
values[2]	3605	1			T2	40		T3	14		T5	71
values[3]	2880	1			T2	24		T5	70		T8	21
values[4]	3755	1			T2	30		T5	22		T8	20
values[5]	3656	1			T2	20		T6	10		T10	6
values[6]	3403	1			T2	65		T8	81		T27	114
values[7]	2762	1			T8	43		T27	80		T13	55

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3102	1			T2	53		T8	20		T27	44
values[1]	3099	1			T5	26		T39	10		T27	20
values[2]	3199	1			T2	50		T5	20		T8	47
values[3]	3262	1			T2	65		T5	27		T6	10
values[4]	3855	1			T3	14		T5	48		T8	81
values[5]	3571	1			T2	20		T5	25		T27	23
values[6]	4058	1			T2	60		T8	21		T27	90
values[7]	3859	1			T5	42		T27	25		T13	74

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	370	1			T15	70		T56	13		T38	16
auto[0]	values[0]	values[1]	311	1			T14	11		T267	22		T246	2
auto[0]	values[0]	values[2]	253	1			T8	15		T15	7		T164	10
auto[0]	values[0]	values[3]	168	1			T38	10		T185	12		T268	2
auto[0]	values[0]	values[4]	307	1			T33	9		T177	25		T269	8
auto[0]	values[0]	values[5]	127	1			T41	10		T166	11		T182	12
auto[0]	values[0]	values[6]	242	1			T2	12		T33	92		T183	4
auto[0]	values[0]	values[7]	357	1			T15	43		T33	64		T176	13
auto[0]	values[1]	values[0]	230	1			T2	24		T27	9		T36	13
auto[0]	values[1]	values[1]	336	1			T39	10		T38	12		T67	13
auto[0]	values[1]	values[2]	326	1			T14	10		T33	13		T41	10
auto[0]	values[1]	values[3]	175	1			T2	6		T254	16		T14	16
auto[0]	values[1]	values[4]	341	1			T150	6		T120	12		T78	8
auto[0]	values[1]	values[5]	240	1			T5	10		T13	10		T15	14
auto[0]	values[1]	values[6]	264	1			T14	9		T160	12		T192	12
auto[0]	values[1]	values[7]	305	1			T27	10		T14	22		T270	22
auto[0]	values[2]	values[0]	235	1			T271	10		T160	12		T175	2
auto[0]	values[2]	values[1]	135	1			T27	14		T36	18		T37	10
auto[0]	values[2]	values[2]	215	1			T2	12		T27	13		T13	13
auto[0]	values[2]	values[3]	195	1			T5	18		T8	23		T177	9
auto[0]	values[2]	values[4]	444	1			T3	14		T5	13		T27	11
auto[0]	values[2]	values[5]	262	1			T2	10		T13	26		T15	8
auto[0]	values[2]	values[6]	433	1			T33	73		T37	10		T67	15
auto[0]	values[2]	values[7]	272	1			T5	10		T15	22		T33	71
auto[0]	values[3]	values[0]	178	1			T2	12		T14	9		T252	16
auto[0]	values[3]	values[1]	298	1			T5	11		T14	11		T152	16
auto[0]	values[3]	values[2]	265	1			T5	11		T191	18		T272	8
auto[0]	values[3]	values[3]	155	1			T27	11		T167	15		T260	16
auto[0]	values[3]	values[4]	244	1			T5	15		T8	16		T14	8
auto[0]	values[3]	values[5]	179	1			T14	14		T171	25		T273	2
auto[0]	values[3]	values[6]	207	1			T15	16		T20	14		T41	14
auto[0]	values[3]	values[7]	189	1			T149	20		T67	15		T193	18
auto[0]	values[4]	values[0]	266	1			T79	4		T37	8		T20	13
auto[0]	values[4]	values[1]	180	1			T14	11		T56	11		T67	22
auto[0]	values[4]	values[2]	287	1			T2	19		T15	14		T38	17
auto[0]	values[4]	values[3]	268	1			T14	17		T154	10		T167	14
auto[0]	values[4]	values[4]	168	1			T8	13		T36	11		T274	2
auto[0]	values[4]	values[5]	424	1			T13	12		T37	10		T67	11
auto[0]	values[4]	values[6]	212	1			T15	11		T167	14		T275	12
auto[0]	values[4]	values[7]	226	1			T5	11		T13	8		T38	23
auto[0]	values[5]	values[0]	228	1			T117	2		T37	13		T38	14
auto[0]	values[5]	values[1]	227	1			T154	23		T167	56		T41	6
auto[0]	values[5]	values[2]	183	1			T27	22		T36	25		T14	14
auto[0]	values[5]	values[3]	243	1			T67	13		T184	13		T276	10
auto[0]	values[5]	values[4]	307	1			T10	6		T27	14		T37	50
auto[0]	values[5]	values[5]	284	1			T15	14		T56	15		T67	76
auto[0]	values[5]	values[6]	165	1			T2	10		T37	11		T195	14
auto[0]	values[5]	values[7]	328	1			T13	42		T184	10		T167	10
auto[0]	values[6]	values[0]	225	1			T8	14		T27	10		T136	4
auto[0]	values[6]	values[1]	115	1			T211	10		T277	13		T278	29
auto[0]	values[6]	values[2]	236	1			T8	12		T13	11		T15	13
auto[0]	values[6]	values[3]	325	1			T2	23		T194	69		T37	15
auto[0]	values[6]	values[4]	281	1			T8	12		T13	73		T62	6
auto[0]	values[6]	values[5]	218	1			T14	21		T167	14		T258	14
auto[0]	values[6]	values[6]	426	1			T2	15		T8	8		T27	71
auto[0]	values[6]	values[7]	316	1			T14	31		T37	44		T38	13
auto[0]	values[7]	values[0]	83	1			T177	11		T76	16		T196	16
auto[0]	values[7]	values[1]	128	1			T13	22		T119	6		T170	12
auto[0]	values[7]	values[2]	137	1			T37	10		T188	4		T255	14
auto[0]	values[7]	values[3]	252	1			T8	17		T27	19		T177	18
auto[0]	values[7]	values[4]	260	1			T8	10		T27	9		T13	16
auto[0]	values[7]	values[5]	255	1			T27	6		T14	12		T167	9
auto[0]	values[7]	values[6]	296	1			T33	31		T37	12		T184	17
auto[0]	values[7]	values[7]	153	1			T168	24		T208	11		T211	13
auto[1]	values[0]	values[0]	140	1			T15	9		T56	7		T38	4
auto[1]	values[0]	values[1]	96	1			T14	9		T279	2		T182	9
auto[1]	values[0]	values[2]	225	1			T8	12		T15	21		T165	12
auto[1]	values[0]	values[3]	248	1			T38	18		T206	58		T277	7
auto[1]	values[0]	values[4]	225	1			T33	51		T177	13		T160	11
auto[1]	values[0]	values[5]	293	1			T41	10		T280	10		T166	16
auto[1]	values[0]	values[6]	107	1			T2	8		T33	9		T215	10
auto[1]	values[0]	values[7]	132	1			T15	6		T33	9		T176	26
auto[1]	values[1]	values[0]	142	1			T2	5		T27	11		T36	7
auto[1]	values[1]	values[1]	360	1			T38	8		T67	7		T167	12
auto[1]	values[1]	values[2]	111	1			T14	10		T33	7		T41	15
auto[1]	values[1]	values[3]	300	1			T2	14		T14	4		T20	10
auto[1]	values[1]	values[4]	163	1			T155	7		T211	9		T197	23
auto[1]	values[1]	values[5]	236	1			T5	15		T13	21		T15	17
auto[1]	values[1]	values[6]	407	1			T14	19		T160	8		T211	173
auto[1]	values[1]	values[7]	407	1			T27	15		T14	7		T189	11
auto[1]	values[2]	values[0]	94	1			T160	8		T121	26		T166	5
auto[1]	values[2]	values[1]	108	1			T27	6		T36	8		T37	10
auto[1]	values[2]	values[2]	234	1			T2	8		T27	7		T13	15
auto[1]	values[2]	values[3]	79	1			T5	9		T8	5		T177	11
auto[1]	values[2]	values[4]	257	1			T5	11		T27	9		T13	11
auto[1]	values[2]	values[5]	137	1			T2	10		T13	3		T15	12
auto[1]	values[2]	values[6]	359	1			T33	232		T37	10		T67	28
auto[1]	values[2]	values[7]	146	1			T5	10		T15	13		T33	13
auto[1]	values[3]	values[0]	134	1			T2	12		T14	13		T215	10
auto[1]	values[3]	values[1]	170	1			T5	15		T14	10		T176	5
auto[1]	values[3]	values[2]	125	1			T5	9		T161	10		T189	11
auto[1]	values[3]	values[3]	241	1			T27	9		T167	48		T168	43
auto[1]	values[3]	values[4]	172	1			T5	9		T8	5		T22	22
auto[1]	values[3]	values[5]	112	1			T14	10		T171	15		T223	28
auto[1]	values[3]	values[6]	115	1			T15	4		T20	6		T41	6
auto[1]	values[3]	values[7]	96	1			T67	5		T226	13		T121	4
auto[1]	values[4]	values[0]	156	1			T37	29		T20	23		T160	12
auto[1]	values[4]	values[1]	188	1			T14	14		T56	13		T67	11
auto[1]	values[4]	values[2]	129	1			T2	11		T15	6		T38	10
auto[1]	values[4]	values[3]	137	1			T14	10		T154	10		T167	10
auto[1]	values[4]	values[4]	101	1			T8	7		T36	9		T189	10
auto[1]	values[4]	values[5]	361	1			T13	8		T37	76		T67	104
auto[1]	values[4]	values[6]	264	1			T15	9		T167	44		T208	7
auto[1]	values[4]	values[7]	388	1			T5	11		T13	18		T38	13
auto[1]	values[5]	values[0]	307	1			T37	7		T38	6		T217	8
auto[1]	values[5]	values[1]	329	1			T154	14		T167	11		T41	14
auto[1]	values[5]	values[2]	104	1			T27	10		T36	4		T14	6
auto[1]	values[5]	values[3]	183	1			T6	10		T67	11		T184	7
auto[1]	values[5]	values[4]	200	1			T27	6		T37	4		T154	9
auto[1]	values[5]	values[5]	130	1			T15	6		T56	5		T67	26
auto[1]	values[5]	values[6]	237	1			T2	10		T37	34		T195	10
auto[1]	values[5]	values[7]	201	1			T13	6		T184	10		T167	37
auto[1]	values[6]	values[0]	135	1			T8	6		T27	14		T13	10
auto[1]	values[6]	values[1]	88	1			T211	10		T277	7		T278	11
auto[1]	values[6]	values[2]	227	1			T8	8		T13	18		T15	7
auto[1]	values[6]	values[3]	141	1			T2	22		T37	5		T41	8
auto[1]	values[6]	values[4]	168	1			T8	8		T13	6		T41	9
auto[1]	values[6]	values[5]	139	1			T14	7		T167	16		T171	12
auto[1]	values[6]	values[6]	224	1			T2	5		T8	13		T27	19
auto[1]	values[6]	values[7]	139	1			T14	13		T37	8		T38	7
auto[1]	values[7]	values[0]	179	1			T177	34		T171	5		T200	93
auto[1]	values[7]	values[1]	30	1			T13	8		T213	9		T201	6
auto[1]	values[7]	values[2]	142	1			T37	10		T226	6		T281	12
auto[1]	values[7]	values[3]	152	1			T8	6		T27	8		T177	11
auto[1]	values[7]	values[4]	217	1			T8	10		T27	21		T13	9
auto[1]	values[7]	values[5]	174	1			T27	17		T14	8		T167	11
auto[1]	values[7]	values[6]	100	1			T33	9		T113	10		T37	8
auto[1]	values[7]	values[7]	204	1			T168	4		T208	102		T211	7