Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2539745	1			T1	1865		T2	49803		T3	1
all_pins[1]	2539745	1			T1	1865		T2	49803		T3	1
all_pins[2]	2539745	1			T1	1865		T2	49803		T3	1
all_pins[3]	2539745	1			T1	1865		T2	49803		T3	1
all_pins[4]	2539745	1			T1	1865		T2	49803		T3	1
all_pins[5]	2539745	1			T1	1865		T2	49803		T3	1
all_pins[6]	2539745	1			T1	1865		T2	49803		T3	1
all_pins[7]	2539745	1			T1	1865		T2	49803		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20180036	1			T1	14920		T2	398424		T3	8
values[0x1]	137924	1			T13	498		T14	21		T15	8
transitions[0x0=>0x1]	136960	1			T13	496		T14	13		T15	8
transitions[0x1=>0x0]	136977	1			T13	496		T14	13		T15	8

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2539370	1			T1	1865		T2	49803		T3	1
all_pins[0]	values[0x1]	375	1			T13	110		T14	6		T56	3
all_pins[0]	transitions[0x0=>0x1]	328	1			T13	109		T14	2		T56	3
all_pins[0]	transitions[0x1=>0x0]	463	1			T14	1		T15	3		T56	1
all_pins[1]	values[0x0]	2539235	1			T1	1865		T2	49803		T3	1
all_pins[1]	values[0x1]	510	1			T13	1		T14	5		T15	3
all_pins[1]	transitions[0x0=>0x1]	303	1			T13	1		T14	5		T15	3
all_pins[1]	transitions[0x1=>0x0]	290	1			T14	1		T56	22		T154	59
all_pins[2]	values[0x0]	2539248	1			T1	1865		T2	49803		T3	1
all_pins[2]	values[0x1]	497	1			T14	1		T56	22		T154	59
all_pins[2]	transitions[0x0=>0x1]	459	1			T56	22		T154	59		T20	25
all_pins[2]	transitions[0x1=>0x0]	133	1			T13	2		T56	1		T17	3
all_pins[3]	values[0x0]	2539574	1			T1	1865		T2	49803		T3	1
all_pins[3]	values[0x1]	171	1			T13	2		T14	1		T56	1
all_pins[3]	transitions[0x0=>0x1]	137	1			T13	2		T14	1		T56	1
all_pins[3]	transitions[0x1=>0x0]	146	1			T15	4		T56	3		T17	2
all_pins[4]	values[0x0]	2539565	1			T1	1865		T2	49803		T3	1
all_pins[4]	values[0x1]	180	1			T15	4		T56	3		T17	2
all_pins[4]	transitions[0x0=>0x1]	150	1			T15	4		T56	3		T17	2
all_pins[4]	transitions[0x1=>0x0]	1869	1			T13	383		T14	3		T56	2
all_pins[5]	values[0x0]	2537846	1			T1	1865		T2	49803		T3	1
all_pins[5]	values[0x1]	1899	1			T13	383		T14	3		T56	2
all_pins[5]	transitions[0x0=>0x1]	1406	1			T13	382		T14	3		T56	2
all_pins[5]	transitions[0x1=>0x0]	133603	1			T13	1		T14	1		T15	1
all_pins[6]	values[0x0]	2405649	1			T1	1865		T2	49803		T3	1
all_pins[6]	values[0x1]	134096	1			T13	2		T14	1		T15	1
all_pins[6]	transitions[0x0=>0x1]	134048	1			T13	2		T14	1		T15	1
all_pins[6]	transitions[0x1=>0x0]	148	1			T14	4		T56	2		T17	3
all_pins[7]	values[0x0]	2539549	1			T1	1865		T2	49803		T3	1
all_pins[7]	values[0x1]	196	1			T14	4		T56	3		T17	3
all_pins[7]	transitions[0x0=>0x1]	129	1			T14	1		T56	3		T17	1
all_pins[7]	transitions[0x1=>0x0]	325	1			T13	110		T14	3		T56	3