Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	66	0	66	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	64	0	64	100.00	100	1	1	64

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14186

1

T2

126

T3

7

T5

95

auto[1]

41574

1

T2

122

T3

7

T4

335

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	64	0	64	100.00

Automatically Generated Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	1158	1			T2	8		T3	2		T4	1
auto[4:7]	24997	1			T2	49		T4	145		T5	53
auto[8:11]	1187	1			T2	12		T4	4		T5	5
auto[12:15]	271	1			T2	4		T4	5		T5	3
auto[16:19]	252	1			T2	2		T4	1		T5	1
auto[20:23]	1571	1			T2	7		T4	16		T5	12
auto[24:27]	238	1			T2	2		T8	1		T9	2
auto[28:31]	263	1			T2	4		T4	1		T5	2
auto[32:35]	293	1			T4	1		T5	1		T9	4
auto[36:39]	307	1			T2	1		T4	1		T5	3
auto[40:43]	324	1			T2	2		T5	5		T8	3
auto[44:47]	257	1			T4	1		T5	1		T8	1
auto[48:51]	275	1			T2	1		T4	1		T5	2
auto[52:55]	1498	1			T2	13		T4	9		T5	8
auto[56:59]	1161	1			T2	8		T3	2		T4	4
auto[60:63]	327	1			T4	5		T5	1		T9	5
auto[64:67]	263	1			T4	4		T5	1		T8	2
auto[68:71]	290	1			T2	1		T4	1		T5	1
auto[72:75]	278	1			T2	2		T5	1		T8	1
auto[76:79]	283	1			T4	1		T5	1		T8	1
auto[80:83]	312	1			T2	2		T4	4		T9	3
auto[84:87]	274	1			T4	3		T5	2		T26	1
auto[88:91]	1521	1			T2	9		T3	2		T4	12
auto[92:95]	232	1			T2	1		T4	3		T9	2
auto[96:99]	267	1			T2	2		T4	1		T9	1
auto[100:103]	282	1			T2	1		T4	2		T26	1
auto[104:107]	1159	1			T2	5		T3	2		T4	2
auto[108:111]	248	1			T2	3		T5	4		T9	1
auto[112:115]	291	1			T4	1		T5	1		T27	2
auto[116:119]	277	1			T4	1		T5	2		T26	1
auto[120:123]	272	1			T2	1		T4	2		T5	4
auto[124:127]	342	1			T2	1		T4	4		T5	7
auto[128:131]	284	1			T2	2		T4	4		T5	1
auto[132:135]	300	1			T2	2		T4	3		T5	2
auto[136:139]	279	1			T2	2		T5	8		T9	1
auto[140:143]	268	1			T2	2		T4	5		T5	3
auto[144:147]	284	1			T4	1		T9	1		T26	1
auto[148:151]	300	1			T2	3		T4	4		T8	3
auto[152:155]	268	1			T2	1		T5	1		T8	2
auto[156:159]	1621	1			T2	11		T3	2		T4	20
auto[160:163]	290	1			T2	2		T5	5		T8	5
auto[164:167]	274	1			T2	1		T5	4		T26	3
auto[168:171]	318	1			T2	3		T4	1		T5	2
auto[172:175]	250	1			T2	4		T4	1		T9	1
auto[176:179]	324	1			T2	2		T5	2		T9	1
auto[180:183]	1642	1			T2	6		T4	8		T5	16
auto[184:187]	1161	1			T2	15		T4	5		T5	8
auto[188:191]	267	1			T2	2		T5	2		T8	4
auto[192:195]	313	1			T2	5		T4	2		T5	4
auto[196:199]	274	1			T2	6		T4	2		T5	2
auto[200:203]	265	1			T4	4		T8	1		T9	4
auto[204:207]	298	1			T2	2		T4	4		T5	2
auto[208:211]	283	1			T2	1		T4	2		T8	1
auto[212:215]	282	1			T2	3		T4	6		T6	4
auto[216:219]	248	1			T2	1		T4	2		T5	1
auto[220:223]	253	1			T2	1		T5	3		T8	2
auto[224:227]	315	1			T2	1		T4	2		T5	1
auto[228:231]	300	1			T2	4		T4	6		T5	5
auto[232:235]	2386	1			T2	16		T3	4		T4	6
auto[236:239]	295	1			T2	5		T8	6		T27	1
auto[240:243]	301	1			T2	2		T4	3		T5	4
auto[244:247]	246	1			T4	1		T5	1		T8	1
auto[248:251]	327	1			T2	1		T4	2		T26	4
auto[252:255]	274	1			T2	1		T4	5		T5	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	auto[0]	408	1			T2	3		T3	1		T5	3
auto[0:3]	auto[1]	750	1			T2	5		T3	1		T4	1
auto[4:7]	auto[0]	5816	1			T2	11		T5	20		T6	1
auto[4:7]	auto[1]	19181	1			T2	38		T4	145		T5	33
auto[8:11]	auto[0]	425	1			T2	10		T5	2		T8	9
auto[8:11]	auto[1]	762	1			T2	2		T4	4		T5	3
auto[12:15]	auto[0]	70	1			T2	1		T8	2		T36	1
auto[12:15]	auto[1]	201	1			T2	3		T4	5		T5	3
auto[16:19]	auto[0]	65	1			T5	1		T27	1		T13	1
auto[16:19]	auto[1]	187	1			T2	2		T4	1		T9	1
auto[20:23]	auto[0]	387	1			T2	6		T5	2		T8	6
auto[20:23]	auto[1]	1184	1			T2	1		T4	16		T5	10
auto[24:27]	auto[0]	41	1			T2	2		T8	1		T27	3
auto[24:27]	auto[1]	197	1			T9	2		T26	2		T27	3
auto[28:31]	auto[0]	55	1			T2	3		T13	1		T14	2
auto[28:31]	auto[1]	208	1			T2	1		T4	1		T5	2
auto[32:35]	auto[0]	73	1			T27	1		T14	2		T15	3
auto[32:35]	auto[1]	220	1			T4	1		T5	1		T9	4
auto[36:39]	auto[0]	69	1			T13	4		T14	2		T113	1
auto[36:39]	auto[1]	238	1			T2	1		T4	1		T5	3
auto[40:43]	auto[0]	72	1			T2	1		T5	3		T10	1
auto[40:43]	auto[1]	252	1			T2	1		T5	2		T8	3
auto[44:47]	auto[0]	72	1			T8	1		T27	2		T14	2
auto[44:47]	auto[1]	185	1			T4	1		T5	1		T9	3
auto[48:51]	auto[0]	69	1			T2	1		T27	2		T14	1
auto[48:51]	auto[1]	206	1			T4	1		T5	2		T8	4
auto[52:55]	auto[0]	402	1			T2	7		T5	2		T8	5
auto[52:55]	auto[1]	1096	1			T2	6		T4	9		T5	6
auto[56:59]	auto[0]	431	1			T2	4		T3	1		T5	4
auto[56:59]	auto[1]	730	1			T2	4		T3	1		T4	4
auto[60:63]	auto[0]	80	1			T5	1		T27	1		T13	3
auto[60:63]	auto[1]	247	1			T4	5		T9	5		T26	4
auto[64:67]	auto[0]	77	1			T5	1		T8	2		T13	4
auto[64:67]	auto[1]	186	1			T4	4		T9	3		T13	1
auto[68:71]	auto[0]	68	1			T2	1		T5	1		T6	1
auto[68:71]	auto[1]	222	1			T4	1		T6	1		T9	2
auto[72:75]	auto[0]	79	1			T2	2		T5	1		T8	1
auto[72:75]	auto[1]	199	1			T26	1		T27	1		T40	1
auto[76:79]	auto[0]	67	1			T5	1		T8	1		T13	2
auto[76:79]	auto[1]	216	1			T4	1		T26	3		T27	4
auto[80:83]	auto[0]	71	1			T2	2		T14	5		T15	3
auto[80:83]	auto[1]	241	1			T4	4		T9	3		T40	1
auto[84:87]	auto[0]	73	1			T5	2		T14	1		T56	1
auto[84:87]	auto[1]	201	1			T4	3		T26	1		T27	3
auto[88:91]	auto[0]	377	1			T2	7		T3	1		T5	5
auto[88:91]	auto[1]	1144	1			T2	2		T3	1		T4	12
auto[92:95]	auto[0]	51	1			T27	2		T13	1		T191	1
auto[92:95]	auto[1]	181	1			T2	1		T4	3		T9	2
auto[96:99]	auto[0]	65	1			T2	2		T27	3		T14	1
auto[96:99]	auto[1]	202	1			T4	1		T9	1		T26	4
auto[100:103]	auto[0]	56	1			T27	2		T38	1		T67	2
auto[100:103]	auto[1]	226	1			T2	1		T4	2		T26	1
auto[104:107]	auto[0]	405	1			T2	1		T3	1		T5	7
auto[104:107]	auto[1]	754	1			T2	4		T3	1		T4	2
auto[108:111]	auto[0]	64	1			T2	3		T5	3		T27	1
auto[108:111]	auto[1]	184	1			T5	1		T9	1		T26	1
auto[112:115]	auto[0]	77	1			T5	1		T27	2		T13	2
auto[112:115]	auto[1]	214	1			T4	1		T40	3		T13	1
auto[116:119]	auto[0]	75	1			T5	2		T27	2		T254	1
auto[116:119]	auto[1]	202	1			T4	1		T26	1		T40	1
auto[120:123]	auto[0]	59	1			T2	1		T5	2		T8	3
auto[120:123]	auto[1]	213	1			T4	2		T5	2		T9	1
auto[124:127]	auto[0]	82	1			T2	1		T8	1		T27	1
auto[124:127]	auto[1]	260	1			T4	4		T5	7		T9	3
auto[128:131]	auto[0]	61	1			T13	2		T15	2		T282	3
auto[128:131]	auto[1]	223	1			T2	2		T4	4		T5	1
auto[132:135]	auto[0]	95	1			T8	4		T27	4		T194	1
auto[132:135]	auto[1]	205	1			T2	2		T4	3		T5	2
auto[136:139]	auto[0]	76	1			T2	2		T5	4		T27	2
auto[136:139]	auto[1]	203	1			T5	4		T9	1		T40	4
auto[140:143]	auto[0]	62	1			T14	1		T15	4		T37	1
auto[140:143]	auto[1]	206	1			T2	2		T4	5		T5	3
auto[144:147]	auto[0]	78	1			T36	1		T14	1		T15	1
auto[144:147]	auto[1]	206	1			T4	1		T9	1		T26	1
auto[148:151]	auto[0]	85	1			T2	2		T8	3		T13	3
auto[148:151]	auto[1]	215	1			T2	1		T4	4		T9	9
auto[152:155]	auto[0]	55	1			T8	1		T14	1		T15	1
auto[152:155]	auto[1]	213	1			T2	1		T5	1		T8	1
auto[156:159]	auto[0]	423	1			T2	3		T3	1		T5	6
auto[156:159]	auto[1]	1198	1			T2	8		T3	1		T4	20
auto[160:163]	auto[0]	76	1			T2	2		T8	2		T13	3
auto[160:163]	auto[1]	214	1			T5	5		T8	3		T9	5
auto[164:167]	auto[0]	69	1			T2	1		T5	1		T27	1
auto[164:167]	auto[1]	205	1			T5	3		T26	3		T13	1
auto[168:171]	auto[0]	76	1			T2	3		T5	2		T36	1
auto[168:171]	auto[1]	242	1			T4	1		T8	1		T9	1
auto[172:175]	auto[0]	61	1			T2	1		T27	1		T13	2
auto[172:175]	auto[1]	189	1			T2	3		T4	1		T9	1
auto[176:179]	auto[0]	91	1			T2	2		T13	1		T36	1
auto[176:179]	auto[1]	233	1			T5	2		T9	1		T26	2
auto[180:183]	auto[0]	423	1			T2	6		T5	3		T8	6
auto[180:183]	auto[1]	1219	1			T4	8		T5	13		T8	3
auto[184:187]	auto[0]	415	1			T2	9		T5	1		T6	1
auto[184:187]	auto[1]	746	1			T2	6		T4	5		T5	7
auto[188:191]	auto[0]	55	1			T2	1		T5	1		T8	1
auto[188:191]	auto[1]	212	1			T2	1		T5	1		T8	3
auto[192:195]	auto[0]	70	1			T2	3		T27	1		T13	1
auto[192:195]	auto[1]	243	1			T2	2		T4	2		T5	4
auto[196:199]	auto[0]	66	1			T2	1		T5	1		T27	2
auto[196:199]	auto[1]	208	1			T2	5		T4	2		T5	1
auto[200:203]	auto[0]	56	1			T13	1		T15	4		T33	3
auto[200:203]	auto[1]	209	1			T4	4		T8	1		T9	4
auto[204:207]	auto[0]	71	1			T5	2		T8	3		T14	1
auto[204:207]	auto[1]	227	1			T2	2		T4	4		T8	1
auto[208:211]	auto[0]	65	1			T2	1		T27	1		T14	1
auto[208:211]	auto[1]	218	1			T4	2		T8	1		T9	1
auto[212:215]	auto[0]	72	1			T2	3		T6	2		T13	1
auto[212:215]	auto[1]	210	1			T4	6		T6	2		T9	1
auto[216:219]	auto[0]	75	1			T2	1		T5	1		T8	5
auto[216:219]	auto[1]	173	1			T4	2		T9	2		T40	2
auto[220:223]	auto[0]	53	1			T5	1		T8	1		T27	1
auto[220:223]	auto[1]	200	1			T2	1		T5	2		T8	1
auto[224:227]	auto[0]	62	1			T2	1		T8	1		T27	1
auto[224:227]	auto[1]	253	1			T4	2		T5	1		T26	2
auto[228:231]	auto[0]	60	1			T2	2		T5	2		T8	1
auto[228:231]	auto[1]	240	1			T2	2		T4	6		T5	3
auto[232:235]	auto[0]	727	1			T2	9		T3	2		T5	3
auto[232:235]	auto[1]	1659	1			T2	7		T3	2		T4	6
auto[236:239]	auto[0]	74	1			T2	1		T27	1		T13	2
auto[236:239]	auto[1]	221	1			T2	4		T8	6		T13	1
auto[240:243]	auto[0]	73	1			T2	2		T5	2		T8	3
auto[240:243]	auto[1]	228	1			T4	3		T5	2		T9	4
auto[244:247]	auto[0]	57	1			T5	1		T27	1		T36	3
auto[244:247]	auto[1]	189	1			T4	1		T8	1		T9	7
auto[248:251]	auto[0]	69	1			T27	3		T14	3		T56	1
auto[248:251]	auto[1]	258	1			T2	1		T4	2		T26	4
auto[252:255]	auto[0]	54	1			T2	1		T8	2		T27	1
auto[252:255]	auto[1]	220	1			T4	5		T5	2		T9	2