Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	405	1			T2	4		T5	4		T8	9
auto[ReadAddrCrossIntoMailbox]	242	1			T5	4		T8	2		T27	3
auto[ReadAddrCrossOutOfMailbox]	270	1			T2	3		T5	1		T8	4
auto[ReadAddrCrossAllMailbox]	206	1			T2	3		T5	2		T8	4
auto[ReadAddrOutsideMailbox]	3144	1			T2	37		T3	10		T5	20

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2153

1

T2

28

T3

5

T5

16

auto[1]

2114

1

T2

19

T3

5

T5

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	747	1			T2	6		T3	2		T5	6
read_ops[0x0b]	715	1			T2	11		T5	5		T8	9
read_ops[0x3b]	735	1			T2	7		T3	2		T5	3
read_ops[0x6b]	692	1			T2	5		T3	2		T5	7
read_ops[0xbb]	693	1			T2	10		T5	3		T6	2
read_ops[0xeb]	685	1			T2	8		T3	4		T5	7

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	52	1			T5	1		T8	1		T27	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T8	1		T79	1		T37	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T27	1		T154	1		T184	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T14	2		T38	1		T160	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T8	2		T14	1		T56	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T14	1		T67	1		T154	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T14	1		T184	1		T170	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	28	1			T2	1		T15	1		T170	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	245	1			T2	2		T3	1		T5	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	271	1			T2	3		T3	1		T5	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T2	1		T8	3		T116	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T13	2		T15	1		T116	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T8	1		T14	2		T167	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T5	1		T27	1		T167	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T56	1		T38	1		T167	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T27	1		T176	1		T255	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T2	1		T8	1		T13	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T8	1		T27	1		T253	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	281	1			T2	8		T5	2		T8	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	274	1			T2	1		T5	2		T22	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T27	1		T116	2		T117	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T2	1		T15	1		T116	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T56	2		T184	1		T171	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	8	1			T14	1		T67	1		T160	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T2	1		T5	1		T136	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T136	1		T14	1		T33	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T185	1		T121	1		T189	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T2	1		T8	2		T168	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	289	1			T2	3		T3	1		T5	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	271	1			T2	1		T3	1		T22	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T5	2		T13	1		T15	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T14	1		T38	1		T67	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T5	1		T160	1		T212	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T15	1		T195	1		T253	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T8	2		T14	1		T154	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	12	1			T14	1		T38	2		T185	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T67	1		T170	1		T252	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T15	1		T177	1		T170	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	252	1			T2	1		T3	1		T5	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	263	1			T2	4		T3	1		T22	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T2	2		T5	1		T37	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T8	2		T27	1		T36	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T15	1		T33	1		T180	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T8	1		T27	1		T13	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	14	1			T2	1		T217	1		T255	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T13	2		T56	1		T154	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T13	1		T14	1		T177	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T27	1		T154	2		T180	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	260	1			T2	3		T6	1		T8	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	249	1			T2	4		T5	2		T6	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T8	1		T15	2		T37	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T8	1		T27	1		T13	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T14	1		T33	1		T171	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T5	2		T15	1		T37	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T2	1		T14	3		T15	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T27	1		T13	2		T15	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T15	1		T171	1		T182	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T5	2		T13	1		T15	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	238	1			T2	4		T3	2		T8	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	251	1			T2	3		T3	2		T5	3