Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3829	1			T5	47		T8	43		T27	43
values[1]	3256	1			T2	59		T5	69		T27	24
values[2]	3807	1			T3	14		T8	61		T27	67
values[3]	3805	1			T2	40		T8	20		T39	10
values[4]	3546	1			T2	45		T8	20		T10	6
values[5]	3063	1			T2	60		T5	22		T8	28
values[6]	3037	1			T6	10		T8	48		T27	62
values[7]	3662	1			T2	44		T5	50		T27	90

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4465	1			T2	45		T3	14		T8	92
values[1]	3309	1			T2	49		T5	48		T27	70
values[2]	3146	1			T8	40		T27	20		T13	176
values[3]	3511	1			T2	40		T5	47		T8	21
values[4]	3411	1			T5	51		T6	10		T8	27
values[5]	2837	1			T2	44		T8	20		T27	82
values[6]	4029	1			T2	20		T10	6		T27	45
values[7]	3297	1			T2	50		T5	42		T8	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27308

1

T2

245

T3

14

T5

184

auto[1]

697

1

T2

3

T5

4

T8

8

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[6]]	[values[3]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	724	1			T8	22		T14	19		T33	37
auto[0]	values[0]	values[1]	342	1			T154	23		T160	24		T161	6
auto[0]	values[0]	values[2]	277	1			T27	20		T38	20		T162	6
auto[0]	values[0]	values[3]	605	1			T5	26		T36	28		T33	160
auto[0]	values[0]	values[4]	392	1			T15	63		T78	8		T163	14
auto[0]	values[0]	values[5]	276	1			T8	20		T14	20		T37	17
auto[0]	values[0]	values[6]	575	1			T120	12		T37	16		T154	20
auto[0]	values[0]	values[7]	552	1			T5	20		T27	23		T56	24
auto[0]	values[1]	values[0]	412	1			T150	6		T33	84		T117	2
auto[0]	values[1]	values[1]	438	1			T2	29		T5	23		T164	10
auto[0]	values[1]	values[2]	389	1			T20	20		T165	20		T166	25
auto[0]	values[1]	values[3]	428	1			T5	20		T27	24		T13	29
auto[0]	values[1]	values[4]	254	1			T5	25		T13	30		T154	19
auto[0]	values[1]	values[5]	392	1			T36	20		T167	19		T168	19
auto[0]	values[1]	values[6]	629	1			T14	48		T56	20		T33	19
auto[0]	values[1]	values[7]	253	1			T2	30		T13	48		T167	20
auto[0]	values[2]	values[0]	702	1			T3	14		T8	38		T27	47
auto[0]	values[2]	values[1]	441	1			T37	84		T167	63		T169	6
auto[0]	values[2]	values[2]	420	1			T13	66		T149	20		T15	19
auto[0]	values[2]	values[3]	398	1			T13	29		T166	55		T42	20
auto[0]	values[2]	values[4]	515	1			T113	10		T170	12		T171	20
auto[0]	values[2]	values[5]	279	1			T13	28		T172	4		T173	2
auto[0]	values[2]	values[6]	463	1			T27	20		T14	20		T67	24
auto[0]	values[2]	values[7]	503	1			T8	18		T14	26		T174	4
auto[0]	values[3]	values[0]	534	1			T14	20		T37	36		T67	25
auto[0]	values[3]	values[1]	570	1			T33	227		T167	28		T175	2
auto[0]	values[3]	values[2]	344	1			T8	20		T152	16		T167	47
auto[0]	values[3]	values[3]	553	1			T13	25		T14	47		T15	20
auto[0]	values[3]	values[4]	321	1			T39	10		T62	6		T41	18
auto[0]	values[3]	values[5]	538	1			T2	20		T27	20		T56	20
auto[0]	values[3]	values[6]	400	1			T2	20		T14	20		T176	30
auto[0]	values[3]	values[7]	464	1			T79	4		T177	20		T67	20
auto[0]	values[4]	values[0]	582	1			T2	25		T56	19		T37	20
auto[0]	values[4]	values[1]	397	1			T67	29		T178	10		T171	20
auto[0]	values[4]	values[2]	446	1			T8	20		T15	20		T179	14
auto[0]	values[4]	values[3]	287	1			T2	20		T13	20		T176	20
auto[0]	values[4]	values[4]	565	1			T27	20		T15	19		T38	20
auto[0]	values[4]	values[5]	314	1			T177	44		T168	20		T180	20
auto[0]	values[4]	values[6]	521	1			T10	6		T13	30		T67	73
auto[0]	values[4]	values[7]	317	1			T14	50		T181	20		T182	39
auto[0]	values[5]	values[0]	286	1			T2	18		T8	26		T14	20
auto[0]	values[5]	values[1]	233	1			T2	20		T56	25		T183	4
auto[0]	values[5]	values[2]	394	1			T13	30		T184	20		T166	41
auto[0]	values[5]	values[3]	429	1			T38	26		T185	12		T186	4
auto[0]	values[5]	values[4]	420	1			T177	34		T76	16		T184	20
auto[0]	values[5]	values[5]	312	1			T65	4		T38	23		T187	33
auto[0]	values[5]	values[6]	230	1			T27	25		T37	20		T188	4
auto[0]	values[5]	values[7]	682	1			T2	20		T5	22		T22	22
auto[0]	values[6]	values[0]	434	1			T15	50		T41	20		T187	130
auto[0]	values[6]	values[1]	278	1			T167	30		T189	30		T190	52
auto[0]	values[6]	values[2]	297	1			T167	21		T160	20		T143	19
auto[0]	values[6]	values[3]	301	1			T8	21		T36	20		T191	18
auto[0]	values[6]	values[4]	526	1			T6	10		T8	27		T166	46
auto[0]	values[6]	values[5]	398	1			T27	62		T136	4		T67	40
auto[0]	values[6]	values[6]	475	1			T37	52		T38	20		T192	12
auto[0]	values[6]	values[7]	235	1			T15	18		T119	6		T167	19
auto[0]	values[7]	values[0]	663	1			T36	19		T177	29		T193	18
auto[0]	values[7]	values[1]	523	1			T5	23		T27	68		T13	24
auto[0]	values[7]	values[2]	517	1			T13	79		T194	69		T15	101
auto[0]	values[7]	values[3]	436	1			T2	20		T14	20		T37	45
auto[0]	values[7]	values[4]	319	1			T5	25		T14	20		T15	65
auto[0]	values[7]	values[5]	255	1			T2	23		T33	73		T67	24
auto[0]	values[7]	values[6]	635	1			T36	24		T67	112		T195	24
auto[0]	values[7]	values[7]	218	1			T27	20		T196	16		T171	20
auto[1]	values[0]	values[0]	18	1			T8	1		T14	1		T33	3
auto[1]	values[0]	values[1]	15	1			T161	4		T197	1		T148	1
auto[1]	values[0]	values[2]	3	1			T198	1		T125	1		T199	1
auto[1]	values[0]	values[3]	10	1			T5	1		T36	1		T33	1
auto[1]	values[0]	values[4]	8	1			T160	5		T42	1		T125	1
auto[1]	values[0]	values[5]	7	1			T37	3		T38	1		T148	1
auto[1]	values[0]	values[6]	15	1			T37	4		T166	1		T200	1
auto[1]	values[0]	values[7]	10	1			T33	2		T201	4		T202	1
auto[1]	values[1]	values[0]	7	1			T37	2		T203	4		T204	1
auto[1]	values[1]	values[1]	13	1			T5	1		T189	1		T205	3
auto[1]	values[1]	values[2]	3	1			T166	2		T206	1		-	-
auto[1]	values[1]	values[3]	7	1			T14	2		T182	1		T197	1
auto[1]	values[1]	values[4]	2	1			T154	1		T207	1		-	-
auto[1]	values[1]	values[5]	15	1			T167	1		T168	1		T208	2
auto[1]	values[1]	values[6]	11	1			T14	3		T33	1		T176	1
auto[1]	values[1]	values[7]	3	1			T182	1		T209	1		T210	1
auto[1]	values[2]	values[0]	17	1			T8	3		T14	2		T154	1
auto[1]	values[2]	values[1]	7	1			T37	2		T211	1		T206	1
auto[1]	values[2]	values[2]	8	1			T15	1		T212	2		T211	1
auto[1]	values[2]	values[3]	9	1			T197	1		T213	2		T214	2
auto[1]	values[2]	values[4]	15	1			T155	1		T143	2		T215	1
auto[1]	values[2]	values[5]	1	1			T216	1		-	-		-	-
auto[1]	values[2]	values[6]	15	1			T67	2		T217	5		T160	2
auto[1]	values[2]	values[7]	14	1			T8	2		T14	2		T174	2
auto[1]	values[3]	values[0]	11	1			T14	1		T37	1		T67	2
auto[1]	values[3]	values[1]	6	1			T33	1		T182	2		T218	3
auto[1]	values[3]	values[2]	4	1			T219	4		-	-		-	-
auto[1]	values[3]	values[3]	15	1			T13	1		T14	2		T167	1
auto[1]	values[3]	values[4]	9	1			T41	2		T189	4		T29	1
auto[1]	values[3]	values[5]	16	1			T37	1		T67	1		T154	2
auto[1]	values[3]	values[6]	10	1			T20	2		T41	1		T155	1
auto[1]	values[3]	values[7]	10	1			T41	2		T220	2		T148	1
auto[1]	values[4]	values[0]	21	1			T56	1		T67	2		T167	2
auto[1]	values[4]	values[1]	19	1			T67	4		T215	1		T148	2
auto[1]	values[4]	values[2]	10	1			T179	4		T167	1		T207	1
auto[1]	values[4]	values[3]	13	1			T148	1		T214	2		T221	6
auto[1]	values[4]	values[4]	18	1			T15	1		T155	4		T181	3
auto[1]	values[4]	values[5]	6	1			T177	1		T202	1		T222	2
auto[1]	values[4]	values[6]	20	1			T67	4		T20	2		T223	2
auto[1]	values[4]	values[7]	10	1			T14	5		T211	2		T197	1
auto[1]	values[5]	values[0]	12	1			T2	2		T8	2		T15	3
auto[1]	values[5]	values[1]	1	1			T56	1		-	-		-	-
auto[1]	values[5]	values[2]	11	1			T13	1		T166	4		T208	2
auto[1]	values[5]	values[3]	11	1			T38	2		T212	1		T189	1
auto[1]	values[5]	values[4]	17	1			T177	4		T160	1		T215	1
auto[1]	values[5]	values[5]	15	1			T38	4		T187	4		T189	1
auto[1]	values[5]	values[6]	5	1			T224	4		T225	1		-	-
auto[1]	values[5]	values[7]	5	1			T226	1		T29	1		T126	1
auto[1]	values[6]	values[0]	20	1			T15	1		T187	4		T215	3
auto[1]	values[6]	values[1]	9	1			T227	4		T199	1		T228	4
auto[1]	values[6]	values[2]	11	1			T167	3		T160	1		T143	3
auto[1]	values[6]	values[4]	21	1			T166	4		T211	1		T213	3
auto[1]	values[6]	values[5]	9	1			T67	3		T143	3		T126	1
auto[1]	values[6]	values[6]	12	1			T121	2		T201	4		T229	4
auto[1]	values[6]	values[7]	11	1			T15	2		T167	1		T29	6
auto[1]	values[7]	values[0]	22	1			T36	1		T41	4		T160	3
auto[1]	values[7]	values[1]	17	1			T5	1		T27	2		T13	1
auto[1]	values[7]	values[2]	12	1			T15	2		T20	2		T42	1
auto[1]	values[7]	values[3]	9	1			T42	2		T230	1		T231	6
auto[1]	values[7]	values[4]	9	1			T5	1		T15	5		T171	1
auto[1]	values[7]	values[5]	4	1			T2	1		T41	2		T232	1
auto[1]	values[7]	values[6]	13	1			T36	2		T67	3		T182	2
auto[1]	values[7]	values[7]	10	1			T160	2		T126	4		T233	4