Group : spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg
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Group : spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_prev_wr_en 2 0 2 100.00 100 1 1 2
cp_wr_en 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 4 0 4 100.00 100 1 1 0


Summary for Variable cp_prev_wr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_prev_wr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2002 1 T2 11 T4 13 T5 8
auto[1] 660 1 T2 2 T4 6 T5 1


Summary for Variable cp_wr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_wr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1298 1 T2 5 T4 9 T5 7
auto[1] 1364 1 T2 8 T4 10 T5 2


Summary for Cross cr_all

Samples crossed: cp_wr_en cp_prev_wr_en
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_wr_en   cp_prev_wr_en   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] 1003 1 T2 5 T4 7 T5 6
auto[0] auto[1] 295 1 T4 2 T5 1 T8 2
auto[1] auto[0] 999 1 T2 6 T4 6 T5 2
auto[1] auto[1] 365 1 T2 2 T4 4 T8 1