Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1756

1

T2

9

T5

21

T8

18

auto[1]

1719

1

T1

2

T2

10

T5

16

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1812

1

T1

2

T2

16

T5

35

auto[1]

1663

1

T2

3

T5

2

T8

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2776

1

T2

16

T5

22

T8

17

auto[1]

699

1

T1

2

T2

3

T5

15

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	664	1			T2	6		T5	5		T8	5
valid[1]	714	1			T2	3		T5	7		T8	4
valid[2]	689	1			T1	1		T2	2		T5	5
valid[3]	681	1			T1	1		T2	4		T5	9
valid[4]	727	1			T2	4		T5	11		T8	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	101	1			T2	3		T5	2		T9	2
auto[0]	auto[0]	valid[0]	auto[1]	167	1			T8	2		T11	1		T26	2
auto[0]	auto[0]	valid[1]	auto[0]	108	1			T5	4		T27	1		T40	1
auto[0]	auto[0]	valid[1]	auto[1]	160	1			T2	1		T8	2		T25	2
auto[0]	auto[0]	valid[2]	auto[0]	106	1			T2	1		T8	3		T24	1
auto[0]	auto[0]	valid[2]	auto[1]	167	1			T8	1		T11	1		T25	2
auto[0]	auto[0]	valid[3]	auto[0]	94	1			T8	1		T9	2		T26	1
auto[0]	auto[0]	valid[3]	auto[1]	175	1			T8	2		T11	1		T73	1
auto[0]	auto[0]	valid[4]	auto[0]	134	1			T2	1		T5	6		T8	1
auto[0]	auto[0]	valid[4]	auto[1]	180	1			T2	1		T5	1		T8	1
auto[0]	auto[1]	valid[0]	auto[0]	99	1			T2	2		T5	2		T9	2
auto[0]	auto[1]	valid[0]	auto[1]	166	1			T5	1		T8	1		T73	1
auto[0]	auto[1]	valid[1]	auto[0]	134	1			T2	2		T5	1		T26	1
auto[0]	auto[1]	valid[1]	auto[1]	170	1			T8	1		T25	1		T26	1
auto[0]	auto[1]	valid[2]	auto[0]	105	1			T40	3		T73	2		T13	3
auto[0]	auto[1]	valid[2]	auto[1]	159	1			T2	1		T11	1		T26	1
auto[0]	auto[1]	valid[3]	auto[0]	113	1			T2	3		T5	3		T9	2
auto[0]	auto[1]	valid[3]	auto[1]	153	1			T27	1		T72	1		T74	1
auto[0]	auto[1]	valid[4]	auto[0]	119	1			T2	1		T5	2		T8	2
auto[0]	auto[1]	valid[4]	auto[1]	166	1			T25	1		T72	1		T74	2
auto[1]	auto[0]	valid[0]	auto[0]	73	1			T8	2		T9	2		T11	1
auto[1]	auto[0]	valid[1]	auto[0]	73	1			T8	1		T73	2		T13	1
auto[1]	auto[0]	valid[2]	auto[0]	79	1			T5	3		T8	1		T9	1
auto[1]	auto[0]	valid[3]	auto[0]	79	1			T2	1		T5	4		T73	2
auto[1]	auto[0]	valid[4]	auto[0]	60	1			T2	1		T5	1		T8	1
auto[1]	auto[1]	valid[0]	auto[0]	58	1			T2	1		T9	1		T26	1
auto[1]	auto[1]	valid[1]	auto[0]	69	1			T5	2		T11	1		T26	1
auto[1]	auto[1]	valid[2]	auto[0]	73	1			T1	1		T5	2		T8	1
auto[1]	auto[1]	valid[3]	auto[0]	67	1			T1	1		T5	2		T73	1
auto[1]	auto[1]	valid[4]	auto[0]	68	1			T5	1		T40	1		T13	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal