Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	732	1			T13	7		T14	10		T15	7
all_values[1]	732	1			T13	7		T14	10		T15	7
all_values[2]	732	1			T13	7		T14	10		T15	7
all_values[3]	732	1			T13	7		T14	10		T15	7
all_values[4]	732	1			T13	7		T14	10		T15	7
all_values[5]	732	1			T13	7		T14	10		T15	7
all_values[6]	732	1			T13	7		T14	10		T15	7
all_values[7]	732	1			T13	7		T14	10		T15	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3206

1

T13

31

T14

50

T15

28

auto[1]

2650

1

T13

25

T14

30

T15

28

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2302

1

T13

28

T14

25

T15

29

auto[1]

3554

1

T13

28

T14

55

T15

27

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3357

1

T13

35

T14

38

T15

38

auto[1]

2499

1

T13

21

T14

42

T15

18

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	138	1			T13	2		T14	2		T15	6
all_values[0]	auto[0]	auto[0]	auto[1]	89	1			T14	1		T56	1		T154	1
all_values[0]	auto[0]	auto[1]	auto[0]	104	1			T13	3		T15	1		T56	2
all_values[0]	auto[0]	auto[1]	auto[1]	72	1			T13	1		T14	1		T17	2
all_values[0]	auto[1]	auto[0]	auto[1]	178	1			T14	1		T56	2		T17	2
all_values[0]	auto[1]	auto[1]	auto[1]	151	1			T13	1		T14	5		T56	5
all_values[1]	auto[0]	auto[0]	auto[0]	149	1			T13	2		T56	4		T17	3
all_values[1]	auto[0]	auto[0]	auto[1]	93	1			T13	1		T14	3		T15	2
all_values[1]	auto[0]	auto[1]	auto[0]	87	1			T13	2		T15	1		T56	3
all_values[1]	auto[0]	auto[1]	auto[1]	64	1			T14	1		T15	2		T56	1
all_values[1]	auto[1]	auto[0]	auto[1]	206	1			T14	4		T15	2		T56	3
all_values[1]	auto[1]	auto[1]	auto[1]	133	1			T13	2		T14	2		T154	1
all_values[2]	auto[0]	auto[0]	auto[0]	150	1			T13	3		T14	1		T15	2
all_values[2]	auto[0]	auto[0]	auto[1]	66	1			T14	1		T56	2		T17	1
all_values[2]	auto[0]	auto[1]	auto[0]	150	1			T13	1		T14	3		T15	4
all_values[2]	auto[0]	auto[1]	auto[1]	67	1			T56	1		T154	1		T155	1
all_values[2]	auto[1]	auto[0]	auto[1]	171	1			T13	2		T14	4		T56	4
all_values[2]	auto[1]	auto[1]	auto[1]	128	1			T13	1		T14	1		T15	1
all_values[3]	auto[0]	auto[0]	auto[0]	153	1			T13	1		T14	5		T15	1
all_values[3]	auto[0]	auto[0]	auto[1]	74	1			T13	2		T15	1		T56	1
all_values[3]	auto[0]	auto[1]	auto[0]	140	1			T14	1		T15	1		T56	7
all_values[3]	auto[0]	auto[1]	auto[1]	66	1			T13	1		T14	1		T17	2
all_values[3]	auto[1]	auto[0]	auto[1]	162	1			T13	2		T14	2		T15	3
all_values[3]	auto[1]	auto[1]	auto[1]	137	1			T13	1		T14	1		T15	1
all_values[4]	auto[0]	auto[0]	auto[0]	149	1			T13	3		T14	3		T15	1
all_values[4]	auto[0]	auto[0]	auto[1]	80	1			T14	1		T15	1		T56	1
all_values[4]	auto[0]	auto[1]	auto[0]	118	1			T13	1		T56	1		T154	1
all_values[4]	auto[0]	auto[1]	auto[1]	76	1			T15	3		T17	2		T154	1
all_values[4]	auto[1]	auto[0]	auto[1]	166	1			T13	3		T14	6		T56	2
all_values[4]	auto[1]	auto[1]	auto[1]	143	1			T15	2		T56	3		T17	1
all_values[5]	auto[0]	auto[0]	auto[0]	222	1			T13	1		T14	1		T15	2
all_values[5]	auto[0]	auto[1]	auto[0]	192	1			T13	2		T14	4		T15	4
all_values[5]	auto[1]	auto[0]	auto[1]	170	1			T13	2		T14	2		T15	1
all_values[5]	auto[1]	auto[1]	auto[1]	148	1			T13	2		T14	3		T56	3
all_values[6]	auto[0]	auto[0]	auto[0]	151	1			T13	2		T14	1		T15	1
all_values[6]	auto[0]	auto[0]	auto[1]	73	1			T14	1		T17	1		T154	1
all_values[6]	auto[0]	auto[1]	auto[0]	141	1			T13	3		T14	2		T15	1
all_values[6]	auto[0]	auto[1]	auto[1]	69	1			T56	2		T154	1		T19	2
all_values[6]	auto[1]	auto[0]	auto[1]	158	1			T14	6		T15	3		T56	1
all_values[6]	auto[1]	auto[1]	auto[1]	140	1			T13	2		T15	2		T56	5
all_values[7]	auto[0]	auto[0]	auto[0]	154	1			T13	1		T14	1		T15	2
all_values[7]	auto[0]	auto[0]	auto[1]	83	1			T13	2		T14	1		T56	3
all_values[7]	auto[0]	auto[1]	auto[0]	104	1			T13	1		T14	1		T15	2
all_values[7]	auto[0]	auto[1]	auto[1]	83	1			T14	2		T56	1		T17	1
all_values[7]	auto[1]	auto[0]	auto[1]	171	1			T13	2		T14	3		T56	6
all_values[7]	auto[1]	auto[1]	auto[1]	137	1			T13	1		T14	2		T15	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal