Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45999

1

T1

81

T2

329

T5

725

auto[1]

16658

1

T2

51

T5

86

T8

74

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45712

1

T1

51

T2

239

T5

543

auto[1]

16945

1

T1

30

T2

141

T5

268

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32257	1			T1	43		T2	215		T5	382
others[1]	5214	1			T1	4		T2	25		T5	76
others[2]	5273	1			T1	5		T2	48		T5	78
others[3]	5949	1			T1	10		T2	33		T5	79
interest[1]	3455	1			T1	6		T2	16		T5	49
interest[4]	21092	1			T1	27		T2	138		T5	257
interest[64]	10509	1			T1	13		T2	43		T5	147

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14827	1			T1	28		T2	102		T5	214
auto[0]	auto[0]	others[1]	2404	1			T1	4		T2	15		T5	44
auto[0]	auto[0]	others[2]	2460	1			T1	3		T2	23		T5	47
auto[0]	auto[0]	others[3]	2757	1			T1	4		T2	18		T5	42
auto[0]	auto[0]	interest[1]	1617	1			T1	4		T2	8		T5	31
auto[0]	auto[0]	interest[4]	9611	1			T1	18		T2	65		T5	145
auto[0]	auto[0]	interest[64]	4989	1			T1	8		T2	22		T5	79
auto[0]	auto[1]	others[0]	8691	1			T2	29		T5	39		T8	38
auto[0]	auto[1]	others[1]	1381	1			T2	5		T5	5		T8	3
auto[0]	auto[1]	others[2]	1383	1			T2	5		T5	10		T8	11
auto[0]	auto[1]	others[3]	1580	1			T2	3		T5	11		T8	4
auto[0]	auto[1]	interest[1]	919	1			T2	3		T5	4		T8	6
auto[0]	auto[1]	interest[4]	5752	1			T2	15		T5	23		T8	21
auto[0]	auto[1]	interest[64]	2704	1			T2	6		T5	17		T8	12
auto[1]	auto[0]	others[0]	8739	1			T1	15		T2	84		T5	129
auto[1]	auto[0]	others[1]	1429	1			T2	5		T5	27		T8	17
auto[1]	auto[0]	others[2]	1430	1			T1	2		T2	20		T5	21
auto[1]	auto[0]	others[3]	1612	1			T1	6		T2	12		T5	26
auto[1]	auto[0]	interest[1]	919	1			T1	2		T2	5		T5	14
auto[1]	auto[0]	interest[4]	5729	1			T1	9		T2	58		T5	89
auto[1]	auto[0]	interest[64]	2816	1			T1	5		T2	15		T5	51

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal