Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2547793	1			T1	1		T2	1		T4	4
all_values[1]	2547793	1			T1	1		T2	1		T4	4
all_values[2]	2547793	1			T1	1		T2	1		T4	4
all_values[3]	2547793	1			T1	1		T2	1		T4	4
all_values[4]	2547793	1			T1	1		T2	1		T4	4
all_values[5]	2547793	1			T1	1		T2	1		T4	4
all_values[6]	2547793	1			T1	1		T2	1		T4	4
all_values[7]	2547793	1			T1	1		T2	1		T4	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19859380

1

T1

8

T2

8

T4

32

auto[1]

522964

1

T14

45

T15

90

T16

103

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20355887

1

T1

8

T2

8

T4

32

auto[1]

26457

1

T7

142

T11

17

T25

6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2474466	1			T1	1		T2	1		T4	4
all_values[0]	auto[0]	auto[1]	12340	1			T7	83		T11	17		T25	6
all_values[0]	auto[1]	auto[0]	60167	1			T14	2		T15	9		T16	9
all_values[0]	auto[1]	auto[1]	820	1			T14	3		T15	4		T16	4
all_values[1]	auto[0]	auto[0]	2487755	1			T1	1		T2	1		T4	4
all_values[1]	auto[0]	auto[1]	8033	1			T7	36		T26	123		T13	428
all_values[1]	auto[1]	auto[0]	51604	1			T14	5		T15	9		T16	4
all_values[1]	auto[1]	auto[1]	401	1			T14	1		T15	2		T16	9
all_values[2]	auto[0]	auto[0]	2500926	1			T1	1		T2	1		T4	4
all_values[2]	auto[0]	auto[1]	2673	1			T7	23		T26	19		T13	114
all_values[2]	auto[1]	auto[0]	43943	1			T14	3		T15	7		T16	7
all_values[2]	auto[1]	auto[1]	251	1			T14	1		T15	5		T16	2
all_values[3]	auto[0]	auto[0]	2424417	1			T1	1		T2	1		T4	4
all_values[3]	auto[0]	auto[1]	182	1			T15	5		T16	5		T18	7
all_values[3]	auto[1]	auto[0]	122978	1			T14	5		T15	2		T16	5
all_values[3]	auto[1]	auto[1]	216	1			T14	2		T15	5		T16	6
all_values[4]	auto[0]	auto[0]	2514691	1			T1	1		T2	1		T4	4
all_values[4]	auto[0]	auto[1]	187	1			T38	2		T14	5		T16	3
all_values[4]	auto[1]	auto[0]	32710	1			T14	3		T15	13		T16	9
all_values[4]	auto[1]	auto[1]	205	1			T14	2		T15	1		T16	8
all_values[5]	auto[0]	auto[0]	2451504	1			T1	1		T2	1		T4	4
all_values[5]	auto[0]	auto[1]	196	1			T14	2		T15	2		T16	3
all_values[5]	auto[1]	auto[0]	95930	1			T14	5		T15	8		T16	7
all_values[5]	auto[1]	auto[1]	163	1			T14	1		T15	3		T16	4
all_values[6]	auto[0]	auto[0]	2500495	1			T1	1		T2	1		T4	4
all_values[6]	auto[0]	auto[1]	216	1			T14	3		T15	4		T16	2
all_values[6]	auto[1]	auto[0]	46910	1			T14	1		T15	7		T16	13
all_values[6]	auto[1]	auto[1]	172	1			T14	5		T15	4		T16	3
all_values[7]	auto[0]	auto[0]	2481107	1			T1	1		T2	1		T4	4
all_values[7]	auto[0]	auto[1]	192	1			T14	1		T15	6		T16	6
all_values[7]	auto[1]	auto[0]	66284	1			T14	3		T15	6		T16	10
all_values[7]	auto[1]	auto[1]	210	1			T14	3		T15	5		T16	3