Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	31294	1			T1	2		T6	6		T7	86
auto[SpiFlashAddrCfg]	6209	1			T1	6		T4	5		T7	38
auto[SpiFlashAddr3b]	7807	1			T1	2		T4	1		T5	2
auto[SpiFlashAddr4b]	6118	1			T1	4		T7	39		T10	43

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29172

1

T4

6

T5

2

T6

6

auto[1]

22256

1

T1

14

T7

95

T10

223

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27845

1

T1

10

T4

2

T6

6

auto[1]

23583

1

T1

4

T4

4

T5

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	35214	1			T1	2		T6	6		T7	119
values[1]	928	1			T7	6		T10	5		T11	2
values[2]	1151	1			T7	7		T10	2		T24	1
values[3]	1142	1			T7	4		T10	6		T23	2
values[4]	1150	1			T4	1		T7	2		T10	13
values[5]	1208	1			T1	2		T7	7		T10	7
values[6]	1175	1			T4	5		T7	10		T10	2
values[7]	1294	1			T7	9		T10	13		T11	1
values[8]	8166	1			T1	10		T5	2		T7	36

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25715

1

T1

14

T5

2

T6

6

auto[1]

25713

1

T4

6

T7

200

T11

24

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

48698

1

T1

14

T4

6

T5

2

write

2730

1

T7

22

T10

22

T11

1

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16018

1

T1

8

T4

6

T5

2

valids[0x1]

35410

1

T1

6

T6

4

T7

110

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1342	1			T1	2		T6	4		T7	5
internal_process_ops[0x5a]	1275	1			T7	3		T10	6		T24	3
internal_process_ops[0x05]	19699	1			T7	27		T10	299		T11	5
internal_process_ops[0x35]	1215	1			T7	6		T10	9		T24	2
internal_process_ops[0x15]	1332	1			T7	5		T10	8		T24	6
internal_process_ops[0x03]	808	1			T1	2		T7	1		T10	5
internal_process_ops[0x0b]	855	1			T7	1		T10	7		T23	6
internal_process_ops[0x3b]	922	1			T1	2		T4	1		T5	2
internal_process_ops[0x6b]	890	1			T1	2		T4	1		T7	4
internal_process_ops[0xbb]	862	1			T4	4		T10	8		T23	4
internal_process_ops[0xeb]	874	1			T10	6		T24	1		T26	9

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50135

1

T1

14

T4

6

T5

2

auto[1]

1293

1

T7

7

T10

16

T24

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49449

1

T1

14

T4

6

T5

2

auto[1]

1979

1

T7

16

T10

16

T11

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9550

1

T6

6

T8

12

T9

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5044

1

T1

2

T10

134

T25

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1626

1

T10

17

T23

2

T25

3

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1368

1

T1

6

T10

27

T25

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2057

1

T5

2

T9

2

T10

24

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1780

1

T1

2

T10

26

T25

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1630

1

T10

15

T26

16

T37

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1389

1

T1

4

T10

25

T26

17

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

84

1

T13

3

T41

2

T43

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

83

1

T10

2

T13

8

T15

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

47

1

T10

1

T26

2

T13

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

93

1

T10

1

T13

5

T40

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

112

1

T10

1

T13

2

T85

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

59

1

T10

2

T26

1

T43

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

64

1

T13

2

T44

1

T46

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

84

1

T10

6

T25

2

T26

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

116

1

T10

2

T26

4

T13

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

71

1

T10

3

T13

1

T40

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

57

1

T10

1

T26

1

T13

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

84

1

T40

1

T41

3

T42

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

97

1

T26

1

T13

3

T85

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

53

1

T10

1

T13

4

T40

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

67

1

T10

1

T13

8

T41

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

100

1

T10

1

T26

2

T13

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8608

1

T7

57

T11

5

T24

51

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7420

1

T7

28

T11

8

T24

128

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1319

1

T4

5

T7

9

T11

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1201

1

T7

24

T11

1

T24

10

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1734

1

T4

1

T7

12

T22

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1531

1

T7

15

T11

4

T24

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1261

1

T7

18

T11

3

T24

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1180

1

T7

15

T24

1

T13

15

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

111

1

T7

1

T29

2

T152

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

70

1

T29

2

T76

2

T17

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

85

1

T153

1

T154

2

T155

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

99

1

T156

1

T155

2

T20

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

95

1

T7

1

T24

4

T36

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

82

1

T7

2

T24

2

T14

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

107

1

T7

1

T13

4

T36

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

92

1

T7

1

T13

1

T29

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

109

1

T7

4

T24

3

T29

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

88

1

T7

1

T154

1

T157

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

90

1

T7

3

T24

1

T13

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

90

1

T7

2

T29

3

T36

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

96

1

T11

1

T158

2

T159

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

61

1

T29

1

T36

4

T14

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

100

1

T7

5

T13

2

T36

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

84

1

T7

1

T14

3

T152

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3040	1			T6	2		T8	12		T9	2
auto[0]	values[0]	valids[0x1]	13834	1			T1	2		T6	4		T9	2
auto[0]	values[1]	valids[0x1]	413	1			T10	5		T26	4		T13	16
auto[0]	values[2]	valids[0x0]	409	1			T10	2		T26	8		T13	12
auto[0]	values[2]	valids[0x1]	215	1			T26	2		T13	6		T41	7
auto[0]	values[3]	valids[0x0]	413	1			T10	4		T23	2		T26	8
auto[0]	values[3]	valids[0x1]	260	1			T10	2		T26	3		T13	1
auto[0]	values[4]	valids[0x0]	408	1			T10	10		T26	11		T13	5
auto[0]	values[4]	valids[0x1]	242	1			T10	3		T23	6		T26	2
auto[0]	values[5]	valids[0x0]	399	1			T1	2		T10	6		T26	6
auto[0]	values[5]	valids[0x1]	230	1			T10	1		T26	4		T37	2
auto[0]	values[6]	valids[0x0]	410	1			T10	2		T26	10		T13	15
auto[0]	values[6]	valids[0x1]	217	1			T26	4		T13	2		T41	2
auto[0]	values[7]	valids[0x0]	449	1			T10	11		T26	11		T37	4
auto[0]	values[7]	valids[0x1]	197	1			T10	2		T26	1		T13	6
auto[0]	values[8]	valids[0x0]	2887	1			T1	6		T5	2		T10	36
auto[0]	values[8]	valids[0x1]	1692	1			T1	4		T10	24		T25	3
auto[1]	values[0]	valids[0x0]	3483	1			T7	42		T11	6		T24	20
auto[1]	values[0]	valids[0x1]	14857	1			T7	77		T11	6		T24	174
auto[1]	values[1]	valids[0x1]	515	1			T7	6		T11	2		T13	10
auto[1]	values[2]	valids[0x0]	319	1			T7	7		T24	1		T13	3
auto[1]	values[2]	valids[0x1]	208	1			T38	6		T13	3		T29	2
auto[1]	values[3]	valids[0x0]	298	1			T7	4		T24	6		T38	2
auto[1]	values[3]	valids[0x1]	171	1			T24	3		T29	3		T36	2
auto[1]	values[4]	valids[0x0]	278	1			T4	1		T13	4		T29	4
auto[1]	values[4]	valids[0x1]	222	1			T7	2		T29	3		T14	2
auto[1]	values[5]	valids[0x0]	368	1			T7	3		T22	1		T24	1
auto[1]	values[5]	valids[0x1]	211	1			T7	4		T11	4		T29	8
auto[1]	values[6]	valids[0x0]	345	1			T4	5		T7	8		T29	9
auto[1]	values[6]	valids[0x1]	203	1			T7	2		T24	1		T13	2
auto[1]	values[7]	valids[0x0]	424	1			T7	4		T24	4		T38	3
auto[1]	values[7]	valids[0x1]	224	1			T7	5		T11	1		T13	3
auto[1]	values[8]	valids[0x0]	2088	1			T7	22		T11	3		T24	8
auto[1]	values[8]	valids[0x1]	1499	1			T7	14		T11	2		T24	7