Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2929276

1

T1

1

T4

609

T5

714

auto[1]

18331

1

T7

20

T10

288

T11

4

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

949329

1

T1

1

T4

609

T5

714

auto[1]

1998278

1

T7

7627

T10

26095

T11

260

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	576825	1			T1	1		T4	356		T5	711
auto[524288:1048575]	360706	1			T4	6		T7	661		T8	3
auto[1048576:1572863]	357273	1			T7	269		T10	1931		T23	6002
auto[1572864:2097151]	349721	1			T4	36		T7	1975		T10	2679
auto[2097152:2621439]	362018	1			T7	3		T8	5		T10	554
auto[2621440:3145727]	313457	1			T7	136		T8	8		T10	8722
auto[3145728:3670015]	320528	1			T4	211		T5	3		T7	2519
auto[3670016:4194303]	307079	1			T7	6		T8	6		T10	8267

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2016544

1

T1

1

T4

16

T5

3

auto[1]

931063

1

T4

593

T5

711

T8

9

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2571006

1

T1

1

T4

609

T5

714

auto[1]

376601

1

T7

260

T8

2

T10

1286

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	225444	1			T1	1		T4	356		T5	711
auto[0]	auto[0]	auto[0:524287]	auto[1]	286760	1			T7	2104		T10	3315		T24	4004
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	92295	1			T4	6		T7	4		T8	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	220679	1			T7	655		T10	389		T11	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	126797	1			T7	4		T10	10		T23	6002
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	175204	1			T7	2		T10	1878		T26	3692
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	85653	1			T4	36		T7	7		T10	9
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	213682	1			T7	1965		T10	2576		T26	5893
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	126305	1			T7	1		T8	5		T10	10
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	187890	1			T7	1		T10	513		T25	256
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	99684	1			T7	4		T8	7		T10	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	181612	1			T7	130		T10	7970		T26	512
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	100729	1			T4	211		T5	3		T7	8
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	188582	1			T7	2508		T26	4364		T13	1158
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	78261	1			T7	4		T8	5		T10	9
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	167277	1			T7	1		T10	7957		T26	2829
auto[0]	auto[1]	auto[0:524287]	auto[0]	328	1			T7	1		T10	1		T11	5
auto[0]	auto[1]	auto[0:524287]	auto[1]	61353	1			T10	256		T11	1		T26	5723
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	317	1			T11	1		T24	1		T25	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	45139	1			T11	256		T25	2993		T26	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	6158	1			T7	2		T13	5		T29	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	46719	1			T7	257		T13	512		T29	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	617	1			T29	2		T36	3		T40	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	47780	1			T29	512		T41	1		T220	517
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	3243	1			T10	1		T24	1		T26	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	42430	1			T10	1		T24	256		T26	574
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	251	1			T8	1		T10	4		T24	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	29644	1			T10	704		T24	6		T13	129
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	551	1			T10	2		T24	1		T13	13
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	28566	1			T13	258		T36	256		T220	128
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	713	1			T8	1		T10	5		T24	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	58613	1			T10	264		T24	2		T13	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	268	1			T7	2		T10	1		T24	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	2211	1			T7	2		T10	4		T24	27
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	198	1			T7	2		T10	2		T11	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1668	1			T10	45		T24	26		T26	26
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	178	1			T7	2		T10	2		T26	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1523	1			T7	2		T10	41		T26	11
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	161	1			T7	3		T10	3		T26	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1365	1			T10	91		T26	5		T36	37
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	170	1			T7	1		T10	1		T26	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1358	1			T10	5		T26	4		T13	24
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	182	1			T7	2		T10	1		T13	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1564	1			T10	16		T13	9		T41	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	184	1			T7	3		T26	2		T13	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1492	1			T26	37		T13	58		T36	60
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	180	1			T7	1		T10	3		T26	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1450	1			T10	25		T26	7		T29	4
auto[1]	auto[1]	auto[0:524287]	auto[0]	62	1			T11	1		T13	3		T44	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	399	1			T11	2		T13	2		T153	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	58	1			T25	1		T13	2		T40	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	352	1			T13	2		T41	59		T43	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	65	1			T29	1		T76	1		T202	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	629	1			T29	1		T76	1		T202	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	48	1			T41	1		T220	1		T14	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	415	1			T41	1		T14	5		T204	39
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	52	1			T10	1		T13	1		T43	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	570	1			T10	22		T13	2		T43	25
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	49	1			T10	1		T24	1		T13	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	471	1			T10	20		T24	49		T13	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	61	1			T13	2		T153	1		T155	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	363	1			T13	12		T155	4		T76	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	67	1			T10	1		T24	2		T13	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	518	1			T10	3		T24	36		T13	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1635937	1			T1	1		T4	16		T5	3
auto[0]	auto[0]	auto[1]	920917	1			T4	593		T5	711		T8	8
auto[0]	auto[1]	auto[0]	362671	1			T7	260		T8	1		T10	1237
auto[0]	auto[1]	auto[1]	9751	1			T8	1		T10	1		T24	1
auto[1]	auto[0]	auto[0]	13838	1			T7	20		T10	234		T11	1
auto[1]	auto[0]	auto[1]	314	1			T10	6		T24	2		T26	5
auto[1]	auto[1]	auto[0]	4098	1			T10	47		T11	3		T24	87
auto[1]	auto[1]	auto[1]	81	1			T10	1		T24	1		T153	1