Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15538

1

T5

2

T6

6

T8

12

auto[1]

10177

1

T1

14

T10

223

T25

8

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2926	1			T10	20		T13	159		T85	26
values[1]	3055	1			T5	2		T13	69		T41	91
values[2]	3968	1			T9	4		T10	205		T23	12
values[3]	2958	1			T6	6		T10	154		T25	22
values[4]	3532	1			T26	82		T13	143		T86	8
values[5]	3471	1			T1	14		T37	12		T13	53
values[6]	2440	1			T8	12		T10	86		T26	40
values[7]	3365	1			T10	63		T26	83		T43	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3298	1			T10	81		T23	12		T26	20
values[1]	3172	1			T6	6		T9	4		T26	60
values[2]	3202	1			T8	12		T10	21		T26	141
values[3]	3289	1			T1	14		T10	46		T26	20
values[4]	3018	1			T37	12		T13	109		T196	20
values[5]	2776	1			T5	2		T10	60		T26	43
values[6]	3679	1			T10	45		T25	22		T26	42
values[7]	3281	1			T10	275		T26	40		T13	110

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	237	1			T10	11		T179	27		T237	20
auto[0]	values[0]	values[1]	160	1			T46	10		T209	21		T208	9
auto[0]	values[0]	values[2]	248	1			T40	10		T202	11		T128	12
auto[0]	values[0]	values[3]	177	1			T13	8		T85	26		T15	16
auto[0]	values[0]	values[4]	219	1			T238	6		T202	20		T179	14
auto[0]	values[0]	values[5]	142	1			T13	10		T44	15		T184	13
auto[0]	values[0]	values[6]	287	1			T13	38		T239	4		T15	10
auto[0]	values[0]	values[7]	285	1			T13	25		T225	14		T202	88
auto[0]	values[1]	values[0]	209	1			T41	11		T240	8		T202	8
auto[0]	values[1]	values[1]	208	1			T184	25		T30	5		T224	12
auto[0]	values[1]	values[2]	169	1			T13	57		T220	20		T202	10
auto[0]	values[1]	values[3]	312	1			T41	9		T150	24		T222	62
auto[0]	values[1]	values[4]	261	1			T241	59		T208	8		T180	9
auto[0]	values[1]	values[5]	209	1			T5	2		T187	36		T199	12
auto[0]	values[1]	values[6]	99	1			T202	19		T188	9		T189	18
auto[0]	values[1]	values[7]	298	1			T104	8		T208	14		T191	14
auto[0]	values[2]	values[0]	479	1			T10	55		T23	12		T26	12
auto[0]	values[2]	values[1]	320	1			T9	4		T13	12		T43	20
auto[0]	values[2]	values[2]	313	1			T26	11		T30	14		T242	2
auto[0]	values[2]	values[3]	212	1			T243	6		T193	11		T30	11
auto[0]	values[2]	values[4]	169	1			T236	14		T185	2		T193	11
auto[0]	values[2]	values[5]	217	1			T41	74		T44	15		T244	8
auto[0]	values[2]	values[6]	487	1			T13	19		T40	16		T15	10
auto[0]	values[2]	values[7]	339	1			T10	117		T13	24		T44	12
auto[0]	values[3]	values[0]	275	1			T245	6		T202	18		T193	38
auto[0]	values[3]	values[1]	301	1			T6	6		T26	23		T13	10
auto[0]	values[3]	values[2]	160	1			T26	32		T246	4		T199	37
auto[0]	values[3]	values[3]	274	1			T10	31		T247	2		T182	12
auto[0]	values[3]	values[4]	298	1			T234	14		T248	24		T199	25
auto[0]	values[3]	values[5]	114	1			T10	6		T30	11		T197	30
auto[0]	values[3]	values[6]	207	1			T25	14		T26	9		T13	25
auto[0]	values[3]	values[7]	170	1			T10	43		T185	10		T249	10
auto[0]	values[4]	values[0]	379	1			T86	8		T208	13		T180	4
auto[0]	values[4]	values[1]	247	1			T42	10		T44	5		T17	12
auto[0]	values[4]	values[2]	280	1			T26	65		T13	18		T250	10
auto[0]	values[4]	values[3]	368	1			T13	13		T44	11		T251	2
auto[0]	values[4]	values[4]	360	1			T13	50		T41	11		T43	38
auto[0]	values[4]	values[5]	193	1			T187	27		T201	16		T181	80
auto[0]	values[4]	values[6]	307	1			T13	12		T42	15		T187	34
auto[0]	values[4]	values[7]	163	1			T180	24		T252	10		T199	10
auto[0]	values[5]	values[0]	117	1			T41	11		T105	2		T182	10
auto[0]	values[5]	values[1]	283	1			T221	11		T30	5		T199	70
auto[0]	values[5]	values[2]	244	1			T44	11		T15	16		T179	30
auto[0]	values[5]	values[3]	214	1			T41	9		T180	11		T197	13
auto[0]	values[5]	values[4]	316	1			T37	12		T13	13		T196	11
auto[0]	values[5]	values[5]	217	1			T45	14		T253	16		T184	8
auto[0]	values[5]	values[6]	251	1			T185	12		T210	13		T193	8
auto[0]	values[5]	values[7]	300	1			T13	12		T43	10		T15	12
auto[0]	values[6]	values[0]	166	1			T236	11		T202	14		T188	13
auto[0]	values[6]	values[1]	213	1			T46	9		T182	27		T254	24
auto[0]	values[6]	values[2]	196	1			T8	12		T10	11		T41	16
auto[0]	values[6]	values[3]	244	1			T13	18		T182	10		T199	13
auto[0]	values[6]	values[4]	131	1			T144	13		T224	24		T255	10
auto[0]	values[6]	values[5]	140	1			T44	7		T182	8		T184	12
auto[0]	values[6]	values[6]	283	1			T10	13		T41	15		T43	6
auto[0]	values[6]	values[7]	124	1			T10	8		T26	27		T41	11
auto[0]	values[7]	values[0]	219	1			T230	19		T256	12		T257	12
auto[0]	values[7]	values[1]	220	1			T26	9		T214	10		T185	13
auto[0]	values[7]	values[2]	188	1			T43	13		T199	11		T144	8
auto[0]	values[7]	values[3]	243	1			T26	13		T193	13		T184	16
auto[0]	values[7]	values[4]	200	1			T258	4		T182	11		T259	12
auto[0]	values[7]	values[5]	218	1			T26	35		T184	10		T30	21
auto[0]	values[7]	values[6]	442	1			T260	8		T30	20		T123	12
auto[0]	values[7]	values[7]	217	1			T10	10		T180	47		T30	13
auto[1]	values[0]	values[0]	139	1			T10	9		T179	14		T261	6
auto[1]	values[0]	values[1]	121	1			T46	19		T178	14		T208	11
auto[1]	values[0]	values[2]	136	1			T40	11		T202	9		T128	16
auto[1]	values[0]	values[3]	87	1			T13	12		T15	5		T262	22
auto[1]	values[0]	values[4]	177	1			T202	6		T179	13		T208	5
auto[1]	values[0]	values[5]	94	1			T13	10		T44	7		T184	8
auto[1]	values[0]	values[6]	242	1			T13	37		T15	10		T45	19
auto[1]	values[0]	values[7]	175	1			T13	19		T202	7		T182	4
auto[1]	values[1]	values[0]	197	1			T41	9		T202	12		T193	5
auto[1]	values[1]	values[1]	152	1			T184	33		T30	15		T224	8
auto[1]	values[1]	values[2]	134	1			T13	12		T220	21		T202	10
auto[1]	values[1]	values[3]	264	1			T41	62		T222	11		T199	40
auto[1]	values[1]	values[4]	68	1			T208	14		T180	11		T201	10
auto[1]	values[1]	values[5]	170	1			T207	18		T187	12		T199	8
auto[1]	values[1]	values[6]	120	1			T202	8		T188	11		T263	20
auto[1]	values[1]	values[7]	185	1			T208	6		T180	17		T222	16
auto[1]	values[2]	values[0]	82	1			T10	6		T26	8		T193	4
auto[1]	values[2]	values[1]	220	1			T13	9		T87	16		T43	7
auto[1]	values[2]	values[2]	243	1			T26	9		T264	10		T30	15
auto[1]	values[2]	values[3]	100	1			T193	9		T30	9		T144	13
auto[1]	values[2]	values[4]	170	1			T236	8		T185	18		T193	13
auto[1]	values[2]	values[5]	224	1			T41	6		T44	5		T179	24
auto[1]	values[2]	values[6]	223	1			T13	6		T40	4		T15	11
auto[1]	values[2]	values[7]	170	1			T10	27		T13	21		T44	8
auto[1]	values[3]	values[0]	134	1			T202	8		T193	6		T222	21
auto[1]	values[3]	values[1]	134	1			T26	17		T13	22		T40	8
auto[1]	values[3]	values[2]	88	1			T26	7		T198	12		T265	8
auto[1]	values[3]	values[3]	126	1			T10	15		T182	8		T210	6
auto[1]	values[3]	values[4]	132	1			T266	4		T199	5		T267	4
auto[1]	values[3]	values[5]	237	1			T10	54		T30	9		T197	50
auto[1]	values[3]	values[6]	177	1			T25	8		T26	33		T13	32
auto[1]	values[3]	values[7]	131	1			T10	5		T185	10		T268	6
auto[1]	values[4]	values[0]	162	1			T208	44		T180	19		T197	8
auto[1]	values[4]	values[1]	161	1			T42	13		T44	16		T17	8
auto[1]	values[4]	values[2]	261	1			T26	17		T13	8		T208	7
auto[1]	values[4]	values[3]	161	1			T13	7		T44	17		T269	20
auto[1]	values[4]	values[4]	165	1			T13	27		T41	9		T43	8
auto[1]	values[4]	values[5]	133	1			T187	12		T201	65		T181	18
auto[1]	values[4]	values[6]	131	1			T13	8		T42	8		T187	8
auto[1]	values[4]	values[7]	61	1			T180	13		T199	18		T188	8
auto[1]	values[5]	values[0]	153	1			T41	15		T270	6		T182	29
auto[1]	values[5]	values[1]	195	1			T221	15		T30	18		T199	8
auto[1]	values[5]	values[2]	110	1			T44	9		T15	6		T179	10
auto[1]	values[5]	values[3]	218	1			T1	14		T41	58		T180	9
auto[1]	values[5]	values[4]	117	1			T13	19		T196	9		T43	8
auto[1]	values[5]	values[5]	229	1			T45	6		T184	39		T201	92
auto[1]	values[5]	values[6]	148	1			T185	17		T210	11		T193	22
auto[1]	values[5]	values[7]	359	1			T13	9		T43	10		T15	8
auto[1]	values[6]	values[0]	95	1			T236	10		T202	6		T188	7
auto[1]	values[6]	values[1]	78	1			T46	11		T182	9		T199	5
auto[1]	values[6]	values[2]	118	1			T10	10		T41	6		T268	15
auto[1]	values[6]	values[3]	190	1			T13	10		T182	37		T199	7
auto[1]	values[6]	values[4]	84	1			T144	8		T224	19		T256	6
auto[1]	values[6]	values[5]	133	1			T44	13		T182	62		T184	28
auto[1]	values[6]	values[6]	142	1			T10	32		T41	7		T43	14
auto[1]	values[6]	values[7]	103	1			T10	12		T26	13		T41	10
auto[1]	values[7]	values[0]	255	1			T230	22		T256	8		T32	8
auto[1]	values[7]	values[1]	159	1			T26	11		T185	7		T182	8
auto[1]	values[7]	values[2]	314	1			T43	7		T199	15		T211	26
auto[1]	values[7]	values[3]	99	1			T26	7		T193	7		T184	4
auto[1]	values[7]	values[4]	151	1			T182	9		T187	11		T224	22
auto[1]	values[7]	values[5]	106	1			T26	8		T184	59		T30	5
auto[1]	values[7]	values[6]	133	1			T30	22		T123	8		T271	8
auto[1]	values[7]	values[7]	201	1			T10	53		T180	8		T30	9