Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2547793	1			T1	1		T2	1		T4	4
all_pins[1]	2547793	1			T1	1		T2	1		T4	4
all_pins[2]	2547793	1			T1	1		T2	1		T4	4
all_pins[3]	2547793	1			T1	1		T2	1		T4	4
all_pins[4]	2547793	1			T1	1		T2	1		T4	4
all_pins[5]	2547793	1			T1	1		T2	1		T4	4
all_pins[6]	2547793	1			T1	1		T2	1		T4	4
all_pins[7]	2547793	1			T1	1		T2	1		T4	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20331585	1			T1	8		T2	8		T4	32
values[0x1]	50759	1			T14	18		T15	29		T16	39
transitions[0x0=>0x1]	49742	1			T14	12		T15	27		T16	28
transitions[0x1=>0x0]	49750	1			T14	12		T15	27		T16	29

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2546928	1			T1	1		T2	1		T4	4
all_pins[0]	values[0x1]	865	1			T14	3		T15	4		T16	4
all_pins[0]	transitions[0x0=>0x1]	597	1			T14	2		T15	4		T16	1
all_pins[0]	transitions[0x1=>0x0]	155	1			T15	2		T16	6		T18	7
all_pins[1]	values[0x0]	2547370	1			T1	1		T2	1		T4	4
all_pins[1]	values[0x1]	423	1			T14	1		T15	2		T16	9
all_pins[1]	transitions[0x0=>0x1]	343	1			T15	1		T16	7		T20	3
all_pins[1]	transitions[0x1=>0x0]	179	1			T15	4		T18	3		T20	3
all_pins[2]	values[0x0]	2547534	1			T1	1		T2	1		T4	4
all_pins[2]	values[0x1]	259	1			T14	1		T15	5		T16	2
all_pins[2]	transitions[0x0=>0x1]	205	1			T15	4		T16	2		T18	8
all_pins[2]	transitions[0x1=>0x0]	162	1			T14	1		T15	4		T16	6
all_pins[3]	values[0x0]	2547577	1			T1	1		T2	1		T4	4
all_pins[3]	values[0x1]	216	1			T14	2		T15	5		T16	6
all_pins[3]	transitions[0x0=>0x1]	156	1			T14	1		T15	5		T16	3
all_pins[3]	transitions[0x1=>0x0]	145	1			T14	1		T15	1		T16	5
all_pins[4]	values[0x0]	2547588	1			T1	1		T2	1		T4	4
all_pins[4]	values[0x1]	205	1			T14	2		T15	1		T16	8
all_pins[4]	transitions[0x0=>0x1]	165	1			T14	2		T15	1		T16	7
all_pins[4]	transitions[0x1=>0x0]	1836	1			T14	1		T15	3		T16	3
all_pins[5]	values[0x0]	2545917	1			T1	1		T2	1		T4	4
all_pins[5]	values[0x1]	1876	1			T14	1		T15	3		T16	4
all_pins[5]	transitions[0x0=>0x1]	1457	1			T14	1		T15	3		T16	4
all_pins[5]	transitions[0x1=>0x0]	46286	1			T14	5		T15	4		T16	3
all_pins[6]	values[0x0]	2501088	1			T1	1		T2	1		T4	4
all_pins[6]	values[0x1]	46705	1			T14	5		T15	4		T16	3
all_pins[6]	transitions[0x0=>0x1]	46661	1			T14	3		T15	4		T16	3
all_pins[6]	transitions[0x1=>0x0]	166	1			T14	1		T15	5		T16	3
all_pins[7]	values[0x0]	2547583	1			T1	1		T2	1		T4	4
all_pins[7]	values[0x1]	210	1			T14	3		T15	5		T16	3
all_pins[7]	transitions[0x0=>0x1]	158	1			T14	3		T15	5		T16	1
all_pins[7]	transitions[0x1=>0x0]	821	1			T14	3		T15	4		T16	3