Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	311	1			T10	4		T25	1		T26	1
auto[ReadAddrCrossIntoMailbox]	220	1			T10	5		T26	3		T37	2
auto[ReadAddrCrossOutOfMailbox]	236	1			T10	5		T26	1		T13	12
auto[ReadAddrCrossAllMailbox]	196	1			T10	3		T26	2		T13	8
auto[ReadAddrOutsideMailbox]	2914	1			T1	6		T5	2		T10	25

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1960

1

T1

3

T5

1

T10

18

auto[1]

1917

1

T1

3

T5

1

T10

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	595	1			T1	2		T10	5		T26	11
read_ops[0x0b]	649	1			T10	7		T23	6		T26	7
read_ops[0x3b]	673	1			T1	2		T5	2		T10	8
read_ops[0x6b]	647	1			T1	2		T10	8		T25	1
read_ops[0xbb]	647	1			T10	8		T23	4		T26	8
read_ops[0xeb]	666	1			T10	6		T26	9		T37	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T13	2		T44	2		T214	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T13	1		T41	2		T44	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T26	1		T13	5		T220	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T13	2		T41	3		T30	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	12	1			T180	3		T188	1		T230	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T10	1		T40	1		T236	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T185	1		T184	1		T222	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T13	1		T41	1		T15	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	210	1			T1	1		T10	1		T26	8
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	236	1			T1	1		T10	3		T26	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T10	1		T13	1		T15	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	19	1			T10	1		T41	1		T43	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T236	1		T185	1		T180	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T13	1		T193	1		T184	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T13	3		T45	1		T236	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T26	1		T13	1		T41	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T10	1		T13	1		T258	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T10	1		T13	1		T17	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	240	1			T23	3		T26	5		T37	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	248	1			T10	3		T23	3		T26	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T10	1		T273	1		T235	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T13	1		T41	1		T43	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T10	2		T41	1		T235	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T13	1		T220	1		T235	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T10	1		T13	1		T41	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T13	1		T193	1		T187	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T13	1		T185	1		T123	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T13	1		T40	1		T41	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	253	1			T1	1		T5	1		T10	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	247	1			T1	1		T5	1		T10	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T25	1		T273	1		T185	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T26	1		T41	1		T45	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	13	1			T44	1		T236	1		T17	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	15	1			T10	1		T41	1		T43	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T13	1		T17	1		T180	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	15	1			T13	2		T43	1		T182	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T40	1		T252	1		T187	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T26	1		T13	1		T41	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	258	1			T1	1		T10	3		T26	7
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	251	1			T1	1		T10	4		T26	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T13	1		T220	1		T43	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T206	1		T180	1		T123	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T13	1		T41	1		T182	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	13	1			T10	1		T182	1		T206	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T10	1		T13	1		T43	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T10	2		T13	1		T202	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T43	1		T44	1		T235	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T13	1		T41	2		T235	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	229	1			T10	1		T23	2		T26	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	243	1			T10	3		T23	2		T26	6
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T13	1		T15	1		T179	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T10	1		T13	1		T44	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T10	1		T26	1		T37	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	12	1			T26	1		T37	1		T193	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T13	1		T43	2		T44	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	11	1			T44	1		T182	1		T193	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T26	1		T13	1		T43	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T10	1		T185	1		T252	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	266	1			T10	2		T26	2		T37	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	233	1			T10	1		T26	4		T37	1