Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2937	1			T10	46		T13	131		T40	21
values[1]	3171	1			T10	20		T26	59		T13	41
values[2]	3276	1			T5	2		T8	12		T26	99
values[3]	2913	1			T1	14		T10	82		T23	12
values[4]	3850	1			T10	124		T13	73		T247	2
values[5]	3419	1			T10	63		T26	20		T13	41
values[6]	3327	1			T6	6		T10	40		T26	63
values[7]	2822	1			T9	4		T10	153		T25	22

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3594	1			T10	65		T23	12		T26	20
values[1]	3124	1			T5	2		T10	80		T26	83
values[2]	3520	1			T6	6		T10	124		T26	99
values[3]	2700	1			T1	14		T26	40		T13	113
values[4]	3365	1			T8	12		T9	4		T10	102
values[5]	3550	1			T37	12		T13	140		T41	68
values[6]	3354	1			T26	101		T13	120		T43	66
values[7]	2508	1			T10	157		T13	55		T40	21

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25088

1

T1

14

T5

2

T6

6

auto[1]

627

1

T10

16

T25

2

T26

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	376	1			T272	19		T252	10		T274	6
auto[0]	values[0]	values[1]	336	1			T13	32		T15	26		T192	10
auto[0]	values[0]	values[2]	528	1			T202	28		T180	37		T230	121
auto[0]	values[0]	values[3]	406	1			T13	36		T45	27		T185	20
auto[0]	values[0]	values[4]	317	1			T241	59		T182	19		T208	23
auto[0]	values[0]	values[5]	339	1			T41	20		T182	39		T190	16
auto[0]	values[0]	values[6]	328	1			T13	57		T46	26		T150	24
auto[0]	values[0]	values[7]	227	1			T10	45		T40	16		T220	21
auto[0]	values[1]	values[0]	447	1			T10	20		T193	43		T184	20
auto[0]	values[1]	values[1]	245	1			T275	2		T210	19		T268	26
auto[0]	values[1]	values[2]	692	1			T26	39		T41	69		T43	20
auto[0]	values[1]	values[3]	244	1			T26	20		T13	20		T276	4
auto[0]	values[1]	values[4]	410	1			T44	21		T208	19		T199	43
auto[0]	values[1]	values[5]	552	1			T13	21		T44	18		T194	22
auto[0]	values[1]	values[6]	348	1			T15	21		T74	18		T184	36
auto[0]	values[1]	values[7]	158	1			T44	28		T15	20		T184	20
auto[0]	values[2]	values[0]	480	1			T41	64		T182	19		T210	24
auto[0]	values[2]	values[1]	321	1			T5	2		T43	20		T30	20
auto[0]	values[2]	values[2]	471	1			T26	40		T44	20		T184	55
auto[0]	values[2]	values[3]	303	1			T13	28		T182	62		T208	41
auto[0]	values[2]	values[4]	474	1			T8	12		T43	25		T17	20
auto[0]	values[2]	values[5]	429	1			T41	21		T179	41		T182	33
auto[0]	values[2]	values[6]	531	1			T26	57		T245	6		T183	16
auto[0]	values[2]	values[7]	171	1			T44	20		T199	20		T188	28
auto[0]	values[3]	values[0]	364	1			T23	12		T13	20		T236	21
auto[0]	values[3]	values[1]	308	1			T40	19		T45	20		T243	6
auto[0]	values[3]	values[2]	280	1			T196	20		T238	6		T210	19
auto[0]	values[3]	values[3]	161	1			T1	14		T26	20		T85	26
auto[0]	values[3]	values[4]	361	1			T10	77		T240	8		T222	72
auto[0]	values[3]	values[5]	531	1			T13	20		T41	25		T208	20
auto[0]	values[3]	values[6]	425	1			T26	42		T13	55		T43	20
auto[0]	values[3]	values[7]	416	1			T41	20		T42	20		T205	24
auto[0]	values[4]	values[0]	428	1			T247	2		T225	14		T264	10
auto[0]	values[4]	values[1]	506	1			T202	92		T199	20		T271	69
auto[0]	values[4]	values[2]	433	1			T10	123		T13	20		T83	22
auto[0]	values[4]	values[3]	511	1			T13	24		T104	8		T81	20
auto[0]	values[4]	values[4]	708	1			T202	46		T179	27		T184	47
auto[0]	values[4]	values[5]	383	1			T13	27		T239	4		T44	20
auto[0]	values[4]	values[6]	371	1			T193	20		T265	8		T187	65
auto[0]	values[4]	values[7]	430	1			T42	21		T43	18		T254	24
auto[0]	values[5]	values[0]	486	1			T26	20		T87	16		T198	12
auto[0]	values[5]	values[1]	298	1			T41	79		T15	20		T180	20
auto[0]	values[5]	values[2]	368	1			T270	6		T234	14		T277	14
auto[0]	values[5]	values[3]	268	1			T185	20		T184	31		T123	20
auto[0]	values[5]	values[4]	396	1			T13	20		T86	8		T180	19
auto[0]	values[5]	values[5]	503	1			T44	20		T184	66		T199	97
auto[0]	values[5]	values[6]	688	1			T43	45		T244	8		T236	20
auto[0]	values[5]	values[7]	346	1			T10	61		T13	21		T44	20
auto[0]	values[6]	values[0]	571	1			T13	20		T41	22		T246	4
auto[0]	values[6]	values[1]	499	1			T10	18		T26	63		T220	20
auto[0]	values[6]	values[2]	390	1			T6	6		T178	14		T202	17
auto[0]	values[6]	values[3]	331	1			T43	20		T193	30		T199	19
auto[0]	values[6]	values[4]	311	1			T10	20		T105	2		T210	20
auto[0]	values[6]	values[5]	406	1			T37	12		T46	20		T193	20
auto[0]	values[6]	values[6]	288	1			T209	21		T193	22		T199	20
auto[0]	values[6]	values[7]	453	1			T13	34		T41	19		T253	16
auto[0]	values[7]	values[0]	364	1			T10	43		T214	10		T208	20
auto[0]	values[7]	values[1]	528	1			T10	59		T26	19		T13	22
auto[0]	values[7]	values[2]	278	1			T26	20		T40	20		T260	8
auto[0]	values[7]	values[3]	423	1			T278	16		T248	24		T222	39
auto[0]	values[7]	values[4]	305	1			T9	4		T25	20		T26	22
auto[0]	values[7]	values[5]	320	1			T13	64		T273	10		T202	24
auto[0]	values[7]	values[6]	283	1			T179	32		T199	20		T188	19
auto[0]	values[7]	values[7]	236	1			T10	46		T206	20		T279	12
auto[1]	values[0]	values[0]	14	1			T272	1		T32	2		T280	3
auto[1]	values[0]	values[1]	15	1			T15	2		T185	1		T32	2
auto[1]	values[0]	values[2]	4	1			T230	3		T219	1		-	-
auto[1]	values[0]	values[3]	10	1			T13	4		T45	3		T268	1
auto[1]	values[0]	values[4]	5	1			T182	1		T221	1		T256	1
auto[1]	values[0]	values[5]	11	1			T190	2		T281	2		T271	1
auto[1]	values[0]	values[6]	9	1			T13	2		T46	3		T123	1
auto[1]	values[0]	values[7]	12	1			T10	1		T40	5		T179	1
auto[1]	values[1]	values[0]	12	1			T193	1		T188	3		T219	1
auto[1]	values[1]	values[1]	5	1			T210	2		T219	1		T48	1
auto[1]	values[1]	values[2]	19	1			T41	2		T180	1		T222	3
auto[1]	values[1]	values[3]	6	1			T184	1		T271	2		T282	2
auto[1]	values[1]	values[4]	13	1			T44	2		T208	1		T281	1
auto[1]	values[1]	values[5]	10	1			T44	3		T202	1		T188	1
auto[1]	values[1]	values[6]	9	1			T15	1		T184	4		T224	1
auto[1]	values[1]	values[7]	1	1			T283	1		-	-		-	-
auto[1]	values[2]	values[0]	18	1			T41	3		T182	1		T224	1
auto[1]	values[2]	values[1]	5	1			T144	1		T284	1		T285	2
auto[1]	values[2]	values[2]	17	1			T184	2		T180	2		T269	4
auto[1]	values[2]	values[3]	3	1			T208	1		T286	1		T287	1
auto[1]	values[2]	values[4]	17	1			T43	2		T197	1		T282	1
auto[1]	values[2]	values[5]	11	1			T41	1		T182	3		T187	2
auto[1]	values[2]	values[6]	22	1			T26	2		T208	2		T180	1
auto[1]	values[2]	values[7]	3	1			T288	2		T289	1		-	-
auto[1]	values[3]	values[0]	5	1			T236	1		T32	4		-	-
auto[1]	values[3]	values[1]	11	1			T40	3		T230	2		T181	2
auto[1]	values[3]	values[2]	6	1			T210	2		T290	1		T291	1
auto[1]	values[3]	values[3]	1	1			T15	1		-	-		-	-
auto[1]	values[3]	values[4]	8	1			T10	5		T218	2		T292	1
auto[1]	values[3]	values[5]	13	1			T13	4		T41	1		T281	2
auto[1]	values[3]	values[6]	10	1			T13	6		T293	2		T291	2
auto[1]	values[3]	values[7]	13	1			T42	3		T236	1		T193	1
auto[1]	values[4]	values[0]	3	1			T187	1		T230	1		T290	1
auto[1]	values[4]	values[1]	17	1			T202	3		T271	2		T292	2
auto[1]	values[4]	values[2]	7	1			T10	1		T193	1		T281	1
auto[1]	values[4]	values[3]	5	1			T13	1		T185	1		T292	1
auto[1]	values[4]	values[4]	12	1			T184	2		T262	2		T30	1
auto[1]	values[4]	values[5]	14	1			T13	1		T179	2		T197	2
auto[1]	values[4]	values[6]	7	1			T187	2		T199	1		T200	1
auto[1]	values[4]	values[7]	15	1			T42	2		T43	2		T184	3
auto[1]	values[5]	values[0]	8	1			T215	2		T224	3		T293	1
auto[1]	values[5]	values[1]	4	1			T41	1		T207	2		T231	1
auto[1]	values[5]	values[2]	3	1			T277	2		T224	1		-	-
auto[1]	values[5]	values[3]	6	1			T184	1		T123	2		T271	1
auto[1]	values[5]	values[4]	9	1			T180	1		T130	2		T286	1
auto[1]	values[5]	values[5]	7	1			T184	1		T199	1		T201	2
auto[1]	values[5]	values[6]	18	1			T43	1		T208	1		T187	2
auto[1]	values[5]	values[7]	11	1			T10	2		T182	2		T271	2
auto[1]	values[6]	values[0]	7	1			T199	1		T268	1		T294	3
auto[1]	values[6]	values[1]	12	1			T10	2		T201	2		T230	1
auto[1]	values[6]	values[2]	15	1			T202	3		T30	1		T123	4
auto[1]	values[6]	values[3]	8	1			T199	1		T218	2		T131	5
auto[1]	values[6]	values[4]	9	1			T180	2		T224	2		T261	1
auto[1]	values[6]	values[5]	9	1			T184	3		T230	1		T224	3
auto[1]	values[6]	values[6]	7	1			T268	1		T295	1		T296	3
auto[1]	values[6]	values[7]	11	1			T41	2		T185	1		T187	1
auto[1]	values[7]	values[0]	11	1			T10	2		T199	2		T271	6
auto[1]	values[7]	values[1]	14	1			T10	1		T26	1		T13	1
auto[1]	values[7]	values[2]	9	1			T297	2		T30	1		T298	2
auto[1]	values[7]	values[3]	14	1			T278	2		T222	1		T197	3
auto[1]	values[7]	values[4]	10	1			T25	2		T26	1		T13	1
auto[1]	values[7]	values[5]	12	1			T13	3		T202	2		T188	3
auto[1]	values[7]	values[6]	10	1			T179	2		T188	1		T224	3
auto[1]	values[7]	values[7]	5	1			T10	2		T280	1		T299	2