Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1908

1

T2

4

T7

8

T11

1

auto[1]

1852

1

T2

3

T7

11

T11

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2003

1

T7

19

T11

5

T25

16

auto[1]

1757

1

T2

7

T11

1

T12

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3006

1

T2

7

T7

13

T11

5

auto[1]

754

1

T7

6

T11

1

T25

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	757	1			T2	1		T11	2		T12	1
valid[1]	765	1			T2	1		T7	2		T11	1
valid[2]	738	1			T2	2		T7	4		T12	1
valid[3]	733	1			T7	7		T11	2		T12	2
valid[4]	767	1			T2	3		T7	6		T11	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	110	1			T11	1		T25	1		T13	2
auto[0]	auto[0]	valid[0]	auto[1]	190	1			T12	1		T13	1		T28	1
auto[0]	auto[0]	valid[1]	auto[0]	134	1			T7	1		T13	3		T29	3
auto[0]	auto[0]	valid[1]	auto[1]	178	1			T2	1		T13	2		T42	1
auto[0]	auto[0]	valid[2]	auto[0]	109	1			T13	3		T29	1		T42	1
auto[0]	auto[0]	valid[2]	auto[1]	170	1			T2	1		T12	1		T13	2
auto[0]	auto[0]	valid[3]	auto[0]	127	1			T7	3		T25	2		T13	2
auto[0]	auto[0]	valid[3]	auto[1]	168	1			T12	1		T26	1		T13	1
auto[0]	auto[0]	valid[4]	auto[0]	128	1			T7	1		T25	2		T13	2
auto[0]	auto[0]	valid[4]	auto[1]	183	1			T2	2		T80	1		T316	7
auto[0]	auto[1]	valid[0]	auto[0]	126	1			T11	1		T25	2		T13	2
auto[0]	auto[1]	valid[0]	auto[1]	179	1			T2	1		T13	2		T41	1
auto[0]	auto[1]	valid[1]	auto[0]	124	1			T7	1		T11	1		T25	1
auto[0]	auto[1]	valid[1]	auto[1]	177	1			T12	1		T13	2		T29	2
auto[0]	auto[1]	valid[2]	auto[0]	127	1			T7	1		T13	1		T29	2
auto[0]	auto[1]	valid[2]	auto[1]	180	1			T2	1		T28	2		T42	2
auto[0]	auto[1]	valid[3]	auto[0]	125	1			T7	3		T11	1		T25	3
auto[0]	auto[1]	valid[3]	auto[1]	179	1			T12	1		T13	2		T28	1
auto[0]	auto[1]	valid[4]	auto[0]	139	1			T7	3		T13	4		T40	2
auto[0]	auto[1]	valid[4]	auto[1]	153	1			T2	1		T11	1		T12	1
auto[1]	auto[0]	valid[0]	auto[0]	81	1			T25	1		T13	3		T29	1
auto[1]	auto[0]	valid[1]	auto[0]	86	1			T26	1		T13	1		T154	1
auto[1]	auto[0]	valid[2]	auto[0]	82	1			T7	2		T13	4		T29	3
auto[1]	auto[0]	valid[3]	auto[0]	73	1			T25	1		T13	5		T42	1
auto[1]	auto[0]	valid[4]	auto[0]	89	1			T7	1		T26	1		T13	2
auto[1]	auto[1]	valid[0]	auto[0]	71	1			T25	2		T13	1		T29	1
auto[1]	auto[1]	valid[1]	auto[0]	66	1			T13	3		T154	1		T20	1
auto[1]	auto[1]	valid[2]	auto[0]	70	1			T7	1		T44	1		T154	1
auto[1]	auto[1]	valid[3]	auto[0]	61	1			T7	1		T11	1		T25	1
auto[1]	auto[1]	valid[4]	auto[0]	75	1			T7	1		T42	1		T44	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal