Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	790	1			T14	10		T15	17		T16	21
all_values[1]	790	1			T14	10		T15	17		T16	21
all_values[2]	790	1			T14	10		T15	17		T16	21
all_values[3]	790	1			T14	10		T15	17		T16	21
all_values[4]	790	1			T14	10		T15	17		T16	21
all_values[5]	790	1			T14	10		T15	17		T16	21
all_values[6]	790	1			T14	10		T15	17		T16	21
all_values[7]	790	1			T14	10		T15	17		T16	21

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3347

1

T14

37

T15

68

T16

74

auto[1]

2973

1

T14

43

T15

68

T16

94

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2463

1

T14

37

T15

65

T16

76

auto[1]

3857

1

T14

43

T15

71

T16

92

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3582

1

T14

46

T15

80

T16

104

auto[1]

2738

1

T14

34

T15

56

T16

64

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	162	1			T15	4		T16	4		T18	7
all_values[0]	auto[0]	auto[0]	auto[1]	72	1			T14	1		T16	3		T18	2
all_values[0]	auto[0]	auto[1]	auto[0]	143	1			T14	1		T15	3		T16	6
all_values[0]	auto[0]	auto[1]	auto[1]	72	1			T14	1		T15	1		T16	1
all_values[0]	auto[1]	auto[0]	auto[1]	178	1			T14	5		T15	5		T16	3
all_values[0]	auto[1]	auto[1]	auto[1]	163	1			T14	2		T15	4		T16	4
all_values[1]	auto[0]	auto[0]	auto[0]	146	1			T14	3		T15	3		T16	5
all_values[1]	auto[0]	auto[0]	auto[1]	94	1			T15	1		T16	1		T18	1
all_values[1]	auto[0]	auto[1]	auto[0]	126	1			T14	5		T15	5		T16	2
all_values[1]	auto[0]	auto[1]	auto[1]	78	1			T16	1		T18	4		T21	2
all_values[1]	auto[1]	auto[0]	auto[1]	186	1			T14	1		T15	5		T16	2
all_values[1]	auto[1]	auto[1]	auto[1]	160	1			T14	1		T15	3		T16	10
all_values[2]	auto[0]	auto[0]	auto[0]	151	1			T14	5		T15	4		T16	5
all_values[2]	auto[0]	auto[0]	auto[1]	79	1			T16	2		T20	3		T21	1
all_values[2]	auto[0]	auto[1]	auto[0]	154	1			T14	1		T15	4		T16	5
all_values[2]	auto[0]	auto[1]	auto[1]	81	1			T15	3		T16	2		T18	3
all_values[2]	auto[1]	auto[0]	auto[1]	160	1			T14	1		T15	3		T16	6
all_values[2]	auto[1]	auto[1]	auto[1]	165	1			T14	3		T15	3		T16	1
all_values[3]	auto[0]	auto[0]	auto[0]	155	1			T14	2		T15	2		T16	3
all_values[3]	auto[0]	auto[0]	auto[1]	73	1			T15	1		T16	2		T18	4
all_values[3]	auto[0]	auto[1]	auto[0]	122	1			T14	3		T15	2		T16	5
all_values[3]	auto[0]	auto[1]	auto[1]	100	1			T14	1		T15	2		T16	3
all_values[3]	auto[1]	auto[0]	auto[1]	176	1			T14	1		T15	8		T16	3
all_values[3]	auto[1]	auto[1]	auto[1]	164	1			T14	3		T15	2		T16	5
all_values[4]	auto[0]	auto[0]	auto[0]	161	1			T15	5		T16	4		T18	6
all_values[4]	auto[0]	auto[0]	auto[1]	66	1			T14	1		T16	1		T18	1
all_values[4]	auto[0]	auto[1]	auto[0]	133	1			T14	2		T15	8		T16	4
all_values[4]	auto[0]	auto[1]	auto[1]	96	1			T16	6		T18	4		T20	2
all_values[4]	auto[1]	auto[0]	auto[1]	169	1			T14	5		T15	1		T16	1
all_values[4]	auto[1]	auto[1]	auto[1]	165	1			T14	2		T15	3		T16	5
all_values[5]	auto[0]	auto[0]	auto[0]	234	1			T14	3		T15	5		T16	8
all_values[5]	auto[0]	auto[1]	auto[0]	197	1			T14	4		T15	7		T16	6
all_values[5]	auto[1]	auto[0]	auto[1]	201	1			T14	1		T15	3		T16	3
all_values[5]	auto[1]	auto[1]	auto[1]	158	1			T14	2		T15	2		T16	4
all_values[6]	auto[0]	auto[0]	auto[0]	158	1			T15	2		T16	7		T18	1
all_values[6]	auto[0]	auto[0]	auto[1]	81	1			T14	2		T15	2		T18	2
all_values[6]	auto[0]	auto[1]	auto[0]	141	1			T14	2		T15	7		T16	4
all_values[6]	auto[0]	auto[1]	auto[1]	75	1			T14	1		T16	2		T18	7
all_values[6]	auto[1]	auto[0]	auto[1]	207	1			T14	1		T15	3		T16	1
all_values[6]	auto[1]	auto[1]	auto[1]	128	1			T14	4		T15	3		T16	7
all_values[7]	auto[0]	auto[0]	auto[0]	154	1			T14	3		T15	3		T16	3
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T14	1		T15	3		T16	2
all_values[7]	auto[0]	auto[1]	auto[0]	126	1			T14	3		T15	1		T16	5
all_values[7]	auto[0]	auto[1]	auto[1]	75	1			T14	1		T15	2		T16	2
all_values[7]	auto[1]	auto[0]	auto[1]	207	1			T14	1		T15	5		T16	5
all_values[7]	auto[1]	auto[1]	auto[1]	151	1			T14	1		T15	3		T16	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal