Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48722

1

T7

378

T11

142

T25

239

auto[1]

17968

1

T2

7

T11

30

T12

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49034

1

T2

7

T7

259

T11

119

auto[1]

17656

1

T7

119

T11

53

T25

77

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34365	1			T2	7		T7	178		T11	89
others[1]	5571	1			T7	41		T11	13		T25	25
others[2]	5631	1			T7	35		T11	8		T25	13
others[3]	6284	1			T7	37		T11	21		T25	22
interest[1]	3726	1			T7	23		T11	8		T25	17
interest[4]	22444	1			T2	7		T7	113		T11	55
interest[64]	11113	1			T7	64		T11	33		T25	44

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15834	1			T7	122		T11	52		T25	83
auto[0]	auto[0]	others[1]	2647	1			T7	26		T11	4		T25	15
auto[0]	auto[0]	others[2]	2636	1			T7	22		T11	6		T25	8
auto[0]	auto[0]	others[3]	2983	1			T7	22		T11	9		T25	15
auto[0]	auto[0]	interest[1]	1736	1			T7	17		T11	2		T25	12
auto[0]	auto[0]	interest[4]	10295	1			T7	76		T11	31		T25	53
auto[0]	auto[0]	interest[64]	5230	1			T7	50		T11	16		T25	29
auto[0]	auto[1]	others[0]	9451	1			T2	7		T11	12		T12	6
auto[0]	auto[1]	others[1]	1471	1			T11	3		T26	5		T13	12
auto[0]	auto[1]	others[2]	1486	1			T11	1		T26	4		T13	14
auto[0]	auto[1]	others[3]	1603	1			T11	4		T26	5		T13	11
auto[0]	auto[1]	interest[1]	1027	1			T11	4		T26	5		T13	11
auto[0]	auto[1]	interest[4]	6294	1			T2	7		T11	8		T12	6
auto[0]	auto[1]	interest[64]	2930	1			T11	6		T26	3		T13	37
auto[1]	auto[0]	others[0]	9080	1			T7	56		T11	25		T25	35
auto[1]	auto[0]	others[1]	1453	1			T7	15		T11	6		T25	10
auto[1]	auto[0]	others[2]	1509	1			T7	13		T11	1		T25	5
auto[1]	auto[0]	others[3]	1698	1			T7	15		T11	8		T25	7
auto[1]	auto[0]	interest[1]	963	1			T7	6		T11	2		T25	5
auto[1]	auto[0]	interest[4]	5855	1			T7	37		T11	16		T25	24
auto[1]	auto[0]	interest[64]	2953	1			T7	14		T11	11		T25	15

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal