Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.10 98.62 89.36 97.28 95.43 99.25


Total test records in report: 1101
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1012 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1196613117 Jun 22 04:39:18 PM PDT 24 Jun 22 04:39:28 PM PDT 24 3144789612 ps
T1013 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2358943138 Jun 22 04:39:24 PM PDT 24 Jun 22 04:39:26 PM PDT 24 43326316 ps
T1014 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3721218617 Jun 22 04:39:40 PM PDT 24 Jun 22 04:39:43 PM PDT 24 22986983 ps
T1015 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1325475722 Jun 22 04:39:31 PM PDT 24 Jun 22 04:39:38 PM PDT 24 63191011 ps
T1016 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3525739909 Jun 22 04:39:23 PM PDT 24 Jun 22 04:39:58 PM PDT 24 548210262 ps
T1017 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3493013145 Jun 22 04:39:33 PM PDT 24 Jun 22 04:39:39 PM PDT 24 88789434 ps
T1018 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.4125736739 Jun 22 04:39:50 PM PDT 24 Jun 22 04:39:51 PM PDT 24 44432811 ps
T1019 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1785709363 Jun 22 04:39:47 PM PDT 24 Jun 22 04:39:49 PM PDT 24 17164836 ps
T1020 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.197245653 Jun 22 04:39:30 PM PDT 24 Jun 22 04:39:33 PM PDT 24 13491163 ps
T1021 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.687067991 Jun 22 04:39:32 PM PDT 24 Jun 22 04:39:36 PM PDT 24 13509390 ps
T1022 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.666105099 Jun 22 04:39:23 PM PDT 24 Jun 22 04:39:25 PM PDT 24 100823677 ps
T168 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2545089813 Jun 22 04:39:43 PM PDT 24 Jun 22 04:39:51 PM PDT 24 715263646 ps
T1023 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2689212608 Jun 22 04:39:30 PM PDT 24 Jun 22 04:39:58 PM PDT 24 1202394154 ps
T1024 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2925704591 Jun 22 04:39:36 PM PDT 24 Jun 22 04:39:40 PM PDT 24 14508275 ps
T1025 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.590187414 Jun 22 04:39:41 PM PDT 24 Jun 22 04:39:45 PM PDT 24 2061939410 ps
T1026 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.752137377 Jun 22 04:39:33 PM PDT 24 Jun 22 04:39:36 PM PDT 24 15287291 ps
T165 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4078626957 Jun 22 04:39:39 PM PDT 24 Jun 22 04:40:02 PM PDT 24 1186909296 ps
T172 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.171161882 Jun 22 04:39:23 PM PDT 24 Jun 22 04:39:32 PM PDT 24 911257702 ps
T171 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2215208429 Jun 22 04:39:34 PM PDT 24 Jun 22 04:39:57 PM PDT 24 826706079 ps
T1027 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2343542490 Jun 22 04:39:30 PM PDT 24 Jun 22 04:39:36 PM PDT 24 174458054 ps
T1028 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3508452920 Jun 22 04:39:33 PM PDT 24 Jun 22 04:39:37 PM PDT 24 137657012 ps
T1029 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2904979271 Jun 22 04:39:26 PM PDT 24 Jun 22 04:39:30 PM PDT 24 286846961 ps
T1030 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1242549133 Jun 22 04:39:29 PM PDT 24 Jun 22 04:39:32 PM PDT 24 28985854 ps
T1031 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2817667292 Jun 22 04:39:35 PM PDT 24 Jun 22 04:39:43 PM PDT 24 170581957 ps
T163 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.451879181 Jun 22 04:39:43 PM PDT 24 Jun 22 04:39:59 PM PDT 24 724777077 ps
T1032 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.129258725 Jun 22 04:39:36 PM PDT 24 Jun 22 04:39:40 PM PDT 24 14193071 ps
T1033 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.369537010 Jun 22 04:39:29 PM PDT 24 Jun 22 04:39:46 PM PDT 24 2723871376 ps
T1034 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.456354596 Jun 22 04:39:31 PM PDT 24 Jun 22 04:39:36 PM PDT 24 212560283 ps
T1035 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1557268925 Jun 22 04:39:19 PM PDT 24 Jun 22 04:39:23 PM PDT 24 276922461 ps
T1036 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.845792818 Jun 22 04:39:47 PM PDT 24 Jun 22 04:39:48 PM PDT 24 93202992 ps
T1037 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.769075324 Jun 22 04:39:33 PM PDT 24 Jun 22 04:39:41 PM PDT 24 360891189 ps
T1038 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.383634405 Jun 22 04:39:37 PM PDT 24 Jun 22 04:39:41 PM PDT 24 225354246 ps
T1039 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4273780222 Jun 22 04:39:29 PM PDT 24 Jun 22 04:39:32 PM PDT 24 146090993 ps
T1040 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.87932586 Jun 22 04:40:03 PM PDT 24 Jun 22 04:40:07 PM PDT 24 186853941 ps
T169 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3828407568 Jun 22 04:39:45 PM PDT 24 Jun 22 04:40:01 PM PDT 24 732959976 ps
T1041 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.543548292 Jun 22 04:39:30 PM PDT 24 Jun 22 04:39:32 PM PDT 24 39969334 ps
T1042 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3914038414 Jun 22 04:39:53 PM PDT 24 Jun 22 04:39:56 PM PDT 24 82267119 ps
T1043 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4220252124 Jun 22 04:39:35 PM PDT 24 Jun 22 04:39:40 PM PDT 24 181415975 ps
T78 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2943424583 Jun 22 04:39:31 PM PDT 24 Jun 22 04:39:35 PM PDT 24 48450759 ps
T1044 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.174144121 Jun 22 04:39:33 PM PDT 24 Jun 22 04:39:39 PM PDT 24 211006746 ps
T1045 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3048578428 Jun 22 04:39:44 PM PDT 24 Jun 22 04:39:47 PM PDT 24 200239022 ps
T79 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2058384100 Jun 22 04:39:25 PM PDT 24 Jun 22 04:39:27 PM PDT 24 168069959 ps
T1046 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1713423479 Jun 22 04:39:30 PM PDT 24 Jun 22 04:39:55 PM PDT 24 4331978946 ps
T1047 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2480486657 Jun 22 04:39:34 PM PDT 24 Jun 22 04:39:46 PM PDT 24 376485924 ps
T1048 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2873575097 Jun 22 04:39:32 PM PDT 24 Jun 22 04:39:37 PM PDT 24 185699875 ps
T1049 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.278484354 Jun 22 04:39:49 PM PDT 24 Jun 22 04:40:01 PM PDT 24 195936697 ps
T1050 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3782988193 Jun 22 04:40:03 PM PDT 24 Jun 22 04:40:06 PM PDT 24 26763294 ps
T1051 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.89978961 Jun 22 04:39:53 PM PDT 24 Jun 22 04:39:54 PM PDT 24 33876588 ps
T1052 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.9823940 Jun 22 04:39:43 PM PDT 24 Jun 22 04:39:45 PM PDT 24 50228198 ps
T1053 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1774142665 Jun 22 04:39:34 PM PDT 24 Jun 22 04:39:38 PM PDT 24 44824159 ps
T1054 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.478324636 Jun 22 04:39:38 PM PDT 24 Jun 22 04:39:41 PM PDT 24 26426249 ps
T1055 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2776012421 Jun 22 04:39:33 PM PDT 24 Jun 22 04:39:38 PM PDT 24 12063161 ps
T1056 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2743690611 Jun 22 04:39:34 PM PDT 24 Jun 22 04:39:45 PM PDT 24 414979610 ps
T1057 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3944588679 Jun 22 04:39:35 PM PDT 24 Jun 22 04:39:40 PM PDT 24 72555343 ps
T1058 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.178646721 Jun 22 04:39:29 PM PDT 24 Jun 22 04:39:51 PM PDT 24 331706836 ps
T1059 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1941938961 Jun 22 04:39:29 PM PDT 24 Jun 22 04:39:33 PM PDT 24 23855575 ps
T1060 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.357453041 Jun 22 04:39:50 PM PDT 24 Jun 22 04:39:52 PM PDT 24 22505977 ps
T1061 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2069282304 Jun 22 04:39:36 PM PDT 24 Jun 22 04:39:41 PM PDT 24 267252298 ps
T1062 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.360276564 Jun 22 04:39:27 PM PDT 24 Jun 22 04:39:32 PM PDT 24 634165715 ps
T1063 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3522833957 Jun 22 04:39:26 PM PDT 24 Jun 22 04:39:30 PM PDT 24 222221280 ps
T1064 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2034209975 Jun 22 04:39:31 PM PDT 24 Jun 22 04:39:37 PM PDT 24 992886256 ps
T1065 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2061811208 Jun 22 04:39:54 PM PDT 24 Jun 22 04:39:57 PM PDT 24 67776643 ps
T1066 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2021636592 Jun 22 04:39:35 PM PDT 24 Jun 22 04:39:39 PM PDT 24 29665452 ps
T1067 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2603728817 Jun 22 04:39:44 PM PDT 24 Jun 22 04:39:46 PM PDT 24 85229879 ps
T1068 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.319642998 Jun 22 04:39:48 PM PDT 24 Jun 22 04:39:49 PM PDT 24 19206388 ps
T1069 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.611491222 Jun 22 04:39:57 PM PDT 24 Jun 22 04:40:00 PM PDT 24 51181358 ps
T1070 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1389961410 Jun 22 04:39:32 PM PDT 24 Jun 22 04:39:36 PM PDT 24 17402692 ps
T1071 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2358441957 Jun 22 04:39:52 PM PDT 24 Jun 22 04:39:56 PM PDT 24 199133071 ps
T1072 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4284823669 Jun 22 04:39:34 PM PDT 24 Jun 22 04:39:42 PM PDT 24 71708264 ps
T1073 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3813771172 Jun 22 04:39:34 PM PDT 24 Jun 22 04:39:40 PM PDT 24 82813797 ps
T1074 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1051401345 Jun 22 04:39:35 PM PDT 24 Jun 22 04:39:39 PM PDT 24 59220595 ps
T1075 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2711231489 Jun 22 04:39:33 PM PDT 24 Jun 22 04:39:37 PM PDT 24 104343436 ps
T1076 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.980379346 Jun 22 04:39:30 PM PDT 24 Jun 22 04:39:39 PM PDT 24 1013697624 ps
T1077 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1534976943 Jun 22 04:39:50 PM PDT 24 Jun 22 04:39:52 PM PDT 24 11400850 ps
T1078 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.846285231 Jun 22 04:39:36 PM PDT 24 Jun 22 04:39:42 PM PDT 24 144673837 ps
T1079 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3296247990 Jun 22 04:39:50 PM PDT 24 Jun 22 04:39:54 PM PDT 24 502135357 ps
T1080 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.447890489 Jun 22 04:39:59 PM PDT 24 Jun 22 04:40:02 PM PDT 24 62830675 ps
T1081 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2443036060 Jun 22 04:39:30 PM PDT 24 Jun 22 04:39:34 PM PDT 24 79921526 ps
T1082 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3857964303 Jun 22 04:39:22 PM PDT 24 Jun 22 04:39:26 PM PDT 24 151966670 ps
T1083 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3112779198 Jun 22 04:39:28 PM PDT 24 Jun 22 04:39:32 PM PDT 24 227976363 ps
T1084 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3441109214 Jun 22 04:39:33 PM PDT 24 Jun 22 04:39:36 PM PDT 24 133617245 ps
T1085 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.499401109 Jun 22 04:39:31 PM PDT 24 Jun 22 04:39:34 PM PDT 24 24353827 ps
T1086 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1659956132 Jun 22 04:39:45 PM PDT 24 Jun 22 04:39:48 PM PDT 24 338464060 ps
T1087 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3536979425 Jun 22 04:39:34 PM PDT 24 Jun 22 04:39:39 PM PDT 24 36896706 ps
T1088 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4078406534 Jun 22 04:39:19 PM PDT 24 Jun 22 04:39:23 PM PDT 24 88000966 ps
T1089 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1253584653 Jun 22 04:39:29 PM PDT 24 Jun 22 04:39:32 PM PDT 24 34659209 ps
T1090 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3011379543 Jun 22 04:39:27 PM PDT 24 Jun 22 04:39:32 PM PDT 24 166779443 ps
T1091 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.765904167 Jun 22 04:39:53 PM PDT 24 Jun 22 04:39:56 PM PDT 24 110466405 ps
T1092 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1654905596 Jun 22 04:39:50 PM PDT 24 Jun 22 04:39:52 PM PDT 24 14536630 ps
T1093 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1077772135 Jun 22 04:39:31 PM PDT 24 Jun 22 04:39:37 PM PDT 24 211060792 ps
T1094 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2588822014 Jun 22 04:39:21 PM PDT 24 Jun 22 04:39:24 PM PDT 24 88424843 ps
T1095 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1583013489 Jun 22 04:39:33 PM PDT 24 Jun 22 04:39:37 PM PDT 24 79914845 ps
T1096 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2552219466 Jun 22 04:39:30 PM PDT 24 Jun 22 04:39:33 PM PDT 24 287589397 ps
T164 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4177284960 Jun 22 04:39:39 PM PDT 24 Jun 22 04:39:57 PM PDT 24 1442374500 ps
T166 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.208736791 Jun 22 04:39:31 PM PDT 24 Jun 22 04:39:57 PM PDT 24 906950009 ps
T1097 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1968980059 Jun 22 04:39:51 PM PDT 24 Jun 22 04:39:55 PM PDT 24 486469458 ps
T1098 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.894298325 Jun 22 04:39:48 PM PDT 24 Jun 22 04:39:51 PM PDT 24 382897207 ps
T1099 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2079000551 Jun 22 04:39:28 PM PDT 24 Jun 22 04:39:30 PM PDT 24 55478569 ps
T1100 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3307785892 Jun 22 04:39:29 PM PDT 24 Jun 22 04:39:34 PM PDT 24 130817227 ps
T167 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1347367738 Jun 22 04:39:30 PM PDT 24 Jun 22 04:39:47 PM PDT 24 648299874 ps
T1101 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.895978512 Jun 22 04:39:38 PM PDT 24 Jun 22 04:39:41 PM PDT 24 50697471 ps

Test location /workspace/coverage/default/33.spi_device_flash_all.4040325777
Short name T10
Test name
Test status
Simulation time 60124323472 ps
CPU time 270.55 seconds
Started Jun 22 05:19:22 PM PDT 24
Finished Jun 22 05:23:54 PM PDT 24
Peak memory 265080 kb
Host smart-9db2ed82-56d3-447a-a3ee-ff9fde46c414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040325777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.4040325777
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.4140468247
Short name T13
Test name
Test status
Simulation time 82310826146 ps
CPU time 389.58 seconds
Started Jun 22 05:18:21 PM PDT 24
Finished Jun 22 05:24:52 PM PDT 24
Peak memory 285152 kb
Host smart-d67d1578-9b58-4e61-89d0-a62fac749b47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140468247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.4140468247
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2699796693
Short name T202
Test name
Test status
Simulation time 50555385361 ps
CPU time 192.62 seconds
Started Jun 22 05:17:37 PM PDT 24
Finished Jun 22 05:20:52 PM PDT 24
Peak memory 274228 kb
Host smart-7dd9a11e-fd6c-42e4-9a3a-85651d6f823f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699796693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2699796693
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1428192366
Short name T92
Test name
Test status
Simulation time 643473884 ps
CPU time 7.5 seconds
Started Jun 22 04:39:32 PM PDT 24
Finished Jun 22 04:39:42 PM PDT 24
Peak memory 215756 kb
Host smart-05a8c047-0932-4722-8b6f-36d41e9abd1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428192366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1428192366
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1128903480
Short name T63
Test name
Test status
Simulation time 43970710 ps
CPU time 0.73 seconds
Started Jun 22 05:17:53 PM PDT 24
Finished Jun 22 05:17:54 PM PDT 24
Peak memory 217080 kb
Host smart-46376173-242c-4133-b6b5-3a1236a32d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128903480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1128903480
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1408372485
Short name T199
Test name
Test status
Simulation time 42114905234 ps
CPU time 324.72 seconds
Started Jun 22 05:18:43 PM PDT 24
Finished Jun 22 05:24:09 PM PDT 24
Peak memory 276400 kb
Host smart-a6719ec8-f655-4697-a11c-aeb20af68f1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408372485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1408372485
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1198260453
Short name T95
Test name
Test status
Simulation time 583960243 ps
CPU time 4.38 seconds
Started Jun 22 04:39:25 PM PDT 24
Finished Jun 22 04:39:31 PM PDT 24
Peak memory 215224 kb
Host smart-9f16d80b-c8b8-43c2-a956-81317f8a829e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198260453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
198260453
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.4093091045
Short name T17
Test name
Test status
Simulation time 220204709236 ps
CPU time 512.04 seconds
Started Jun 22 05:19:45 PM PDT 24
Finished Jun 22 05:28:19 PM PDT 24
Peak memory 250348 kb
Host smart-de3bdfe4-51e4-461e-bd7a-1353f4fd4493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093091045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.4093091045
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2768769589
Short name T4
Test name
Test status
Simulation time 528416902 ps
CPU time 8.89 seconds
Started Jun 22 05:18:47 PM PDT 24
Finished Jun 22 05:18:57 PM PDT 24
Peak memory 251148 kb
Host smart-4233617d-f382-4f4a-8dfb-d4fb0878065d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768769589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2768769589
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1739104164
Short name T19
Test name
Test status
Simulation time 47122029 ps
CPU time 0.99 seconds
Started Jun 22 05:17:39 PM PDT 24
Finished Jun 22 05:17:42 PM PDT 24
Peak memory 236348 kb
Host smart-522708c1-205f-454f-a4d4-d7c1a271b730
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739104164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1739104164
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3511591355
Short name T15
Test name
Test status
Simulation time 11828518324 ps
CPU time 101.51 seconds
Started Jun 22 05:19:44 PM PDT 24
Finished Jun 22 05:21:27 PM PDT 24
Peak memory 257660 kb
Host smart-5be388d2-36c7-456c-9999-484fb8de125a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511591355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3511591355
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2633572022
Short name T30
Test name
Test status
Simulation time 337934117728 ps
CPU time 874.27 seconds
Started Jun 22 05:19:59 PM PDT 24
Finished Jun 22 05:34:34 PM PDT 24
Peak memory 272280 kb
Host smart-bf4d0bb3-5ec2-4f0b-8c3b-20e3fd50a794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633572022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2633572022
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1995118661
Short name T224
Test name
Test status
Simulation time 58258483695 ps
CPU time 575.53 seconds
Started Jun 22 05:17:58 PM PDT 24
Finished Jun 22 05:27:34 PM PDT 24
Peak memory 274600 kb
Host smart-02a6e338-ddb5-4f00-8b68-9e24dde44143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995118661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1995118661
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.4277629232
Short name T181
Test name
Test status
Simulation time 84563267961 ps
CPU time 191.17 seconds
Started Jun 22 05:20:16 PM PDT 24
Finished Jun 22 05:23:27 PM PDT 24
Peak memory 255396 kb
Host smart-6c293aa4-df62-44b8-8317-e285a5f019ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277629232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.4277629232
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3064007031
Short name T106
Test name
Test status
Simulation time 142566516 ps
CPU time 1.21 seconds
Started Jun 22 04:39:29 PM PDT 24
Finished Jun 22 04:39:32 PM PDT 24
Peak memory 206972 kb
Host smart-b1876282-9b4d-4114-b111-8a11a97941fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064007031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
064007031
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.916036388
Short name T7
Test name
Test status
Simulation time 56653363200 ps
CPU time 295.43 seconds
Started Jun 22 05:19:50 PM PDT 24
Finished Jun 22 05:24:46 PM PDT 24
Peak memory 272076 kb
Host smart-9c0af441-6c67-466b-8232-466666514896
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916036388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.916036388
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3523706408
Short name T345
Test name
Test status
Simulation time 94320298 ps
CPU time 1.11 seconds
Started Jun 22 05:17:39 PM PDT 24
Finished Jun 22 05:17:42 PM PDT 24
Peak memory 218848 kb
Host smart-e9ab7c29-eb37-4782-b623-a65132ff9926
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523706408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3523706408
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3274918067
Short name T185
Test name
Test status
Simulation time 5311820831 ps
CPU time 86.59 seconds
Started Jun 22 05:18:22 PM PDT 24
Finished Jun 22 05:19:50 PM PDT 24
Peak memory 252320 kb
Host smart-74e399e7-0d12-4db1-a2a1-dbe5d4b234ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274918067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3274918067
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.4105803365
Short name T256
Test name
Test status
Simulation time 176441915203 ps
CPU time 207.28 seconds
Started Jun 22 05:19:06 PM PDT 24
Finished Jun 22 05:22:34 PM PDT 24
Peak memory 254416 kb
Host smart-d88d8578-a62d-4e74-8e33-8e8ca03baf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105803365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.4105803365
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2664354713
Short name T188
Test name
Test status
Simulation time 68792739369 ps
CPU time 675.67 seconds
Started Jun 22 05:19:22 PM PDT 24
Finished Jun 22 05:30:39 PM PDT 24
Peak memory 274528 kb
Host smart-a5e23aa9-4e20-46d6-8da9-614f417d221e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664354713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2664354713
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.592917465
Short name T38
Test name
Test status
Simulation time 920223886 ps
CPU time 19.83 seconds
Started Jun 22 05:17:59 PM PDT 24
Finished Jun 22 05:18:19 PM PDT 24
Peak memory 234620 kb
Host smart-f7e3eb5e-2ac9-46c4-a781-3f08ec33e216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592917465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.592917465
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.4216476735
Short name T180
Test name
Test status
Simulation time 7540071409 ps
CPU time 115.68 seconds
Started Jun 22 05:19:21 PM PDT 24
Finished Jun 22 05:21:18 PM PDT 24
Peak memory 251356 kb
Host smart-9c9dc4bc-d165-493d-aa60-9cf47429eb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216476735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.4216476735
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2863823321
Short name T48
Test name
Test status
Simulation time 28923346791 ps
CPU time 155.64 seconds
Started Jun 22 05:17:56 PM PDT 24
Finished Jun 22 05:20:32 PM PDT 24
Peak memory 274664 kb
Host smart-4dfb7b1f-20dd-49b3-8836-530bb5e5018e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863823321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2863823321
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1882598206
Short name T315
Test name
Test status
Simulation time 2555899420 ps
CPU time 55.93 seconds
Started Jun 22 05:18:28 PM PDT 24
Finished Jun 22 05:19:25 PM PDT 24
Peak memory 257660 kb
Host smart-db740478-ced0-4208-a6e8-83885af4fa61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882598206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1882598206
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2380133202
Short name T335
Test name
Test status
Simulation time 14598583 ps
CPU time 0.8 seconds
Started Jun 22 05:18:03 PM PDT 24
Finished Jun 22 05:18:05 PM PDT 24
Peak memory 205728 kb
Host smart-41c0dc98-6bc1-4396-a757-a2749ea6f390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380133202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
380133202
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3492006594
Short name T99
Test name
Test status
Simulation time 597865240 ps
CPU time 16.14 seconds
Started Jun 22 04:39:34 PM PDT 24
Finished Jun 22 04:39:54 PM PDT 24
Peak memory 215300 kb
Host smart-d74646fa-6e19-447c-8783-8843e1419796
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492006594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3492006594
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2302165667
Short name T290
Test name
Test status
Simulation time 277729928444 ps
CPU time 470.4 seconds
Started Jun 22 05:20:01 PM PDT 24
Finished Jun 22 05:27:53 PM PDT 24
Peak memory 258032 kb
Host smart-3d1a5ea2-befa-4214-949a-9378cc68ce52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302165667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2302165667
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1449362238
Short name T144
Test name
Test status
Simulation time 33481653906 ps
CPU time 373.86 seconds
Started Jun 22 05:19:46 PM PDT 24
Finished Jun 22 05:26:01 PM PDT 24
Peak memory 258512 kb
Host smart-9f2a4ebd-d70a-4991-82d1-31411be00648
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449362238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1449362238
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.614310441
Short name T204
Test name
Test status
Simulation time 112855304907 ps
CPU time 124.83 seconds
Started Jun 22 05:18:59 PM PDT 24
Finished Jun 22 05:21:04 PM PDT 24
Peak memory 241944 kb
Host smart-f8664f47-0b9d-48ee-8e98-73bcf490aeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614310441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.614310441
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.447035568
Short name T77
Test name
Test status
Simulation time 20143802 ps
CPU time 1.22 seconds
Started Jun 22 04:39:35 PM PDT 24
Finished Jun 22 04:39:40 PM PDT 24
Peak memory 216280 kb
Host smart-b0b56714-937d-4de6-8393-2557e074a077
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447035568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.447035568
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.208736791
Short name T166
Test name
Test status
Simulation time 906950009 ps
CPU time 22.69 seconds
Started Jun 22 04:39:31 PM PDT 24
Finished Jun 22 04:39:57 PM PDT 24
Peak memory 215504 kb
Host smart-4cac1661-c26d-48be-8c77-1eb2ccb2e538
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208736791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.208736791
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.764063507
Short name T329
Test name
Test status
Simulation time 2729335955 ps
CPU time 6.82 seconds
Started Jun 22 05:17:34 PM PDT 24
Finished Jun 22 05:17:42 PM PDT 24
Peak memory 217428 kb
Host smart-2a0d32c8-0c96-44e0-a384-36bd2cab77b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764063507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.764063507
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.589662997
Short name T288
Test name
Test status
Simulation time 145465713574 ps
CPU time 767.71 seconds
Started Jun 22 05:17:51 PM PDT 24
Finished Jun 22 05:30:39 PM PDT 24
Peak memory 256064 kb
Host smart-6a3f3b61-0461-4a7b-943b-69adce17df20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589662997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.589662997
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2200163497
Short name T227
Test name
Test status
Simulation time 73605241 ps
CPU time 3.61 seconds
Started Jun 22 05:18:04 PM PDT 24
Finished Jun 22 05:18:08 PM PDT 24
Peak memory 225580 kb
Host smart-31a0e9ec-dcc7-4228-8e0c-d741d37e6374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200163497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2200163497
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.664589759
Short name T190
Test name
Test status
Simulation time 1208423162 ps
CPU time 9.89 seconds
Started Jun 22 05:17:45 PM PDT 24
Finished Jun 22 05:17:55 PM PDT 24
Peak memory 233736 kb
Host smart-9da4e4f9-beab-488d-826d-4d1645a3ef65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664589759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
664589759
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3210875364
Short name T192
Test name
Test status
Simulation time 400920274 ps
CPU time 10.68 seconds
Started Jun 22 05:17:38 PM PDT 24
Finished Jun 22 05:17:51 PM PDT 24
Peak memory 233932 kb
Host smart-bb320b03-8fc3-4b37-b5f9-09d6a1cb72d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210875364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3210875364
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2266837438
Short name T98
Test name
Test status
Simulation time 167947118 ps
CPU time 4.51 seconds
Started Jun 22 04:39:30 PM PDT 24
Finished Jun 22 04:39:37 PM PDT 24
Peak memory 215456 kb
Host smart-e0f8aa37-337a-4525-91bb-a27c259aa454
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266837438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
266837438
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2545089813
Short name T168
Test name
Test status
Simulation time 715263646 ps
CPU time 7.46 seconds
Started Jun 22 04:39:43 PM PDT 24
Finished Jun 22 04:39:51 PM PDT 24
Peak memory 215220 kb
Host smart-a8a98af1-a549-4a34-b533-660fcc5db2f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545089813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2545089813
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2643136178
Short name T76
Test name
Test status
Simulation time 23494172200 ps
CPU time 253.42 seconds
Started Jun 22 05:18:12 PM PDT 24
Finished Jun 22 05:22:26 PM PDT 24
Peak memory 273904 kb
Host smart-b61d9585-16bb-4ee8-86ca-923de3ed37d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643136178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2643136178
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.583904890
Short name T175
Test name
Test status
Simulation time 873757622 ps
CPU time 10.17 seconds
Started Jun 22 05:18:21 PM PDT 24
Finished Jun 22 05:18:32 PM PDT 24
Peak memory 225492 kb
Host smart-5653232f-3bb4-4aaf-9187-2c215242f73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583904890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.583904890
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1184582914
Short name T211
Test name
Test status
Simulation time 26028551691 ps
CPU time 19.88 seconds
Started Jun 22 05:18:31 PM PDT 24
Finished Jun 22 05:18:51 PM PDT 24
Peak memory 233808 kb
Host smart-b506b547-8076-4685-8db3-d8e7899a0fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184582914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1184582914
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2702374426
Short name T966
Test name
Test status
Simulation time 18237201878 ps
CPU time 57.81 seconds
Started Jun 22 05:18:22 PM PDT 24
Finished Jun 22 05:19:21 PM PDT 24
Peak memory 233764 kb
Host smart-5ce94c20-0c75-48c0-9db5-590bba8b7fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702374426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2702374426
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.527691749
Short name T44
Test name
Test status
Simulation time 28180487694 ps
CPU time 319.31 seconds
Started Jun 22 05:18:21 PM PDT 24
Finished Jun 22 05:23:42 PM PDT 24
Peak memory 253548 kb
Host smart-29f48fc4-42e5-4a4f-9ca8-f9d576f54c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527691749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.527691749
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3111233078
Short name T207
Test name
Test status
Simulation time 5255238913 ps
CPU time 4.62 seconds
Started Jun 22 05:18:26 PM PDT 24
Finished Jun 22 05:18:32 PM PDT 24
Peak memory 233868 kb
Host smart-f6e6d3a8-8617-4e02-a11d-803cf1ca22a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111233078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3111233078
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2430912194
Short name T850
Test name
Test status
Simulation time 6122277563 ps
CPU time 16.33 seconds
Started Jun 22 05:18:22 PM PDT 24
Finished Jun 22 05:18:39 PM PDT 24
Peak memory 225568 kb
Host smart-a527c96c-0bfa-4185-8af7-6f44a95cc3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430912194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2430912194
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.544848664
Short name T230
Test name
Test status
Simulation time 3849129780 ps
CPU time 76.75 seconds
Started Jun 22 05:18:24 PM PDT 24
Finished Jun 22 05:19:42 PM PDT 24
Peak memory 251216 kb
Host smart-d7d2843b-3968-4939-a00b-5b0fa789f065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544848664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.544848664
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2087031407
Short name T283
Test name
Test status
Simulation time 29508423482 ps
CPU time 79.05 seconds
Started Jun 22 05:18:28 PM PDT 24
Finished Jun 22 05:19:48 PM PDT 24
Peak memory 240208 kb
Host smart-4304fbef-be60-401f-afd3-00add1b64c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087031407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2087031407
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.445884906
Short name T236
Test name
Test status
Simulation time 33777192914 ps
CPU time 72.39 seconds
Started Jun 22 05:17:42 PM PDT 24
Finished Jun 22 05:18:55 PM PDT 24
Peak memory 240388 kb
Host smart-c3a0dd68-a1e9-4895-a1e8-0e963a6618bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445884906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.445884906
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2377080416
Short name T287
Test name
Test status
Simulation time 84354479217 ps
CPU time 792.38 seconds
Started Jun 22 05:18:40 PM PDT 24
Finished Jun 22 05:31:53 PM PDT 24
Peak memory 289164 kb
Host smart-cefac264-c48c-48fa-82a0-4bd14d4cae77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377080416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2377080416
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1502591347
Short name T217
Test name
Test status
Simulation time 4211148659 ps
CPU time 24.77 seconds
Started Jun 22 05:18:58 PM PDT 24
Finished Jun 22 05:19:23 PM PDT 24
Peak memory 255804 kb
Host smart-22f1e501-3f94-4740-aed2-e9b0ad2df6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502591347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1502591347
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1673348798
Short name T203
Test name
Test status
Simulation time 36233796955 ps
CPU time 93.27 seconds
Started Jun 22 05:19:26 PM PDT 24
Finished Jun 22 05:21:01 PM PDT 24
Peak memory 250316 kb
Host smart-95c85122-4c08-4bb2-8b37-af6a9e637071
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673348798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1673348798
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_upload.1760256214
Short name T84
Test name
Test status
Simulation time 5762947278 ps
CPU time 13.57 seconds
Started Jun 22 05:19:34 PM PDT 24
Finished Jun 22 05:19:49 PM PDT 24
Peak memory 233880 kb
Host smart-feb8499d-4e5b-4fd4-84f7-105ceaec5510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760256214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1760256214
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1196613117
Short name T1012
Test name
Test status
Simulation time 3144789612 ps
CPU time 8.6 seconds
Started Jun 22 04:39:18 PM PDT 24
Finished Jun 22 04:39:28 PM PDT 24
Peak memory 207036 kb
Host smart-dc6d831e-d2ee-4258-9443-3406a7ea131a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196613117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1196613117
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3525739909
Short name T1016
Test name
Test status
Simulation time 548210262 ps
CPU time 34.37 seconds
Started Jun 22 04:39:23 PM PDT 24
Finished Jun 22 04:39:58 PM PDT 24
Peak memory 215156 kb
Host smart-ced9c438-491f-4377-abd4-ef4380fec51a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525739909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3525739909
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2588822014
Short name T1094
Test name
Test status
Simulation time 88424843 ps
CPU time 1.36 seconds
Started Jun 22 04:39:21 PM PDT 24
Finished Jun 22 04:39:24 PM PDT 24
Peak memory 216284 kb
Host smart-8e74ddfe-05fe-4b6a-9cd3-f1baa94d3c99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588822014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2588822014
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4078406534
Short name T1088
Test name
Test status
Simulation time 88000966 ps
CPU time 3.03 seconds
Started Jun 22 04:39:19 PM PDT 24
Finished Jun 22 04:39:23 PM PDT 24
Peak memory 217960 kb
Host smart-8359bb5e-e2bb-49ae-bbb5-212cb47e64fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078406534 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4078406534
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4272090374
Short name T986
Test name
Test status
Simulation time 119953510 ps
CPU time 0.75 seconds
Started Jun 22 04:39:24 PM PDT 24
Finished Jun 22 04:39:25 PM PDT 24
Peak memory 203608 kb
Host smart-dd34a360-eb14-4b94-9553-49c80c438884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272090374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.4
272090374
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.666105099
Short name T1022
Test name
Test status
Simulation time 100823677 ps
CPU time 1.25 seconds
Started Jun 22 04:39:23 PM PDT 24
Finished Jun 22 04:39:25 PM PDT 24
Peak memory 215292 kb
Host smart-21657ccb-3ab3-4d78-81b0-86a103fd4c46
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666105099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.666105099
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.687067991
Short name T1021
Test name
Test status
Simulation time 13509390 ps
CPU time 0.64 seconds
Started Jun 22 04:39:32 PM PDT 24
Finished Jun 22 04:39:36 PM PDT 24
Peak memory 203544 kb
Host smart-870276d6-196d-4608-bdb1-fb4f02204e1e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687067991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.687067991
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2063399580
Short name T140
Test name
Test status
Simulation time 196997413 ps
CPU time 4.25 seconds
Started Jun 22 04:39:28 PM PDT 24
Finished Jun 22 04:39:34 PM PDT 24
Peak memory 215376 kb
Host smart-0ed41bbb-1485-48ef-872d-0a9c9711ec8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063399580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2063399580
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3796124532
Short name T995
Test name
Test status
Simulation time 699308907 ps
CPU time 2.5 seconds
Started Jun 22 04:39:22 PM PDT 24
Finished Jun 22 04:39:26 PM PDT 24
Peak memory 215364 kb
Host smart-783ccfba-ac2b-4dfd-bd9b-136e3bc0049e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796124532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
796124532
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.980379346
Short name T1076
Test name
Test status
Simulation time 1013697624 ps
CPU time 6.6 seconds
Started Jun 22 04:39:30 PM PDT 24
Finished Jun 22 04:39:39 PM PDT 24
Peak memory 215268 kb
Host smart-1b69a7d1-5eaa-4164-bb53-8dee0979a786
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980379346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.980379346
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.369537010
Short name T1033
Test name
Test status
Simulation time 2723871376 ps
CPU time 14.84 seconds
Started Jun 22 04:39:29 PM PDT 24
Finished Jun 22 04:39:46 PM PDT 24
Peak memory 215276 kb
Host smart-0a2c804f-607d-4a98-be11-de2547aa15a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369537010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.369537010
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2689212608
Short name T1023
Test name
Test status
Simulation time 1202394154 ps
CPU time 25.67 seconds
Started Jun 22 04:39:30 PM PDT 24
Finished Jun 22 04:39:58 PM PDT 24
Peak memory 215172 kb
Host smart-a7ce692b-ad3a-4407-bf28-29b73b070582
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689212608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2689212608
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2943424583
Short name T78
Test name
Test status
Simulation time 48450759 ps
CPU time 1.41 seconds
Started Jun 22 04:39:31 PM PDT 24
Finished Jun 22 04:39:35 PM PDT 24
Peak memory 207024 kb
Host smart-db7f1efd-3b16-48b1-944d-b2d69cb3065f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943424583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2943424583
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3404003564
Short name T987
Test name
Test status
Simulation time 42702934 ps
CPU time 2.66 seconds
Started Jun 22 04:39:25 PM PDT 24
Finished Jun 22 04:39:35 PM PDT 24
Peak memory 218188 kb
Host smart-4949be5f-9b7d-4610-9cab-f7c5483beaae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404003564 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3404003564
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3446153696
Short name T114
Test name
Test status
Simulation time 40224162 ps
CPU time 1.25 seconds
Started Jun 22 04:39:19 PM PDT 24
Finished Jun 22 04:39:21 PM PDT 24
Peak memory 207044 kb
Host smart-f79b9214-dd34-43f6-b869-82db95b351ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446153696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
446153696
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.478324636
Short name T1054
Test name
Test status
Simulation time 26426249 ps
CPU time 0.74 seconds
Started Jun 22 04:39:38 PM PDT 24
Finished Jun 22 04:39:41 PM PDT 24
Peak memory 203672 kb
Host smart-9c9551bf-f766-4792-bf52-2de8b0a86a4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478324636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.478324636
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.571301599
Short name T116
Test name
Test status
Simulation time 275990227 ps
CPU time 1.72 seconds
Started Jun 22 04:39:16 PM PDT 24
Finished Jun 22 04:39:19 PM PDT 24
Peak memory 215252 kb
Host smart-700d1e11-e522-48c6-abd0-727d7009f734
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571301599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.571301599
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2776012421
Short name T1055
Test name
Test status
Simulation time 12063161 ps
CPU time 0.67 seconds
Started Jun 22 04:39:33 PM PDT 24
Finished Jun 22 04:39:38 PM PDT 24
Peak memory 203536 kb
Host smart-6aa2d11c-aff2-4533-acac-0ae515ba89f8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776012421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2776012421
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2034209975
Short name T1064
Test name
Test status
Simulation time 992886256 ps
CPU time 4.15 seconds
Started Jun 22 04:39:31 PM PDT 24
Finished Jun 22 04:39:37 PM PDT 24
Peak memory 215276 kb
Host smart-6dc9efb2-5a0a-47c9-97d3-10aff51e35c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034209975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2034209975
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.171161882
Short name T172
Test name
Test status
Simulation time 911257702 ps
CPU time 8.1 seconds
Started Jun 22 04:39:23 PM PDT 24
Finished Jun 22 04:39:32 PM PDT 24
Peak memory 215612 kb
Host smart-28fede09-92cf-40d2-91db-16e5792fd39f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171161882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.171161882
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3307785892
Short name T1100
Test name
Test status
Simulation time 130817227 ps
CPU time 3.79 seconds
Started Jun 22 04:39:29 PM PDT 24
Finished Jun 22 04:39:34 PM PDT 24
Peak memory 217364 kb
Host smart-441f7882-1f32-4cf2-8486-e54b1b5bdb71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307785892 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3307785892
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3441109214
Short name T1084
Test name
Test status
Simulation time 133617245 ps
CPU time 1.25 seconds
Started Jun 22 04:39:33 PM PDT 24
Finished Jun 22 04:39:36 PM PDT 24
Peak memory 215228 kb
Host smart-6ab8eca8-68db-4f1e-8ca9-53afb90f3db6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441109214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3441109214
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.865728585
Short name T1010
Test name
Test status
Simulation time 16999047 ps
CPU time 0.77 seconds
Started Jun 22 04:39:48 PM PDT 24
Finished Jun 22 04:39:50 PM PDT 24
Peak memory 203912 kb
Host smart-e5c94c3d-c9d3-48b1-a194-6f428a7dfa0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865728585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.865728585
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1954799430
Short name T142
Test name
Test status
Simulation time 781677059 ps
CPU time 4.24 seconds
Started Jun 22 04:39:29 PM PDT 24
Finished Jun 22 04:39:35 PM PDT 24
Peak memory 215220 kb
Host smart-f6c830e2-40cf-4b00-86ab-ee3d64555065
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954799430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1954799430
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4245707756
Short name T89
Test name
Test status
Simulation time 581965597 ps
CPU time 3.44 seconds
Started Jun 22 04:39:32 PM PDT 24
Finished Jun 22 04:39:38 PM PDT 24
Peak memory 215492 kb
Host smart-ab15bebc-7c59-4530-839a-239c07187409
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245707756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4245707756
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3619790272
Short name T1001
Test name
Test status
Simulation time 36090636 ps
CPU time 2.49 seconds
Started Jun 22 04:39:37 PM PDT 24
Finished Jun 22 04:39:43 PM PDT 24
Peak memory 216308 kb
Host smart-257bfd87-7418-48d0-bf7b-8bd06824b45f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619790272 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3619790272
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1253584653
Short name T1089
Test name
Test status
Simulation time 34659209 ps
CPU time 1.23 seconds
Started Jun 22 04:39:29 PM PDT 24
Finished Jun 22 04:39:32 PM PDT 24
Peak memory 206960 kb
Host smart-ec796812-2806-483a-854e-cf5959d379b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253584653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1253584653
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.197245653
Short name T1020
Test name
Test status
Simulation time 13491163 ps
CPU time 0.7 seconds
Started Jun 22 04:39:30 PM PDT 24
Finished Jun 22 04:39:33 PM PDT 24
Peak memory 203560 kb
Host smart-a475c438-b008-492a-89dd-184b1521c2fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197245653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.197245653
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.292157527
Short name T993
Test name
Test status
Simulation time 94771972 ps
CPU time 1.75 seconds
Started Jun 22 04:39:33 PM PDT 24
Finished Jun 22 04:39:37 PM PDT 24
Peak memory 207036 kb
Host smart-7c494710-2918-42f0-9820-828e9d9f962f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292157527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.292157527
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.552250592
Short name T1004
Test name
Test status
Simulation time 187007055 ps
CPU time 2.98 seconds
Started Jun 22 04:39:52 PM PDT 24
Finished Jun 22 04:39:56 PM PDT 24
Peak memory 215312 kb
Host smart-6e0b1013-3335-42c0-b74b-117b5e7f0995
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552250592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.552250592
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3296247990
Short name T1079
Test name
Test status
Simulation time 502135357 ps
CPU time 3.48 seconds
Started Jun 22 04:39:50 PM PDT 24
Finished Jun 22 04:39:54 PM PDT 24
Peak memory 217504 kb
Host smart-87883763-eb7d-4c98-ab15-7a402e2ee60d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296247990 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3296247990
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4130150417
Short name T109
Test name
Test status
Simulation time 72719500 ps
CPU time 2.37 seconds
Started Jun 22 04:39:41 PM PDT 24
Finished Jun 22 04:39:45 PM PDT 24
Peak memory 206852 kb
Host smart-c6ce9119-a4cc-4f51-a4fe-c09f924e037e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130150417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4130150417
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.447890489
Short name T1080
Test name
Test status
Simulation time 62830675 ps
CPU time 0.69 seconds
Started Jun 22 04:39:59 PM PDT 24
Finished Jun 22 04:40:02 PM PDT 24
Peak memory 203548 kb
Host smart-1628696c-da29-4d68-9dd1-6c7a4fd46543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447890489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.447890489
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3813771172
Short name T1073
Test name
Test status
Simulation time 82813797 ps
CPU time 2.6 seconds
Started Jun 22 04:39:34 PM PDT 24
Finished Jun 22 04:39:40 PM PDT 24
Peak memory 215220 kb
Host smart-d67a7ade-6366-41b1-a7fd-aa0dab19ae89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813771172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3813771172
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1968980059
Short name T1097
Test name
Test status
Simulation time 486469458 ps
CPU time 3.19 seconds
Started Jun 22 04:39:51 PM PDT 24
Finished Jun 22 04:39:55 PM PDT 24
Peak memory 215424 kb
Host smart-dfffcd34-8dd3-41ce-8290-fe3a572c0a66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968980059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1968980059
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2743690611
Short name T1056
Test name
Test status
Simulation time 414979610 ps
CPU time 6.2 seconds
Started Jun 22 04:39:34 PM PDT 24
Finished Jun 22 04:39:45 PM PDT 24
Peak memory 215500 kb
Host smart-88305d1c-d51e-4a74-bb01-67e0a55fb42e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743690611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2743690611
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2343542490
Short name T1027
Test name
Test status
Simulation time 174458054 ps
CPU time 3.93 seconds
Started Jun 22 04:39:30 PM PDT 24
Finished Jun 22 04:39:36 PM PDT 24
Peak memory 217096 kb
Host smart-4a422576-cf47-4450-b50f-f952593f0aa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343542490 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2343542490
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1583013489
Short name T1095
Test name
Test status
Simulation time 79914845 ps
CPU time 1.33 seconds
Started Jun 22 04:39:33 PM PDT 24
Finished Jun 22 04:39:37 PM PDT 24
Peak memory 206992 kb
Host smart-4459f32e-c840-4313-b717-79fc4a5f1f8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583013489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1583013489
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1592508786
Short name T998
Test name
Test status
Simulation time 24057660 ps
CPU time 0.69 seconds
Started Jun 22 04:39:34 PM PDT 24
Finished Jun 22 04:39:38 PM PDT 24
Peak memory 203768 kb
Host smart-b6a20edc-6ba8-486e-8715-251f33af7b32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592508786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1592508786
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1941938961
Short name T1059
Test name
Test status
Simulation time 23855575 ps
CPU time 1.51 seconds
Started Jun 22 04:39:29 PM PDT 24
Finished Jun 22 04:39:33 PM PDT 24
Peak memory 207040 kb
Host smart-235c7345-d406-4fc8-bc26-9e7cf944045d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941938961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1941938961
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1338230945
Short name T1000
Test name
Test status
Simulation time 122257057 ps
CPU time 1.99 seconds
Started Jun 22 04:39:31 PM PDT 24
Finished Jun 22 04:39:36 PM PDT 24
Peak memory 215308 kb
Host smart-28eaaaa6-5cf0-4c1a-8383-b88dcdade74b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338230945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1338230945
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1347367738
Short name T167
Test name
Test status
Simulation time 648299874 ps
CPU time 14.67 seconds
Started Jun 22 04:39:30 PM PDT 24
Finished Jun 22 04:39:47 PM PDT 24
Peak memory 215296 kb
Host smart-8c0b39d0-6f39-4db4-835d-565c74988bb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347367738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1347367738
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4208120553
Short name T991
Test name
Test status
Simulation time 257158077 ps
CPU time 3.61 seconds
Started Jun 22 04:39:38 PM PDT 24
Finished Jun 22 04:39:44 PM PDT 24
Peak memory 217084 kb
Host smart-9c059ebd-c1c6-428a-9803-caf4fb9759e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208120553 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.4208120553
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2061811208
Short name T1065
Test name
Test status
Simulation time 67776643 ps
CPU time 1.34 seconds
Started Jun 22 04:39:54 PM PDT 24
Finished Jun 22 04:39:57 PM PDT 24
Peak memory 206984 kb
Host smart-4ba361df-6a32-4125-8b4d-1f7ae41d5671
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061811208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2061811208
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.9823940
Short name T1052
Test name
Test status
Simulation time 50228198 ps
CPU time 0.74 seconds
Started Jun 22 04:39:43 PM PDT 24
Finished Jun 22 04:39:45 PM PDT 24
Peak memory 203564 kb
Host smart-edec74bd-bdcc-4e71-8848-1f29e56d2149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9823940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.9823940
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2817667292
Short name T1031
Test name
Test status
Simulation time 170581957 ps
CPU time 4.03 seconds
Started Jun 22 04:39:35 PM PDT 24
Finished Jun 22 04:39:43 PM PDT 24
Peak memory 215248 kb
Host smart-43eee8cd-cc44-4f96-8977-325a04c55daf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817667292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2817667292
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4284823669
Short name T1072
Test name
Test status
Simulation time 71708264 ps
CPU time 4.03 seconds
Started Jun 22 04:39:34 PM PDT 24
Finished Jun 22 04:39:42 PM PDT 24
Peak memory 215264 kb
Host smart-b5269eff-1cd6-4b86-9b56-d7d43b40521c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284823669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
4284823669
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4177284960
Short name T164
Test name
Test status
Simulation time 1442374500 ps
CPU time 15.91 seconds
Started Jun 22 04:39:39 PM PDT 24
Finished Jun 22 04:39:57 PM PDT 24
Peak memory 215252 kb
Host smart-b01a6f92-0d3e-4f9f-aad7-747a43ba5413
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177284960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.4177284960
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.846285231
Short name T1078
Test name
Test status
Simulation time 144673837 ps
CPU time 2.5 seconds
Started Jun 22 04:39:36 PM PDT 24
Finished Jun 22 04:39:42 PM PDT 24
Peak memory 216468 kb
Host smart-06b535c1-4bb5-431a-9e28-3830ace81e63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846285231 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.846285231
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2443036060
Short name T1081
Test name
Test status
Simulation time 79921526 ps
CPU time 1.37 seconds
Started Jun 22 04:39:30 PM PDT 24
Finished Jun 22 04:39:34 PM PDT 24
Peak memory 206756 kb
Host smart-7c8dc936-59e1-425d-b066-3050692a1661
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443036060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2443036060
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.189793394
Short name T980
Test name
Test status
Simulation time 42572023 ps
CPU time 0.71 seconds
Started Jun 22 04:39:34 PM PDT 24
Finished Jun 22 04:39:38 PM PDT 24
Peak memory 203608 kb
Host smart-1d7d49fc-e3a2-4256-af05-1864d5f8c980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189793394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.189793394
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3493013145
Short name T1017
Test name
Test status
Simulation time 88789434 ps
CPU time 2.84 seconds
Started Jun 22 04:39:33 PM PDT 24
Finished Jun 22 04:39:39 PM PDT 24
Peak memory 215272 kb
Host smart-e9ff5b52-de00-4264-bdbc-8c83f70ffe33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493013145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3493013145
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3048578428
Short name T1045
Test name
Test status
Simulation time 200239022 ps
CPU time 1.73 seconds
Started Jun 22 04:39:44 PM PDT 24
Finished Jun 22 04:39:47 PM PDT 24
Peak memory 216368 kb
Host smart-25c9ab90-0040-4a6c-8d64-f5d2053c2961
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048578428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3048578428
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2866796162
Short name T162
Test name
Test status
Simulation time 439749592 ps
CPU time 7.46 seconds
Started Jun 22 04:39:30 PM PDT 24
Finished Jun 22 04:39:40 PM PDT 24
Peak memory 215000 kb
Host smart-16640ba1-cfa1-4d4d-a93b-1d9686cd66e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866796162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2866796162
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1449744635
Short name T141
Test name
Test status
Simulation time 1509254459 ps
CPU time 3.32 seconds
Started Jun 22 04:39:34 PM PDT 24
Finished Jun 22 04:39:41 PM PDT 24
Peak memory 217060 kb
Host smart-510af774-c63d-445e-b441-66e8fd2f709a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449744635 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1449744635
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1774142665
Short name T1053
Test name
Test status
Simulation time 44824159 ps
CPU time 1.18 seconds
Started Jun 22 04:39:34 PM PDT 24
Finished Jun 22 04:39:38 PM PDT 24
Peak memory 215260 kb
Host smart-1c1e3ec0-c9f9-41b2-b28d-4ead5672b691
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774142665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1774142665
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.53329516
Short name T985
Test name
Test status
Simulation time 93317861 ps
CPU time 0.7 seconds
Started Jun 22 04:39:52 PM PDT 24
Finished Jun 22 04:39:54 PM PDT 24
Peak memory 203956 kb
Host smart-483ada8e-ac13-4756-a1f2-64b262b60780
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53329516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.53329516
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.174144121
Short name T1044
Test name
Test status
Simulation time 211006746 ps
CPU time 3.15 seconds
Started Jun 22 04:39:33 PM PDT 24
Finished Jun 22 04:39:39 PM PDT 24
Peak memory 215208 kb
Host smart-9bcb35f0-7591-40f1-a7aa-172059760c8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174144121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.174144121
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1801687746
Short name T100
Test name
Test status
Simulation time 143306146 ps
CPU time 2.97 seconds
Started Jun 22 04:39:33 PM PDT 24
Finished Jun 22 04:39:44 PM PDT 24
Peak memory 216320 kb
Host smart-225570bb-9c27-4519-992e-53fadc11385c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801687746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1801687746
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.650693761
Short name T103
Test name
Test status
Simulation time 306121694 ps
CPU time 7.38 seconds
Started Jun 22 04:39:32 PM PDT 24
Finished Jun 22 04:39:42 PM PDT 24
Peak memory 215440 kb
Host smart-27443f22-3ecc-4da6-ae9f-642ada5444c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650693761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.650693761
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1659956132
Short name T1086
Test name
Test status
Simulation time 338464060 ps
CPU time 2.47 seconds
Started Jun 22 04:39:45 PM PDT 24
Finished Jun 22 04:39:48 PM PDT 24
Peak memory 216200 kb
Host smart-8ac8f983-b49d-4a43-a41a-38307598e512
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659956132 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1659956132
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.636258604
Short name T110
Test name
Test status
Simulation time 72520814 ps
CPU time 1.81 seconds
Started Jun 22 04:39:34 PM PDT 24
Finished Jun 22 04:39:40 PM PDT 24
Peak memory 214536 kb
Host smart-0d7eacd3-054b-4e05-bd8c-18b37c36e1a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636258604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.636258604
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.383634405
Short name T1038
Test name
Test status
Simulation time 225354246 ps
CPU time 0.81 seconds
Started Jun 22 04:39:37 PM PDT 24
Finished Jun 22 04:39:41 PM PDT 24
Peak memory 203948 kb
Host smart-04c13c1d-146d-4cd5-9a33-08b8933fccd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383634405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.383634405
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1520953198
Short name T1007
Test name
Test status
Simulation time 218510404 ps
CPU time 2.95 seconds
Started Jun 22 04:39:34 PM PDT 24
Finished Jun 22 04:39:40 PM PDT 24
Peak memory 215228 kb
Host smart-9ae8cf6f-b096-429a-b236-6fb9bfc115a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520953198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1520953198
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.379932291
Short name T160
Test name
Test status
Simulation time 161765471 ps
CPU time 3.01 seconds
Started Jun 22 04:39:35 PM PDT 24
Finished Jun 22 04:39:42 PM PDT 24
Peak memory 215504 kb
Host smart-e12cc430-5668-447b-8479-dcb35bfeedb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379932291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.379932291
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.451879181
Short name T163
Test name
Test status
Simulation time 724777077 ps
CPU time 15.15 seconds
Started Jun 22 04:39:43 PM PDT 24
Finished Jun 22 04:39:59 PM PDT 24
Peak memory 215432 kb
Host smart-c97518cf-8ef7-40c2-9f56-84b2027063bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451879181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.451879181
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.87932586
Short name T1040
Test name
Test status
Simulation time 186853941 ps
CPU time 1.7 seconds
Started Jun 22 04:40:03 PM PDT 24
Finished Jun 22 04:40:07 PM PDT 24
Peak memory 215284 kb
Host smart-01190681-9993-49a8-b9ef-46bb4152ab72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87932586 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.87932586
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3721218617
Short name T1014
Test name
Test status
Simulation time 22986983 ps
CPU time 1.43 seconds
Started Jun 22 04:39:40 PM PDT 24
Finished Jun 22 04:39:43 PM PDT 24
Peak memory 206904 kb
Host smart-96c90647-6ee7-4f0d-ba4b-573a17256a0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721218617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3721218617
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.319642998
Short name T1068
Test name
Test status
Simulation time 19206388 ps
CPU time 0.78 seconds
Started Jun 22 04:39:48 PM PDT 24
Finished Jun 22 04:39:49 PM PDT 24
Peak memory 203700 kb
Host smart-94c42aab-b30f-4af4-870e-311e8b6f16a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319642998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.319642998
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3914038414
Short name T1042
Test name
Test status
Simulation time 82267119 ps
CPU time 2.8 seconds
Started Jun 22 04:39:53 PM PDT 24
Finished Jun 22 04:39:56 PM PDT 24
Peak memory 215268 kb
Host smart-48fcd573-eba7-49d1-b80e-fc057fe52fc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914038414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3914038414
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.769075324
Short name T1037
Test name
Test status
Simulation time 360891189 ps
CPU time 4.48 seconds
Started Jun 22 04:39:33 PM PDT 24
Finished Jun 22 04:39:41 PM PDT 24
Peak memory 215516 kb
Host smart-1d7f1267-ae39-4deb-932e-e3f131922737
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769075324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.769075324
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.278484354
Short name T1049
Test name
Test status
Simulation time 195936697 ps
CPU time 11.76 seconds
Started Jun 22 04:39:49 PM PDT 24
Finished Jun 22 04:40:01 PM PDT 24
Peak memory 215532 kb
Host smart-b008671f-320b-487b-8c5c-12e420a92cba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278484354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.278484354
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2358441957
Short name T1071
Test name
Test status
Simulation time 199133071 ps
CPU time 3.12 seconds
Started Jun 22 04:39:52 PM PDT 24
Finished Jun 22 04:39:56 PM PDT 24
Peak memory 216916 kb
Host smart-d11a74cc-10c8-4fcc-a473-b122bdb12f14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358441957 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2358441957
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1007200935
Short name T113
Test name
Test status
Simulation time 344525498 ps
CPU time 2.04 seconds
Started Jun 22 04:39:35 PM PDT 24
Finished Jun 22 04:39:40 PM PDT 24
Peak memory 207024 kb
Host smart-b4196531-19ab-41ba-91e8-f8fd8967e7b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007200935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1007200935
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3165473804
Short name T984
Test name
Test status
Simulation time 17290373 ps
CPU time 0.79 seconds
Started Jun 22 04:39:34 PM PDT 24
Finished Jun 22 04:39:38 PM PDT 24
Peak memory 203588 kb
Host smart-ccfd9abb-0b33-46f1-95ad-83c392f62729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165473804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3165473804
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.746766016
Short name T997
Test name
Test status
Simulation time 492002288 ps
CPU time 1.74 seconds
Started Jun 22 04:40:03 PM PDT 24
Finished Jun 22 04:40:07 PM PDT 24
Peak memory 215268 kb
Host smart-3f75b614-91ce-43ae-b9fe-836fdcda9376
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746766016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.746766016
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1077772135
Short name T1093
Test name
Test status
Simulation time 211060792 ps
CPU time 3.52 seconds
Started Jun 22 04:39:31 PM PDT 24
Finished Jun 22 04:39:37 PM PDT 24
Peak memory 215348 kb
Host smart-436d9923-811f-4cd2-8970-b11a0285f152
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077772135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1077772135
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.178646721
Short name T1058
Test name
Test status
Simulation time 331706836 ps
CPU time 21.41 seconds
Started Jun 22 04:39:29 PM PDT 24
Finished Jun 22 04:39:51 PM PDT 24
Peak memory 215172 kb
Host smart-a3488049-28e0-4efd-aedd-cafbda3e1548
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178646721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.178646721
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.944669462
Short name T115
Test name
Test status
Simulation time 9374616413 ps
CPU time 35.23 seconds
Started Jun 22 04:39:28 PM PDT 24
Finished Jun 22 04:40:04 PM PDT 24
Peak memory 207072 kb
Host smart-f18fcdcd-fb6a-49f3-8cb1-7633549d5931
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944669462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.944669462
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3637815508
Short name T111
Test name
Test status
Simulation time 279097402 ps
CPU time 1.25 seconds
Started Jun 22 04:39:23 PM PDT 24
Finished Jun 22 04:39:25 PM PDT 24
Peak memory 206872 kb
Host smart-cd050366-81fa-4446-bdb2-de0acb2ac669
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637815508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3637815508
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.389709187
Short name T102
Test name
Test status
Simulation time 88972728 ps
CPU time 1.79 seconds
Started Jun 22 04:39:41 PM PDT 24
Finished Jun 22 04:39:44 PM PDT 24
Peak memory 215316 kb
Host smart-17571961-5b36-4101-bdb9-66e44853146b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389709187 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.389709187
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3522833957
Short name T1063
Test name
Test status
Simulation time 222221280 ps
CPU time 2.69 seconds
Started Jun 22 04:39:26 PM PDT 24
Finished Jun 22 04:39:30 PM PDT 24
Peak memory 215224 kb
Host smart-22e432e7-d022-4c62-9ed7-7080f5de0c17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522833957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
522833957
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1389961410
Short name T1070
Test name
Test status
Simulation time 17402692 ps
CPU time 0.78 seconds
Started Jun 22 04:39:32 PM PDT 24
Finished Jun 22 04:39:36 PM PDT 24
Peak memory 203696 kb
Host smart-4b0dc53b-02c3-4ca9-b1ab-d9bf7ecdb58f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389961410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
389961410
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4273780222
Short name T1039
Test name
Test status
Simulation time 146090993 ps
CPU time 1.3 seconds
Started Jun 22 04:39:29 PM PDT 24
Finished Jun 22 04:39:32 PM PDT 24
Peak memory 215256 kb
Host smart-e55de6dc-3f45-4d5d-8962-c889a589114a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273780222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.4273780222
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2855113313
Short name T1003
Test name
Test status
Simulation time 31276306 ps
CPU time 0.65 seconds
Started Jun 22 04:39:30 PM PDT 24
Finished Jun 22 04:39:33 PM PDT 24
Peak memory 203448 kb
Host smart-550ea3e9-698a-4c0a-9b60-da2083dd55c0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855113313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2855113313
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3112779198
Short name T1083
Test name
Test status
Simulation time 227976363 ps
CPU time 1.74 seconds
Started Jun 22 04:39:28 PM PDT 24
Finished Jun 22 04:39:32 PM PDT 24
Peak memory 215632 kb
Host smart-d2489808-2b83-4754-b9cc-b0b7fd2a51c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112779198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3112779198
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1592471985
Short name T94
Test name
Test status
Simulation time 184179610 ps
CPU time 4.25 seconds
Started Jun 22 04:39:29 PM PDT 24
Finished Jun 22 04:39:35 PM PDT 24
Peak memory 215476 kb
Host smart-32b94422-89e4-41ee-aa9c-699a6134cf4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592471985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
592471985
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3828407568
Short name T169
Test name
Test status
Simulation time 732959976 ps
CPU time 15.46 seconds
Started Jun 22 04:39:45 PM PDT 24
Finished Jun 22 04:40:01 PM PDT 24
Peak memory 215516 kb
Host smart-3675e0a9-b83e-4c66-92a6-e3c26ce2a5ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828407568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3828407568
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2141397531
Short name T1011
Test name
Test status
Simulation time 32342408 ps
CPU time 0.69 seconds
Started Jun 22 04:39:36 PM PDT 24
Finished Jun 22 04:39:40 PM PDT 24
Peak memory 203584 kb
Host smart-eaa246fa-72dc-4cfd-adc9-879ba2b96eee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141397531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2141397531
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2711231489
Short name T1075
Test name
Test status
Simulation time 104343436 ps
CPU time 0.73 seconds
Started Jun 22 04:39:33 PM PDT 24
Finished Jun 22 04:39:37 PM PDT 24
Peak memory 203580 kb
Host smart-2af5ca3b-4ee8-451e-80c9-f5e7b2564c53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711231489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2711231489
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3536979425
Short name T1087
Test name
Test status
Simulation time 36896706 ps
CPU time 0.76 seconds
Started Jun 22 04:39:34 PM PDT 24
Finished Jun 22 04:39:39 PM PDT 24
Peak memory 203560 kb
Host smart-a9f53d09-3b46-4879-94b3-4080dbb8ce7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536979425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3536979425
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3944588679
Short name T1057
Test name
Test status
Simulation time 72555343 ps
CPU time 0.74 seconds
Started Jun 22 04:39:35 PM PDT 24
Finished Jun 22 04:39:40 PM PDT 24
Peak memory 203660 kb
Host smart-f28f99f0-7193-4e8d-bb7a-62241ada1295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944588679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3944588679
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4220252124
Short name T1043
Test name
Test status
Simulation time 181415975 ps
CPU time 0.72 seconds
Started Jun 22 04:39:35 PM PDT 24
Finished Jun 22 04:39:40 PM PDT 24
Peak memory 203996 kb
Host smart-c9456d03-af7c-4277-b6e8-3e4596cce257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220252124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
4220252124
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2133878501
Short name T988
Test name
Test status
Simulation time 16178819 ps
CPU time 0.72 seconds
Started Jun 22 04:39:40 PM PDT 24
Finished Jun 22 04:39:42 PM PDT 24
Peak memory 203648 kb
Host smart-bb6e87b7-30bf-4f82-b696-54988cef029a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133878501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2133878501
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2168080618
Short name T983
Test name
Test status
Simulation time 13926929 ps
CPU time 0.72 seconds
Started Jun 22 04:39:59 PM PDT 24
Finished Jun 22 04:40:02 PM PDT 24
Peak memory 203660 kb
Host smart-fe4aea3b-fbdb-4f5c-ab3d-45b4bdd59eaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168080618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2168080618
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3478622177
Short name T1005
Test name
Test status
Simulation time 21719549 ps
CPU time 0.71 seconds
Started Jun 22 04:39:55 PM PDT 24
Finished Jun 22 04:39:57 PM PDT 24
Peak memory 203832 kb
Host smart-dc830c24-19d6-4f02-8106-4006ab4cf6ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478622177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3478622177
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.357453041
Short name T1060
Test name
Test status
Simulation time 22505977 ps
CPU time 0.68 seconds
Started Jun 22 04:39:50 PM PDT 24
Finished Jun 22 04:39:52 PM PDT 24
Peak memory 203568 kb
Host smart-0255b6f5-b5fa-40ef-931b-6fd8cbce25ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357453041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.357453041
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4136358611
Short name T989
Test name
Test status
Simulation time 19373303 ps
CPU time 0.67 seconds
Started Jun 22 04:39:47 PM PDT 24
Finished Jun 22 04:39:48 PM PDT 24
Peak memory 203484 kb
Host smart-11542c9f-8715-4d8a-9bb1-5323fda3bfa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136358611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
4136358611
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1468515222
Short name T107
Test name
Test status
Simulation time 4144218234 ps
CPU time 22.38 seconds
Started Jun 22 04:39:32 PM PDT 24
Finished Jun 22 04:39:57 PM PDT 24
Peak memory 216292 kb
Host smart-56488a23-e778-4e50-b861-e73b13cac09d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468515222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1468515222
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1713423479
Short name T1046
Test name
Test status
Simulation time 4331978946 ps
CPU time 23.7 seconds
Started Jun 22 04:39:30 PM PDT 24
Finished Jun 22 04:39:55 PM PDT 24
Peak memory 207132 kb
Host smart-523fedd5-00a7-4d9a-8689-00ea629323ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713423479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1713423479
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2069282304
Short name T1061
Test name
Test status
Simulation time 267252298 ps
CPU time 1.62 seconds
Started Jun 22 04:39:36 PM PDT 24
Finished Jun 22 04:39:41 PM PDT 24
Peak memory 215344 kb
Host smart-59ea118b-20d9-4386-9001-c509d577838b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069282304 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2069282304
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3857964303
Short name T1082
Test name
Test status
Simulation time 151966670 ps
CPU time 2.63 seconds
Started Jun 22 04:39:22 PM PDT 24
Finished Jun 22 04:39:26 PM PDT 24
Peak memory 215144 kb
Host smart-8d1f9655-b8c5-4030-ac74-c2c5e333e180
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857964303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
857964303
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.752137377
Short name T1026
Test name
Test status
Simulation time 15287291 ps
CPU time 0.76 seconds
Started Jun 22 04:39:33 PM PDT 24
Finished Jun 22 04:39:36 PM PDT 24
Peak memory 203700 kb
Host smart-60d42ab6-7d00-4dfc-ae78-389ac78ef429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752137377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.752137377
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2079000551
Short name T1099
Test name
Test status
Simulation time 55478569 ps
CPU time 1.19 seconds
Started Jun 22 04:39:28 PM PDT 24
Finished Jun 22 04:39:30 PM PDT 24
Peak memory 215288 kb
Host smart-4c227c87-6250-49cb-906d-38279fb62316
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079000551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2079000551
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.543548292
Short name T1041
Test name
Test status
Simulation time 39969334 ps
CPU time 0.66 seconds
Started Jun 22 04:39:30 PM PDT 24
Finished Jun 22 04:39:32 PM PDT 24
Peak memory 203536 kb
Host smart-1937a2da-5643-4e74-9b1f-730d9acb0f29
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543548292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.543548292
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2723140470
Short name T133
Test name
Test status
Simulation time 88799223 ps
CPU time 2.86 seconds
Started Jun 22 04:39:25 PM PDT 24
Finished Jun 22 04:39:30 PM PDT 24
Peak memory 215028 kb
Host smart-08f80c23-fc36-4f6a-bdf7-7e7c26d93590
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723140470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2723140470
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2215208429
Short name T171
Test name
Test status
Simulation time 826706079 ps
CPU time 19.11 seconds
Started Jun 22 04:39:34 PM PDT 24
Finished Jun 22 04:39:57 PM PDT 24
Peak memory 215284 kb
Host smart-ed6b5356-6eed-44c2-819c-5ff4c4ae5476
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215208429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2215208429
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2925704591
Short name T1024
Test name
Test status
Simulation time 14508275 ps
CPU time 0.7 seconds
Started Jun 22 04:39:36 PM PDT 24
Finished Jun 22 04:39:40 PM PDT 24
Peak memory 203564 kb
Host smart-6c3a4ac0-fa8f-486c-8df7-dcda22e08cb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925704591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2925704591
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.189212652
Short name T979
Test name
Test status
Simulation time 21997605 ps
CPU time 0.72 seconds
Started Jun 22 04:39:55 PM PDT 24
Finished Jun 22 04:39:57 PM PDT 24
Peak memory 203540 kb
Host smart-4fa17767-07a5-443c-91b0-c8d2864869b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189212652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.189212652
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2426480608
Short name T1006
Test name
Test status
Simulation time 39037675 ps
CPU time 0.73 seconds
Started Jun 22 04:39:35 PM PDT 24
Finished Jun 22 04:39:40 PM PDT 24
Peak memory 203964 kb
Host smart-690c1da0-74dc-4cea-b8e2-7aadd7715351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426480608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2426480608
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1051401345
Short name T1074
Test name
Test status
Simulation time 59220595 ps
CPU time 0.76 seconds
Started Jun 22 04:39:35 PM PDT 24
Finished Jun 22 04:39:39 PM PDT 24
Peak memory 203584 kb
Host smart-2d3fa5f7-6f2f-4a88-85d9-8dd240800c1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051401345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1051401345
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.89978961
Short name T1051
Test name
Test status
Simulation time 33876588 ps
CPU time 0.73 seconds
Started Jun 22 04:39:53 PM PDT 24
Finished Jun 22 04:39:54 PM PDT 24
Peak memory 203876 kb
Host smart-01a33ff0-b94a-4489-ae2e-7eb6a421b721
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89978961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.89978961
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2610194593
Short name T1002
Test name
Test status
Simulation time 15390829 ps
CPU time 0.75 seconds
Started Jun 22 04:40:05 PM PDT 24
Finished Jun 22 04:40:07 PM PDT 24
Peak memory 203588 kb
Host smart-6fd00f23-2509-4807-9c07-42a3ea94e729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610194593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2610194593
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2210763079
Short name T990
Test name
Test status
Simulation time 11829221 ps
CPU time 0.75 seconds
Started Jun 22 04:39:40 PM PDT 24
Finished Jun 22 04:39:42 PM PDT 24
Peak memory 203600 kb
Host smart-1a0b978a-4dac-4ceb-98a1-a6cc5ff8ca23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210763079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2210763079
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2432791
Short name T982
Test name
Test status
Simulation time 12332732 ps
CPU time 0.72 seconds
Started Jun 22 04:39:48 PM PDT 24
Finished Jun 22 04:39:50 PM PDT 24
Peak memory 203488 kb
Host smart-20416799-e31a-4081-b914-c0b1e1ebf284
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.2432791
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.611491222
Short name T1069
Test name
Test status
Simulation time 51181358 ps
CPU time 0.73 seconds
Started Jun 22 04:39:57 PM PDT 24
Finished Jun 22 04:40:00 PM PDT 24
Peak memory 203596 kb
Host smart-0d95cf42-9868-4076-b9e7-03e23a15e9e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611491222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.611491222
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1785709363
Short name T1019
Test name
Test status
Simulation time 17164836 ps
CPU time 0.75 seconds
Started Jun 22 04:39:47 PM PDT 24
Finished Jun 22 04:39:49 PM PDT 24
Peak memory 203584 kb
Host smart-752bb809-6229-447e-ab9b-d85e870bf6ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785709363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1785709363
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2480486657
Short name T1047
Test name
Test status
Simulation time 376485924 ps
CPU time 8.26 seconds
Started Jun 22 04:39:34 PM PDT 24
Finished Jun 22 04:39:46 PM PDT 24
Peak memory 214484 kb
Host smart-6dc5f723-73fb-4f16-8de9-3c78f2ab2326
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480486657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2480486657
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.236782340
Short name T117
Test name
Test status
Simulation time 3272721541 ps
CPU time 34.26 seconds
Started Jun 22 04:39:32 PM PDT 24
Finished Jun 22 04:40:09 PM PDT 24
Peak memory 215520 kb
Host smart-515d879e-0ba5-4082-a0f3-70cb4dacd652
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236782340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.236782340
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2058384100
Short name T79
Test name
Test status
Simulation time 168069959 ps
CPU time 1.18 seconds
Started Jun 22 04:39:25 PM PDT 24
Finished Jun 22 04:39:27 PM PDT 24
Peak memory 216236 kb
Host smart-f4fe5830-e52d-4c6b-ac2c-bb90cb42b2dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058384100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2058384100
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.360276564
Short name T1062
Test name
Test status
Simulation time 634165715 ps
CPU time 3.69 seconds
Started Jun 22 04:39:27 PM PDT 24
Finished Jun 22 04:39:32 PM PDT 24
Peak memory 216664 kb
Host smart-b701942e-57d4-4ff7-9105-4551415555ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360276564 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.360276564
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2358943138
Short name T1013
Test name
Test status
Simulation time 43326316 ps
CPU time 1.38 seconds
Started Jun 22 04:39:24 PM PDT 24
Finished Jun 22 04:39:26 PM PDT 24
Peak memory 207040 kb
Host smart-f46e7ec2-897c-4bce-b3c7-b9344490a1ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358943138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
358943138
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3726587995
Short name T1008
Test name
Test status
Simulation time 116570143 ps
CPU time 0.7 seconds
Started Jun 22 04:39:30 PM PDT 24
Finished Jun 22 04:39:33 PM PDT 24
Peak memory 203676 kb
Host smart-82cb7d43-242f-48b9-ac2f-4d624e856813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726587995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
726587995
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1688875105
Short name T112
Test name
Test status
Simulation time 176985676 ps
CPU time 1.91 seconds
Started Jun 22 04:39:31 PM PDT 24
Finished Jun 22 04:39:36 PM PDT 24
Peak memory 215240 kb
Host smart-7eb30632-40c1-4497-a54d-87b59829cb70
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688875105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1688875105
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.845792818
Short name T1036
Test name
Test status
Simulation time 93202992 ps
CPU time 0.64 seconds
Started Jun 22 04:39:47 PM PDT 24
Finished Jun 22 04:39:48 PM PDT 24
Peak memory 203456 kb
Host smart-5ab483d6-d430-4e08-8f5a-1bfc34a9db65
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845792818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.845792818
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1557268925
Short name T1035
Test name
Test status
Simulation time 276922461 ps
CPU time 3.23 seconds
Started Jun 22 04:39:19 PM PDT 24
Finished Jun 22 04:39:23 PM PDT 24
Peak memory 215248 kb
Host smart-8da561c1-09f2-49e5-ba3c-8bd08429fb14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557268925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1557268925
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3011379543
Short name T1090
Test name
Test status
Simulation time 166779443 ps
CPU time 4.22 seconds
Started Jun 22 04:39:27 PM PDT 24
Finished Jun 22 04:39:32 PM PDT 24
Peak memory 216380 kb
Host smart-cd886ab3-a07f-4ab6-b349-74b12348173b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011379543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
011379543
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.810674434
Short name T994
Test name
Test status
Simulation time 45153697 ps
CPU time 0.72 seconds
Started Jun 22 04:39:36 PM PDT 24
Finished Jun 22 04:39:43 PM PDT 24
Peak memory 203660 kb
Host smart-5d3cd274-46aa-457f-ac9f-a2699bab0db8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810674434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.810674434
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.895978512
Short name T1101
Test name
Test status
Simulation time 50697471 ps
CPU time 0.77 seconds
Started Jun 22 04:39:38 PM PDT 24
Finished Jun 22 04:39:41 PM PDT 24
Peak memory 203668 kb
Host smart-0fdc739f-a6b9-488a-87f5-28b1c72d97b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895978512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.895978512
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1534976943
Short name T1077
Test name
Test status
Simulation time 11400850 ps
CPU time 0.74 seconds
Started Jun 22 04:39:50 PM PDT 24
Finished Jun 22 04:39:52 PM PDT 24
Peak memory 203588 kb
Host smart-badd9787-9e05-4d49-bfe4-5675bc330e36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534976943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1534976943
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1654905596
Short name T1092
Test name
Test status
Simulation time 14536630 ps
CPU time 0.7 seconds
Started Jun 22 04:39:50 PM PDT 24
Finished Jun 22 04:39:52 PM PDT 24
Peak memory 203492 kb
Host smart-d6af4458-4f68-43d7-9014-7ab0ec15ca4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654905596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1654905596
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1494284861
Short name T1009
Test name
Test status
Simulation time 43296658 ps
CPU time 0.71 seconds
Started Jun 22 04:39:32 PM PDT 24
Finished Jun 22 04:39:36 PM PDT 24
Peak memory 202952 kb
Host smart-c5e67265-25ac-4c0a-a9de-e09f115714cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494284861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1494284861
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4243301370
Short name T996
Test name
Test status
Simulation time 18789197 ps
CPU time 0.76 seconds
Started Jun 22 04:39:54 PM PDT 24
Finished Jun 22 04:39:56 PM PDT 24
Peak memory 203916 kb
Host smart-030782b7-c789-4110-a535-efd0fc36a84f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243301370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
4243301370
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3782988193
Short name T1050
Test name
Test status
Simulation time 26763294 ps
CPU time 0.69 seconds
Started Jun 22 04:40:03 PM PDT 24
Finished Jun 22 04:40:06 PM PDT 24
Peak memory 203504 kb
Host smart-5186cbc4-ab4d-4a99-b8b2-584adcfa9c8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782988193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3782988193
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.129258725
Short name T1032
Test name
Test status
Simulation time 14193071 ps
CPU time 0.71 seconds
Started Jun 22 04:39:36 PM PDT 24
Finished Jun 22 04:39:40 PM PDT 24
Peak memory 203616 kb
Host smart-b5fde9c4-8b0c-4ba4-b985-04a97fbafece
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129258725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.129258725
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3508452920
Short name T1028
Test name
Test status
Simulation time 137657012 ps
CPU time 0.74 seconds
Started Jun 22 04:39:33 PM PDT 24
Finished Jun 22 04:39:37 PM PDT 24
Peak memory 203928 kb
Host smart-45a118d7-6be5-4ae3-8cb8-a461f57698df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508452920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3508452920
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.4125736739
Short name T1018
Test name
Test status
Simulation time 44432811 ps
CPU time 0.77 seconds
Started Jun 22 04:39:50 PM PDT 24
Finished Jun 22 04:39:51 PM PDT 24
Peak memory 203584 kb
Host smart-b41b23b4-85e3-47f1-adc9-856418e9e8a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125736739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
4125736739
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3985394674
Short name T101
Test name
Test status
Simulation time 106071164 ps
CPU time 3.59 seconds
Started Jun 22 04:39:26 PM PDT 24
Finished Jun 22 04:39:31 PM PDT 24
Peak memory 217180 kb
Host smart-03296c98-0464-4b97-bb1d-e2d3806ab492
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985394674 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3985394674
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.633702237
Short name T118
Test name
Test status
Simulation time 57564319 ps
CPU time 1.95 seconds
Started Jun 22 04:39:24 PM PDT 24
Finished Jun 22 04:39:26 PM PDT 24
Peak memory 206996 kb
Host smart-fc4f941c-f572-4011-b809-257650a82a8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633702237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.633702237
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2021636592
Short name T1066
Test name
Test status
Simulation time 29665452 ps
CPU time 0.72 seconds
Started Jun 22 04:39:35 PM PDT 24
Finished Jun 22 04:39:39 PM PDT 24
Peak memory 203616 kb
Host smart-8197da24-1819-4291-a1f0-86e4fe3ec075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021636592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
021636592
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2904979271
Short name T1029
Test name
Test status
Simulation time 286846961 ps
CPU time 3.06 seconds
Started Jun 22 04:39:26 PM PDT 24
Finished Jun 22 04:39:30 PM PDT 24
Peak memory 215180 kb
Host smart-f2ff8fd8-ce28-4fab-bea5-4731d43bee59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904979271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2904979271
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3110843816
Short name T90
Test name
Test status
Simulation time 131605079 ps
CPU time 3.64 seconds
Started Jun 22 04:39:29 PM PDT 24
Finished Jun 22 04:39:34 PM PDT 24
Peak memory 215440 kb
Host smart-b38e91c2-278b-4788-929f-a763d7c274a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110843816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
110843816
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4088289511
Short name T170
Test name
Test status
Simulation time 848886389 ps
CPU time 21.37 seconds
Started Jun 22 04:39:29 PM PDT 24
Finished Jun 22 04:39:52 PM PDT 24
Peak memory 215328 kb
Host smart-e88441c4-3e4e-4ef9-939d-ade61a3b48bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088289511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.4088289511
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.894298325
Short name T1098
Test name
Test status
Simulation time 382897207 ps
CPU time 2.62 seconds
Started Jun 22 04:39:48 PM PDT 24
Finished Jun 22 04:39:51 PM PDT 24
Peak memory 216736 kb
Host smart-531ddbd8-ef86-4570-8885-61d696e7693e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894298325 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.894298325
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.765904167
Short name T1091
Test name
Test status
Simulation time 110466405 ps
CPU time 1.96 seconds
Started Jun 22 04:39:53 PM PDT 24
Finished Jun 22 04:39:56 PM PDT 24
Peak memory 215304 kb
Host smart-0f540f76-d34f-4cdf-8b0f-ce231ed3d464
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765904167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.765904167
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.499401109
Short name T1085
Test name
Test status
Simulation time 24353827 ps
CPU time 0.67 seconds
Started Jun 22 04:39:31 PM PDT 24
Finished Jun 22 04:39:34 PM PDT 24
Peak memory 203624 kb
Host smart-4a4467bf-0235-4b23-954d-fb7e4aae4d24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499401109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.499401109
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1325475722
Short name T1015
Test name
Test status
Simulation time 63191011 ps
CPU time 3.69 seconds
Started Jun 22 04:39:31 PM PDT 24
Finished Jun 22 04:39:38 PM PDT 24
Peak memory 215180 kb
Host smart-6f724767-60db-401b-86f9-30d7897120fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325475722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1325475722
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3093417532
Short name T992
Test name
Test status
Simulation time 318103727 ps
CPU time 2.27 seconds
Started Jun 22 04:39:21 PM PDT 24
Finished Jun 22 04:39:25 PM PDT 24
Peak memory 216456 kb
Host smart-b8896934-2471-4784-b54f-5439b035f183
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093417532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
093417532
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.4093386608
Short name T161
Test name
Test status
Simulation time 1504616562 ps
CPU time 7.35 seconds
Started Jun 22 04:39:30 PM PDT 24
Finished Jun 22 04:39:39 PM PDT 24
Peak memory 215248 kb
Host smart-dbc9ccc6-770f-44f2-aa7b-e682a8122909
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093386608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.4093386608
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2873575097
Short name T1048
Test name
Test status
Simulation time 185699875 ps
CPU time 1.67 seconds
Started Jun 22 04:39:32 PM PDT 24
Finished Jun 22 04:39:37 PM PDT 24
Peak memory 215224 kb
Host smart-e46282dd-c9f0-44ea-bf2f-ccefa226ffc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873575097 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2873575097
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.590187414
Short name T1025
Test name
Test status
Simulation time 2061939410 ps
CPU time 2.74 seconds
Started Jun 22 04:39:41 PM PDT 24
Finished Jun 22 04:39:45 PM PDT 24
Peak memory 215228 kb
Host smart-381cf29b-0e1a-4f67-b9da-a50375866896
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590187414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.590187414
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1209100614
Short name T981
Test name
Test status
Simulation time 12651883 ps
CPU time 0.68 seconds
Started Jun 22 04:39:33 PM PDT 24
Finished Jun 22 04:39:36 PM PDT 24
Peak memory 203644 kb
Host smart-013d029a-0536-490c-8b49-f73f4bf5df1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209100614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
209100614
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1242549133
Short name T1030
Test name
Test status
Simulation time 28985854 ps
CPU time 1.69 seconds
Started Jun 22 04:39:29 PM PDT 24
Finished Jun 22 04:39:32 PM PDT 24
Peak memory 206920 kb
Host smart-b08246cb-923f-4d60-9753-90b2553a20d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242549133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1242549133
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1355329925
Short name T97
Test name
Test status
Simulation time 155668349 ps
CPU time 3.68 seconds
Started Jun 22 04:39:31 PM PDT 24
Finished Jun 22 04:39:37 PM PDT 24
Peak memory 215316 kb
Host smart-9cd45d61-d850-4dbd-b134-f97833e14f64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355329925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
355329925
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4078626957
Short name T165
Test name
Test status
Simulation time 1186909296 ps
CPU time 21.19 seconds
Started Jun 22 04:39:39 PM PDT 24
Finished Jun 22 04:40:02 PM PDT 24
Peak memory 215416 kb
Host smart-2957bcd5-fff3-49d2-9cdb-34b69e146710
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078626957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.4078626957
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.456354596
Short name T1034
Test name
Test status
Simulation time 212560283 ps
CPU time 1.67 seconds
Started Jun 22 04:39:31 PM PDT 24
Finished Jun 22 04:39:36 PM PDT 24
Peak memory 216348 kb
Host smart-c976cb7e-5c25-4218-b52e-d979baf1a579
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456354596 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.456354596
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2603728817
Short name T1067
Test name
Test status
Simulation time 85229879 ps
CPU time 2.1 seconds
Started Jun 22 04:39:44 PM PDT 24
Finished Jun 22 04:39:46 PM PDT 24
Peak memory 215212 kb
Host smart-a9657d75-6e05-4848-b4fb-f0b266b9409d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603728817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
603728817
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2498235925
Short name T999
Test name
Test status
Simulation time 26800994 ps
CPU time 0.71 seconds
Started Jun 22 04:39:25 PM PDT 24
Finished Jun 22 04:39:27 PM PDT 24
Peak memory 203540 kb
Host smart-361b4760-ce5d-4308-b0c8-13d10b67569d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498235925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
498235925
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2298593749
Short name T134
Test name
Test status
Simulation time 237276666 ps
CPU time 2.6 seconds
Started Jun 22 04:39:34 PM PDT 24
Finished Jun 22 04:39:40 PM PDT 24
Peak memory 215220 kb
Host smart-97f720db-0c45-4a59-ac09-8a7b35890c8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298593749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2298593749
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.203791792
Short name T88
Test name
Test status
Simulation time 846818351 ps
CPU time 4.22 seconds
Started Jun 22 04:39:29 PM PDT 24
Finished Jun 22 04:39:35 PM PDT 24
Peak memory 216484 kb
Host smart-270696fb-2228-47ff-bd4a-87c81d1db22d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203791792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.203791792
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1755930902
Short name T91
Test name
Test status
Simulation time 921271430 ps
CPU time 20.64 seconds
Started Jun 22 04:39:38 PM PDT 24
Finished Jun 22 04:40:01 PM PDT 24
Peak memory 215472 kb
Host smart-2267cf08-731a-4084-8ac2-4b00fe99e1b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755930902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1755930902
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3456615719
Short name T143
Test name
Test status
Simulation time 150499174 ps
CPU time 3.44 seconds
Started Jun 22 04:39:33 PM PDT 24
Finished Jun 22 04:39:39 PM PDT 24
Peak memory 217832 kb
Host smart-23a40e87-71b3-4599-9f2f-a4f24829b942
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456615719 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3456615719
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.932908770
Short name T108
Test name
Test status
Simulation time 113015960 ps
CPU time 2.76 seconds
Started Jun 22 04:39:33 PM PDT 24
Finished Jun 22 04:39:38 PM PDT 24
Peak memory 215236 kb
Host smart-4c37ebff-1081-4e84-8522-8d2486c1dc89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932908770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.932908770
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1747304094
Short name T978
Test name
Test status
Simulation time 15341966 ps
CPU time 0.68 seconds
Started Jun 22 04:39:40 PM PDT 24
Finished Jun 22 04:39:42 PM PDT 24
Peak memory 203876 kb
Host smart-265bcaf2-b999-4a29-a83e-b0209829b643
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747304094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
747304094
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2552219466
Short name T1096
Test name
Test status
Simulation time 287589397 ps
CPU time 1.87 seconds
Started Jun 22 04:39:30 PM PDT 24
Finished Jun 22 04:39:33 PM PDT 24
Peak memory 215280 kb
Host smart-6d4ad119-4ab3-4d80-9d88-f94a63d79d1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552219466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2552219466
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.99957161
Short name T96
Test name
Test status
Simulation time 1495650502 ps
CPU time 4.64 seconds
Started Jun 22 04:39:42 PM PDT 24
Finished Jun 22 04:39:48 PM PDT 24
Peak memory 215292 kb
Host smart-afe2394c-5db5-422d-bf35-8077c525a05b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99957161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.99957161
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3590337375
Short name T93
Test name
Test status
Simulation time 980258891 ps
CPU time 20.67 seconds
Started Jun 22 04:39:32 PM PDT 24
Finished Jun 22 04:39:55 PM PDT 24
Peak memory 215304 kb
Host smart-4bed1872-8dde-4e59-8899-71946a465f3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590337375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3590337375
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3042147756
Short name T684
Test name
Test status
Simulation time 59405978 ps
CPU time 0.77 seconds
Started Jun 22 05:17:43 PM PDT 24
Finished Jun 22 05:17:45 PM PDT 24
Peak memory 205716 kb
Host smart-32ecf19b-3337-4103-9592-91f797b7bfc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042147756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
042147756
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2845750284
Short name T454
Test name
Test status
Simulation time 1002439083 ps
CPU time 3.75 seconds
Started Jun 22 05:17:33 PM PDT 24
Finished Jun 22 05:17:38 PM PDT 24
Peak memory 233732 kb
Host smart-65ad97dc-02b4-4112-b1fe-f82ce20218fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845750284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2845750284
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2229297542
Short name T914
Test name
Test status
Simulation time 18661731 ps
CPU time 0.76 seconds
Started Jun 22 05:17:42 PM PDT 24
Finished Jun 22 05:17:44 PM PDT 24
Peak memory 206452 kb
Host smart-ea5fb4ee-2fb3-4b78-b183-b2322a485cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229297542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2229297542
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1343811885
Short name T484
Test name
Test status
Simulation time 37300345674 ps
CPU time 73.48 seconds
Started Jun 22 05:17:44 PM PDT 24
Finished Jun 22 05:18:58 PM PDT 24
Peak memory 250432 kb
Host smart-3042287d-1273-46dd-884a-d03ff3cc159e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343811885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1343811885
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2517417435
Short name T663
Test name
Test status
Simulation time 7260051372 ps
CPU time 85.05 seconds
Started Jun 22 05:17:39 PM PDT 24
Finished Jun 22 05:19:06 PM PDT 24
Peak memory 255972 kb
Host smart-d68cdc95-8ee6-4415-b622-b0d80eb0dfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517417435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2517417435
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2953249973
Short name T449
Test name
Test status
Simulation time 28688227121 ps
CPU time 13.63 seconds
Started Jun 22 05:17:36 PM PDT 24
Finished Jun 22 05:17:52 PM PDT 24
Peak memory 218652 kb
Host smart-54dc7125-1d6e-49cf-b841-af57216f663c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953249973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2953249973
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1695508039
Short name T604
Test name
Test status
Simulation time 7400804594 ps
CPU time 29.19 seconds
Started Jun 22 05:17:35 PM PDT 24
Finished Jun 22 05:18:07 PM PDT 24
Peak memory 250268 kb
Host smart-775a47e6-ddcd-4546-b552-207c31b16e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695508039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1695508039
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.7585459
Short name T814
Test name
Test status
Simulation time 111506893 ps
CPU time 4.42 seconds
Started Jun 22 05:17:49 PM PDT 24
Finished Jun 22 05:17:54 PM PDT 24
Peak memory 233768 kb
Host smart-2f18f8c6-4b46-4b1c-b53c-1a32726bdc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7585459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.7585459
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3082757463
Short name T445
Test name
Test status
Simulation time 4827070850 ps
CPU time 29.1 seconds
Started Jun 22 05:17:39 PM PDT 24
Finished Jun 22 05:18:10 PM PDT 24
Peak memory 233856 kb
Host smart-6373321e-c9b6-4c85-9da2-127260395311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082757463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3082757463
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2578865661
Short name T683
Test name
Test status
Simulation time 59423310 ps
CPU time 2.5 seconds
Started Jun 22 05:17:35 PM PDT 24
Finished Jun 22 05:17:40 PM PDT 24
Peak memory 233504 kb
Host smart-a75bac5a-8157-4ea3-8ae8-dfed0f581868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578865661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2578865661
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3675017895
Short name T521
Test name
Test status
Simulation time 185117322 ps
CPU time 3.45 seconds
Started Jun 22 05:17:41 PM PDT 24
Finished Jun 22 05:17:46 PM PDT 24
Peak memory 233696 kb
Host smart-7e6ca6c9-173e-45bb-902f-bfa9fd066c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675017895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3675017895
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3059544692
Short name T39
Test name
Test status
Simulation time 1124567152 ps
CPU time 5.61 seconds
Started Jun 22 05:17:40 PM PDT 24
Finished Jun 22 05:17:47 PM PDT 24
Peak memory 220704 kb
Host smart-c7cf5e91-b8aa-4560-91a5-5aa29631b137
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3059544692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3059544692
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2813944747
Short name T968
Test name
Test status
Simulation time 4002686391 ps
CPU time 13.91 seconds
Started Jun 22 05:17:33 PM PDT 24
Finished Jun 22 05:17:48 PM PDT 24
Peak memory 217504 kb
Host smart-6b05a4d6-a938-4dbd-ab21-9ce53c076fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813944747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2813944747
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3850874293
Short name T120
Test name
Test status
Simulation time 14609191 ps
CPU time 0.72 seconds
Started Jun 22 05:17:36 PM PDT 24
Finished Jun 22 05:17:40 PM PDT 24
Peak memory 206868 kb
Host smart-31e8defe-5447-4587-bcd6-036d460625d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850874293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3850874293
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1762531242
Short name T517
Test name
Test status
Simulation time 30338356 ps
CPU time 0.76 seconds
Started Jun 22 05:17:42 PM PDT 24
Finished Jun 22 05:17:43 PM PDT 24
Peak memory 206868 kb
Host smart-1ffb6912-0b4d-4a96-9a22-9a76afc5c2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762531242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1762531242
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1857662588
Short name T559
Test name
Test status
Simulation time 1553483178 ps
CPU time 9.23 seconds
Started Jun 22 05:17:35 PM PDT 24
Finished Jun 22 05:17:47 PM PDT 24
Peak memory 233740 kb
Host smart-09a215ce-6599-41b7-9085-1308d6bd5d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857662588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1857662588
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1270703182
Short name T590
Test name
Test status
Simulation time 34153465 ps
CPU time 0.72 seconds
Started Jun 22 05:17:50 PM PDT 24
Finished Jun 22 05:17:52 PM PDT 24
Peak memory 205752 kb
Host smart-7079a301-e681-4bac-b3c8-b6cf6273dfa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270703182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
270703182
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.4166078118
Short name T373
Test name
Test status
Simulation time 1335810746 ps
CPU time 14.75 seconds
Started Jun 22 05:17:35 PM PDT 24
Finished Jun 22 05:17:52 PM PDT 24
Peak memory 225572 kb
Host smart-14796daa-9fbe-4e18-8f74-c8113b9b7df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166078118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.4166078118
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3713883849
Short name T669
Test name
Test status
Simulation time 26441290 ps
CPU time 0.83 seconds
Started Jun 22 05:17:50 PM PDT 24
Finished Jun 22 05:17:51 PM PDT 24
Peak memory 207828 kb
Host smart-1a5b1544-7fab-4ec9-9ed0-523d244ebc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713883849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3713883849
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3467543506
Short name T434
Test name
Test status
Simulation time 70424788231 ps
CPU time 150.48 seconds
Started Jun 22 05:17:33 PM PDT 24
Finished Jun 22 05:20:11 PM PDT 24
Peak memory 257476 kb
Host smart-613a68dc-10c9-4e15-ac3a-ae1c859cb423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467543506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3467543506
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.761380166
Short name T201
Test name
Test status
Simulation time 56605839696 ps
CPU time 239.66 seconds
Started Jun 22 05:17:52 PM PDT 24
Finished Jun 22 05:21:52 PM PDT 24
Peak memory 265648 kb
Host smart-86430607-f838-49b0-9a9f-d3ea3e06c7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761380166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.761380166
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1090087791
Short name T154
Test name
Test status
Simulation time 8804999804 ps
CPU time 71.63 seconds
Started Jun 22 05:17:46 PM PDT 24
Finished Jun 22 05:18:59 PM PDT 24
Peak memory 240768 kb
Host smart-62c8ad0e-3093-4596-b914-6c04c1e6e69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090087791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1090087791
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3935386960
Short name T781
Test name
Test status
Simulation time 2125068824 ps
CPU time 39.11 seconds
Started Jun 22 05:17:38 PM PDT 24
Finished Jun 22 05:18:20 PM PDT 24
Peak memory 250112 kb
Host smart-35b8265e-c781-4997-a1bd-e658fecb9313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935386960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3935386960
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2308439439
Short name T777
Test name
Test status
Simulation time 36776074 ps
CPU time 2.56 seconds
Started Jun 22 05:17:54 PM PDT 24
Finished Jun 22 05:17:57 PM PDT 24
Peak memory 233484 kb
Host smart-05371077-b32e-424b-b6ce-eec45bb2a358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308439439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2308439439
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.4196430963
Short name T379
Test name
Test status
Simulation time 26039250 ps
CPU time 1 seconds
Started Jun 22 05:17:53 PM PDT 24
Finished Jun 22 05:17:54 PM PDT 24
Peak memory 218748 kb
Host smart-01778286-d625-454e-951f-8e697a1e4891
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196430963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.4196430963
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3741740138
Short name T805
Test name
Test status
Simulation time 247159469 ps
CPU time 3.2 seconds
Started Jun 22 05:17:39 PM PDT 24
Finished Jun 22 05:17:44 PM PDT 24
Peak memory 233736 kb
Host smart-404ffd9d-dcfc-4d90-9237-082d993a2437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741740138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3741740138
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2352507899
Short name T894
Test name
Test status
Simulation time 1094415429 ps
CPU time 9.84 seconds
Started Jun 22 05:17:48 PM PDT 24
Finished Jun 22 05:17:58 PM PDT 24
Peak memory 224160 kb
Host smart-b3b4bbe1-2949-4de9-ae47-e405bb384413
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2352507899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2352507899
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3823361001
Short name T64
Test name
Test status
Simulation time 40020677 ps
CPU time 1.01 seconds
Started Jun 22 05:17:41 PM PDT 24
Finished Jun 22 05:17:43 PM PDT 24
Peak memory 236420 kb
Host smart-e3602ae9-b3aa-4bf5-ae2c-8a65c35b5fef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823361001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3823361001
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3468585652
Short name T20
Test name
Test status
Simulation time 97351481919 ps
CPU time 163.26 seconds
Started Jun 22 05:17:55 PM PDT 24
Finished Jun 22 05:20:38 PM PDT 24
Peak memory 250388 kb
Host smart-abf9435e-9515-4e47-84e7-dfaf7f537859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468585652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3468585652
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3510116380
Short name T756
Test name
Test status
Simulation time 10394149674 ps
CPU time 14.13 seconds
Started Jun 22 05:17:53 PM PDT 24
Finished Jun 22 05:18:08 PM PDT 24
Peak memory 217504 kb
Host smart-0a9b8e4e-70f7-4df9-a667-742f60b71bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510116380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3510116380
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.735937524
Short name T821
Test name
Test status
Simulation time 18936361631 ps
CPU time 27.07 seconds
Started Jun 22 05:17:37 PM PDT 24
Finished Jun 22 05:18:07 PM PDT 24
Peak memory 217412 kb
Host smart-596d16ff-d8f7-4117-8175-456881198085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735937524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.735937524
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.481731648
Short name T386
Test name
Test status
Simulation time 56587690 ps
CPU time 1.06 seconds
Started Jun 22 05:17:36 PM PDT 24
Finished Jun 22 05:17:40 PM PDT 24
Peak memory 208928 kb
Host smart-fce189c4-1c61-484d-ab6e-b0801e38d0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481731648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.481731648
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1594935983
Short name T357
Test name
Test status
Simulation time 142663653 ps
CPU time 0.89 seconds
Started Jun 22 05:17:45 PM PDT 24
Finished Jun 22 05:17:46 PM PDT 24
Peak memory 207904 kb
Host smart-5d41d50d-9679-4b72-99bc-0d3ea5caee5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594935983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1594935983
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1617136526
Short name T636
Test name
Test status
Simulation time 2712461602 ps
CPU time 6.86 seconds
Started Jun 22 05:17:43 PM PDT 24
Finished Jun 22 05:17:50 PM PDT 24
Peak memory 225688 kb
Host smart-6e053c4f-25a1-4092-845c-45a2a0eb94fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617136526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1617136526
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1939652710
Short name T797
Test name
Test status
Simulation time 13806159 ps
CPU time 0.76 seconds
Started Jun 22 05:18:31 PM PDT 24
Finished Jun 22 05:18:32 PM PDT 24
Peak memory 206600 kb
Host smart-c9b0b66e-5aa7-4c2a-8d35-4b2930132a4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939652710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1939652710
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.110331662
Short name T794
Test name
Test status
Simulation time 153579883 ps
CPU time 2.17 seconds
Started Jun 22 05:18:21 PM PDT 24
Finished Jun 22 05:18:24 PM PDT 24
Peak memory 225552 kb
Host smart-87e4339d-c5fa-4170-a11f-7427a136b3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110331662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.110331662
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.299812006
Short name T324
Test name
Test status
Simulation time 12941238 ps
CPU time 0.76 seconds
Started Jun 22 05:18:09 PM PDT 24
Finished Jun 22 05:18:10 PM PDT 24
Peak memory 206812 kb
Host smart-fb3decc6-faa5-490f-9623-7d9e776a1af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299812006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.299812006
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2368939980
Short name T292
Test name
Test status
Simulation time 125634702295 ps
CPU time 184.08 seconds
Started Jun 22 05:18:14 PM PDT 24
Finished Jun 22 05:21:19 PM PDT 24
Peak memory 255464 kb
Host smart-f26b9ffc-425e-4571-9759-c96c620d8fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368939980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2368939980
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3339921689
Short name T701
Test name
Test status
Simulation time 57387908677 ps
CPU time 522.33 seconds
Started Jun 22 05:18:14 PM PDT 24
Finished Jun 22 05:26:57 PM PDT 24
Peak memory 256220 kb
Host smart-402caae6-c629-4a3a-9bc6-4e6bb21bb798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339921689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3339921689
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3415807196
Short name T125
Test name
Test status
Simulation time 77611111241 ps
CPU time 150.9 seconds
Started Jun 22 05:18:21 PM PDT 24
Finished Jun 22 05:20:53 PM PDT 24
Peak memory 255280 kb
Host smart-b72edb57-9b78-49ea-a475-944eb954192d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415807196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3415807196
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3719939791
Short name T672
Test name
Test status
Simulation time 2361732743 ps
CPU time 19.1 seconds
Started Jun 22 05:18:15 PM PDT 24
Finished Jun 22 05:18:35 PM PDT 24
Peak memory 225704 kb
Host smart-19e94c5f-2ae8-4577-af08-f375dbdec320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719939791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3719939791
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1260644229
Short name T250
Test name
Test status
Simulation time 3124602964 ps
CPU time 7.37 seconds
Started Jun 22 05:18:20 PM PDT 24
Finished Jun 22 05:18:28 PM PDT 24
Peak memory 233928 kb
Host smart-3c8891c1-a89a-4fbc-8ce9-e24949c525b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260644229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1260644229
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2183223572
Short name T917
Test name
Test status
Simulation time 396931479 ps
CPU time 6.02 seconds
Started Jun 22 05:18:11 PM PDT 24
Finished Jun 22 05:18:18 PM PDT 24
Peak memory 233764 kb
Host smart-d58a97f8-20a9-457a-853e-1c88ef340fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183223572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2183223572
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3186620248
Short name T367
Test name
Test status
Simulation time 26747200 ps
CPU time 1.1 seconds
Started Jun 22 05:18:22 PM PDT 24
Finished Jun 22 05:18:24 PM PDT 24
Peak memory 217624 kb
Host smart-3c1c48a7-fda1-4279-9888-712928c9c703
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186620248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3186620248
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.4040224133
Short name T269
Test name
Test status
Simulation time 1071826668 ps
CPU time 8.69 seconds
Started Jun 22 05:18:23 PM PDT 24
Finished Jun 22 05:18:33 PM PDT 24
Peak memory 249588 kb
Host smart-76291289-987f-4a44-be6a-4e4b43bc3fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040224133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.4040224133
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.180556385
Short name T104
Test name
Test status
Simulation time 673482748 ps
CPU time 4.41 seconds
Started Jun 22 05:18:11 PM PDT 24
Finished Jun 22 05:18:16 PM PDT 24
Peak memory 233740 kb
Host smart-d23e3439-49e1-4270-b1c3-e73614222d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180556385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.180556385
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1654303641
Short name T792
Test name
Test status
Simulation time 332576795 ps
CPU time 3.91 seconds
Started Jun 22 05:18:25 PM PDT 24
Finished Jun 22 05:18:30 PM PDT 24
Peak memory 219888 kb
Host smart-5f34f923-1003-4998-a580-cc86187113b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1654303641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1654303641
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1504855029
Short name T715
Test name
Test status
Simulation time 16958061598 ps
CPU time 38.93 seconds
Started Jun 22 05:18:03 PM PDT 24
Finished Jun 22 05:18:42 PM PDT 24
Peak memory 217468 kb
Host smart-b68083be-3a7d-426e-a200-32cee49e7580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504855029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1504855029
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3360722548
Short name T631
Test name
Test status
Simulation time 4881407482 ps
CPU time 14.26 seconds
Started Jun 22 05:18:10 PM PDT 24
Finished Jun 22 05:18:25 PM PDT 24
Peak memory 217480 kb
Host smart-cfc63329-403e-43c6-9050-448ffc3159ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360722548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3360722548
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3145178397
Short name T73
Test name
Test status
Simulation time 216094136 ps
CPU time 1.27 seconds
Started Jun 22 05:18:08 PM PDT 24
Finished Jun 22 05:18:10 PM PDT 24
Peak memory 208880 kb
Host smart-99cccf46-82f2-4866-b9a4-525d4d2d7d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145178397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3145178397
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1589105336
Short name T412
Test name
Test status
Simulation time 304530579 ps
CPU time 0.9 seconds
Started Jun 22 05:18:05 PM PDT 24
Finished Jun 22 05:18:07 PM PDT 24
Peak memory 206888 kb
Host smart-e6353d1d-253d-4779-8aef-2efd2d7aec16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589105336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1589105336
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.407653573
Short name T779
Test name
Test status
Simulation time 2055280859 ps
CPU time 6.79 seconds
Started Jun 22 05:18:10 PM PDT 24
Finished Jun 22 05:18:17 PM PDT 24
Peak memory 225492 kb
Host smart-123533f1-de73-48ff-8232-491f0e5bee40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407653573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.407653573
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1209114235
Short name T51
Test name
Test status
Simulation time 84691683 ps
CPU time 0.73 seconds
Started Jun 22 05:18:21 PM PDT 24
Finished Jun 22 05:18:24 PM PDT 24
Peak memory 206244 kb
Host smart-98feacb1-24d9-4bd1-a6be-c49e9737736b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209114235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1209114235
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.672524012
Short name T83
Test name
Test status
Simulation time 145682548 ps
CPU time 2.54 seconds
Started Jun 22 05:18:14 PM PDT 24
Finished Jun 22 05:18:17 PM PDT 24
Peak memory 224872 kb
Host smart-c67a0976-90dc-42ee-a527-fedbae6f32b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672524012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.672524012
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.239592679
Short name T358
Test name
Test status
Simulation time 187941549 ps
CPU time 0.76 seconds
Started Jun 22 05:18:10 PM PDT 24
Finished Jun 22 05:18:12 PM PDT 24
Peak memory 206472 kb
Host smart-b2a51a48-21cc-4eec-8fb3-5c25f4a43979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239592679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.239592679
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3624137390
Short name T436
Test name
Test status
Simulation time 40916353629 ps
CPU time 271.37 seconds
Started Jun 22 05:18:21 PM PDT 24
Finished Jun 22 05:22:53 PM PDT 24
Peak memory 250688 kb
Host smart-9ecde110-313e-4352-a5c5-1b1688392438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624137390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3624137390
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.480182626
Short name T729
Test name
Test status
Simulation time 5805737433 ps
CPU time 79 seconds
Started Jun 22 05:18:36 PM PDT 24
Finished Jun 22 05:19:55 PM PDT 24
Peak memory 255040 kb
Host smart-9b782139-ef24-4146-83e7-9096adc78af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480182626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.480182626
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3319294501
Short name T302
Test name
Test status
Simulation time 1154534162 ps
CPU time 18.47 seconds
Started Jun 22 05:18:35 PM PDT 24
Finished Jun 22 05:18:54 PM PDT 24
Peak memory 241940 kb
Host smart-269ee210-29d3-4630-928c-a80485dbbaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319294501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3319294501
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.105026229
Short name T326
Test name
Test status
Simulation time 1184635421 ps
CPU time 6.75 seconds
Started Jun 22 05:18:21 PM PDT 24
Finished Jun 22 05:18:29 PM PDT 24
Peak memory 225404 kb
Host smart-b2a94d5a-c597-4389-93d6-130e0872e7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105026229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.105026229
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3769918889
Short name T260
Test name
Test status
Simulation time 1679583336 ps
CPU time 24.48 seconds
Started Jun 22 05:18:14 PM PDT 24
Finished Jun 22 05:18:39 PM PDT 24
Peak memory 249392 kb
Host smart-b973b7b0-be3b-43a1-9f97-6affa029d39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769918889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3769918889
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3736784089
Short name T407
Test name
Test status
Simulation time 71427005 ps
CPU time 1.09 seconds
Started Jun 22 05:18:10 PM PDT 24
Finished Jun 22 05:18:12 PM PDT 24
Peak memory 217848 kb
Host smart-dffa8f06-3719-487a-bacb-c7fd767e2b3e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736784089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3736784089
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1755081534
Short name T652
Test name
Test status
Simulation time 510663614 ps
CPU time 7.23 seconds
Started Jun 22 05:18:13 PM PDT 24
Finished Jun 22 05:18:21 PM PDT 24
Peak memory 233636 kb
Host smart-dc3eb9da-40ff-4748-8393-73044af4beb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755081534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1755081534
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2924787231
Short name T938
Test name
Test status
Simulation time 60811944496 ps
CPU time 15.69 seconds
Started Jun 22 05:18:13 PM PDT 24
Finished Jun 22 05:18:29 PM PDT 24
Peak memory 225596 kb
Host smart-8ce482f6-e6d7-4fe2-97b1-3536972d09ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924787231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2924787231
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3553670949
Short name T341
Test name
Test status
Simulation time 355332728 ps
CPU time 4.43 seconds
Started Jun 22 05:18:10 PM PDT 24
Finished Jun 22 05:18:15 PM PDT 24
Peak memory 223656 kb
Host smart-3ca56a4a-bd31-439a-8bfc-c0a3e667c868
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3553670949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3553670949
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3477353247
Short name T21
Test name
Test status
Simulation time 67717969 ps
CPU time 1.01 seconds
Started Jun 22 05:18:15 PM PDT 24
Finished Jun 22 05:18:17 PM PDT 24
Peak memory 207840 kb
Host smart-ee9f5ae0-e8b4-4b89-a861-2f32db73f9c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477353247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3477353247
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2859222165
Short name T55
Test name
Test status
Simulation time 3292454227 ps
CPU time 26.71 seconds
Started Jun 22 05:18:20 PM PDT 24
Finished Jun 22 05:18:48 PM PDT 24
Peak memory 217476 kb
Host smart-b8773b69-6be4-4a39-829c-8ec4cfe0790d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859222165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2859222165
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2751901177
Short name T702
Test name
Test status
Simulation time 10732387263 ps
CPU time 10.77 seconds
Started Jun 22 05:18:10 PM PDT 24
Finished Jun 22 05:18:21 PM PDT 24
Peak memory 217428 kb
Host smart-e5187296-054a-4e3a-a603-7a90b5aefa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751901177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2751901177
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2002406142
Short name T775
Test name
Test status
Simulation time 21505956 ps
CPU time 0.74 seconds
Started Jun 22 05:18:21 PM PDT 24
Finished Jun 22 05:18:23 PM PDT 24
Peak memory 206240 kb
Host smart-e781a61f-a981-46ad-a693-aebccf362c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002406142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2002406142
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.4028703625
Short name T624
Test name
Test status
Simulation time 362685557 ps
CPU time 0.95 seconds
Started Jun 22 05:18:30 PM PDT 24
Finished Jun 22 05:18:32 PM PDT 24
Peak memory 206784 kb
Host smart-ffd0f340-acd4-431e-9767-c28c94bd204f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028703625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.4028703625
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2945242513
Short name T580
Test name
Test status
Simulation time 2558599323 ps
CPU time 7.68 seconds
Started Jun 22 05:18:21 PM PDT 24
Finished Jun 22 05:18:30 PM PDT 24
Peak memory 233848 kb
Host smart-7cdbf461-3084-4e7f-8ff3-031522d8f48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945242513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2945242513
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1931309791
Short name T381
Test name
Test status
Simulation time 23045815 ps
CPU time 0.72 seconds
Started Jun 22 05:18:17 PM PDT 24
Finished Jun 22 05:18:18 PM PDT 24
Peak memory 206256 kb
Host smart-a1c68729-de58-42fb-8306-8bc86679d0c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931309791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1931309791
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.136265618
Short name T865
Test name
Test status
Simulation time 14962828 ps
CPU time 0.76 seconds
Started Jun 22 05:18:33 PM PDT 24
Finished Jun 22 05:18:34 PM PDT 24
Peak memory 206456 kb
Host smart-184b37c7-976d-418e-b98b-999f4ee2f34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136265618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.136265618
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1101572990
Short name T121
Test name
Test status
Simulation time 20075596307 ps
CPU time 148.5 seconds
Started Jun 22 05:18:22 PM PDT 24
Finished Jun 22 05:20:51 PM PDT 24
Peak memory 250288 kb
Host smart-56596693-082b-4729-bf27-300a07f4005a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101572990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1101572990
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2618305055
Short name T159
Test name
Test status
Simulation time 14659262716 ps
CPU time 37.96 seconds
Started Jun 22 05:18:20 PM PDT 24
Finished Jun 22 05:18:59 PM PDT 24
Peak memory 250448 kb
Host smart-a743be5d-cfdd-4656-874a-3a2d98b46724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618305055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2618305055
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2822607176
Short name T221
Test name
Test status
Simulation time 2431840973 ps
CPU time 44.38 seconds
Started Jun 22 05:18:21 PM PDT 24
Finished Jun 22 05:19:07 PM PDT 24
Peak memory 251488 kb
Host smart-6f5597bf-80b0-49da-9a35-495fca1c2f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822607176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2822607176
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.46460961
Short name T504
Test name
Test status
Simulation time 1477951242 ps
CPU time 4.86 seconds
Started Jun 22 05:18:13 PM PDT 24
Finished Jun 22 05:18:18 PM PDT 24
Peak memory 225792 kb
Host smart-21e2dc26-fdc5-4ef3-aa0b-b3ed601df016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46460961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.46460961
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3136590887
Short name T331
Test name
Test status
Simulation time 5263833923 ps
CPU time 28.09 seconds
Started Jun 22 05:18:17 PM PDT 24
Finished Jun 22 05:18:46 PM PDT 24
Peak memory 225644 kb
Host smart-79b57954-45fe-4e68-97c9-ea4ab599205e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136590887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3136590887
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2026565180
Short name T564
Test name
Test status
Simulation time 1667989860 ps
CPU time 10.97 seconds
Started Jun 22 05:18:31 PM PDT 24
Finished Jun 22 05:18:42 PM PDT 24
Peak memory 250140 kb
Host smart-af0c177a-f066-401c-add2-523be7526fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026565180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2026565180
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3356008033
Short name T33
Test name
Test status
Simulation time 139502103 ps
CPU time 1.11 seconds
Started Jun 22 05:18:15 PM PDT 24
Finished Jun 22 05:18:16 PM PDT 24
Peak memory 218856 kb
Host smart-5724af5b-3515-4f3e-b46a-1979352333b3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356008033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3356008033
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2981115257
Short name T972
Test name
Test status
Simulation time 6355023412 ps
CPU time 7.63 seconds
Started Jun 22 05:18:12 PM PDT 24
Finished Jun 22 05:18:20 PM PDT 24
Peak memory 225632 kb
Host smart-1ba6f3bf-ee8b-444c-b898-e9a60bbcec8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981115257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2981115257
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1110574168
Short name T473
Test name
Test status
Simulation time 823925976 ps
CPU time 4.94 seconds
Started Jun 22 05:18:12 PM PDT 24
Finished Jun 22 05:18:17 PM PDT 24
Peak memory 223756 kb
Host smart-50e63bc5-e0ed-4ce7-b2f6-eb26a8d30e07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1110574168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1110574168
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2309943055
Short name T147
Test name
Test status
Simulation time 22495797175 ps
CPU time 124.18 seconds
Started Jun 22 05:18:24 PM PDT 24
Finished Jun 22 05:20:29 PM PDT 24
Peak memory 274908 kb
Host smart-6aa74cb4-b8ec-49a0-b985-32c64570f8f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309943055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2309943055
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.942687956
Short name T767
Test name
Test status
Simulation time 1201710701 ps
CPU time 5.53 seconds
Started Jun 22 05:18:11 PM PDT 24
Finished Jun 22 05:18:17 PM PDT 24
Peak memory 217316 kb
Host smart-f270f3a9-2e40-49c2-840f-53e5c0a2280c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942687956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.942687956
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2454432456
Short name T392
Test name
Test status
Simulation time 1422743884 ps
CPU time 2.65 seconds
Started Jun 22 05:18:15 PM PDT 24
Finished Jun 22 05:18:18 PM PDT 24
Peak memory 217248 kb
Host smart-125156ee-f728-43d1-97ef-69c54de318d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454432456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2454432456
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2732383263
Short name T351
Test name
Test status
Simulation time 955823119 ps
CPU time 2.33 seconds
Started Jun 22 05:18:14 PM PDT 24
Finished Jun 22 05:18:16 PM PDT 24
Peak memory 217320 kb
Host smart-113169de-ada1-4344-80dc-b467d3403a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732383263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2732383263
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2950729039
Short name T328
Test name
Test status
Simulation time 85373917 ps
CPU time 0.87 seconds
Started Jun 22 05:18:24 PM PDT 24
Finished Jun 22 05:18:27 PM PDT 24
Peak memory 206864 kb
Host smart-7f6a7f19-e1ff-4773-b873-1e363f26bfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950729039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2950729039
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2560775796
Short name T698
Test name
Test status
Simulation time 5335320944 ps
CPU time 12.81 seconds
Started Jun 22 05:18:11 PM PDT 24
Finished Jun 22 05:18:25 PM PDT 24
Peak memory 236064 kb
Host smart-10edb7e6-e4da-4850-b401-13439ff7f0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560775796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2560775796
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.836274215
Short name T926
Test name
Test status
Simulation time 48553738 ps
CPU time 0.75 seconds
Started Jun 22 05:18:23 PM PDT 24
Finished Jun 22 05:18:25 PM PDT 24
Peak memory 206564 kb
Host smart-f79daef1-8d57-4b76-8378-2abc7dedeef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836274215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.836274215
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3929843606
Short name T902
Test name
Test status
Simulation time 59105953 ps
CPU time 2.45 seconds
Started Jun 22 05:18:19 PM PDT 24
Finished Jun 22 05:18:22 PM PDT 24
Peak memory 233448 kb
Host smart-b0df2857-05ca-40f4-a333-28bb05f2b68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929843606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3929843606
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3401814426
Short name T513
Test name
Test status
Simulation time 31914768 ps
CPU time 0.8 seconds
Started Jun 22 05:18:08 PM PDT 24
Finished Jun 22 05:18:10 PM PDT 24
Peak memory 207484 kb
Host smart-e3f30426-2dc0-4754-8812-25094f536f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401814426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3401814426
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.893249478
Short name T196
Test name
Test status
Simulation time 583901142 ps
CPU time 5.41 seconds
Started Jun 22 05:18:29 PM PDT 24
Finished Jun 22 05:18:35 PM PDT 24
Peak memory 225544 kb
Host smart-2ef22c74-864d-4bcc-8e57-bcba9b95d017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893249478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.893249478
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3915928304
Short name T428
Test name
Test status
Simulation time 204328813658 ps
CPU time 244.8 seconds
Started Jun 22 05:18:27 PM PDT 24
Finished Jun 22 05:22:33 PM PDT 24
Peak memory 258372 kb
Host smart-c82919cc-43d8-4adc-b208-ba4eac61cca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915928304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3915928304
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.4191756640
Short name T313
Test name
Test status
Simulation time 6721500386 ps
CPU time 24.21 seconds
Started Jun 22 05:18:22 PM PDT 24
Finished Jun 22 05:18:48 PM PDT 24
Peak memory 241984 kb
Host smart-98c046fa-2123-4f9b-9abc-8d5d35867f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191756640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.4191756640
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2200003343
Short name T541
Test name
Test status
Simulation time 363250730 ps
CPU time 3.6 seconds
Started Jun 22 05:18:31 PM PDT 24
Finished Jun 22 05:18:35 PM PDT 24
Peak memory 233780 kb
Host smart-7b672109-22df-4e1f-aa3c-1854c02d15a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200003343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2200003343
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1084229877
Short name T816
Test name
Test status
Simulation time 2614478518 ps
CPU time 24.91 seconds
Started Jun 22 05:18:20 PM PDT 24
Finished Jun 22 05:18:45 PM PDT 24
Peak memory 233868 kb
Host smart-46501a27-72cb-42ad-82dd-324fdb3a3218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084229877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1084229877
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1574989236
Short name T909
Test name
Test status
Simulation time 12343251581 ps
CPU time 131.67 seconds
Started Jun 22 05:18:20 PM PDT 24
Finished Jun 22 05:20:32 PM PDT 24
Peak memory 251848 kb
Host smart-2215b008-94ba-4a95-8ffa-685411fd0cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574989236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1574989236
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.986849953
Short name T514
Test name
Test status
Simulation time 28008795 ps
CPU time 1.05 seconds
Started Jun 22 05:18:21 PM PDT 24
Finished Jun 22 05:18:24 PM PDT 24
Peak memory 217620 kb
Host smart-4a560ac4-afc6-452f-9abd-1af309efd43f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986849953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.986849953
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.582063917
Short name T278
Test name
Test status
Simulation time 692560012 ps
CPU time 6.92 seconds
Started Jun 22 05:18:21 PM PDT 24
Finished Jun 22 05:18:29 PM PDT 24
Peak memory 225504 kb
Host smart-ee2997a9-5708-41fd-aa4e-4079274d98b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582063917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.582063917
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3063570745
Short name T936
Test name
Test status
Simulation time 2341208431 ps
CPU time 7.84 seconds
Started Jun 22 05:18:21 PM PDT 24
Finished Jun 22 05:18:31 PM PDT 24
Peak memory 250240 kb
Host smart-e06f08e2-48a3-4a66-bc73-e1887add8bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063570745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3063570745
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.996412327
Short name T570
Test name
Test status
Simulation time 1184959307 ps
CPU time 12.37 seconds
Started Jun 22 05:18:20 PM PDT 24
Finished Jun 22 05:18:34 PM PDT 24
Peak memory 223472 kb
Host smart-1ecade67-bbd2-44e7-82b7-a59dc52732c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=996412327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.996412327
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3810063663
Short name T388
Test name
Test status
Simulation time 1185809544 ps
CPU time 16.87 seconds
Started Jun 22 05:18:21 PM PDT 24
Finished Jun 22 05:18:38 PM PDT 24
Peak memory 217588 kb
Host smart-6c93d63a-77ee-405f-8804-e448e900e2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810063663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3810063663
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1009961170
Short name T378
Test name
Test status
Simulation time 8250195932 ps
CPU time 8.49 seconds
Started Jun 22 05:18:19 PM PDT 24
Finished Jun 22 05:18:28 PM PDT 24
Peak memory 217444 kb
Host smart-e596007a-347b-42ea-849f-7bcd8bc0ffa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009961170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1009961170
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1564585961
Short name T925
Test name
Test status
Simulation time 158685987 ps
CPU time 2 seconds
Started Jun 22 05:18:14 PM PDT 24
Finished Jun 22 05:18:16 PM PDT 24
Peak memory 217272 kb
Host smart-a1f112c1-fb67-4f96-a5a7-fb10df66091f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564585961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1564585961
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2645052504
Short name T380
Test name
Test status
Simulation time 12665604 ps
CPU time 0.71 seconds
Started Jun 22 05:18:14 PM PDT 24
Finished Jun 22 05:18:15 PM PDT 24
Peak memory 206492 kb
Host smart-68ae3d57-c188-4feb-8d85-aa60b908d2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645052504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2645052504
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.4270979691
Short name T241
Test name
Test status
Simulation time 4836812399 ps
CPU time 8.39 seconds
Started Jun 22 05:18:22 PM PDT 24
Finished Jun 22 05:18:32 PM PDT 24
Peak memory 225604 kb
Host smart-ea9b920e-b84a-4260-a8f1-262021fe9e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270979691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.4270979691
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3541474620
Short name T793
Test name
Test status
Simulation time 31655658 ps
CPU time 0.71 seconds
Started Jun 22 05:18:24 PM PDT 24
Finished Jun 22 05:18:26 PM PDT 24
Peak memory 206436 kb
Host smart-201b8051-8f1a-446e-9583-a9878e312aab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541474620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3541474620
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2757334395
Short name T783
Test name
Test status
Simulation time 161825703 ps
CPU time 3.64 seconds
Started Jun 22 05:18:24 PM PDT 24
Finished Jun 22 05:18:29 PM PDT 24
Peak memory 225528 kb
Host smart-eba06b45-7e48-4b83-bd6b-8b0aa851d8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757334395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2757334395
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3030618249
Short name T365
Test name
Test status
Simulation time 21067389 ps
CPU time 0.78 seconds
Started Jun 22 05:18:24 PM PDT 24
Finished Jun 22 05:18:26 PM PDT 24
Peak memory 207836 kb
Host smart-919d04ba-8843-4d31-9d83-d745be467415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030618249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3030618249
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3119133404
Short name T508
Test name
Test status
Simulation time 23543056403 ps
CPU time 183.13 seconds
Started Jun 22 05:18:29 PM PDT 24
Finished Jun 22 05:21:33 PM PDT 24
Peak memory 250292 kb
Host smart-fcb02651-3e65-46a4-bba0-a76b91a8d28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119133404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3119133404
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3467039826
Short name T186
Test name
Test status
Simulation time 11106934077 ps
CPU time 106.26 seconds
Started Jun 22 05:18:21 PM PDT 24
Finished Jun 22 05:20:08 PM PDT 24
Peak memory 256812 kb
Host smart-1dfc68b2-9b28-490e-b101-58cbb904a264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467039826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3467039826
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3340095190
Short name T432
Test name
Test status
Simulation time 25462167842 ps
CPU time 82.32 seconds
Started Jun 22 05:18:17 PM PDT 24
Finished Jun 22 05:19:40 PM PDT 24
Peak memory 265316 kb
Host smart-7c6c4e7b-0620-4a58-a664-2c8c886447dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340095190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3340095190
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1483516017
Short name T942
Test name
Test status
Simulation time 4563527403 ps
CPU time 21.71 seconds
Started Jun 22 05:18:29 PM PDT 24
Finished Jun 22 05:18:52 PM PDT 24
Peak memory 233868 kb
Host smart-1d8ba37c-781e-4e7c-867e-a2c4dd19c5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483516017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1483516017
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.15012638
Short name T322
Test name
Test status
Simulation time 413753042 ps
CPU time 3.58 seconds
Started Jun 22 05:18:18 PM PDT 24
Finished Jun 22 05:18:22 PM PDT 24
Peak memory 225548 kb
Host smart-aa8b1cd6-66e0-4ef4-8ced-f899b3d8b39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15012638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.15012638
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3059534634
Short name T438
Test name
Test status
Simulation time 87905405 ps
CPU time 1.1 seconds
Started Jun 22 05:18:36 PM PDT 24
Finished Jun 22 05:18:37 PM PDT 24
Peak memory 217568 kb
Host smart-1e3b6e67-5de2-49ea-b94b-d8d1f529bba7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059534634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3059534634
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.644140399
Short name T864
Test name
Test status
Simulation time 1048505986 ps
CPU time 5.28 seconds
Started Jun 22 05:18:27 PM PDT 24
Finished Jun 22 05:18:34 PM PDT 24
Peak memory 233700 kb
Host smart-29decaa8-e187-4f38-b00f-a4fb3fb25ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644140399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.644140399
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3177068842
Short name T382
Test name
Test status
Simulation time 117282772 ps
CPU time 2.44 seconds
Started Jun 22 05:18:24 PM PDT 24
Finished Jun 22 05:18:28 PM PDT 24
Peak memory 225568 kb
Host smart-3a779ad1-8402-434e-8276-544c38962361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177068842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3177068842
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3374722398
Short name T353
Test name
Test status
Simulation time 1267925547 ps
CPU time 12.61 seconds
Started Jun 22 05:18:32 PM PDT 24
Finished Jun 22 05:18:45 PM PDT 24
Peak memory 223304 kb
Host smart-d84e9c68-39cc-4454-8314-bf2eb7b0f0fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3374722398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3374722398
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1007138135
Short name T182
Test name
Test status
Simulation time 5008372107 ps
CPU time 96.1 seconds
Started Jun 22 05:18:22 PM PDT 24
Finished Jun 22 05:19:59 PM PDT 24
Peak memory 251372 kb
Host smart-6220fa75-69bd-417b-ae4b-c3514d86b314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007138135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1007138135
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3094367513
Short name T314
Test name
Test status
Simulation time 15520401769 ps
CPU time 39.45 seconds
Started Jun 22 05:18:27 PM PDT 24
Finished Jun 22 05:19:08 PM PDT 24
Peak memory 217512 kb
Host smart-ec6d3e4c-08df-49db-b540-471ae29b2e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094367513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3094367513
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3774992475
Short name T771
Test name
Test status
Simulation time 20560029004 ps
CPU time 17.4 seconds
Started Jun 22 05:18:25 PM PDT 24
Finished Jun 22 05:18:43 PM PDT 24
Peak memory 218588 kb
Host smart-453555de-bebd-4725-8f94-b5775ef4e36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774992475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3774992475
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2093915454
Short name T944
Test name
Test status
Simulation time 440823227 ps
CPU time 2.12 seconds
Started Jun 22 05:18:26 PM PDT 24
Finished Jun 22 05:18:29 PM PDT 24
Peak memory 217376 kb
Host smart-c4ea2658-0052-4ed5-9688-3c15ba66f051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093915454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2093915454
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.486653922
Short name T512
Test name
Test status
Simulation time 291077963 ps
CPU time 0.93 seconds
Started Jun 22 05:18:22 PM PDT 24
Finished Jun 22 05:18:24 PM PDT 24
Peak memory 206880 kb
Host smart-cf8cd7b4-cb08-41b2-95b3-56aa50d0ad3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486653922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.486653922
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.374662385
Short name T705
Test name
Test status
Simulation time 2097786534 ps
CPU time 6.64 seconds
Started Jun 22 05:18:21 PM PDT 24
Finished Jun 22 05:18:29 PM PDT 24
Peak memory 233316 kb
Host smart-845cc775-939d-4efa-b09c-abd7f8a756fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374662385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.374662385
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2219232680
Short name T579
Test name
Test status
Simulation time 90912361 ps
CPU time 0.73 seconds
Started Jun 22 05:18:26 PM PDT 24
Finished Jun 22 05:18:27 PM PDT 24
Peak memory 206156 kb
Host smart-d59bc540-5b3c-47cd-9c8a-f78a68d6cda8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219232680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2219232680
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3420050174
Short name T150
Test name
Test status
Simulation time 350678358 ps
CPU time 2.99 seconds
Started Jun 22 05:18:22 PM PDT 24
Finished Jun 22 05:18:26 PM PDT 24
Peak memory 225484 kb
Host smart-4aca1ce1-5caa-46c6-915a-6ac32d319924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420050174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3420050174
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1528134710
Short name T960
Test name
Test status
Simulation time 58017563 ps
CPU time 0.78 seconds
Started Jun 22 05:18:23 PM PDT 24
Finished Jun 22 05:18:24 PM PDT 24
Peak memory 207820 kb
Host smart-f82d466c-2244-49dd-a1d6-7bcb7013aaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528134710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1528134710
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.297788566
Short name T153
Test name
Test status
Simulation time 16102051822 ps
CPU time 62.72 seconds
Started Jun 22 05:18:16 PM PDT 24
Finished Jun 22 05:19:20 PM PDT 24
Peak memory 240528 kb
Host smart-4057cfac-2ba8-4d83-9cf8-1f2c376df613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297788566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.297788566
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.284869717
Short name T280
Test name
Test status
Simulation time 100519450152 ps
CPU time 213.64 seconds
Started Jun 22 05:18:30 PM PDT 24
Finished Jun 22 05:22:05 PM PDT 24
Peak memory 266712 kb
Host smart-7787f7c2-b020-4087-840e-babc8a750085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284869717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.284869717
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3985218021
Short name T640
Test name
Test status
Simulation time 611288388 ps
CPU time 13.68 seconds
Started Jun 22 05:18:26 PM PDT 24
Finished Jun 22 05:18:40 PM PDT 24
Peak memory 251900 kb
Host smart-71df75a2-0e85-414b-bfb4-bf3d1ad63b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985218021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3985218021
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.20576346
Short name T632
Test name
Test status
Simulation time 1677946658 ps
CPU time 15.74 seconds
Started Jun 22 05:18:26 PM PDT 24
Finished Jun 22 05:18:43 PM PDT 24
Peak memory 225508 kb
Host smart-2a93cc8b-dd4f-4108-8dfb-21a75b0ad1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20576346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.20576346
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2027684225
Short name T581
Test name
Test status
Simulation time 515588658 ps
CPU time 7.78 seconds
Started Jun 22 05:18:25 PM PDT 24
Finished Jun 22 05:18:34 PM PDT 24
Peak memory 233760 kb
Host smart-05da0c67-0331-49e9-ba55-9b7aef2b95c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027684225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2027684225
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1334566413
Short name T627
Test name
Test status
Simulation time 28169636 ps
CPU time 1.1 seconds
Started Jun 22 05:18:22 PM PDT 24
Finished Jun 22 05:18:24 PM PDT 24
Peak memory 218852 kb
Host smart-d0898e04-a3d5-4d15-b890-38ad9e73a8d5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334566413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1334566413
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2034036610
Short name T398
Test name
Test status
Simulation time 33033145 ps
CPU time 2.63 seconds
Started Jun 22 05:18:27 PM PDT 24
Finished Jun 22 05:18:30 PM PDT 24
Peak memory 233392 kb
Host smart-8a3dfec8-a9fd-46e3-a0cd-72ce2d3af3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034036610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2034036610
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3577155197
Short name T721
Test name
Test status
Simulation time 472839690 ps
CPU time 9.85 seconds
Started Jun 22 05:18:24 PM PDT 24
Finished Jun 22 05:18:35 PM PDT 24
Peak memory 221872 kb
Host smart-c6f26780-6155-4430-83d4-756ebbaca209
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3577155197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3577155197
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.505370683
Short name T913
Test name
Test status
Simulation time 29259370449 ps
CPU time 170.72 seconds
Started Jun 22 05:18:27 PM PDT 24
Finished Jun 22 05:21:19 PM PDT 24
Peak memory 266708 kb
Host smart-01dce5ab-9845-4162-a66b-eb2e7ca81daa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505370683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.505370683
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1150227346
Short name T364
Test name
Test status
Simulation time 6018141012 ps
CPU time 14.65 seconds
Started Jun 22 05:18:28 PM PDT 24
Finished Jun 22 05:18:43 PM PDT 24
Peak memory 217452 kb
Host smart-771621cc-6946-4b31-9fd0-133f9267b66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150227346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1150227346
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2633923795
Short name T609
Test name
Test status
Simulation time 527814269 ps
CPU time 1.48 seconds
Started Jun 22 05:18:42 PM PDT 24
Finished Jun 22 05:18:45 PM PDT 24
Peak memory 207968 kb
Host smart-b8ab624c-bd49-41ae-80d3-5a6c75544f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633923795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2633923795
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.836953214
Short name T399
Test name
Test status
Simulation time 201536939 ps
CPU time 2.05 seconds
Started Jun 22 05:18:22 PM PDT 24
Finished Jun 22 05:18:25 PM PDT 24
Peak memory 217204 kb
Host smart-af873fd8-4ef0-4368-a910-870f268de848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836953214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.836953214
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1411430579
Short name T421
Test name
Test status
Simulation time 840859930 ps
CPU time 0.9 seconds
Started Jun 22 05:18:16 PM PDT 24
Finished Jun 22 05:18:18 PM PDT 24
Peak memory 206888 kb
Host smart-0a7f20b7-2f42-41d0-9bf5-74012a206c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411430579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1411430579
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2906625422
Short name T748
Test name
Test status
Simulation time 111140272 ps
CPU time 2.72 seconds
Started Jun 22 05:18:19 PM PDT 24
Finished Jun 22 05:18:22 PM PDT 24
Peak memory 233768 kb
Host smart-aa763f1b-7257-4185-9501-43f5d21c8e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906625422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2906625422
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2174364635
Short name T410
Test name
Test status
Simulation time 33142735 ps
CPU time 0.71 seconds
Started Jun 22 05:18:43 PM PDT 24
Finished Jun 22 05:18:44 PM PDT 24
Peak memory 205612 kb
Host smart-c0ddb7dc-8212-4736-a85f-e556e5367913
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174364635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2174364635
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3616544763
Short name T915
Test name
Test status
Simulation time 96958311 ps
CPU time 2.16 seconds
Started Jun 22 05:18:24 PM PDT 24
Finished Jun 22 05:18:27 PM PDT 24
Peak memory 225444 kb
Host smart-366bd7ef-c986-4a15-8852-8aa311bc6129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616544763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3616544763
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2150956354
Short name T895
Test name
Test status
Simulation time 34418089 ps
CPU time 0.79 seconds
Started Jun 22 05:18:23 PM PDT 24
Finished Jun 22 05:18:25 PM PDT 24
Peak memory 207388 kb
Host smart-3d8c57d0-1b02-4679-8c8e-381c5c268175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150956354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2150956354
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3299459632
Short name T538
Test name
Test status
Simulation time 11768557 ps
CPU time 0.78 seconds
Started Jun 22 05:18:34 PM PDT 24
Finished Jun 22 05:18:35 PM PDT 24
Peak memory 216808 kb
Host smart-95cde721-3b42-4031-b619-c46e78043743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299459632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3299459632
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.678770103
Short name T232
Test name
Test status
Simulation time 14802668362 ps
CPU time 154.04 seconds
Started Jun 22 05:18:38 PM PDT 24
Finished Jun 22 05:21:12 PM PDT 24
Peak memory 250324 kb
Host smart-84c9c590-f2bc-4673-8267-343169d5b841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678770103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.678770103
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.704659999
Short name T435
Test name
Test status
Simulation time 39900446215 ps
CPU time 398.39 seconds
Started Jun 22 05:18:25 PM PDT 24
Finished Jun 22 05:25:04 PM PDT 24
Peak memory 257696 kb
Host smart-b2549265-2ed1-494c-9428-88aaa8a75efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704659999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.704659999
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3594426744
Short name T75
Test name
Test status
Simulation time 583266905 ps
CPU time 4.25 seconds
Started Jun 22 05:18:36 PM PDT 24
Finished Jun 22 05:18:41 PM PDT 24
Peak memory 225588 kb
Host smart-e00d601d-57cf-4c77-a9fe-0c3ab694c5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594426744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3594426744
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1513956704
Short name T552
Test name
Test status
Simulation time 1113885617 ps
CPU time 4.2 seconds
Started Jun 22 05:18:24 PM PDT 24
Finished Jun 22 05:18:29 PM PDT 24
Peak memory 225364 kb
Host smart-d00dab4b-0265-4d80-9d6c-1aea37dd4aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513956704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1513956704
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.123732003
Short name T782
Test name
Test status
Simulation time 3687681049 ps
CPU time 31.41 seconds
Started Jun 22 05:18:23 PM PDT 24
Finished Jun 22 05:18:56 PM PDT 24
Peak memory 233824 kb
Host smart-f306348a-281e-4c71-a706-bfe02592a06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123732003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.123732003
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.430233910
Short name T524
Test name
Test status
Simulation time 221297121 ps
CPU time 1.12 seconds
Started Jun 22 05:18:29 PM PDT 24
Finished Jun 22 05:18:31 PM PDT 24
Peak memory 217592 kb
Host smart-bee88da5-b0cf-4a4f-a651-15517397f0db
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430233910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.430233910
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2628948956
Short name T245
Test name
Test status
Simulation time 1329675246 ps
CPU time 6.54 seconds
Started Jun 22 05:18:24 PM PDT 24
Finished Jun 22 05:18:36 PM PDT 24
Peak memory 233624 kb
Host smart-440ba0a2-9132-46ef-9e04-c1db1757c69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628948956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2628948956
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2618907850
Short name T900
Test name
Test status
Simulation time 6515868496 ps
CPU time 7.66 seconds
Started Jun 22 05:18:26 PM PDT 24
Finished Jun 22 05:18:35 PM PDT 24
Peak memory 224040 kb
Host smart-28a4e5db-3f2b-4770-8216-2f6d3bc76774
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2618907850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2618907850
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3170138143
Short name T795
Test name
Test status
Simulation time 30296495040 ps
CPU time 327.13 seconds
Started Jun 22 05:18:31 PM PDT 24
Finished Jun 22 05:23:59 PM PDT 24
Peak memory 264216 kb
Host smart-e86c4579-327a-4ea6-8efd-4252401e0f8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170138143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3170138143
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3154465352
Short name T854
Test name
Test status
Simulation time 7624822270 ps
CPU time 20.46 seconds
Started Jun 22 05:18:24 PM PDT 24
Finished Jun 22 05:18:46 PM PDT 24
Peak memory 217500 kb
Host smart-c83a339e-3974-4305-8a6e-a05a6f202277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154465352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3154465352
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.195370593
Short name T441
Test name
Test status
Simulation time 6795288982 ps
CPU time 20.84 seconds
Started Jun 22 05:18:19 PM PDT 24
Finished Jun 22 05:18:40 PM PDT 24
Peak memory 217524 kb
Host smart-65c0acbe-a696-4b8d-a099-5b6dbdf75196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195370593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.195370593
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.646867494
Short name T861
Test name
Test status
Simulation time 14094005 ps
CPU time 0.69 seconds
Started Jun 22 05:18:22 PM PDT 24
Finished Jun 22 05:18:24 PM PDT 24
Peak memory 206512 kb
Host smart-798619f2-1f6d-420c-967f-5eab3476916c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646867494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.646867494
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.155287668
Short name T571
Test name
Test status
Simulation time 207047907 ps
CPU time 0.9 seconds
Started Jun 22 05:18:22 PM PDT 24
Finished Jun 22 05:18:24 PM PDT 24
Peak memory 207876 kb
Host smart-19ef7288-70c9-455a-bca9-5705460e9d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155287668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.155287668
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.910337472
Short name T458
Test name
Test status
Simulation time 23021742937 ps
CPU time 20.96 seconds
Started Jun 22 05:18:26 PM PDT 24
Finished Jun 22 05:18:48 PM PDT 24
Peak memory 251688 kb
Host smart-314ea203-39fd-46c6-ad28-b5090ecc8d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910337472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.910337472
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1839980508
Short name T478
Test name
Test status
Simulation time 26133548 ps
CPU time 0.75 seconds
Started Jun 22 05:18:30 PM PDT 24
Finished Jun 22 05:18:36 PM PDT 24
Peak memory 205716 kb
Host smart-e50158cf-f90a-4277-bd1a-4ce1125b3875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839980508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1839980508
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2216650766
Short name T709
Test name
Test status
Simulation time 404582056 ps
CPU time 2.99 seconds
Started Jun 22 05:18:26 PM PDT 24
Finished Jun 22 05:18:31 PM PDT 24
Peak memory 225468 kb
Host smart-fcee2548-a976-4b85-81b6-30885ad79bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216650766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2216650766
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1837408314
Short name T377
Test name
Test status
Simulation time 38476591 ps
CPU time 0.75 seconds
Started Jun 22 05:18:24 PM PDT 24
Finished Jun 22 05:18:26 PM PDT 24
Peak memory 207832 kb
Host smart-9c687b2a-bcb3-443b-9261-1296ed37463e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837408314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1837408314
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2058503451
Short name T233
Test name
Test status
Simulation time 43753546686 ps
CPU time 98.2 seconds
Started Jun 22 05:18:36 PM PDT 24
Finished Jun 22 05:20:15 PM PDT 24
Peak memory 250288 kb
Host smart-263f4eb4-6dce-4992-b8ef-5d9e6f6a65a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058503451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2058503451
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.4156734422
Short name T303
Test name
Test status
Simulation time 562145525 ps
CPU time 6.82 seconds
Started Jun 22 05:18:28 PM PDT 24
Finished Jun 22 05:18:35 PM PDT 24
Peak memory 238304 kb
Host smart-a306678d-22a6-4b36-949e-08ea16b7b7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156734422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.4156734422
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1089427113
Short name T214
Test name
Test status
Simulation time 4469269600 ps
CPU time 21.53 seconds
Started Jun 22 05:18:45 PM PDT 24
Finished Jun 22 05:19:07 PM PDT 24
Peak memory 225644 kb
Host smart-f452a8d5-6204-48d1-aaf2-4a84cf0d181c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089427113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1089427113
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1524515392
Short name T770
Test name
Test status
Simulation time 2272249313 ps
CPU time 23.6 seconds
Started Jun 22 05:18:26 PM PDT 24
Finished Jun 22 05:18:51 PM PDT 24
Peak memory 240028 kb
Host smart-63acc3b0-a0fe-43f0-8543-60451e5851a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524515392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1524515392
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1362236676
Short name T408
Test name
Test status
Simulation time 146261278 ps
CPU time 1.07 seconds
Started Jun 22 05:18:24 PM PDT 24
Finished Jun 22 05:18:27 PM PDT 24
Peak memory 217624 kb
Host smart-c8d56d8e-38ac-440d-bc73-f0dc653c65bd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362236676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1362236676
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2909324687
Short name T728
Test name
Test status
Simulation time 169979001 ps
CPU time 3.97 seconds
Started Jun 22 05:18:27 PM PDT 24
Finished Jun 22 05:18:32 PM PDT 24
Peak memory 233704 kb
Host smart-242b7ebf-7366-48ac-947c-c52f75fcf52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909324687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2909324687
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3718107920
Short name T490
Test name
Test status
Simulation time 6412535037 ps
CPU time 9.26 seconds
Started Jun 22 05:18:41 PM PDT 24
Finished Jun 22 05:18:51 PM PDT 24
Peak memory 233856 kb
Host smart-e31f596a-f7a7-43b2-8060-29bcac31fa6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718107920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3718107920
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.4214731334
Short name T406
Test name
Test status
Simulation time 768708448 ps
CPU time 9.09 seconds
Started Jun 22 05:18:32 PM PDT 24
Finished Jun 22 05:18:42 PM PDT 24
Peak memory 223364 kb
Host smart-0e1ba480-6566-410a-836f-a940caeeccc1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4214731334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.4214731334
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3041224897
Short name T839
Test name
Test status
Simulation time 136632740820 ps
CPU time 242.71 seconds
Started Jun 22 05:18:43 PM PDT 24
Finished Jun 22 05:22:46 PM PDT 24
Peak memory 258124 kb
Host smart-07d91cb2-6cf9-4129-b38b-d540b6eff39c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041224897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3041224897
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.306119640
Short name T752
Test name
Test status
Simulation time 6462656543 ps
CPU time 33.77 seconds
Started Jun 22 05:18:28 PM PDT 24
Finished Jun 22 05:19:03 PM PDT 24
Peak memory 217512 kb
Host smart-09285148-790f-44af-bb34-5d47e06388a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306119640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.306119640
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.856255690
Short name T608
Test name
Test status
Simulation time 1852564131 ps
CPU time 8.05 seconds
Started Jun 22 05:18:26 PM PDT 24
Finished Jun 22 05:18:35 PM PDT 24
Peak memory 217280 kb
Host smart-5db19eff-ce82-455a-9b13-2d19319b761c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856255690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.856255690
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3730368726
Short name T488
Test name
Test status
Simulation time 15341303 ps
CPU time 1.09 seconds
Started Jun 22 05:18:42 PM PDT 24
Finished Jun 22 05:18:44 PM PDT 24
Peak memory 217124 kb
Host smart-f34c1bec-89b7-484e-a623-54e966d55781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730368726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3730368726
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.459072259
Short name T876
Test name
Test status
Simulation time 101416387 ps
CPU time 0.71 seconds
Started Jun 22 05:18:26 PM PDT 24
Finished Jun 22 05:18:28 PM PDT 24
Peak memory 206848 kb
Host smart-2ca402c6-e020-42e6-9ad8-905082307802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459072259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.459072259
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1863858944
Short name T727
Test name
Test status
Simulation time 11785106262 ps
CPU time 22.46 seconds
Started Jun 22 05:18:39 PM PDT 24
Finished Jun 22 05:19:02 PM PDT 24
Peak memory 233828 kb
Host smart-d68d2d40-a021-4a52-9af8-bfbd172d8e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863858944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1863858944
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3445532544
Short name T366
Test name
Test status
Simulation time 10516275 ps
CPU time 0.76 seconds
Started Jun 22 05:18:31 PM PDT 24
Finished Jun 22 05:18:32 PM PDT 24
Peak memory 206588 kb
Host smart-d7bf48bc-90fd-447a-a985-3e89a7a1842a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445532544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3445532544
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1943599699
Short name T413
Test name
Test status
Simulation time 1018926581 ps
CPU time 4.31 seconds
Started Jun 22 05:18:26 PM PDT 24
Finished Jun 22 05:18:32 PM PDT 24
Peak memory 233768 kb
Host smart-eae3a31d-1e4f-4719-8ef8-87fb54426447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943599699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1943599699
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3418900689
Short name T325
Test name
Test status
Simulation time 60637639 ps
CPU time 0.78 seconds
Started Jun 22 05:18:32 PM PDT 24
Finished Jun 22 05:18:33 PM PDT 24
Peak memory 207356 kb
Host smart-9877eda7-6ff7-43f4-8afb-d85584c4dde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418900689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3418900689
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1424296629
Short name T152
Test name
Test status
Simulation time 5228393333 ps
CPU time 11.09 seconds
Started Jun 22 05:18:31 PM PDT 24
Finished Jun 22 05:18:42 PM PDT 24
Peak memory 236644 kb
Host smart-a25aadd8-0931-469b-a9dd-a2f75999c892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424296629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1424296629
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1022956819
Short name T545
Test name
Test status
Simulation time 31803435686 ps
CPU time 171.4 seconds
Started Jun 22 05:18:31 PM PDT 24
Finished Jun 22 05:21:23 PM PDT 24
Peak memory 252424 kb
Host smart-3e43ae62-af78-4fba-8c39-5c0d82096167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022956819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1022956819
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.660387997
Short name T306
Test name
Test status
Simulation time 228873781 ps
CPU time 6.14 seconds
Started Jun 22 05:18:37 PM PDT 24
Finished Jun 22 05:18:44 PM PDT 24
Peak memory 225588 kb
Host smart-bb7fecef-5794-45d2-a488-07e53df7dc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660387997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.660387997
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3378125178
Short name T758
Test name
Test status
Simulation time 7053071658 ps
CPU time 17.78 seconds
Started Jun 22 05:18:29 PM PDT 24
Finished Jun 22 05:18:48 PM PDT 24
Peak memory 233872 kb
Host smart-6b7dd5e8-745d-464a-b57b-8010a627411d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378125178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3378125178
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1865241037
Short name T957
Test name
Test status
Simulation time 5026341322 ps
CPU time 53.9 seconds
Started Jun 22 05:18:25 PM PDT 24
Finished Jun 22 05:19:20 PM PDT 24
Peak memory 233744 kb
Host smart-0d59bcc0-6354-4559-bc80-0ff15fc8604a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865241037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1865241037
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1020859003
Short name T594
Test name
Test status
Simulation time 144330101 ps
CPU time 1.01 seconds
Started Jun 22 05:18:31 PM PDT 24
Finished Jun 22 05:18:33 PM PDT 24
Peak memory 219016 kb
Host smart-c6fb45ce-6a1b-4c27-8898-94e5c57296dc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020859003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1020859003
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3159334976
Short name T212
Test name
Test status
Simulation time 640930377 ps
CPU time 6.91 seconds
Started Jun 22 05:18:28 PM PDT 24
Finished Jun 22 05:18:36 PM PDT 24
Peak memory 233728 kb
Host smart-1b96b076-ccdc-483a-9480-eace12fbb987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159334976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3159334976
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.4253686070
Short name T789
Test name
Test status
Simulation time 60523742 ps
CPU time 2.22 seconds
Started Jun 22 05:18:27 PM PDT 24
Finished Jun 22 05:18:30 PM PDT 24
Peak memory 233472 kb
Host smart-568c9d9e-05c0-4724-8abc-fbe2130d88eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253686070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.4253686070
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.888057452
Short name T529
Test name
Test status
Simulation time 835574281 ps
CPU time 11.27 seconds
Started Jun 22 05:18:32 PM PDT 24
Finished Jun 22 05:18:44 PM PDT 24
Peak memory 223044 kb
Host smart-f34dafd7-96f1-4b69-9ad0-48aebb1a8bd2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=888057452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.888057452
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3038745099
Short name T722
Test name
Test status
Simulation time 6361382749 ps
CPU time 35.79 seconds
Started Jun 22 05:18:31 PM PDT 24
Finished Jun 22 05:19:08 PM PDT 24
Peak memory 217500 kb
Host smart-e53ebaff-7b07-4a12-a797-a897cff5fff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038745099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3038745099
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.944293095
Short name T323
Test name
Test status
Simulation time 168999339 ps
CPU time 1.39 seconds
Started Jun 22 05:18:26 PM PDT 24
Finished Jun 22 05:18:29 PM PDT 24
Peak memory 208880 kb
Host smart-e0abadc4-ede6-43b1-9b37-5c1f7c29b987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944293095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.944293095
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1759505854
Short name T543
Test name
Test status
Simulation time 130744478 ps
CPU time 1.8 seconds
Started Jun 22 05:18:26 PM PDT 24
Finished Jun 22 05:18:29 PM PDT 24
Peak memory 217320 kb
Host smart-5ac3fa85-701f-4e22-82f3-1b8c51cf74b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759505854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1759505854
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.326025072
Short name T824
Test name
Test status
Simulation time 564406502 ps
CPU time 0.96 seconds
Started Jun 22 05:18:32 PM PDT 24
Finished Jun 22 05:18:33 PM PDT 24
Peak memory 207064 kb
Host smart-c2becee1-0f65-4a40-9df5-ffe5e05b1f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326025072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.326025072
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.4161079548
Short name T479
Test name
Test status
Simulation time 60550406 ps
CPU time 2.19 seconds
Started Jun 22 05:18:25 PM PDT 24
Finished Jun 22 05:18:28 PM PDT 24
Peak memory 224032 kb
Host smart-0da50176-ff23-42d4-bdd3-dd1669ec15a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161079548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.4161079548
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1596043276
Short name T838
Test name
Test status
Simulation time 42662711 ps
CPU time 0.76 seconds
Started Jun 22 05:18:35 PM PDT 24
Finished Jun 22 05:18:37 PM PDT 24
Peak memory 205688 kb
Host smart-d199135f-2de5-42c2-b58b-e6c4c9c30837
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596043276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1596043276
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3637536305
Short name T610
Test name
Test status
Simulation time 221528457 ps
CPU time 2.86 seconds
Started Jun 22 05:18:36 PM PDT 24
Finished Jun 22 05:18:40 PM PDT 24
Peak memory 233748 kb
Host smart-1ab73d3f-255b-484c-810a-7a1667b69015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637536305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3637536305
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1034448678
Short name T733
Test name
Test status
Simulation time 51058130 ps
CPU time 0.81 seconds
Started Jun 22 05:18:39 PM PDT 24
Finished Jun 22 05:18:40 PM PDT 24
Peak memory 207460 kb
Host smart-85df62a1-29c4-4af0-963d-8ba2a21ccb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034448678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1034448678
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1880577957
Short name T187
Test name
Test status
Simulation time 655917956223 ps
CPU time 325.73 seconds
Started Jun 22 05:18:39 PM PDT 24
Finished Jun 22 05:24:05 PM PDT 24
Peak memory 258464 kb
Host smart-3b02d91e-53be-4029-9772-2f58860bed9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880577957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1880577957
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3084772435
Short name T184
Test name
Test status
Simulation time 4755667356 ps
CPU time 113.3 seconds
Started Jun 22 05:18:31 PM PDT 24
Finished Jun 22 05:20:25 PM PDT 24
Peak memory 284608 kb
Host smart-d5d04780-6e46-4c0f-ad4f-628e1bec279b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084772435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3084772435
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3264471201
Short name T281
Test name
Test status
Simulation time 24335246507 ps
CPU time 153.37 seconds
Started Jun 22 05:18:34 PM PDT 24
Finished Jun 22 05:21:08 PM PDT 24
Peak memory 266712 kb
Host smart-808e22f4-80d2-4d9a-94d9-8dacb04f927a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264471201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3264471201
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1791771131
Short name T308
Test name
Test status
Simulation time 1563733938 ps
CPU time 16.94 seconds
Started Jun 22 05:18:40 PM PDT 24
Finished Jun 22 05:18:58 PM PDT 24
Peak memory 225476 kb
Host smart-00c2933d-adec-426d-8618-9096ec99c512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791771131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1791771131
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.285355062
Short name T375
Test name
Test status
Simulation time 295332860 ps
CPU time 3.18 seconds
Started Jun 22 05:18:39 PM PDT 24
Finished Jun 22 05:18:43 PM PDT 24
Peak memory 225444 kb
Host smart-a8c16157-94aa-456a-a59d-a08edf44c1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285355062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.285355062
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1309082025
Short name T23
Test name
Test status
Simulation time 12514198471 ps
CPU time 40.01 seconds
Started Jun 22 05:18:36 PM PDT 24
Finished Jun 22 05:19:17 PM PDT 24
Peak memory 241968 kb
Host smart-550e0d90-37ce-451d-8f7c-38fd56f522bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309082025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1309082025
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1664038539
Short name T397
Test name
Test status
Simulation time 17348044 ps
CPU time 1.14 seconds
Started Jun 22 05:18:39 PM PDT 24
Finished Jun 22 05:18:41 PM PDT 24
Peak memory 218844 kb
Host smart-b80673bd-6d41-4936-a533-3cce789a61e4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664038539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1664038539
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2731601552
Short name T642
Test name
Test status
Simulation time 28134548027 ps
CPU time 10.57 seconds
Started Jun 22 05:18:37 PM PDT 24
Finished Jun 22 05:18:48 PM PDT 24
Peak memory 225604 kb
Host smart-717e38d0-56ad-4a41-a101-b7d692452236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731601552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2731601552
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3630841589
Short name T666
Test name
Test status
Simulation time 276474546 ps
CPU time 2.53 seconds
Started Jun 22 05:18:40 PM PDT 24
Finished Jun 22 05:18:43 PM PDT 24
Peak memory 233796 kb
Host smart-280b60e7-2184-4632-a68d-4a098f782e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630841589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3630841589
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1264346442
Short name T958
Test name
Test status
Simulation time 993410149 ps
CPU time 9.82 seconds
Started Jun 22 05:18:36 PM PDT 24
Finished Jun 22 05:18:47 PM PDT 24
Peak memory 220900 kb
Host smart-dea3b29f-9091-4f57-9876-539ade94b680
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1264346442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1264346442
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1456038377
Short name T268
Test name
Test status
Simulation time 293246913564 ps
CPU time 698.2 seconds
Started Jun 22 05:18:38 PM PDT 24
Finished Jun 22 05:30:17 PM PDT 24
Peak memory 274644 kb
Host smart-4b7efbbf-53c9-4565-b9da-f0170798cc71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456038377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1456038377
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.427440881
Short name T825
Test name
Test status
Simulation time 25489827983 ps
CPU time 22.53 seconds
Started Jun 22 05:18:40 PM PDT 24
Finished Jun 22 05:19:03 PM PDT 24
Peak memory 217628 kb
Host smart-1520e017-3696-41fa-8fd4-cd58404c70fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427440881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.427440881
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3940838662
Short name T553
Test name
Test status
Simulation time 46774577 ps
CPU time 0.75 seconds
Started Jun 22 05:18:41 PM PDT 24
Finished Jun 22 05:18:42 PM PDT 24
Peak memory 206584 kb
Host smart-cf5f65f7-bf5d-44dc-b34e-c505fd9aa828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940838662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3940838662
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.42927932
Short name T591
Test name
Test status
Simulation time 41609506 ps
CPU time 1.28 seconds
Started Jun 22 05:18:43 PM PDT 24
Finished Jun 22 05:18:45 PM PDT 24
Peak memory 217380 kb
Host smart-7f10fd58-17a9-4520-9e0d-16d11c8ae96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42927932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.42927932
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2413614616
Short name T80
Test name
Test status
Simulation time 333482181 ps
CPU time 0.98 seconds
Started Jun 22 05:18:40 PM PDT 24
Finished Jun 22 05:18:42 PM PDT 24
Peak memory 206768 kb
Host smart-516b4d5c-9286-41a3-a3fd-a76f110f125c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413614616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2413614616
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2601284901
Short name T661
Test name
Test status
Simulation time 4553789741 ps
CPU time 6.1 seconds
Started Jun 22 05:18:35 PM PDT 24
Finished Jun 22 05:18:41 PM PDT 24
Peak memory 233860 kb
Host smart-46da7aeb-19d8-40d1-bef6-0eae9bac1fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601284901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2601284901
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.806140392
Short name T583
Test name
Test status
Simulation time 1147189572 ps
CPU time 3.33 seconds
Started Jun 22 05:17:59 PM PDT 24
Finished Jun 22 05:18:03 PM PDT 24
Peak memory 225488 kb
Host smart-ca3f8c4b-7a91-4b44-b883-563c8a77253a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806140392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.806140392
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.381304156
Short name T332
Test name
Test status
Simulation time 51794824 ps
CPU time 0.75 seconds
Started Jun 22 05:17:41 PM PDT 24
Finished Jun 22 05:17:43 PM PDT 24
Peak memory 207816 kb
Host smart-895c1796-60fe-4cb4-a930-b7ced83dccbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381304156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.381304156
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.320134163
Short name T707
Test name
Test status
Simulation time 243228970 ps
CPU time 5.71 seconds
Started Jun 22 05:17:41 PM PDT 24
Finished Jun 22 05:17:48 PM PDT 24
Peak memory 236992 kb
Host smart-b2d5e3c0-93b5-4a18-92d4-b7598d9a75d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320134163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.320134163
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2600399693
Short name T741
Test name
Test status
Simulation time 6060699755 ps
CPU time 32.42 seconds
Started Jun 22 05:18:02 PM PDT 24
Finished Jun 22 05:18:35 PM PDT 24
Peak memory 240692 kb
Host smart-1296e3a9-100b-4e86-8cdc-995eb12acbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600399693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2600399693
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3536793720
Short name T573
Test name
Test status
Simulation time 38316640 ps
CPU time 2.86 seconds
Started Jun 22 05:17:57 PM PDT 24
Finished Jun 22 05:18:00 PM PDT 24
Peak memory 233844 kb
Host smart-5d7c2ee2-3767-4da0-a2e1-6cf9d898f5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536793720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3536793720
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3677846102
Short name T229
Test name
Test status
Simulation time 7227995178 ps
CPU time 17.4 seconds
Started Jun 22 05:17:54 PM PDT 24
Finished Jun 22 05:18:12 PM PDT 24
Peak memory 225588 kb
Host smart-7f87c25e-fb11-4571-b00b-0419605bb1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677846102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3677846102
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1878634725
Short name T745
Test name
Test status
Simulation time 722704417 ps
CPU time 8.86 seconds
Started Jun 22 05:17:43 PM PDT 24
Finished Jun 22 05:17:52 PM PDT 24
Peak memory 225504 kb
Host smart-c8c0201a-d174-40a7-910c-bba9043250e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878634725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1878634725
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.252092947
Short name T384
Test name
Test status
Simulation time 28548962 ps
CPU time 1.16 seconds
Started Jun 22 05:17:38 PM PDT 24
Finished Jun 22 05:17:42 PM PDT 24
Peak memory 217596 kb
Host smart-11b9e286-af88-4871-a4cb-8c6ce8543914
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252092947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.252092947
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2522686628
Short name T623
Test name
Test status
Simulation time 3074206937 ps
CPU time 11.41 seconds
Started Jun 22 05:17:45 PM PDT 24
Finished Jun 22 05:17:57 PM PDT 24
Peak memory 233796 kb
Host smart-493226e5-bd26-4a98-921e-8f5772164226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522686628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2522686628
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3847899374
Short name T857
Test name
Test status
Simulation time 673321334 ps
CPU time 4.54 seconds
Started Jun 22 05:17:35 PM PDT 24
Finished Jun 22 05:17:43 PM PDT 24
Peak memory 225456 kb
Host smart-dfe3070f-bcc4-42f6-a45b-0cf2713a4222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847899374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3847899374
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.335329204
Short name T815
Test name
Test status
Simulation time 289516902 ps
CPU time 3.02 seconds
Started Jun 22 05:18:21 PM PDT 24
Finished Jun 22 05:18:25 PM PDT 24
Peak memory 219776 kb
Host smart-dee1e5e3-a3f5-4649-b8fb-db3dc58b8d04
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=335329204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.335329204
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3888993295
Short name T67
Test name
Test status
Simulation time 67324713 ps
CPU time 0.95 seconds
Started Jun 22 05:17:46 PM PDT 24
Finished Jun 22 05:17:48 PM PDT 24
Peak memory 236392 kb
Host smart-1825fabb-9c6d-421d-a6d9-c318ed6403ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888993295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3888993295
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1642036263
Short name T417
Test name
Test status
Simulation time 5319061441 ps
CPU time 32.23 seconds
Started Jun 22 05:17:46 PM PDT 24
Finished Jun 22 05:18:19 PM PDT 24
Peak memory 250352 kb
Host smart-64e79060-9e99-42dd-a968-08292c47c99e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642036263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1642036263
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.876723581
Short name T708
Test name
Test status
Simulation time 2692578477 ps
CPU time 5.45 seconds
Started Jun 22 05:17:40 PM PDT 24
Finished Jun 22 05:17:47 PM PDT 24
Peak memory 217744 kb
Host smart-f8172c7e-3363-469d-a0b7-34322873f5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876723581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.876723581
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2524209124
Short name T749
Test name
Test status
Simulation time 522209768 ps
CPU time 2.92 seconds
Started Jun 22 05:17:40 PM PDT 24
Finished Jun 22 05:17:44 PM PDT 24
Peak memory 217316 kb
Host smart-ac8c264c-21a2-4feb-afc1-fd8baf0e8890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524209124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2524209124
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.185806423
Short name T969
Test name
Test status
Simulation time 38676713 ps
CPU time 0.98 seconds
Started Jun 22 05:17:46 PM PDT 24
Finished Jun 22 05:17:47 PM PDT 24
Peak memory 208888 kb
Host smart-05114a81-3270-4a02-8e27-97962312d784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185806423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.185806423
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3392421353
Short name T760
Test name
Test status
Simulation time 13916480 ps
CPU time 0.72 seconds
Started Jun 22 05:17:52 PM PDT 24
Finished Jun 22 05:17:53 PM PDT 24
Peak memory 206532 kb
Host smart-2b4aceb7-e4ea-4634-bd47-6b6e9196317e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392421353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3392421353
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.997119603
Short name T257
Test name
Test status
Simulation time 958598627 ps
CPU time 8.51 seconds
Started Jun 22 05:17:52 PM PDT 24
Finished Jun 22 05:18:01 PM PDT 24
Peak memory 241440 kb
Host smart-32247bcb-6a16-4229-bea2-67330241abfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997119603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.997119603
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1651018482
Short name T806
Test name
Test status
Simulation time 52322636 ps
CPU time 0.74 seconds
Started Jun 22 05:18:40 PM PDT 24
Finished Jun 22 05:18:42 PM PDT 24
Peak memory 205720 kb
Host smart-76267634-81dc-4b19-ad5c-6e37b1710ec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651018482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1651018482
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3044393733
Short name T242
Test name
Test status
Simulation time 283915103 ps
CPU time 5.31 seconds
Started Jun 22 05:18:37 PM PDT 24
Finished Jun 22 05:18:43 PM PDT 24
Peak memory 233668 kb
Host smart-cfed2bcc-bb2d-4dec-953f-96275e135679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044393733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3044393733
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1775208937
Short name T961
Test name
Test status
Simulation time 36142196 ps
CPU time 0.8 seconds
Started Jun 22 05:18:40 PM PDT 24
Finished Jun 22 05:18:41 PM PDT 24
Peak memory 207472 kb
Host smart-b3797934-f617-4756-a875-65ce2e70ffda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775208937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1775208937
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1759584889
Short name T904
Test name
Test status
Simulation time 64676262779 ps
CPU time 437.67 seconds
Started Jun 22 05:18:41 PM PDT 24
Finished Jun 22 05:26:00 PM PDT 24
Peak memory 257040 kb
Host smart-80afa5d0-821d-43c0-944c-6b3ba91485e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759584889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1759584889
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1006346285
Short name T967
Test name
Test status
Simulation time 7264779605 ps
CPU time 91.22 seconds
Started Jun 22 05:18:38 PM PDT 24
Finished Jun 22 05:20:10 PM PDT 24
Peak memory 256340 kb
Host smart-008be594-1f95-4fb2-85a6-b4fab12c01cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006346285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1006346285
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2365829408
Short name T263
Test name
Test status
Simulation time 57658797745 ps
CPU time 326.61 seconds
Started Jun 22 05:18:56 PM PDT 24
Finished Jun 22 05:24:23 PM PDT 24
Peak memory 266092 kb
Host smart-bf2f8c71-2566-4d92-944e-3e1853798154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365829408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2365829408
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2124844992
Short name T660
Test name
Test status
Simulation time 495617993 ps
CPU time 3.66 seconds
Started Jun 22 05:18:40 PM PDT 24
Finished Jun 22 05:18:44 PM PDT 24
Peak memory 225584 kb
Host smart-6bebd9a9-2f5f-464f-997c-81b097d609a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124844992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2124844992
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3156536291
Short name T238
Test name
Test status
Simulation time 5891582218 ps
CPU time 14.45 seconds
Started Jun 22 05:18:37 PM PDT 24
Finished Jun 22 05:18:52 PM PDT 24
Peak memory 233916 kb
Host smart-15fb1907-e1b1-460b-ab21-59778a043c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156536291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3156536291
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.427403725
Short name T235
Test name
Test status
Simulation time 1461806496 ps
CPU time 22.12 seconds
Started Jun 22 05:18:38 PM PDT 24
Finished Jun 22 05:19:01 PM PDT 24
Peak memory 225472 kb
Host smart-e0a78f9f-c1f1-4714-bec9-9ede4ba88265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427403725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.427403725
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3910521821
Short name T277
Test name
Test status
Simulation time 1037265393 ps
CPU time 4.76 seconds
Started Jun 22 05:18:36 PM PDT 24
Finished Jun 22 05:18:42 PM PDT 24
Peak memory 233656 kb
Host smart-c2de4600-b6f3-4ff3-a441-0bbecbc0002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910521821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3910521821
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2301810237
Short name T875
Test name
Test status
Simulation time 242935198 ps
CPU time 2.98 seconds
Started Jun 22 05:18:40 PM PDT 24
Finished Jun 22 05:18:44 PM PDT 24
Peak memory 225544 kb
Host smart-f2ba8152-4902-4575-a97b-9231f8fcd3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301810237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2301810237
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1558613380
Short name T718
Test name
Test status
Simulation time 5291393505 ps
CPU time 13.65 seconds
Started Jun 22 05:18:43 PM PDT 24
Finished Jun 22 05:18:57 PM PDT 24
Peak memory 224236 kb
Host smart-9d0c6123-1b4a-4757-9e9c-31143b930b9a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1558613380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1558613380
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3648911777
Short name T828
Test name
Test status
Simulation time 216645225 ps
CPU time 3.73 seconds
Started Jun 22 05:18:37 PM PDT 24
Finished Jun 22 05:18:41 PM PDT 24
Peak memory 217612 kb
Host smart-d6224a01-5800-4763-9e18-dcf8e2dbbf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648911777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3648911777
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3781617189
Short name T740
Test name
Test status
Simulation time 3274360632 ps
CPU time 15.17 seconds
Started Jun 22 05:18:43 PM PDT 24
Finished Jun 22 05:18:59 PM PDT 24
Peak memory 217512 kb
Host smart-a11a0210-9b6e-4689-91a3-99edeb65b63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781617189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3781617189
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1459021965
Short name T518
Test name
Test status
Simulation time 36918272 ps
CPU time 1.35 seconds
Started Jun 22 05:18:36 PM PDT 24
Finished Jun 22 05:18:38 PM PDT 24
Peak memory 209092 kb
Host smart-f6b487a9-0bba-4c5f-ac88-133a16153e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459021965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1459021965
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2797692891
Short name T348
Test name
Test status
Simulation time 246468468 ps
CPU time 0.88 seconds
Started Jun 22 05:18:38 PM PDT 24
Finished Jun 22 05:18:39 PM PDT 24
Peak memory 206880 kb
Host smart-88a97b4d-f939-44ad-88ec-2a7b78b22c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797692891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2797692891
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.429201774
Short name T596
Test name
Test status
Simulation time 239263410 ps
CPU time 4.39 seconds
Started Jun 22 05:18:42 PM PDT 24
Finished Jun 22 05:18:47 PM PDT 24
Peak memory 233648 kb
Host smart-d00c8a2e-b2bc-4487-93d2-20914f3f1179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429201774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.429201774
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3962796479
Short name T344
Test name
Test status
Simulation time 11616286 ps
CPU time 0.72 seconds
Started Jun 22 05:18:45 PM PDT 24
Finished Jun 22 05:18:47 PM PDT 24
Peak memory 206652 kb
Host smart-516c80df-95de-478c-9a63-f5f29baa4cbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962796479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3962796479
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.550607900
Short name T757
Test name
Test status
Simulation time 221536756 ps
CPU time 2.27 seconds
Started Jun 22 05:18:39 PM PDT 24
Finished Jun 22 05:18:42 PM PDT 24
Peak memory 225460 kb
Host smart-9c434cb7-347a-4237-ae23-df1c0a4f09dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550607900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.550607900
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1813783218
Short name T465
Test name
Test status
Simulation time 71022996 ps
CPU time 0.83 seconds
Started Jun 22 05:18:50 PM PDT 24
Finished Jun 22 05:18:52 PM PDT 24
Peak memory 207800 kb
Host smart-a32ba41e-8bc4-470c-97b7-df60582c0067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813783218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1813783218
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1286081763
Short name T272
Test name
Test status
Simulation time 27217446142 ps
CPU time 32.5 seconds
Started Jun 22 05:18:43 PM PDT 24
Finished Jun 22 05:19:16 PM PDT 24
Peak memory 225704 kb
Host smart-24c792c7-2701-4f52-ae4b-70770ad89101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286081763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1286081763
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.23838597
Short name T128
Test name
Test status
Simulation time 13235510377 ps
CPU time 105.24 seconds
Started Jun 22 05:18:46 PM PDT 24
Finished Jun 22 05:20:32 PM PDT 24
Peak memory 250332 kb
Host smart-db1285f5-a33e-4b6f-9917-89ebdb8c32d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23838597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.23838597
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.984888253
Short name T853
Test name
Test status
Simulation time 47794408304 ps
CPU time 115.93 seconds
Started Jun 22 05:18:48 PM PDT 24
Finished Jun 22 05:20:44 PM PDT 24
Peak memory 258508 kb
Host smart-a47962b3-bed3-4cec-a292-9265d8495657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984888253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.984888253
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1979733105
Short name T356
Test name
Test status
Simulation time 14587645252 ps
CPU time 58.76 seconds
Started Jun 22 05:18:41 PM PDT 24
Finished Jun 22 05:19:41 PM PDT 24
Peak memory 250264 kb
Host smart-a909a335-cac5-42a6-9ebc-7b21437cf489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979733105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1979733105
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2662114946
Short name T812
Test name
Test status
Simulation time 451199738 ps
CPU time 6.02 seconds
Started Jun 22 05:18:45 PM PDT 24
Finished Jun 22 05:18:52 PM PDT 24
Peak memory 233788 kb
Host smart-9ce56f21-275a-46e7-b985-0f47e4fb5601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662114946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2662114946
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3891352394
Short name T674
Test name
Test status
Simulation time 31293182509 ps
CPU time 131.24 seconds
Started Jun 22 05:18:50 PM PDT 24
Finished Jun 22 05:21:02 PM PDT 24
Peak memory 233860 kb
Host smart-3b59671c-97ae-4b36-bb24-e83be2e7719a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891352394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3891352394
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2383598303
Short name T265
Test name
Test status
Simulation time 3809298577 ps
CPU time 14.55 seconds
Started Jun 22 05:18:39 PM PDT 24
Finished Jun 22 05:18:54 PM PDT 24
Peak memory 233796 kb
Host smart-e4128659-8ab9-4f0e-bbde-281dade069e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383598303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2383598303
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.177867031
Short name T510
Test name
Test status
Simulation time 14036078396 ps
CPU time 11.63 seconds
Started Jun 22 05:18:47 PM PDT 24
Finished Jun 22 05:19:00 PM PDT 24
Peak memory 225624 kb
Host smart-d1c90752-3313-4875-a176-d08a3124c744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177867031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.177867031
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3139513106
Short name T973
Test name
Test status
Simulation time 711835515 ps
CPU time 4.23 seconds
Started Jun 22 05:18:39 PM PDT 24
Finished Jun 22 05:18:43 PM PDT 24
Peak memory 223568 kb
Host smart-a2d106e5-20ae-4d06-9054-3a61ae579f38
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3139513106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3139513106
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3446135009
Short name T132
Test name
Test status
Simulation time 15002275649 ps
CPU time 156.28 seconds
Started Jun 22 05:18:43 PM PDT 24
Finished Jun 22 05:21:20 PM PDT 24
Peak memory 250324 kb
Host smart-7b63156f-2b61-4740-80ee-ae788b270b05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446135009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3446135009
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2000508401
Short name T362
Test name
Test status
Simulation time 11873638 ps
CPU time 0.72 seconds
Started Jun 22 05:18:45 PM PDT 24
Finished Jun 22 05:18:46 PM PDT 24
Peak memory 206640 kb
Host smart-e278e0a8-86c2-4564-8e34-4881a3d68297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000508401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2000508401
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2554388306
Short name T650
Test name
Test status
Simulation time 12594362996 ps
CPU time 20.45 seconds
Started Jun 22 05:18:46 PM PDT 24
Finished Jun 22 05:19:07 PM PDT 24
Peak memory 217416 kb
Host smart-39c1dcd9-27fe-476b-a710-51754bd2bf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554388306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2554388306
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2158790315
Short name T635
Test name
Test status
Simulation time 16336976 ps
CPU time 0.85 seconds
Started Jun 22 05:18:44 PM PDT 24
Finished Jun 22 05:18:46 PM PDT 24
Peak memory 207888 kb
Host smart-2474ac8b-0cec-4e89-904f-e989208f5825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158790315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2158790315
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1473211420
Short name T416
Test name
Test status
Simulation time 133480020 ps
CPU time 0.88 seconds
Started Jun 22 05:18:39 PM PDT 24
Finished Jun 22 05:18:41 PM PDT 24
Peak memory 206800 kb
Host smart-38a28d00-3fb8-4854-a361-1571d86fdda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473211420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1473211420
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.437466577
Short name T679
Test name
Test status
Simulation time 2281601709 ps
CPU time 11.9 seconds
Started Jun 22 05:18:40 PM PDT 24
Finished Jun 22 05:18:53 PM PDT 24
Peak memory 233928 kb
Host smart-cefb15fd-6d35-4ad8-9dd5-0c275da45703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437466577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.437466577
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2179384658
Short name T885
Test name
Test status
Simulation time 169822715 ps
CPU time 0.74 seconds
Started Jun 22 05:18:49 PM PDT 24
Finished Jun 22 05:18:50 PM PDT 24
Peak memory 205716 kb
Host smart-b3f6a85c-3769-4e95-b2fe-facb1c29c1cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179384658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2179384658
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2722895795
Short name T453
Test name
Test status
Simulation time 1205581911 ps
CPU time 5.04 seconds
Started Jun 22 05:18:59 PM PDT 24
Finished Jun 22 05:19:05 PM PDT 24
Peak memory 225484 kb
Host smart-cb2d7067-335d-4624-bd20-fcfa1f7d3ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722895795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2722895795
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.534792673
Short name T919
Test name
Test status
Simulation time 14672734 ps
CPU time 0.89 seconds
Started Jun 22 05:18:43 PM PDT 24
Finished Jun 22 05:18:44 PM PDT 24
Peak memory 207496 kb
Host smart-fedbcd0f-2c76-4bcd-8e16-c23dd3189611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534792673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.534792673
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.602946730
Short name T158
Test name
Test status
Simulation time 51461666212 ps
CPU time 71.93 seconds
Started Jun 22 05:18:49 PM PDT 24
Finished Jun 22 05:20:02 PM PDT 24
Peak memory 242088 kb
Host smart-193c4e82-8843-4e73-85fc-c7f6598b8af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602946730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.602946730
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3061462438
Short name T888
Test name
Test status
Simulation time 7732760168 ps
CPU time 69.38 seconds
Started Jun 22 05:18:47 PM PDT 24
Finished Jun 22 05:19:57 PM PDT 24
Peak memory 241880 kb
Host smart-69379d32-bb4f-40e8-ba9c-5d4d50428d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061462438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3061462438
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3213365834
Short name T310
Test name
Test status
Simulation time 55798112410 ps
CPU time 137.51 seconds
Started Jun 22 05:18:51 PM PDT 24
Finished Jun 22 05:21:09 PM PDT 24
Peak memory 249712 kb
Host smart-bf83ead0-3cbb-437d-85fd-d9164a531960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213365834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3213365834
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_intercept.4114757829
Short name T801
Test name
Test status
Simulation time 989514994 ps
CPU time 4.14 seconds
Started Jun 22 05:18:42 PM PDT 24
Finished Jun 22 05:18:47 PM PDT 24
Peak memory 225544 kb
Host smart-a68ffd70-d7f4-431f-86b3-84bdfcf5521d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114757829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.4114757829
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.264351991
Short name T470
Test name
Test status
Simulation time 3296747656 ps
CPU time 5.46 seconds
Started Jun 22 05:18:41 PM PDT 24
Finished Jun 22 05:18:47 PM PDT 24
Peak memory 225680 kb
Host smart-cb3c0c69-f5c0-46a9-8d93-8d20feb75fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264351991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.264351991
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.684355038
Short name T934
Test name
Test status
Simulation time 8615807361 ps
CPU time 13.48 seconds
Started Jun 22 05:18:48 PM PDT 24
Finished Jun 22 05:19:02 PM PDT 24
Peak memory 233852 kb
Host smart-0f443795-7de6-47eb-a403-b505e25a6e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684355038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.684355038
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3887352770
Short name T525
Test name
Test status
Simulation time 5679815583 ps
CPU time 8.01 seconds
Started Jun 22 05:18:45 PM PDT 24
Finished Jun 22 05:18:54 PM PDT 24
Peak memory 233800 kb
Host smart-e228f10b-9ff0-49c4-be85-662ec0dcf325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887352770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3887352770
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3530460691
Short name T578
Test name
Test status
Simulation time 2273694553 ps
CPU time 5.09 seconds
Started Jun 22 05:18:50 PM PDT 24
Finished Jun 22 05:18:56 PM PDT 24
Peak memory 224152 kb
Host smart-7a200681-bb2a-41e3-bc58-9601b8347987
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3530460691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3530460691
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2313906965
Short name T592
Test name
Test status
Simulation time 44654555 ps
CPU time 0.92 seconds
Started Jun 22 05:18:46 PM PDT 24
Finished Jun 22 05:18:47 PM PDT 24
Peak memory 207496 kb
Host smart-9c57eaac-8d75-485f-80eb-08567ffdffce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313906965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2313906965
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.938031124
Short name T665
Test name
Test status
Simulation time 5075696063 ps
CPU time 28.24 seconds
Started Jun 22 05:18:40 PM PDT 24
Finished Jun 22 05:19:10 PM PDT 24
Peak memory 217424 kb
Host smart-6dd8e864-ea53-4648-b255-60f89816114c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938031124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.938031124
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2446437685
Short name T714
Test name
Test status
Simulation time 12179012 ps
CPU time 0.74 seconds
Started Jun 22 05:18:41 PM PDT 24
Finished Jun 22 05:18:48 PM PDT 24
Peak memory 206580 kb
Host smart-b425fc66-7778-40f1-9963-b70ca4da62b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446437685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2446437685
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.802799373
Short name T659
Test name
Test status
Simulation time 73780834 ps
CPU time 0.84 seconds
Started Jun 22 05:18:40 PM PDT 24
Finished Jun 22 05:18:42 PM PDT 24
Peak memory 207904 kb
Host smart-f6a1c7ee-6f99-4f3b-b798-e77c7d08916f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802799373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.802799373
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3092006171
Short name T867
Test name
Test status
Simulation time 39872493 ps
CPU time 0.83 seconds
Started Jun 22 05:18:40 PM PDT 24
Finished Jun 22 05:18:41 PM PDT 24
Peak memory 206848 kb
Host smart-16ae7e18-76a3-417a-8491-3d490dd2f2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092006171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3092006171
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3860212912
Short name T6
Test name
Test status
Simulation time 2099146352 ps
CPU time 7.12 seconds
Started Jun 22 05:18:50 PM PDT 24
Finished Jun 22 05:18:58 PM PDT 24
Peak memory 225496 kb
Host smart-13af8bcb-59b4-4fcd-b250-577c202b19b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860212912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3860212912
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.833490297
Short name T396
Test name
Test status
Simulation time 17980119 ps
CPU time 0.69 seconds
Started Jun 22 05:18:51 PM PDT 24
Finished Jun 22 05:18:52 PM PDT 24
Peak memory 206252 kb
Host smart-0369ac22-0705-4373-88df-9cd4c0b9420d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833490297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.833490297
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2452605409
Short name T8
Test name
Test status
Simulation time 210603201 ps
CPU time 2.8 seconds
Started Jun 22 05:18:45 PM PDT 24
Finished Jun 22 05:18:49 PM PDT 24
Peak memory 233748 kb
Host smart-d9425bc0-916e-4530-b2cb-8ca854120013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452605409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2452605409
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.106722995
Short name T321
Test name
Test status
Simulation time 32485823 ps
CPU time 0.77 seconds
Started Jun 22 05:18:50 PM PDT 24
Finished Jun 22 05:18:51 PM PDT 24
Peak memory 207480 kb
Host smart-1a4da71a-b5fa-444c-b93f-16276e5a09d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106722995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.106722995
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.160735359
Short name T849
Test name
Test status
Simulation time 2421882875 ps
CPU time 44.37 seconds
Started Jun 22 05:18:49 PM PDT 24
Finished Jun 22 05:19:34 PM PDT 24
Peak memory 268352 kb
Host smart-453b6a79-a3f9-4aed-adbc-cf703f553f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160735359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.160735359
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3589120763
Short name T706
Test name
Test status
Simulation time 678616433 ps
CPU time 14.1 seconds
Started Jun 22 05:18:52 PM PDT 24
Finished Jun 22 05:19:07 PM PDT 24
Peak memory 241532 kb
Host smart-222cf01b-df5e-4948-9227-2023c482421d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589120763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3589120763
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.686614465
Short name T124
Test name
Test status
Simulation time 2952986824 ps
CPU time 9.5 seconds
Started Jun 22 05:18:50 PM PDT 24
Finished Jun 22 05:19:01 PM PDT 24
Peak memory 218676 kb
Host smart-826d588c-8439-4f88-8e8f-bbe7b201710f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686614465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.686614465
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2925697542
Short name T542
Test name
Test status
Simulation time 2072292319 ps
CPU time 24.68 seconds
Started Jun 22 05:18:50 PM PDT 24
Finished Jun 22 05:19:15 PM PDT 24
Peak memory 225532 kb
Host smart-00ae0aad-bd8a-4440-a1aa-a45d3eb60c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925697542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2925697542
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1119247991
Short name T550
Test name
Test status
Simulation time 151174432 ps
CPU time 3.42 seconds
Started Jun 22 05:18:50 PM PDT 24
Finished Jun 22 05:18:54 PM PDT 24
Peak memory 225588 kb
Host smart-7927f5a0-3504-4d81-aa51-ae5af3548be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119247991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1119247991
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3274463205
Short name T586
Test name
Test status
Simulation time 56370104 ps
CPU time 2.41 seconds
Started Jun 22 05:18:51 PM PDT 24
Finished Jun 22 05:18:54 PM PDT 24
Peak memory 233512 kb
Host smart-1554ba13-9bab-4bbc-93a4-37b0bb64bff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274463205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3274463205
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3968343671
Short name T773
Test name
Test status
Simulation time 57985286333 ps
CPU time 44.44 seconds
Started Jun 22 05:18:53 PM PDT 24
Finished Jun 22 05:19:38 PM PDT 24
Peak memory 233880 kb
Host smart-8a47e3aa-6605-450e-a089-2e733bee5928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968343671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3968343671
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1457869946
Short name T735
Test name
Test status
Simulation time 406670853 ps
CPU time 2.84 seconds
Started Jun 22 05:18:51 PM PDT 24
Finished Jun 22 05:18:55 PM PDT 24
Peak memory 233776 kb
Host smart-57b7a571-be46-4d16-93bd-62dc0ff7cbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457869946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1457869946
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3263836638
Short name T693
Test name
Test status
Simulation time 693843454 ps
CPU time 6.92 seconds
Started Jun 22 05:18:54 PM PDT 24
Finished Jun 22 05:19:01 PM PDT 24
Peak memory 221656 kb
Host smart-505635fc-6b0f-4015-996d-9151e9f488b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3263836638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3263836638
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3100181874
Short name T148
Test name
Test status
Simulation time 144378600 ps
CPU time 1.24 seconds
Started Jun 22 05:18:51 PM PDT 24
Finished Jun 22 05:18:53 PM PDT 24
Peak memory 208112 kb
Host smart-ef73ff79-68ba-42bd-a74c-c321eaf75291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100181874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3100181874
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3115886653
Short name T430
Test name
Test status
Simulation time 1149455214 ps
CPU time 8.75 seconds
Started Jun 22 05:18:52 PM PDT 24
Finished Jun 22 05:19:01 PM PDT 24
Peak memory 217292 kb
Host smart-4d7536c8-cee3-48a9-a130-ed52fafd813e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115886653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3115886653
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2358936563
Short name T528
Test name
Test status
Simulation time 2561451969 ps
CPU time 5.91 seconds
Started Jun 22 05:18:53 PM PDT 24
Finished Jun 22 05:19:00 PM PDT 24
Peak memory 217612 kb
Host smart-5b1236d2-330d-4a5d-b787-cb66a67cdbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358936563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2358936563
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.669353214
Short name T354
Test name
Test status
Simulation time 292386709 ps
CPU time 10.09 seconds
Started Jun 22 05:18:54 PM PDT 24
Finished Jun 22 05:19:05 PM PDT 24
Peak memory 218724 kb
Host smart-ea65e139-f250-4932-b663-7fd8001a52d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669353214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.669353214
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2018207743
Short name T634
Test name
Test status
Simulation time 59702514 ps
CPU time 0.89 seconds
Started Jun 22 05:18:48 PM PDT 24
Finished Jun 22 05:18:49 PM PDT 24
Peak memory 206880 kb
Host smart-88ba8c45-e7e3-4de8-b7b8-3c86b5d4135d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018207743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2018207743
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1071970512
Short name T249
Test name
Test status
Simulation time 1183637710 ps
CPU time 8.01 seconds
Started Jun 22 05:18:48 PM PDT 24
Finished Jun 22 05:18:57 PM PDT 24
Peak memory 225560 kb
Host smart-ba8063aa-ae55-4af5-8a58-ddc91b54d9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071970512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1071970512
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2844349512
Short name T60
Test name
Test status
Simulation time 32489785 ps
CPU time 0.71 seconds
Started Jun 22 05:18:50 PM PDT 24
Finished Jun 22 05:18:52 PM PDT 24
Peak memory 206768 kb
Host smart-3d136f1d-be0e-4dd0-b49f-bdf9463896a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844349512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2844349512
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.915467648
Short name T889
Test name
Test status
Simulation time 2024180333 ps
CPU time 6.16 seconds
Started Jun 22 05:18:50 PM PDT 24
Finished Jun 22 05:18:56 PM PDT 24
Peak memory 233684 kb
Host smart-f854dad5-2f7a-4ad5-ad07-08dbf6beadd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915467648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.915467648
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1071386870
Short name T539
Test name
Test status
Simulation time 51766413 ps
CPU time 0.74 seconds
Started Jun 22 05:18:52 PM PDT 24
Finished Jun 22 05:18:54 PM PDT 24
Peak memory 206472 kb
Host smart-80f201da-c1ad-4fd7-ae45-f57551a9ba91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071386870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1071386870
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3555118801
Short name T893
Test name
Test status
Simulation time 7383838128 ps
CPU time 34.33 seconds
Started Jun 22 05:18:51 PM PDT 24
Finished Jun 22 05:19:26 PM PDT 24
Peak memory 254288 kb
Host smart-b114302b-aa5b-448a-81ad-cceacc7de5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555118801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3555118801
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3003708185
Short name T943
Test name
Test status
Simulation time 33305261941 ps
CPU time 41.41 seconds
Started Jun 22 05:18:52 PM PDT 24
Finished Jun 22 05:19:34 PM PDT 24
Peak memory 218464 kb
Host smart-0bf4e72c-7694-47ea-94f9-2137f813c883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003708185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3003708185
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3326188275
Short name T179
Test name
Test status
Simulation time 17008340009 ps
CPU time 73.67 seconds
Started Jun 22 05:18:51 PM PDT 24
Finished Jun 22 05:20:05 PM PDT 24
Peak memory 252412 kb
Host smart-fcbd1387-99e1-45ef-a47e-fe10c7884867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326188275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3326188275
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2327572649
Short name T503
Test name
Test status
Simulation time 341005554 ps
CPU time 5.79 seconds
Started Jun 22 05:18:49 PM PDT 24
Finished Jun 22 05:18:55 PM PDT 24
Peak memory 234800 kb
Host smart-7015a679-b92d-4289-a51d-b5dd44e36b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327572649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2327572649
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.93478779
Short name T523
Test name
Test status
Simulation time 307679824 ps
CPU time 4.64 seconds
Started Jun 22 05:18:55 PM PDT 24
Finished Jun 22 05:19:00 PM PDT 24
Peak memory 233772 kb
Host smart-6b74bc58-685f-410d-9877-7fe7cd99ce05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93478779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.93478779
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3599491303
Short name T462
Test name
Test status
Simulation time 5001694289 ps
CPU time 10.29 seconds
Started Jun 22 05:18:55 PM PDT 24
Finished Jun 22 05:19:05 PM PDT 24
Peak memory 233892 kb
Host smart-82734dfe-83e9-432f-92b0-bed050768f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599491303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3599491303
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1934200425
Short name T835
Test name
Test status
Simulation time 185087365 ps
CPU time 2.5 seconds
Started Jun 22 05:18:50 PM PDT 24
Finished Jun 22 05:18:53 PM PDT 24
Peak memory 233480 kb
Host smart-578078e8-1ef7-49c2-8f67-9ac030514e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934200425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1934200425
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.4087847885
Short name T340
Test name
Test status
Simulation time 395050054 ps
CPU time 2.4 seconds
Started Jun 22 05:18:49 PM PDT 24
Finished Jun 22 05:18:52 PM PDT 24
Peak memory 224224 kb
Host smart-9e251785-a8a5-4924-b884-f376517f3242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087847885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.4087847885
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2996983468
Short name T924
Test name
Test status
Simulation time 81571097 ps
CPU time 3.9 seconds
Started Jun 22 05:18:52 PM PDT 24
Finished Jun 22 05:18:57 PM PDT 24
Peak memory 220228 kb
Host smart-ca2ad580-df16-439b-b2b1-15bc358506b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2996983468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2996983468
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.458244823
Short name T16
Test name
Test status
Simulation time 7607365150 ps
CPU time 20.46 seconds
Started Jun 22 05:18:52 PM PDT 24
Finished Jun 22 05:19:14 PM PDT 24
Peak memory 225640 kb
Host smart-534634f9-07c9-4b57-98fe-5cb713547487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458244823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.458244823
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.4134923519
Short name T700
Test name
Test status
Simulation time 6721147495 ps
CPU time 35.16 seconds
Started Jun 22 05:18:52 PM PDT 24
Finished Jun 22 05:19:28 PM PDT 24
Peak memory 217440 kb
Host smart-cc30459e-6010-4a55-9c5a-4a0930c95098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134923519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.4134923519
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1934678744
Short name T826
Test name
Test status
Simulation time 1401711556 ps
CPU time 3 seconds
Started Jun 22 05:18:57 PM PDT 24
Finished Jun 22 05:19:00 PM PDT 24
Peak memory 217320 kb
Host smart-46fd8553-448e-4519-af1e-b8ab4ac22f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934678744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1934678744
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2512375224
Short name T385
Test name
Test status
Simulation time 11247735 ps
CPU time 0.71 seconds
Started Jun 22 05:18:50 PM PDT 24
Finished Jun 22 05:18:51 PM PDT 24
Peak memory 206524 kb
Host smart-f2ce497b-326b-435c-ae9c-66b9b39f8562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512375224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2512375224
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3006680496
Short name T318
Test name
Test status
Simulation time 86893542 ps
CPU time 1 seconds
Started Jun 22 05:18:49 PM PDT 24
Finished Jun 22 05:18:51 PM PDT 24
Peak memory 207916 kb
Host smart-cbd96ac9-936d-47e6-9a01-712f7f2d90c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006680496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3006680496
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3887398947
Short name T646
Test name
Test status
Simulation time 17213486477 ps
CPU time 19.72 seconds
Started Jun 22 05:18:50 PM PDT 24
Finished Jun 22 05:19:10 PM PDT 24
Peak memory 249896 kb
Host smart-0b972aec-796d-4d54-a30a-b42bd56d57ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887398947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3887398947
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1248690216
Short name T638
Test name
Test status
Simulation time 11407878 ps
CPU time 0.72 seconds
Started Jun 22 05:18:55 PM PDT 24
Finished Jun 22 05:18:56 PM PDT 24
Peak memory 206248 kb
Host smart-b1bee801-c135-425d-a503-0551ae6f6967
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248690216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1248690216
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3633526757
Short name T712
Test name
Test status
Simulation time 1647573870 ps
CPU time 3.39 seconds
Started Jun 22 05:18:53 PM PDT 24
Finished Jun 22 05:18:57 PM PDT 24
Peak memory 225496 kb
Host smart-5b5d3922-1af0-4d79-9714-06c9039fa32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633526757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3633526757
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1772392758
Short name T495
Test name
Test status
Simulation time 31625441 ps
CPU time 0.74 seconds
Started Jun 22 05:19:00 PM PDT 24
Finished Jun 22 05:19:01 PM PDT 24
Peak memory 206464 kb
Host smart-aa26bf66-95aa-46d7-a45d-83c17991d472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772392758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1772392758
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.594501446
Short name T25
Test name
Test status
Simulation time 6658684749 ps
CPU time 30.88 seconds
Started Jun 22 05:18:55 PM PDT 24
Finished Jun 22 05:19:26 PM PDT 24
Peak memory 237524 kb
Host smart-9846e4c2-97e1-4c1f-9e28-df3e52b1b26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594501446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.594501446
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3755051228
Short name T544
Test name
Test status
Simulation time 227207299685 ps
CPU time 448.52 seconds
Started Jun 22 05:18:57 PM PDT 24
Finished Jun 22 05:26:26 PM PDT 24
Peak memory 263432 kb
Host smart-d84bc6d5-f98c-4cf7-bfd6-fec0d98efb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755051228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3755051228
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.913800466
Short name T300
Test name
Test status
Simulation time 9002336660 ps
CPU time 37.38 seconds
Started Jun 22 05:18:59 PM PDT 24
Finished Jun 22 05:19:38 PM PDT 24
Peak memory 242092 kb
Host smart-c92d0023-7f36-4718-82fb-ac30c45d0d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913800466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.913800466
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.438237803
Short name T486
Test name
Test status
Simulation time 1412216931 ps
CPU time 4.33 seconds
Started Jun 22 05:18:54 PM PDT 24
Finished Jun 22 05:18:59 PM PDT 24
Peak memory 225708 kb
Host smart-a6108436-e997-4c58-83e1-1ca00822f348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438237803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.438237803
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1784668055
Short name T951
Test name
Test status
Simulation time 27530909085 ps
CPU time 99.53 seconds
Started Jun 22 05:18:56 PM PDT 24
Finished Jun 22 05:20:36 PM PDT 24
Peak memory 241708 kb
Host smart-70ca7645-eabb-4ae3-a395-d73cc5aedc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784668055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1784668055
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.624383264
Short name T198
Test name
Test status
Simulation time 394546821 ps
CPU time 2.76 seconds
Started Jun 22 05:19:02 PM PDT 24
Finished Jun 22 05:19:06 PM PDT 24
Peak memory 225484 kb
Host smart-4d4d4a51-9b7e-4de2-b20e-2e69488c5c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624383264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.624383264
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1972648102
Short name T253
Test name
Test status
Simulation time 1313352132 ps
CPU time 5.94 seconds
Started Jun 22 05:18:52 PM PDT 24
Finished Jun 22 05:18:58 PM PDT 24
Peak memory 225540 kb
Host smart-6596e81a-4cd8-4346-b07f-b3767cf75814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972648102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1972648102
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3091534854
Short name T696
Test name
Test status
Simulation time 4984505523 ps
CPU time 11.64 seconds
Started Jun 22 05:19:02 PM PDT 24
Finished Jun 22 05:19:15 PM PDT 24
Peak memory 221916 kb
Host smart-544b14d3-edb1-4697-a42d-c8d8f36dcb95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3091534854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3091534854
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.943786401
Short name T871
Test name
Test status
Simulation time 1796456355 ps
CPU time 31.93 seconds
Started Jun 22 05:19:00 PM PDT 24
Finished Jun 22 05:19:32 PM PDT 24
Peak memory 250152 kb
Host smart-ea5e125e-26f4-4233-9bf4-f4010ca828f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943786401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.943786401
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1655347572
Short name T533
Test name
Test status
Simulation time 35705644155 ps
CPU time 30.81 seconds
Started Jun 22 05:18:59 PM PDT 24
Finished Jun 22 05:19:31 PM PDT 24
Peak memory 217504 kb
Host smart-1918463c-43f0-4b23-ad5f-3535f08ab41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655347572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1655347572
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.4020057791
Short name T352
Test name
Test status
Simulation time 1709136460 ps
CPU time 6.56 seconds
Started Jun 22 05:18:51 PM PDT 24
Finished Jun 22 05:18:58 PM PDT 24
Peak memory 217388 kb
Host smart-159f67ea-e601-45ff-b7da-a802963737e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020057791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.4020057791
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.827043675
Short name T619
Test name
Test status
Simulation time 160846194 ps
CPU time 0.84 seconds
Started Jun 22 05:18:53 PM PDT 24
Finished Jun 22 05:18:54 PM PDT 24
Peak memory 206884 kb
Host smart-c88453bb-5996-4ad0-9e0d-b12be7bfae95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827043675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.827043675
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1419534197
Short name T338
Test name
Test status
Simulation time 69795946 ps
CPU time 0.72 seconds
Started Jun 22 05:18:58 PM PDT 24
Finished Jun 22 05:19:00 PM PDT 24
Peak memory 206800 kb
Host smart-4c53c7f9-3c78-4957-8d8d-f27174cca4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419534197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1419534197
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3852576377
Short name T602
Test name
Test status
Simulation time 12178516534 ps
CPU time 20.06 seconds
Started Jun 22 05:18:51 PM PDT 24
Finished Jun 22 05:19:12 PM PDT 24
Peak memory 233716 kb
Host smart-35584869-e755-4ddf-bf75-ea47bcfeeca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852576377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3852576377
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.512952483
Short name T389
Test name
Test status
Simulation time 31359253 ps
CPU time 0.74 seconds
Started Jun 22 05:18:52 PM PDT 24
Finished Jun 22 05:18:53 PM PDT 24
Peak memory 206284 kb
Host smart-53938a50-9068-4782-a4f0-a31f84eb9bad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512952483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.512952483
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.465282101
Short name T813
Test name
Test status
Simulation time 46414761 ps
CPU time 2.53 seconds
Started Jun 22 05:18:54 PM PDT 24
Finished Jun 22 05:18:57 PM PDT 24
Peak memory 233648 kb
Host smart-3d874c3d-449a-412a-9eac-f17a9228690d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465282101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.465282101
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2580531641
Short name T59
Test name
Test status
Simulation time 19744361 ps
CPU time 0.81 seconds
Started Jun 22 05:18:59 PM PDT 24
Finished Jun 22 05:19:01 PM PDT 24
Peak memory 207836 kb
Host smart-cf5e0cf2-5fcb-482c-a602-8a796fa8d945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580531641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2580531641
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3609430790
Short name T123
Test name
Test status
Simulation time 50643171919 ps
CPU time 97.8 seconds
Started Jun 22 05:18:54 PM PDT 24
Finished Jun 22 05:20:32 PM PDT 24
Peak memory 241600 kb
Host smart-29f5cd5b-6b35-4d48-b354-de78051c345b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609430790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3609430790
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2273116872
Short name T29
Test name
Test status
Simulation time 29248972998 ps
CPU time 112.5 seconds
Started Jun 22 05:18:52 PM PDT 24
Finished Jun 22 05:20:46 PM PDT 24
Peak memory 257460 kb
Host smart-3a352e07-197a-4823-bba7-bc45fe352c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273116872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2273116872
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.28876535
Short name T22
Test name
Test status
Simulation time 4080580328 ps
CPU time 49.05 seconds
Started Jun 22 05:18:54 PM PDT 24
Finished Jun 22 05:19:44 PM PDT 24
Peak memory 250252 kb
Host smart-b932fdd2-2a9d-4ded-bb82-54e5586454de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28876535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.28876535
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1605236315
Short name T223
Test name
Test status
Simulation time 866015185 ps
CPU time 6.78 seconds
Started Jun 22 05:18:54 PM PDT 24
Finished Jun 22 05:19:01 PM PDT 24
Peak memory 225484 kb
Host smart-cb106f73-5a78-4ea7-a668-fd627a45e389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605236315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1605236315
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3690591078
Short name T866
Test name
Test status
Simulation time 4734365863 ps
CPU time 40.91 seconds
Started Jun 22 05:19:00 PM PDT 24
Finished Jun 22 05:19:42 PM PDT 24
Peak memory 225624 kb
Host smart-4ea23cce-72cd-4d86-bf0e-62986c28cedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690591078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3690591078
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3502013498
Short name T456
Test name
Test status
Simulation time 2329565072 ps
CPU time 8.45 seconds
Started Jun 22 05:18:54 PM PDT 24
Finished Jun 22 05:19:03 PM PDT 24
Peak memory 233820 kb
Host smart-4550e3e7-4e1d-4e37-a71b-688c6b2caaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502013498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3502013498
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2113929571
Short name T85
Test name
Test status
Simulation time 846946979 ps
CPU time 9.81 seconds
Started Jun 22 05:19:01 PM PDT 24
Finished Jun 22 05:19:12 PM PDT 24
Peak memory 241864 kb
Host smart-9816509a-f399-4a37-99d8-1a4c2daabc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113929571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2113929571
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3046168044
Short name T787
Test name
Test status
Simulation time 4071134228 ps
CPU time 13.49 seconds
Started Jun 22 05:18:55 PM PDT 24
Finished Jun 22 05:19:09 PM PDT 24
Peak memory 224104 kb
Host smart-49e6d143-7ef1-45b7-b353-e361365016ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3046168044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3046168044
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3419718710
Short name T261
Test name
Test status
Simulation time 31979291108 ps
CPU time 325.4 seconds
Started Jun 22 05:18:58 PM PDT 24
Finished Jun 22 05:24:24 PM PDT 24
Peak memory 266696 kb
Host smart-876ff7d4-bb36-47e6-a86d-5895a18b8cb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419718710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3419718710
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3913960578
Short name T567
Test name
Test status
Simulation time 5668346636 ps
CPU time 25.68 seconds
Started Jun 22 05:19:01 PM PDT 24
Finished Jun 22 05:19:27 PM PDT 24
Peak memory 217440 kb
Host smart-eb7bd3dc-3f24-4b9c-b387-0a5be7db7394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913960578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3913960578
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1090904190
Short name T597
Test name
Test status
Simulation time 2672146528 ps
CPU time 8.21 seconds
Started Jun 22 05:18:52 PM PDT 24
Finished Jun 22 05:19:01 PM PDT 24
Peak memory 217508 kb
Host smart-b7501f3c-2b5b-43af-a7f1-84c93a3f72b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090904190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1090904190
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3220941474
Short name T747
Test name
Test status
Simulation time 145362738 ps
CPU time 1.07 seconds
Started Jun 22 05:19:02 PM PDT 24
Finished Jun 22 05:19:04 PM PDT 24
Peak memory 208148 kb
Host smart-38de5098-fca3-4dd6-a65b-d4428989606e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220941474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3220941474
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3272543996
Short name T12
Test name
Test status
Simulation time 49788388 ps
CPU time 0.81 seconds
Started Jun 22 05:18:58 PM PDT 24
Finished Jun 22 05:18:59 PM PDT 24
Peak memory 206836 kb
Host smart-b6e92dcd-1117-478e-8565-361fa42b0f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272543996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3272543996
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3044322643
Short name T613
Test name
Test status
Simulation time 2247327923 ps
CPU time 8.72 seconds
Started Jun 22 05:19:02 PM PDT 24
Finished Jun 22 05:19:12 PM PDT 24
Peak memory 225696 kb
Host smart-a3177cc3-b572-41d0-9024-adb991be5fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044322643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3044322643
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3423674431
Short name T350
Test name
Test status
Simulation time 15868369 ps
CPU time 0.71 seconds
Started Jun 22 05:19:09 PM PDT 24
Finished Jun 22 05:19:11 PM PDT 24
Peak memory 206276 kb
Host smart-2e983044-6999-4d2a-9b0d-2b65a9d63534
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423674431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3423674431
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.4046285763
Short name T658
Test name
Test status
Simulation time 241771023 ps
CPU time 4.27 seconds
Started Jun 22 05:19:01 PM PDT 24
Finished Jun 22 05:19:06 PM PDT 24
Peak memory 233708 kb
Host smart-1a26ada3-6bc4-4c31-a24c-7ded841ed3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046285763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.4046285763
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.596945829
Short name T369
Test name
Test status
Simulation time 80351246 ps
CPU time 0.78 seconds
Started Jun 22 05:18:54 PM PDT 24
Finished Jun 22 05:18:56 PM PDT 24
Peak memory 206764 kb
Host smart-d81ae1a5-751f-44e4-a5d0-d76271beafc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596945829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.596945829
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.405692453
Short name T918
Test name
Test status
Simulation time 13050930833 ps
CPU time 48.21 seconds
Started Jun 22 05:19:06 PM PDT 24
Finished Jun 22 05:19:54 PM PDT 24
Peak memory 254640 kb
Host smart-3b0e8450-1f98-407d-b4cc-c24c7daa9658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405692453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.405692453
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3542268931
Short name T231
Test name
Test status
Simulation time 34523724827 ps
CPU time 347.11 seconds
Started Jun 22 05:19:03 PM PDT 24
Finished Jun 22 05:24:51 PM PDT 24
Peak memory 254528 kb
Host smart-27ae2038-4594-402e-9e29-b7995467fff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542268931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3542268931
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2687642713
Short name T830
Test name
Test status
Simulation time 5420812654 ps
CPU time 76.03 seconds
Started Jun 22 05:19:00 PM PDT 24
Finished Jun 22 05:20:17 PM PDT 24
Peak memory 251248 kb
Host smart-6d944884-c7a8-4279-b7cf-61abdb2fc4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687642713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2687642713
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1114408383
Short name T301
Test name
Test status
Simulation time 3394164352 ps
CPU time 38.63 seconds
Started Jun 22 05:19:06 PM PDT 24
Finished Jun 22 05:19:45 PM PDT 24
Peak memory 242048 kb
Host smart-a2736a05-349f-4251-8f18-b65c4f205906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114408383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1114408383
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4199441613
Short name T409
Test name
Test status
Simulation time 473557052 ps
CPU time 6.88 seconds
Started Jun 22 05:19:10 PM PDT 24
Finished Jun 22 05:19:17 PM PDT 24
Peak memory 233280 kb
Host smart-05ffcf20-5e8f-4231-af0c-147e10f49550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199441613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4199441613
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2390436610
Short name T252
Test name
Test status
Simulation time 708946103 ps
CPU time 8.09 seconds
Started Jun 22 05:19:01 PM PDT 24
Finished Jun 22 05:19:10 PM PDT 24
Peak memory 233756 kb
Host smart-b880cead-c644-4682-a332-c7add5a5cc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390436610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2390436610
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2037824394
Short name T647
Test name
Test status
Simulation time 18442019301 ps
CPU time 27.76 seconds
Started Jun 22 05:19:04 PM PDT 24
Finished Jun 22 05:19:33 PM PDT 24
Peak memory 242016 kb
Host smart-25cfebf8-de9b-4c85-a786-a4c9d1218d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037824394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2037824394
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1722684450
Short name T844
Test name
Test status
Simulation time 310643699 ps
CPU time 4.64 seconds
Started Jun 22 05:19:02 PM PDT 24
Finished Jun 22 05:19:07 PM PDT 24
Peak memory 228584 kb
Host smart-94d322ed-a009-41f7-b158-9717b8010154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722684450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1722684450
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3115392141
Short name T618
Test name
Test status
Simulation time 1011493456 ps
CPU time 6.99 seconds
Started Jun 22 05:19:02 PM PDT 24
Finished Jun 22 05:19:10 PM PDT 24
Peak memory 220264 kb
Host smart-41ef83d9-12e1-45f9-8ce8-a8db6105448c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3115392141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3115392141
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.690843624
Short name T130
Test name
Test status
Simulation time 67173216433 ps
CPU time 600.61 seconds
Started Jun 22 05:19:00 PM PDT 24
Finished Jun 22 05:29:02 PM PDT 24
Peak memory 255996 kb
Host smart-021d3f0c-18f4-46f9-aace-3097b994fd53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690843624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.690843624
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1165677637
Short name T466
Test name
Test status
Simulation time 5004470886 ps
CPU time 15.57 seconds
Started Jun 22 05:18:59 PM PDT 24
Finished Jun 22 05:19:15 PM PDT 24
Peak memory 217492 kb
Host smart-c4a3d2ba-896d-4c73-91cb-f55c2d02784c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165677637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1165677637
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2106869407
Short name T703
Test name
Test status
Simulation time 742497064 ps
CPU time 5.18 seconds
Started Jun 22 05:18:52 PM PDT 24
Finished Jun 22 05:18:58 PM PDT 24
Peak memory 217364 kb
Host smart-5bab99b3-c3b2-490a-9945-ffcd917da865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106869407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2106869407
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2207375049
Short name T711
Test name
Test status
Simulation time 53634592 ps
CPU time 0.84 seconds
Started Jun 22 05:19:05 PM PDT 24
Finished Jun 22 05:19:06 PM PDT 24
Peak memory 206880 kb
Host smart-76fe6d39-616c-4014-b704-e77f6b291aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207375049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2207375049
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2537955840
Short name T501
Test name
Test status
Simulation time 92038249 ps
CPU time 0.96 seconds
Started Jun 22 05:19:01 PM PDT 24
Finished Jun 22 05:19:03 PM PDT 24
Peak memory 206880 kb
Host smart-25addb57-571a-489f-83c7-52ee744a4c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537955840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2537955840
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1905475477
Short name T922
Test name
Test status
Simulation time 186677857 ps
CPU time 2.3 seconds
Started Jun 22 05:19:03 PM PDT 24
Finished Jun 22 05:19:06 PM PDT 24
Peak memory 235332 kb
Host smart-1e97ac3b-6c46-44d2-9193-d0a09c8630f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905475477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1905475477
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2059070385
Short name T61
Test name
Test status
Simulation time 10522579 ps
CPU time 0.72 seconds
Started Jun 22 05:19:03 PM PDT 24
Finished Jun 22 05:19:05 PM PDT 24
Peak memory 206568 kb
Host smart-83b8fcd7-7a65-475d-ac8c-88ce6aaf4c2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059070385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2059070385
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1559369028
Short name T651
Test name
Test status
Simulation time 325230697 ps
CPU time 3.5 seconds
Started Jun 22 05:19:01 PM PDT 24
Finished Jun 22 05:19:05 PM PDT 24
Peak memory 233736 kb
Host smart-ced24a10-64cb-4618-9bc9-6efb8bdf2c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559369028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1559369028
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3514046833
Short name T754
Test name
Test status
Simulation time 16624776 ps
CPU time 0.81 seconds
Started Jun 22 05:19:03 PM PDT 24
Finished Jun 22 05:19:05 PM PDT 24
Peak memory 207500 kb
Host smart-d46a930f-1bc5-4270-bf7b-7daed567310a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514046833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3514046833
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3043377852
Short name T219
Test name
Test status
Simulation time 170744151359 ps
CPU time 331.48 seconds
Started Jun 22 05:19:01 PM PDT 24
Finished Jun 22 05:24:33 PM PDT 24
Peak memory 251296 kb
Host smart-694c4fa0-4063-48fd-9902-177d29e28219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043377852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3043377852
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.709840189
Short name T294
Test name
Test status
Simulation time 4355911107 ps
CPU time 70 seconds
Started Jun 22 05:19:01 PM PDT 24
Finished Jun 22 05:20:12 PM PDT 24
Peak memory 267624 kb
Host smart-529f7845-cace-4e33-92c9-c3b916d5de6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709840189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.709840189
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3209728947
Short name T955
Test name
Test status
Simulation time 1832384267 ps
CPU time 9.68 seconds
Started Jun 22 05:19:04 PM PDT 24
Finished Jun 22 05:19:15 PM PDT 24
Peak memory 233796 kb
Host smart-8e449e1f-68bb-44ec-b5f2-1464f7164a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209728947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3209728947
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3330684050
Short name T688
Test name
Test status
Simulation time 416365859 ps
CPU time 4.68 seconds
Started Jun 22 05:19:00 PM PDT 24
Finished Jun 22 05:19:05 PM PDT 24
Peak memory 225584 kb
Host smart-efff46f1-0e85-493d-86b6-a8af7d0c8ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330684050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3330684050
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.180277486
Short name T843
Test name
Test status
Simulation time 90548128 ps
CPU time 2.16 seconds
Started Jun 22 05:19:06 PM PDT 24
Finished Jun 22 05:19:09 PM PDT 24
Peak memory 219420 kb
Host smart-bd0dfb42-1018-4cf0-b5b8-f22c6bdb3c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180277486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.180277486
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2586981831
Short name T394
Test name
Test status
Simulation time 8459924918 ps
CPU time 5.03 seconds
Started Jun 22 05:19:10 PM PDT 24
Finished Jun 22 05:19:15 PM PDT 24
Peak memory 233840 kb
Host smart-fb43beb9-5301-486c-9ac4-83350940e86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586981831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2586981831
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1668393005
Short name T971
Test name
Test status
Simulation time 368428509 ps
CPU time 3.08 seconds
Started Jun 22 05:19:10 PM PDT 24
Finished Jun 22 05:19:13 PM PDT 24
Peak memory 224964 kb
Host smart-8ed64c8b-bca1-4666-bd6a-41e3d25457a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668393005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1668393005
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1274481989
Short name T607
Test name
Test status
Simulation time 266087734 ps
CPU time 3.53 seconds
Started Jun 22 05:19:05 PM PDT 24
Finished Jun 22 05:19:09 PM PDT 24
Peak memory 223980 kb
Host smart-73900856-af0b-4394-8051-6f7d618c5a97
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1274481989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1274481989
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.350048275
Short name T282
Test name
Test status
Simulation time 20113746509 ps
CPU time 297.49 seconds
Started Jun 22 05:19:03 PM PDT 24
Finished Jun 22 05:24:02 PM PDT 24
Peak memory 274552 kb
Host smart-240f7c4f-7974-4a42-a30c-1e53ebfba2ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350048275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.350048275
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.436669148
Short name T312
Test name
Test status
Simulation time 14048019435 ps
CPU time 25.34 seconds
Started Jun 22 05:19:05 PM PDT 24
Finished Jun 22 05:19:31 PM PDT 24
Peak memory 217496 kb
Host smart-79932681-7bab-4f83-a1f9-a125d719258d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436669148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.436669148
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3596226608
Short name T643
Test name
Test status
Simulation time 29228007860 ps
CPU time 11.82 seconds
Started Jun 22 05:19:02 PM PDT 24
Finished Jun 22 05:19:15 PM PDT 24
Peak memory 217460 kb
Host smart-0057aa30-ff66-44cd-bf41-9594212bd4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596226608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3596226608
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3558903867
Short name T577
Test name
Test status
Simulation time 37480029 ps
CPU time 1.09 seconds
Started Jun 22 05:19:02 PM PDT 24
Finished Jun 22 05:19:04 PM PDT 24
Peak memory 208304 kb
Host smart-6f9292ec-0786-463a-bb1b-eb5a5cd4d4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558903867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3558903867
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.289547606
Short name T459
Test name
Test status
Simulation time 189707207 ps
CPU time 0.86 seconds
Started Jun 22 05:19:03 PM PDT 24
Finished Jun 22 05:19:05 PM PDT 24
Peak memory 206880 kb
Host smart-2b8d4770-a9be-41cb-ab76-2b6f310efac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289547606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.289547606
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2820056511
Short name T53
Test name
Test status
Simulation time 698954899 ps
CPU time 4.92 seconds
Started Jun 22 05:19:02 PM PDT 24
Finished Jun 22 05:19:08 PM PDT 24
Peak memory 225476 kb
Host smart-6e3042ff-2180-4ba5-93e8-b47e65dcc40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820056511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2820056511
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.4053265907
Short name T499
Test name
Test status
Simulation time 22408837 ps
CPU time 0.7 seconds
Started Jun 22 05:19:24 PM PDT 24
Finished Jun 22 05:19:25 PM PDT 24
Peak memory 206260 kb
Host smart-37e47d1e-d1c3-44e9-af9e-9e7df319cc73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053265907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
4053265907
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3290419478
Short name T455
Test name
Test status
Simulation time 30590781 ps
CPU time 2.26 seconds
Started Jun 22 05:19:03 PM PDT 24
Finished Jun 22 05:19:06 PM PDT 24
Peak memory 224368 kb
Host smart-042ae16c-3c99-49d4-ac76-7cc5559cd7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290419478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3290419478
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1191668848
Short name T68
Test name
Test status
Simulation time 19130558 ps
CPU time 0.79 seconds
Started Jun 22 05:19:03 PM PDT 24
Finished Jun 22 05:19:05 PM PDT 24
Peak memory 207448 kb
Host smart-49731538-f91f-4cf8-b3d1-804e226a3a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191668848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1191668848
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3722024955
Short name T862
Test name
Test status
Simulation time 24603217430 ps
CPU time 177.8 seconds
Started Jun 22 05:19:17 PM PDT 24
Finished Jun 22 05:22:15 PM PDT 24
Peak memory 242080 kb
Host smart-95ce05d2-8339-486d-b09d-4067519b141e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722024955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3722024955
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3781041828
Short name T442
Test name
Test status
Simulation time 42829303523 ps
CPU time 67.75 seconds
Started Jun 22 05:19:17 PM PDT 24
Finished Jun 22 05:20:26 PM PDT 24
Peak memory 225736 kb
Host smart-c7f5b3b3-d865-4a55-a3ad-0d7128909c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781041828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3781041828
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1010872088
Short name T846
Test name
Test status
Simulation time 6263844797 ps
CPU time 45.08 seconds
Started Jun 22 05:19:18 PM PDT 24
Finished Jun 22 05:20:04 PM PDT 24
Peak memory 250328 kb
Host smart-937a8121-e22e-4b31-aa2a-4ce33991b562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010872088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1010872088
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1799250891
Short name T784
Test name
Test status
Simulation time 3790514700 ps
CPU time 17.09 seconds
Started Jun 22 05:19:18 PM PDT 24
Finished Jun 22 05:19:37 PM PDT 24
Peak memory 239116 kb
Host smart-88feb1c3-c0f7-4ef4-997b-662d88c93609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799250891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1799250891
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3414645345
Short name T836
Test name
Test status
Simulation time 760973786 ps
CPU time 7.83 seconds
Started Jun 22 05:19:02 PM PDT 24
Finished Jun 22 05:19:11 PM PDT 24
Peak memory 225584 kb
Host smart-ce791369-2eec-4876-9ec9-c0ff78b5520b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414645345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3414645345
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1333956741
Short name T932
Test name
Test status
Simulation time 9754562082 ps
CPU time 48.42 seconds
Started Jun 22 05:19:01 PM PDT 24
Finished Jun 22 05:19:51 PM PDT 24
Peak memory 241900 kb
Host smart-eebb0015-56f4-4554-807c-e6188ed87b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333956741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1333956741
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.920277109
Short name T576
Test name
Test status
Simulation time 147293169 ps
CPU time 2.58 seconds
Started Jun 22 05:19:07 PM PDT 24
Finished Jun 22 05:19:10 PM PDT 24
Peak memory 233708 kb
Host smart-5c3b78a5-83a7-4f7a-9a5e-670f30c6c183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920277109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.920277109
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2116536867
Short name T401
Test name
Test status
Simulation time 94908616895 ps
CPU time 21.49 seconds
Started Jun 22 05:19:03 PM PDT 24
Finished Jun 22 05:19:25 PM PDT 24
Peak memory 233888 kb
Host smart-5cb1338a-3cb3-42a9-bb11-21f84ac5d37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116536867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2116536867
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1068240660
Short name T743
Test name
Test status
Simulation time 1668140433 ps
CPU time 5.96 seconds
Started Jun 22 05:19:17 PM PDT 24
Finished Jun 22 05:19:24 PM PDT 24
Peak memory 221356 kb
Host smart-a0d176e7-13fa-4277-a987-131c3c74ae02
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1068240660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1068240660
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2882912884
Short name T206
Test name
Test status
Simulation time 8174731078 ps
CPU time 59.2 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:20:20 PM PDT 24
Peak memory 225764 kb
Host smart-7aaa8d20-5d4b-4e56-964b-6baa28ec0782
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882912884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2882912884
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3593558468
Short name T690
Test name
Test status
Simulation time 26065605642 ps
CPU time 39.13 seconds
Started Jun 22 05:19:01 PM PDT 24
Finished Jun 22 05:19:41 PM PDT 24
Peak memory 217500 kb
Host smart-5ae25460-c053-4155-86a8-2723d42b4d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593558468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3593558468
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.4088139337
Short name T952
Test name
Test status
Simulation time 1522295596 ps
CPU time 2.92 seconds
Started Jun 22 05:19:06 PM PDT 24
Finished Jun 22 05:19:10 PM PDT 24
Peak memory 217360 kb
Host smart-54d624ec-880f-411c-865c-85df8776ed2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088139337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4088139337
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3517369193
Short name T572
Test name
Test status
Simulation time 609120941 ps
CPU time 2.35 seconds
Started Jun 22 05:19:05 PM PDT 24
Finished Jun 22 05:19:07 PM PDT 24
Peak memory 217276 kb
Host smart-26d34680-6d67-445e-bd4d-ab0b0477a819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517369193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3517369193
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.480571599
Short name T633
Test name
Test status
Simulation time 96797710 ps
CPU time 0.86 seconds
Started Jun 22 05:19:10 PM PDT 24
Finished Jun 22 05:19:11 PM PDT 24
Peak memory 206864 kb
Host smart-4da432b7-00bd-4a6a-9402-b3bacd903919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480571599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.480571599
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3958173861
Short name T251
Test name
Test status
Simulation time 172207433 ps
CPU time 4.62 seconds
Started Jun 22 05:19:03 PM PDT 24
Finished Jun 22 05:19:08 PM PDT 24
Peak memory 233652 kb
Host smart-cde80b90-484f-44c2-a53d-42a560e4656c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958173861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3958173861
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1716897600
Short name T910
Test name
Test status
Simulation time 11492031 ps
CPU time 0.69 seconds
Started Jun 22 05:17:50 PM PDT 24
Finished Jun 22 05:17:51 PM PDT 24
Peak memory 205752 kb
Host smart-9bf0f561-baee-48b0-b9c6-eb59c9c253fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716897600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
716897600
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.315597739
Short name T678
Test name
Test status
Simulation time 357145106 ps
CPU time 3.31 seconds
Started Jun 22 05:17:51 PM PDT 24
Finished Jun 22 05:17:55 PM PDT 24
Peak memory 233748 kb
Host smart-17f8015a-cf44-402a-b8d0-01dd249826b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315597739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.315597739
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1221523987
Short name T560
Test name
Test status
Simulation time 71194721 ps
CPU time 0.76 seconds
Started Jun 22 05:17:42 PM PDT 24
Finished Jun 22 05:17:44 PM PDT 24
Peak memory 206492 kb
Host smart-aff4d9f5-44a5-4eda-8f5e-69c015384e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221523987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1221523987
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.4199754286
Short name T43
Test name
Test status
Simulation time 30073779461 ps
CPU time 75.08 seconds
Started Jun 22 05:17:53 PM PDT 24
Finished Jun 22 05:19:09 PM PDT 24
Peak memory 257436 kb
Host smart-cac70ef4-7b3b-4545-acfa-414db436d54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199754286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.4199754286
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2196985832
Short name T119
Test name
Test status
Simulation time 98059560514 ps
CPU time 282.49 seconds
Started Jun 22 05:17:53 PM PDT 24
Finished Jun 22 05:22:36 PM PDT 24
Peak memory 266724 kb
Host smart-103ef2c8-ccca-45da-9bfa-6770501a8ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196985832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2196985832
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2621815193
Short name T271
Test name
Test status
Simulation time 14816277389 ps
CPU time 117.4 seconds
Started Jun 22 05:17:53 PM PDT 24
Finished Jun 22 05:19:51 PM PDT 24
Peak memory 266952 kb
Host smart-84f52afc-8fdf-496a-b3dd-bcf53f3867e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621815193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2621815193
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.426329664
Short name T307
Test name
Test status
Simulation time 406361993 ps
CPU time 5.66 seconds
Started Jun 22 05:17:59 PM PDT 24
Finished Jun 22 05:18:05 PM PDT 24
Peak memory 233772 kb
Host smart-ce2cc127-0b3b-4ae0-9021-fdaa2961cd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426329664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.426329664
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.584780806
Short name T275
Test name
Test status
Simulation time 1450015871 ps
CPU time 9.81 seconds
Started Jun 22 05:17:53 PM PDT 24
Finished Jun 22 05:18:03 PM PDT 24
Peak memory 233764 kb
Host smart-7970dbe6-3779-4f70-a4fe-534dce4cc00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584780806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.584780806
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3000043498
Short name T931
Test name
Test status
Simulation time 903670806 ps
CPU time 5.08 seconds
Started Jun 22 05:17:52 PM PDT 24
Finished Jun 22 05:17:58 PM PDT 24
Peak memory 225564 kb
Host smart-172cb0f6-a507-413d-8d01-065d07b2a8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000043498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3000043498
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.350389463
Short name T34
Test name
Test status
Simulation time 78881807 ps
CPU time 1.05 seconds
Started Jun 22 05:17:42 PM PDT 24
Finished Jun 22 05:17:44 PM PDT 24
Peak memory 217564 kb
Host smart-66d80fe2-ac0a-4901-aca3-22fcf1c5f7ba
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350389463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.350389463
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.260885589
Short name T840
Test name
Test status
Simulation time 3871459655 ps
CPU time 8.86 seconds
Started Jun 22 05:17:41 PM PDT 24
Finished Jun 22 05:17:56 PM PDT 24
Peak memory 240512 kb
Host smart-8d37fef8-f1ac-4074-b55b-0beb0ea31fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260885589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
260885589
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3567859321
Short name T882
Test name
Test status
Simulation time 35920235895 ps
CPU time 12.86 seconds
Started Jun 22 05:17:52 PM PDT 24
Finished Jun 22 05:18:05 PM PDT 24
Peak memory 236496 kb
Host smart-30117048-1c1f-4504-9882-79ac9e9f8463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567859321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3567859321
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1624077270
Short name T374
Test name
Test status
Simulation time 102926081 ps
CPU time 3.65 seconds
Started Jun 22 05:17:59 PM PDT 24
Finished Jun 22 05:18:04 PM PDT 24
Peak memory 223572 kb
Host smart-7ece08ca-389b-4056-b166-ae7ba7e6d427
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1624077270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1624077270
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2412032774
Short name T66
Test name
Test status
Simulation time 86806570 ps
CPU time 1.15 seconds
Started Jun 22 05:17:49 PM PDT 24
Finished Jun 22 05:17:51 PM PDT 24
Peak memory 236700 kb
Host smart-edd6e65e-20df-4c24-90b6-1a6e25ad6e2e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412032774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2412032774
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1293662276
Short name T32
Test name
Test status
Simulation time 381130281856 ps
CPU time 572.79 seconds
Started Jun 22 05:17:49 PM PDT 24
Finished Jun 22 05:27:22 PM PDT 24
Peak memory 274920 kb
Host smart-59242c2b-1367-4661-9cbc-708dafe29913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293662276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1293662276
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1616617894
Short name T668
Test name
Test status
Simulation time 12938568570 ps
CPU time 39.36 seconds
Started Jun 22 05:17:46 PM PDT 24
Finished Jun 22 05:18:26 PM PDT 24
Peak memory 217492 kb
Host smart-bcb35757-9d86-4069-9350-40c58ace470b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616617894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1616617894
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2130885456
Short name T786
Test name
Test status
Simulation time 4338689843 ps
CPU time 12.79 seconds
Started Jun 22 05:18:01 PM PDT 24
Finished Jun 22 05:18:14 PM PDT 24
Peak memory 217504 kb
Host smart-f6083ca4-d4e5-4382-806d-19928bad945a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130885456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2130885456
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2364526310
Short name T873
Test name
Test status
Simulation time 860359633 ps
CPU time 10.95 seconds
Started Jun 22 05:17:55 PM PDT 24
Finished Jun 22 05:18:07 PM PDT 24
Peak memory 217480 kb
Host smart-5d3b4815-2107-4d18-bb85-3ee91d1a4f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364526310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2364526310
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3994946154
Short name T429
Test name
Test status
Simulation time 40479241 ps
CPU time 0.76 seconds
Started Jun 22 05:17:49 PM PDT 24
Finished Jun 22 05:17:50 PM PDT 24
Peak memory 206876 kb
Host smart-2f43066a-42bc-4cb5-8be4-43fd2eec6300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994946154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3994946154
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1891788451
Short name T953
Test name
Test status
Simulation time 3048068648 ps
CPU time 2.59 seconds
Started Jun 22 05:17:51 PM PDT 24
Finished Jun 22 05:17:55 PM PDT 24
Peak memory 225592 kb
Host smart-d318e6f6-1c0a-4588-ad5c-a0d158ce93db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891788451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1891788451
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1067801664
Short name T431
Test name
Test status
Simulation time 13498476 ps
CPU time 0.78 seconds
Started Jun 22 05:19:17 PM PDT 24
Finished Jun 22 05:19:19 PM PDT 24
Peak memory 206580 kb
Host smart-19d9e071-68e8-4faf-9e16-3cabac6b2907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067801664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1067801664
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.444870829
Short name T259
Test name
Test status
Simulation time 43532034 ps
CPU time 2.83 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:19:24 PM PDT 24
Peak memory 233712 kb
Host smart-0cff8081-646a-43dd-8aa5-892bcef520ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444870829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.444870829
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3701673193
Short name T376
Test name
Test status
Simulation time 18392064 ps
CPU time 0.83 seconds
Started Jun 22 05:19:18 PM PDT 24
Finished Jun 22 05:19:20 PM PDT 24
Peak memory 207524 kb
Host smart-8e15087e-b36e-46cb-bceb-2dd714787571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701673193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3701673193
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1992494927
Short name T664
Test name
Test status
Simulation time 13056173 ps
CPU time 0.76 seconds
Started Jun 22 05:19:16 PM PDT 24
Finished Jun 22 05:19:18 PM PDT 24
Peak memory 216844 kb
Host smart-11765fb1-2bfa-43b7-814b-d6046f8ddf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992494927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1992494927
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1887786487
Short name T941
Test name
Test status
Simulation time 134575143850 ps
CPU time 269.38 seconds
Started Jun 22 05:19:17 PM PDT 24
Finished Jun 22 05:23:48 PM PDT 24
Peak memory 250300 kb
Host smart-25970a86-a447-4610-8c39-f1c7485f667d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887786487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1887786487
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2325575326
Short name T296
Test name
Test status
Simulation time 144435499382 ps
CPU time 239.57 seconds
Started Jun 22 05:19:16 PM PDT 24
Finished Jun 22 05:23:16 PM PDT 24
Peak memory 252800 kb
Host smart-716f855c-56b1-41c9-b5cc-e0fc4f8f107d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325575326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2325575326
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1854295084
Short name T336
Test name
Test status
Simulation time 2303029821 ps
CPU time 11.01 seconds
Started Jun 22 05:19:16 PM PDT 24
Finished Jun 22 05:19:27 PM PDT 24
Peak memory 233884 kb
Host smart-e86ad5d6-5d32-4c8f-8802-20b8aea9d2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854295084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1854295084
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3888410980
Short name T975
Test name
Test status
Simulation time 1613456418 ps
CPU time 9.7 seconds
Started Jun 22 05:19:24 PM PDT 24
Finished Jun 22 05:19:34 PM PDT 24
Peak memory 233772 kb
Host smart-6a10a34d-46fd-4202-acfe-73b4bf94f1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888410980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3888410980
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.4149960176
Short name T687
Test name
Test status
Simulation time 3055220632 ps
CPU time 23.63 seconds
Started Jun 22 05:19:17 PM PDT 24
Finished Jun 22 05:19:41 PM PDT 24
Peak memory 233780 kb
Host smart-320f85f6-0fcf-47bf-876a-48040d8dd73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149960176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.4149960176
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.558017925
Short name T933
Test name
Test status
Simulation time 61788488 ps
CPU time 2.57 seconds
Started Jun 22 05:19:21 PM PDT 24
Finished Jun 22 05:19:25 PM PDT 24
Peak memory 233480 kb
Host smart-8add1de0-528f-41c1-a012-8b191d93be0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558017925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.558017925
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1507614074
Short name T505
Test name
Test status
Simulation time 966626279 ps
CPU time 5.55 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:19:26 PM PDT 24
Peak memory 225756 kb
Host smart-85abfcbc-9dde-4d70-89d9-76781ebf6502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507614074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1507614074
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3608248005
Short name T565
Test name
Test status
Simulation time 5756415873 ps
CPU time 19.13 seconds
Started Jun 22 05:19:18 PM PDT 24
Finished Jun 22 05:19:38 PM PDT 24
Peak memory 221344 kb
Host smart-cf2076ed-3387-4888-babf-94bdbc329d31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3608248005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3608248005
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3901420176
Short name T387
Test name
Test status
Simulation time 127454352 ps
CPU time 0.98 seconds
Started Jun 22 05:19:18 PM PDT 24
Finished Jun 22 05:19:20 PM PDT 24
Peak memory 207532 kb
Host smart-994c340e-68b9-478a-bc8b-4e6a748df65d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901420176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3901420176
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2585257447
Short name T446
Test name
Test status
Simulation time 12408927827 ps
CPU time 43.38 seconds
Started Jun 22 05:19:17 PM PDT 24
Finished Jun 22 05:20:01 PM PDT 24
Peak memory 217348 kb
Host smart-74d8bd4e-bae6-4187-9dc1-7b14f8161a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585257447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2585257447
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2359890624
Short name T860
Test name
Test status
Simulation time 1961465607 ps
CPU time 4.64 seconds
Started Jun 22 05:19:18 PM PDT 24
Finished Jun 22 05:19:24 PM PDT 24
Peak memory 217392 kb
Host smart-0652c67b-5f53-43c6-8db0-89802d76761a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359890624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2359890624
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3862352350
Short name T527
Test name
Test status
Simulation time 173874084 ps
CPU time 3.74 seconds
Started Jun 22 05:19:17 PM PDT 24
Finished Jun 22 05:19:22 PM PDT 24
Peak memory 217504 kb
Host smart-145ccafa-cb23-4b58-bc9c-ae2b85b8a082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862352350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3862352350
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.392436110
Short name T639
Test name
Test status
Simulation time 55034635 ps
CPU time 0.89 seconds
Started Jun 22 05:19:17 PM PDT 24
Finished Jun 22 05:19:18 PM PDT 24
Peak memory 207312 kb
Host smart-a50c55ca-3923-4edc-97d8-4e71921749fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392436110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.392436110
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.315069797
Short name T439
Test name
Test status
Simulation time 7104098281 ps
CPU time 14.02 seconds
Started Jun 22 05:19:16 PM PDT 24
Finished Jun 22 05:19:31 PM PDT 24
Peak memory 233888 kb
Host smart-7bf4a87b-9f59-456d-8590-5556644173cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315069797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.315069797
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2341425644
Short name T487
Test name
Test status
Simulation time 28109772 ps
CPU time 0.77 seconds
Started Jun 22 05:19:18 PM PDT 24
Finished Jun 22 05:19:20 PM PDT 24
Peak memory 206540 kb
Host smart-b0426db9-9892-4c23-abeb-00877f90027f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341425644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2341425644
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2919432944
Short name T620
Test name
Test status
Simulation time 701296969 ps
CPU time 6.88 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:19:28 PM PDT 24
Peak memory 225448 kb
Host smart-018024a3-dae9-461a-9747-cfb0cbf2cdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919432944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2919432944
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1191725940
Short name T497
Test name
Test status
Simulation time 16388820 ps
CPU time 0.75 seconds
Started Jun 22 05:19:22 PM PDT 24
Finished Jun 22 05:19:24 PM PDT 24
Peak memory 206808 kb
Host smart-85161542-f310-4a12-8d03-91eb2194c0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191725940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1191725940
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2119208644
Short name T897
Test name
Test status
Simulation time 203440908111 ps
CPU time 443.77 seconds
Started Jun 22 05:19:17 PM PDT 24
Finished Jun 22 05:26:42 PM PDT 24
Peak memory 264776 kb
Host smart-1861ae33-7f19-47f1-915c-dbc2c4df42ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119208644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2119208644
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2880839945
Short name T41
Test name
Test status
Simulation time 8716290356 ps
CPU time 139.11 seconds
Started Jun 22 05:19:20 PM PDT 24
Finished Jun 22 05:21:41 PM PDT 24
Peak memory 255960 kb
Host smart-a92a31b7-9e60-4d11-bab5-eb781e0b4d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880839945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2880839945
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3009199677
Short name T210
Test name
Test status
Simulation time 28629781657 ps
CPU time 267.16 seconds
Started Jun 22 05:19:20 PM PDT 24
Finished Jun 22 05:23:48 PM PDT 24
Peak memory 250324 kb
Host smart-4a70ffad-80bb-4883-b60a-dc39da415071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009199677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3009199677
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.696784003
Short name T841
Test name
Test status
Simulation time 36393662 ps
CPU time 3.29 seconds
Started Jun 22 05:19:21 PM PDT 24
Finished Jun 22 05:19:26 PM PDT 24
Peak memory 233976 kb
Host smart-abbda450-ccac-43fc-8153-04d8498eb268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696784003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.696784003
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3628992064
Short name T605
Test name
Test status
Simulation time 123717485 ps
CPU time 4.32 seconds
Started Jun 22 05:19:17 PM PDT 24
Finished Jun 22 05:19:23 PM PDT 24
Peak memory 225416 kb
Host smart-94ad3326-da44-4d13-80fb-6897858de251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628992064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3628992064
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.433887537
Short name T927
Test name
Test status
Simulation time 5063871216 ps
CPU time 33.2 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:19:54 PM PDT 24
Peak memory 233796 kb
Host smart-993a07ee-9470-4f8b-ae73-436f49f4066e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433887537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.433887537
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.698265905
Short name T285
Test name
Test status
Simulation time 743620612 ps
CPU time 7.14 seconds
Started Jun 22 05:19:20 PM PDT 24
Finished Jun 22 05:19:29 PM PDT 24
Peak memory 233660 kb
Host smart-030540e8-016b-4cb7-b4ac-7f5a8d09ed2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698265905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.698265905
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.333215826
Short name T891
Test name
Test status
Simulation time 779134937 ps
CPU time 3.88 seconds
Started Jun 22 05:19:21 PM PDT 24
Finished Jun 22 05:19:26 PM PDT 24
Peak memory 225496 kb
Host smart-b9197bf9-42f5-438b-b73c-6ee454dc86a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333215826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.333215826
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3244838869
Short name T667
Test name
Test status
Simulation time 1949956690 ps
CPU time 11.95 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:19:33 PM PDT 24
Peak memory 224252 kb
Host smart-74312b7f-750c-40bb-b895-b8cbb967bb60
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3244838869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3244838869
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3936330400
Short name T423
Test name
Test status
Simulation time 141951801 ps
CPU time 1.23 seconds
Started Jun 22 05:19:18 PM PDT 24
Finished Jun 22 05:19:20 PM PDT 24
Peak memory 207920 kb
Host smart-ceadf0b8-9e1a-4023-bf84-748aaae67d73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936330400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3936330400
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1461354178
Short name T716
Test name
Test status
Simulation time 7940741286 ps
CPU time 17.46 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:19:38 PM PDT 24
Peak memory 217612 kb
Host smart-57e8780d-66ea-4b7c-86f5-2b443197c87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461354178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1461354178
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3495052975
Short name T558
Test name
Test status
Simulation time 1200315918 ps
CPU time 3.49 seconds
Started Jun 22 05:19:18 PM PDT 24
Finished Jun 22 05:19:24 PM PDT 24
Peak memory 217276 kb
Host smart-35cd1d3c-7a9a-4e0a-aaa1-8c87c32e60bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495052975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3495052975
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1530987567
Short name T920
Test name
Test status
Simulation time 30363041 ps
CPU time 1.79 seconds
Started Jun 22 05:19:21 PM PDT 24
Finished Jun 22 05:19:25 PM PDT 24
Peak memory 209076 kb
Host smart-5fe1a948-d9d6-4792-8749-39b7f380ee68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530987567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1530987567
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.4005650499
Short name T427
Test name
Test status
Simulation time 134236761 ps
CPU time 0.92 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:19:22 PM PDT 24
Peak memory 206872 kb
Host smart-a4274ba2-8ede-491e-9ba8-5340dfd53fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005650499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.4005650499
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3922489206
Short name T720
Test name
Test status
Simulation time 1091583401 ps
CPU time 9.59 seconds
Started Jun 22 05:19:18 PM PDT 24
Finished Jun 22 05:19:29 PM PDT 24
Peak memory 233716 kb
Host smart-e9032065-60e9-421f-9ab6-b58d9ff08877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922489206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3922489206
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3203212496
Short name T834
Test name
Test status
Simulation time 29181845 ps
CPU time 0.7 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:19:21 PM PDT 24
Peak memory 206188 kb
Host smart-8ca85ff1-7160-4617-a94c-e131ef44ddcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203212496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3203212496
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2379474935
Short name T762
Test name
Test status
Simulation time 34079891 ps
CPU time 2.59 seconds
Started Jun 22 05:19:22 PM PDT 24
Finished Jun 22 05:19:26 PM PDT 24
Peak memory 233428 kb
Host smart-f15e3292-a767-40e6-a5a3-bbffe2247c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379474935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2379474935
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.723257062
Short name T404
Test name
Test status
Simulation time 22976834 ps
CPU time 0.85 seconds
Started Jun 22 05:19:21 PM PDT 24
Finished Jun 22 05:19:24 PM PDT 24
Peak memory 207496 kb
Host smart-507af786-2afe-45eb-a47a-13c9748c9b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723257062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.723257062
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3957253921
Short name T616
Test name
Test status
Simulation time 11267663 ps
CPU time 0.75 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:19:22 PM PDT 24
Peak memory 216844 kb
Host smart-b24dddd2-f755-44a3-9350-e16c1e25af2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957253921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3957253921
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.887374165
Short name T220
Test name
Test status
Simulation time 8668607246 ps
CPU time 78.77 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:20:40 PM PDT 24
Peak memory 225676 kb
Host smart-b2cfb8d7-622f-4aed-89f6-44824ed1f05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887374165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.887374165
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3124058887
Short name T506
Test name
Test status
Simulation time 3889439488 ps
CPU time 13.82 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:19:35 PM PDT 24
Peak memory 231472 kb
Host smart-e0340d34-c31d-4236-ab52-f7bc5db5bd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124058887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3124058887
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1912165365
Short name T935
Test name
Test status
Simulation time 9250331251 ps
CPU time 12.9 seconds
Started Jun 22 05:19:22 PM PDT 24
Finished Jun 22 05:19:36 PM PDT 24
Peak memory 233860 kb
Host smart-9c0d3231-58a2-4244-af7c-4645f4949a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912165365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1912165365
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1476503095
Short name T977
Test name
Test status
Simulation time 5495353303 ps
CPU time 16.71 seconds
Started Jun 22 05:19:18 PM PDT 24
Finished Jun 22 05:19:36 PM PDT 24
Peak memory 236556 kb
Host smart-fdc0d1ab-2f9b-4d33-944d-11abefba7475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476503095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1476503095
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1333879603
Short name T976
Test name
Test status
Simulation time 5391371012 ps
CPU time 19.16 seconds
Started Jun 22 05:19:17 PM PDT 24
Finished Jun 22 05:19:37 PM PDT 24
Peak memory 233896 kb
Host smart-384fa12b-1132-4698-bfa9-4307a418d1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333879603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1333879603
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1268200292
Short name T276
Test name
Test status
Simulation time 681994994 ps
CPU time 3.74 seconds
Started Jun 22 05:19:16 PM PDT 24
Finished Jun 22 05:19:21 PM PDT 24
Peak memory 233724 kb
Host smart-b2ca3662-ef9a-43fd-b21a-f1c63a4541c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268200292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1268200292
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3487970600
Short name T880
Test name
Test status
Simulation time 472088069 ps
CPU time 3.86 seconds
Started Jun 22 05:19:20 PM PDT 24
Finished Jun 22 05:19:25 PM PDT 24
Peak memory 219828 kb
Host smart-72103190-9d7f-4dff-b0fc-a85983e3174a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3487970600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3487970600
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3412972729
Short name T18
Test name
Test status
Simulation time 487285891 ps
CPU time 1.16 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:19:22 PM PDT 24
Peak memory 217084 kb
Host smart-242b4a3f-5aa4-46ce-b8c5-d7fe3894a93a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412972729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3412972729
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.917044161
Short name T593
Test name
Test status
Simulation time 5205641412 ps
CPU time 20.29 seconds
Started Jun 22 05:19:18 PM PDT 24
Finished Jun 22 05:19:39 PM PDT 24
Peak memory 217488 kb
Host smart-8d622de3-1645-4126-ac16-d6f8a9768894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917044161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.917044161
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.344173421
Short name T339
Test name
Test status
Simulation time 18302067388 ps
CPU time 20.01 seconds
Started Jun 22 05:19:18 PM PDT 24
Finished Jun 22 05:19:39 PM PDT 24
Peak memory 217436 kb
Host smart-2db64f1f-9429-43f1-8105-cda8ce6fceda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344173421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.344173421
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2318335216
Short name T494
Test name
Test status
Simulation time 292419872 ps
CPU time 2.22 seconds
Started Jun 22 05:19:18 PM PDT 24
Finished Jun 22 05:19:22 PM PDT 24
Peak memory 217540 kb
Host smart-d9ff54ec-4517-42f8-a78e-eb14dcb19b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318335216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2318335216
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2543162223
Short name T649
Test name
Test status
Simulation time 75709405 ps
CPU time 1.03 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:19:22 PM PDT 24
Peak memory 207360 kb
Host smart-e2db21b4-2f65-4f26-8fa8-283279c69f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543162223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2543162223
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3983300188
Short name T766
Test name
Test status
Simulation time 4738943950 ps
CPU time 7.42 seconds
Started Jun 22 05:19:18 PM PDT 24
Finished Jun 22 05:19:27 PM PDT 24
Peak memory 233864 kb
Host smart-8926d741-059b-4247-96ac-3ec3836a09b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983300188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3983300188
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.4201853873
Short name T689
Test name
Test status
Simulation time 40322190 ps
CPU time 0.73 seconds
Started Jun 22 05:19:25 PM PDT 24
Finished Jun 22 05:19:26 PM PDT 24
Peak memory 206568 kb
Host smart-af1220ec-41f0-4231-86d2-c50a13379380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201853873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
4201853873
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.256036846
Short name T491
Test name
Test status
Simulation time 442694768 ps
CPU time 5.07 seconds
Started Jun 22 05:19:22 PM PDT 24
Finished Jun 22 05:19:28 PM PDT 24
Peak memory 225512 kb
Host smart-bdfe8330-e64c-4da7-b53d-423f3181b55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256036846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.256036846
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2520962484
Short name T884
Test name
Test status
Simulation time 112841021 ps
CPU time 0.81 seconds
Started Jun 22 05:19:21 PM PDT 24
Finished Jun 22 05:19:23 PM PDT 24
Peak memory 207492 kb
Host smart-16a28311-7821-42fa-a35e-be133742d312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520962484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2520962484
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3716216945
Short name T682
Test name
Test status
Simulation time 10230160953 ps
CPU time 63.63 seconds
Started Jun 22 05:19:23 PM PDT 24
Finished Jun 22 05:20:28 PM PDT 24
Peak memory 258484 kb
Host smart-657b1c31-c8d7-4883-8c50-e416d2738ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716216945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3716216945
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.4201158441
Short name T45
Test name
Test status
Simulation time 3854597994 ps
CPU time 56.31 seconds
Started Jun 22 05:19:22 PM PDT 24
Finished Jun 22 05:20:20 PM PDT 24
Peak memory 250320 kb
Host smart-7fdd6111-e924-459b-b9f8-65521ac3b5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201158441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.4201158441
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1516212216
Short name T72
Test name
Test status
Simulation time 12019709188 ps
CPU time 44.2 seconds
Started Jun 22 05:19:20 PM PDT 24
Finished Jun 22 05:20:06 PM PDT 24
Peak memory 242476 kb
Host smart-bffaf139-129f-4093-9ea8-dff725772f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516212216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1516212216
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2061793440
Short name T600
Test name
Test status
Simulation time 583071869 ps
CPU time 4.03 seconds
Started Jun 22 05:19:20 PM PDT 24
Finished Jun 22 05:19:26 PM PDT 24
Peak memory 233784 kb
Host smart-a06b33a8-669d-42d5-9afa-d4bc0aaa52c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061793440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2061793440
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3017354147
Short name T799
Test name
Test status
Simulation time 3792710225 ps
CPU time 42.46 seconds
Started Jun 22 05:19:22 PM PDT 24
Finished Jun 22 05:20:05 PM PDT 24
Peak memory 241496 kb
Host smart-907e9982-3a3f-436b-9cc9-87ce8b6a963a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017354147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3017354147
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3824147896
Short name T692
Test name
Test status
Simulation time 854366289 ps
CPU time 5.35 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:19:26 PM PDT 24
Peak memory 233736 kb
Host smart-b44e15ec-dde7-4e39-87a4-2d1ddf9a65b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824147896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3824147896
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.435135555
Short name T403
Test name
Test status
Simulation time 166772781 ps
CPU time 4.15 seconds
Started Jun 22 05:19:20 PM PDT 24
Finished Jun 22 05:19:26 PM PDT 24
Peak memory 225464 kb
Host smart-7168f282-b3a6-4ee7-b380-80b00cf98c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435135555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.435135555
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.562168234
Short name T420
Test name
Test status
Simulation time 846286535 ps
CPU time 10.6 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:19:31 PM PDT 24
Peak memory 222820 kb
Host smart-ee4b4ea4-93bb-4896-9cab-cc8e87c2bf51
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=562168234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.562168234
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.4273987294
Short name T724
Test name
Test status
Simulation time 75877773 ps
CPU time 0.71 seconds
Started Jun 22 05:19:21 PM PDT 24
Finished Jun 22 05:19:23 PM PDT 24
Peak memory 206636 kb
Host smart-9b83c54e-3ffa-4990-a3eb-b8d9556a9f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273987294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.4273987294
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1680670576
Short name T704
Test name
Test status
Simulation time 1068484591 ps
CPU time 6.98 seconds
Started Jun 22 05:19:20 PM PDT 24
Finished Jun 22 05:19:29 PM PDT 24
Peak memory 217452 kb
Host smart-ab9da1a7-44c8-4260-83a0-81fee012e5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680670576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1680670576
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.984446261
Short name T589
Test name
Test status
Simulation time 316609308 ps
CPU time 2.18 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:19:23 PM PDT 24
Peak memory 217284 kb
Host smart-25d92ffc-43f5-4fce-bbc6-9c96dbc28f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984446261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.984446261
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3204906597
Short name T2
Test name
Test status
Simulation time 158814336 ps
CPU time 0.86 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:19:22 PM PDT 24
Peak memory 206792 kb
Host smart-d4a11143-49a2-433c-af49-7f161e519300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204906597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3204906597
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.439594870
Short name T422
Test name
Test status
Simulation time 23716543419 ps
CPU time 23.05 seconds
Started Jun 22 05:19:20 PM PDT 24
Finished Jun 22 05:19:45 PM PDT 24
Peak memory 233884 kb
Host smart-4533f491-c583-4ba2-a070-639a6156af66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439594870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.439594870
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4260427662
Short name T361
Test name
Test status
Simulation time 13122184 ps
CPU time 0.72 seconds
Started Jun 22 05:19:42 PM PDT 24
Finished Jun 22 05:19:44 PM PDT 24
Peak memory 206240 kb
Host smart-ea400dda-812a-40d0-bb35-a74c06c023a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260427662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4260427662
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1869645634
Short name T566
Test name
Test status
Simulation time 690615130 ps
CPU time 4.78 seconds
Started Jun 22 05:19:28 PM PDT 24
Finished Jun 22 05:19:34 PM PDT 24
Peak memory 233768 kb
Host smart-68ddf8ea-8eb0-424a-a5f1-a8f976c1fa56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869645634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1869645634
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.430602583
Short name T606
Test name
Test status
Simulation time 40751345 ps
CPU time 0.75 seconds
Started Jun 22 05:19:22 PM PDT 24
Finished Jun 22 05:19:24 PM PDT 24
Peak memory 207488 kb
Host smart-f1a9e4cd-18b7-4e52-869f-95decde70ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430602583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.430602583
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1307788937
Short name T444
Test name
Test status
Simulation time 51862323728 ps
CPU time 112.5 seconds
Started Jun 22 05:19:26 PM PDT 24
Finished Jun 22 05:21:20 PM PDT 24
Peak memory 257436 kb
Host smart-6d277208-0625-4d65-8efa-10a7fcebfabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307788937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1307788937
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3021715192
Short name T46
Test name
Test status
Simulation time 13438114249 ps
CPU time 129.07 seconds
Started Jun 22 05:19:27 PM PDT 24
Finished Jun 22 05:21:37 PM PDT 24
Peak memory 253468 kb
Host smart-96d767fd-fc2e-4782-96ab-c7943b44f11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021715192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3021715192
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1581317391
Short name T906
Test name
Test status
Simulation time 5075927953 ps
CPU time 70.71 seconds
Started Jun 22 05:19:27 PM PDT 24
Finished Jun 22 05:20:39 PM PDT 24
Peak memory 251556 kb
Host smart-eaa4d140-76b9-4fc3-9a68-f28417a5866d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581317391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1581317391
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.4080320028
Short name T974
Test name
Test status
Simulation time 36289283719 ps
CPU time 75.51 seconds
Started Jun 22 05:19:26 PM PDT 24
Finished Jun 22 05:20:43 PM PDT 24
Peak memory 237732 kb
Host smart-9bc1face-3603-4497-99f8-468ad51146ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080320028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.4080320028
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2663715628
Short name T929
Test name
Test status
Simulation time 8642524045 ps
CPU time 29.63 seconds
Started Jun 22 05:19:29 PM PDT 24
Finished Jun 22 05:19:59 PM PDT 24
Peak memory 225536 kb
Host smart-e505f5ea-68d3-4676-9efc-27cc87291b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663715628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2663715628
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3529652306
Short name T319
Test name
Test status
Simulation time 145299465 ps
CPU time 2.3 seconds
Started Jun 22 05:19:27 PM PDT 24
Finished Jun 22 05:19:31 PM PDT 24
Peak memory 224168 kb
Host smart-efca3f6c-a7f4-4dff-84ae-0978a9c177a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529652306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3529652306
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.437422319
Short name T562
Test name
Test status
Simulation time 111309461261 ps
CPU time 23.93 seconds
Started Jun 22 05:19:23 PM PDT 24
Finished Jun 22 05:19:48 PM PDT 24
Peak memory 233896 kb
Host smart-bdd8063c-219b-4dab-8d20-151e982ad67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437422319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.437422319
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3720130815
Short name T468
Test name
Test status
Simulation time 21277222893 ps
CPU time 12.89 seconds
Started Jun 22 05:19:23 PM PDT 24
Finished Jun 22 05:19:42 PM PDT 24
Peak memory 225632 kb
Host smart-ee5ebbe7-5c02-4458-8c52-6ed6e5944428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720130815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3720130815
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1140968788
Short name T822
Test name
Test status
Simulation time 102840392 ps
CPU time 4.01 seconds
Started Jun 22 05:19:24 PM PDT 24
Finished Jun 22 05:19:29 PM PDT 24
Peak memory 223564 kb
Host smart-564468ae-c085-4f20-ad80-6286d72d9ec8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1140968788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1140968788
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2903731990
Short name T547
Test name
Test status
Simulation time 20817158201 ps
CPU time 25.95 seconds
Started Jun 22 05:19:22 PM PDT 24
Finished Jun 22 05:19:49 PM PDT 24
Peak memory 217500 kb
Host smart-c0cd63bf-8f8d-4634-a43a-31d7a31db9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903731990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2903731990
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.4365850
Short name T645
Test name
Test status
Simulation time 1718190264 ps
CPU time 2.98 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:19:23 PM PDT 24
Peak memory 208868 kb
Host smart-759ee4f9-3962-4b90-8148-5c106a0d938b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4365850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.4365850
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2537019365
Short name T349
Test name
Test status
Simulation time 69575973 ps
CPU time 1.37 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:19:23 PM PDT 24
Peak memory 217600 kb
Host smart-00318404-7acb-4a80-ab02-4ca1cd09eada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537019365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2537019365
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2198746735
Short name T28
Test name
Test status
Simulation time 42318222 ps
CPU time 0.79 seconds
Started Jun 22 05:19:19 PM PDT 24
Finished Jun 22 05:19:21 PM PDT 24
Peak memory 206904 kb
Host smart-1c4b39e1-b880-4aae-834a-a4d3af9ebbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198746735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2198746735
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3814962608
Short name T243
Test name
Test status
Simulation time 365513634 ps
CPU time 4.55 seconds
Started Jun 22 05:19:27 PM PDT 24
Finished Jun 22 05:19:33 PM PDT 24
Peak memory 225388 kb
Host smart-0904168d-03f4-47b8-a736-f3788def83a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814962608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3814962608
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1047030059
Short name T681
Test name
Test status
Simulation time 14673720 ps
CPU time 0.78 seconds
Started Jun 22 05:19:26 PM PDT 24
Finished Jun 22 05:19:28 PM PDT 24
Peak memory 206272 kb
Host smart-8438acc2-8762-4585-a4c4-aa898d6de7e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047030059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1047030059
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1332782635
Short name T493
Test name
Test status
Simulation time 249413916 ps
CPU time 2.37 seconds
Started Jun 22 05:19:24 PM PDT 24
Finished Jun 22 05:19:27 PM PDT 24
Peak memory 225544 kb
Host smart-10341846-89ac-4bdc-81de-6be5e46c12f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332782635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1332782635
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1863812208
Short name T426
Test name
Test status
Simulation time 14066541 ps
CPU time 0.74 seconds
Started Jun 22 05:19:27 PM PDT 24
Finished Jun 22 05:19:29 PM PDT 24
Peak memory 206412 kb
Host smart-edf7c661-dd39-4d31-b269-7d185d0750e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863812208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1863812208
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1844804214
Short name T908
Test name
Test status
Simulation time 11182517222 ps
CPU time 45.99 seconds
Started Jun 22 05:19:29 PM PDT 24
Finished Jun 22 05:20:16 PM PDT 24
Peak memory 250824 kb
Host smart-5c935572-f9ee-4a85-8d8f-27b898917830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844804214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1844804214
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.707470724
Short name T173
Test name
Test status
Simulation time 4242317723 ps
CPU time 31.41 seconds
Started Jun 22 05:19:27 PM PDT 24
Finished Jun 22 05:20:00 PM PDT 24
Peak memory 223448 kb
Host smart-52882eab-aaa7-4449-b887-c0e9d89045d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707470724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.707470724
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2268077812
Short name T177
Test name
Test status
Simulation time 5672692092 ps
CPU time 67.4 seconds
Started Jun 22 05:19:26 PM PDT 24
Finished Jun 22 05:20:34 PM PDT 24
Peak memory 254852 kb
Host smart-ace9f301-fa39-4fa7-ade1-2f2669b4e478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268077812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2268077812
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1058624000
Short name T309
Test name
Test status
Simulation time 178062302 ps
CPU time 3.66 seconds
Started Jun 22 05:19:27 PM PDT 24
Finished Jun 22 05:19:32 PM PDT 24
Peak memory 233764 kb
Host smart-5049807c-f958-4ab3-9a2c-591e9fc1226c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058624000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1058624000
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1329962685
Short name T691
Test name
Test status
Simulation time 1006040151 ps
CPU time 3.81 seconds
Started Jun 22 05:19:42 PM PDT 24
Finished Jun 22 05:19:47 PM PDT 24
Peak memory 233728 kb
Host smart-dc9b27d3-834b-4023-8e74-309c3bcf62a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329962685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1329962685
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.978551148
Short name T753
Test name
Test status
Simulation time 6049761003 ps
CPU time 26.51 seconds
Started Jun 22 05:19:26 PM PDT 24
Finished Jun 22 05:19:54 PM PDT 24
Peak memory 241704 kb
Host smart-c6cd685d-f0dc-4dc3-abcc-3168fa4a343c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978551148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.978551148
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.82766374
Short name T1
Test name
Test status
Simulation time 4946331359 ps
CPU time 11.98 seconds
Started Jun 22 05:19:26 PM PDT 24
Finished Jun 22 05:19:40 PM PDT 24
Peak memory 225684 kb
Host smart-6f80ef56-6a26-43f6-ab79-068836fa5610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82766374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.82766374
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.359988353
Short name T86
Test name
Test status
Simulation time 3201804285 ps
CPU time 14.91 seconds
Started Jun 22 05:19:31 PM PDT 24
Finished Jun 22 05:19:46 PM PDT 24
Peak memory 241932 kb
Host smart-db006c21-d61b-4d56-9aa0-e01b9189b099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359988353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.359988353
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.810523848
Short name T390
Test name
Test status
Simulation time 164813447 ps
CPU time 5.11 seconds
Started Jun 22 05:19:40 PM PDT 24
Finished Jun 22 05:19:47 PM PDT 24
Peak memory 221772 kb
Host smart-85c5008a-856d-4db4-8256-05d1aed5f14e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=810523848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.810523848
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3083272140
Short name T149
Test name
Test status
Simulation time 16351389000 ps
CPU time 73.4 seconds
Started Jun 22 05:19:39 PM PDT 24
Finished Jun 22 05:20:52 PM PDT 24
Peak memory 242104 kb
Host smart-73c1147a-96a5-45b4-ab4e-9175c200a472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083272140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3083272140
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1993953654
Short name T879
Test name
Test status
Simulation time 22080315760 ps
CPU time 27.59 seconds
Started Jun 22 05:19:35 PM PDT 24
Finished Jun 22 05:20:03 PM PDT 24
Peak memory 217408 kb
Host smart-dc733ff7-e8ab-446d-bfce-650ea8ab250d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993953654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1993953654
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3681530532
Short name T411
Test name
Test status
Simulation time 9218555070 ps
CPU time 8.04 seconds
Started Jun 22 05:19:23 PM PDT 24
Finished Jun 22 05:19:32 PM PDT 24
Peak memory 217452 kb
Host smart-7a725489-15e4-4723-a554-a981252e6c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681530532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3681530532
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2006306228
Short name T959
Test name
Test status
Simulation time 145829798 ps
CPU time 1.27 seconds
Started Jun 22 05:19:34 PM PDT 24
Finished Jun 22 05:19:36 PM PDT 24
Peak memory 208888 kb
Host smart-93596828-5ead-4e64-b029-12946414fb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006306228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2006306228
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2175986080
Short name T886
Test name
Test status
Simulation time 246819346 ps
CPU time 0.91 seconds
Started Jun 22 05:19:27 PM PDT 24
Finished Jun 22 05:19:29 PM PDT 24
Peak memory 206824 kb
Host smart-09561ff8-9f8e-4bf0-b6c6-94706e777ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175986080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2175986080
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3514403881
Short name T74
Test name
Test status
Simulation time 6470518422 ps
CPU time 23.78 seconds
Started Jun 22 05:19:28 PM PDT 24
Finished Jun 22 05:19:53 PM PDT 24
Peak memory 233852 kb
Host smart-b8f23aac-8e56-46ba-b6eb-0c31a95e012f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514403881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3514403881
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1987659138
Short name T780
Test name
Test status
Simulation time 41960156 ps
CPU time 0.72 seconds
Started Jun 22 05:19:26 PM PDT 24
Finished Jun 22 05:19:28 PM PDT 24
Peak memory 205664 kb
Host smart-30bf6ce3-82d1-4cdf-bda7-0c8026888b01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987659138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1987659138
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.814870962
Short name T769
Test name
Test status
Simulation time 384595612 ps
CPU time 3.63 seconds
Started Jun 22 05:19:24 PM PDT 24
Finished Jun 22 05:19:28 PM PDT 24
Peak memory 225556 kb
Host smart-2342612c-b498-4fb3-854d-fb572578c91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814870962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.814870962
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1452251096
Short name T695
Test name
Test status
Simulation time 80202213 ps
CPU time 0.81 seconds
Started Jun 22 05:19:26 PM PDT 24
Finished Jun 22 05:19:27 PM PDT 24
Peak memory 207484 kb
Host smart-dba46144-450d-4018-9fcd-eed77f5a94fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452251096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1452251096
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1851787599
Short name T36
Test name
Test status
Simulation time 47198541793 ps
CPU time 60.24 seconds
Started Jun 22 05:19:33 PM PDT 24
Finished Jun 22 05:20:34 PM PDT 24
Peak memory 242056 kb
Host smart-b3e52124-f570-47d7-b01b-4f0d1bc2dd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851787599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1851787599
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3448766337
Short name T155
Test name
Test status
Simulation time 173115370419 ps
CPU time 116 seconds
Started Jun 22 05:19:40 PM PDT 24
Finished Jun 22 05:21:37 PM PDT 24
Peak memory 250312 kb
Host smart-63b77f25-af06-45d0-a40a-93407251a511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448766337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3448766337
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3615400340
Short name T40
Test name
Test status
Simulation time 26136829414 ps
CPU time 241.29 seconds
Started Jun 22 05:19:28 PM PDT 24
Finished Jun 22 05:23:31 PM PDT 24
Peak memory 256560 kb
Host smart-5a7b873a-c635-4ea3-b19c-55b537a83b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615400340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3615400340
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2919822978
Short name T778
Test name
Test status
Simulation time 526407191 ps
CPU time 7.46 seconds
Started Jun 22 05:19:27 PM PDT 24
Finished Jun 22 05:19:35 PM PDT 24
Peak memory 233716 kb
Host smart-ff71e8b3-3dba-475b-aea6-2dce90bbf1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919822978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2919822978
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2656382399
Short name T881
Test name
Test status
Simulation time 3987296888 ps
CPU time 12.4 seconds
Started Jun 22 05:19:28 PM PDT 24
Finished Jun 22 05:19:42 PM PDT 24
Peak memory 225644 kb
Host smart-ec1a22e2-86eb-439d-86ae-ba9da8c17b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656382399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2656382399
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.615189650
Short name T317
Test name
Test status
Simulation time 29187854 ps
CPU time 2.15 seconds
Started Jun 22 05:19:26 PM PDT 24
Finished Jun 22 05:19:28 PM PDT 24
Peak memory 223896 kb
Host smart-ddbb6ed6-344f-405a-8cc9-befa9642629a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615189650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.615189650
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2813920087
Short name T298
Test name
Test status
Simulation time 17711684150 ps
CPU time 17.41 seconds
Started Jun 22 05:19:42 PM PDT 24
Finished Jun 22 05:20:00 PM PDT 24
Peak memory 241588 kb
Host smart-41087286-462b-4831-82d4-0f60e7c93d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813920087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2813920087
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2481411068
Short name T234
Test name
Test status
Simulation time 487591951 ps
CPU time 2.71 seconds
Started Jun 22 05:19:40 PM PDT 24
Finished Jun 22 05:19:44 PM PDT 24
Peak memory 225484 kb
Host smart-ad0f91e9-1f8c-4abb-b694-9914ac6a0db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481411068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2481411068
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.484904485
Short name T135
Test name
Test status
Simulation time 398890918 ps
CPU time 4.3 seconds
Started Jun 22 05:19:42 PM PDT 24
Finished Jun 22 05:19:47 PM PDT 24
Peak memory 221104 kb
Host smart-bdfb0052-e09d-42bd-8c66-3c11c89e0f16
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=484904485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.484904485
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3516083469
Short name T371
Test name
Test status
Simulation time 75779136 ps
CPU time 1.01 seconds
Started Jun 22 05:19:29 PM PDT 24
Finished Jun 22 05:19:31 PM PDT 24
Peak memory 207628 kb
Host smart-71793427-af2f-442a-8567-4ca8581f4d9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516083469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3516083469
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1870996129
Short name T962
Test name
Test status
Simulation time 5580900193 ps
CPU time 14.85 seconds
Started Jun 22 05:19:25 PM PDT 24
Finished Jun 22 05:19:40 PM PDT 24
Peak memory 217440 kb
Host smart-fc248ae9-2783-4f84-834d-592a4c252951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870996129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1870996129
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2429071173
Short name T469
Test name
Test status
Simulation time 7048736626 ps
CPU time 20.23 seconds
Started Jun 22 05:19:27 PM PDT 24
Finished Jun 22 05:19:49 PM PDT 24
Peak memory 217404 kb
Host smart-34c10c28-0054-45f2-b3c6-1cb37b7c8f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429071173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2429071173
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1904921372
Short name T947
Test name
Test status
Simulation time 1004031143 ps
CPU time 4.38 seconds
Started Jun 22 05:19:42 PM PDT 24
Finished Jun 22 05:19:47 PM PDT 24
Peak memory 217236 kb
Host smart-abc966e4-e164-461d-889e-8969f63c7512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904921372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1904921372
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1156417845
Short name T744
Test name
Test status
Simulation time 58081267 ps
CPU time 0.89 seconds
Started Jun 22 05:19:25 PM PDT 24
Finished Jun 22 05:19:26 PM PDT 24
Peak memory 206880 kb
Host smart-4e68eecc-f26c-4fda-bbe6-6f087d949006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156417845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1156417845
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1430374583
Short name T174
Test name
Test status
Simulation time 34781379 ps
CPU time 2.15 seconds
Started Jun 22 05:19:43 PM PDT 24
Finished Jun 22 05:19:47 PM PDT 24
Peak memory 225468 kb
Host smart-389be823-d60b-4db0-88ed-03e05629eb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430374583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1430374583
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3066758780
Short name T70
Test name
Test status
Simulation time 13905220 ps
CPU time 0.71 seconds
Started Jun 22 05:19:50 PM PDT 24
Finished Jun 22 05:19:52 PM PDT 24
Peak memory 206576 kb
Host smart-bad974eb-2694-4d30-963a-3cb33fb99f19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066758780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3066758780
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2032708260
Short name T81
Test name
Test status
Simulation time 1017941793 ps
CPU time 8.85 seconds
Started Jun 22 05:19:32 PM PDT 24
Finished Jun 22 05:19:41 PM PDT 24
Peak memory 233680 kb
Host smart-d810c903-5048-402e-bb91-116b9b7577ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032708260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2032708260
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1915103964
Short name T697
Test name
Test status
Simulation time 12494723 ps
CPU time 0.78 seconds
Started Jun 22 05:19:43 PM PDT 24
Finished Jun 22 05:19:45 PM PDT 24
Peak memory 206456 kb
Host smart-45c51e2c-6aad-4800-9d12-f700c293e0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915103964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1915103964
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3973268991
Short name T286
Test name
Test status
Simulation time 370503949754 ps
CPU time 289.08 seconds
Started Jun 22 05:19:45 PM PDT 24
Finished Jun 22 05:24:35 PM PDT 24
Peak memory 254204 kb
Host smart-b573f227-f40e-4e97-ad82-26933cf3a248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973268991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3973268991
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.4278817325
Short name T424
Test name
Test status
Simulation time 13866306083 ps
CPU time 72.64 seconds
Started Jun 22 05:19:51 PM PDT 24
Finished Jun 22 05:21:04 PM PDT 24
Peak memory 258468 kb
Host smart-6ee1329a-59df-4c85-8d70-b29c1685ef22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278817325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.4278817325
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1056855960
Short name T791
Test name
Test status
Simulation time 9190890689 ps
CPU time 37.98 seconds
Started Jun 22 05:19:40 PM PDT 24
Finished Jun 22 05:20:19 PM PDT 24
Peak memory 258456 kb
Host smart-b6b8c19a-f4f8-41df-9ba5-32e9b7c38904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056855960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1056855960
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.528564020
Short name T628
Test name
Test status
Simulation time 150754562 ps
CPU time 4.77 seconds
Started Jun 22 05:19:35 PM PDT 24
Finished Jun 22 05:19:41 PM PDT 24
Peak memory 233800 kb
Host smart-7a7f5e67-a1f3-4c9c-90e8-031ceba73394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528564020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.528564020
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.69210501
Short name T273
Test name
Test status
Simulation time 1003337401 ps
CPU time 6.18 seconds
Started Jun 22 05:19:33 PM PDT 24
Finished Jun 22 05:19:40 PM PDT 24
Peak memory 233696 kb
Host smart-6b18daab-1029-49e3-94a5-b1b7c21bf9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69210501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.69210501
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1133042474
Short name T759
Test name
Test status
Simulation time 4961005525 ps
CPU time 41.93 seconds
Started Jun 22 05:19:32 PM PDT 24
Finished Jun 22 05:20:15 PM PDT 24
Peak memory 241948 kb
Host smart-83e645c1-be96-41b8-8d7f-2af91803ac17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133042474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1133042474
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.739125403
Short name T215
Test name
Test status
Simulation time 3451910998 ps
CPU time 10.71 seconds
Started Jun 22 05:19:33 PM PDT 24
Finished Jun 22 05:19:44 PM PDT 24
Peak memory 241856 kb
Host smart-8934798a-4556-4ea6-aa14-36af46ca49be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739125403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.739125403
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.979716777
Short name T817
Test name
Test status
Simulation time 304964980 ps
CPU time 2.28 seconds
Started Jun 22 05:19:34 PM PDT 24
Finished Jun 22 05:19:37 PM PDT 24
Peak memory 225476 kb
Host smart-074514ed-c6a6-4bd2-8703-a2cff833958a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979716777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.979716777
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2108636471
Short name T680
Test name
Test status
Simulation time 344201307 ps
CPU time 3.83 seconds
Started Jun 22 05:19:34 PM PDT 24
Finished Jun 22 05:19:38 PM PDT 24
Peak memory 223828 kb
Host smart-70a99b09-e395-4ce8-a979-08075d724c72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2108636471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2108636471
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2789188137
Short name T414
Test name
Test status
Simulation time 2425930300 ps
CPU time 34.7 seconds
Started Jun 22 05:19:27 PM PDT 24
Finished Jun 22 05:20:03 PM PDT 24
Peak memory 217372 kb
Host smart-4918d2e8-8e05-44d4-b81c-19aecff8cc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789188137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2789188137
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1655493852
Short name T355
Test name
Test status
Simulation time 5312035694 ps
CPU time 13.82 seconds
Started Jun 22 05:19:29 PM PDT 24
Finished Jun 22 05:19:43 PM PDT 24
Peak memory 217484 kb
Host smart-7ca1d15a-992e-4dd5-b88d-7d3e83bffcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655493852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1655493852
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3733394724
Short name T395
Test name
Test status
Simulation time 13187834 ps
CPU time 0.69 seconds
Started Jun 22 05:19:27 PM PDT 24
Finished Jun 22 05:19:29 PM PDT 24
Peak memory 206528 kb
Host smart-d29eb2ca-1249-4bd2-8b22-cc9705dd8e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733394724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3733394724
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2660066128
Short name T419
Test name
Test status
Simulation time 53567668 ps
CPU time 0.81 seconds
Started Jun 22 05:19:26 PM PDT 24
Finished Jun 22 05:19:27 PM PDT 24
Peak memory 206880 kb
Host smart-2dfb2010-1482-4b8c-b28e-b3ba2cae10c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660066128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2660066128
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.880172039
Short name T246
Test name
Test status
Simulation time 1145201369 ps
CPU time 5.29 seconds
Started Jun 22 05:19:33 PM PDT 24
Finished Jun 22 05:19:39 PM PDT 24
Peak memory 225420 kb
Host smart-ed48647b-87c4-4b23-9084-c9fc48112605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880172039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.880172039
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1698016472
Short name T62
Test name
Test status
Simulation time 15535806 ps
CPU time 0.73 seconds
Started Jun 22 05:19:34 PM PDT 24
Finished Jun 22 05:19:36 PM PDT 24
Peak memory 206284 kb
Host smart-df218adb-996a-45bc-b4f5-2f5ddecc93fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698016472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1698016472
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2313587155
Short name T363
Test name
Test status
Simulation time 1922455354 ps
CPU time 7.26 seconds
Started Jun 22 05:19:44 PM PDT 24
Finished Jun 22 05:19:53 PM PDT 24
Peak memory 225508 kb
Host smart-e470f6b3-501c-45d1-b5b2-e14f24b92f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313587155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2313587155
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.4144651454
Short name T818
Test name
Test status
Simulation time 69587643 ps
CPU time 0.81 seconds
Started Jun 22 05:19:45 PM PDT 24
Finished Jun 22 05:19:47 PM PDT 24
Peak memory 207456 kb
Host smart-2157995e-41d1-4a40-916b-7c51cc1cdeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144651454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.4144651454
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1842188166
Short name T208
Test name
Test status
Simulation time 92276393320 ps
CPU time 326.7 seconds
Started Jun 22 05:19:33 PM PDT 24
Finished Jun 22 05:25:00 PM PDT 24
Peak memory 251312 kb
Host smart-929dae79-e8f8-472d-8356-5e0cdc20f229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842188166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1842188166
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2207494651
Short name T222
Test name
Test status
Simulation time 26552123327 ps
CPU time 257 seconds
Started Jun 22 05:19:34 PM PDT 24
Finished Jun 22 05:23:52 PM PDT 24
Peak memory 251344 kb
Host smart-dea0a7d0-08a1-42f7-8435-a198f473c2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207494651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2207494651
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.684344855
Short name T31
Test name
Test status
Simulation time 4453698493 ps
CPU time 93.63 seconds
Started Jun 22 05:19:42 PM PDT 24
Finished Jun 22 05:21:17 PM PDT 24
Peak memory 250764 kb
Host smart-94c2434c-ccf2-40a9-bdfc-33ba2865cd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684344855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.684344855
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2838178619
Short name T725
Test name
Test status
Simulation time 1272108361 ps
CPU time 9.42 seconds
Started Jun 22 05:19:37 PM PDT 24
Finished Jun 22 05:19:46 PM PDT 24
Peak memory 239984 kb
Host smart-7c383c34-d1a1-4cbf-aee4-79c70cc682f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838178619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2838178619
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2874215603
Short name T535
Test name
Test status
Simulation time 47288428 ps
CPU time 2.74 seconds
Started Jun 22 05:19:45 PM PDT 24
Finished Jun 22 05:19:49 PM PDT 24
Peak memory 233744 kb
Host smart-a04d579c-931e-49c7-b7d0-f8bb0f926cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874215603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2874215603
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2959069420
Short name T575
Test name
Test status
Simulation time 6198237048 ps
CPU time 57.21 seconds
Started Jun 22 05:19:33 PM PDT 24
Finished Jun 22 05:20:31 PM PDT 24
Peak memory 233832 kb
Host smart-2302bc3f-9dd0-417b-9670-22ad408626f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959069420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2959069420
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1662774887
Short name T297
Test name
Test status
Simulation time 4355097204 ps
CPU time 14.46 seconds
Started Jun 22 05:19:34 PM PDT 24
Finished Jun 22 05:19:49 PM PDT 24
Peak memory 233816 kb
Host smart-c2427f2d-acc3-4356-b601-8c6f3b513f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662774887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1662774887
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.182327128
Short name T595
Test name
Test status
Simulation time 13003571528 ps
CPU time 21.15 seconds
Started Jun 22 05:19:35 PM PDT 24
Finished Jun 22 05:19:57 PM PDT 24
Peak memory 241608 kb
Host smart-bc399352-e8f0-4046-a5bd-ecf818dd5e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182327128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.182327128
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.798796562
Short name T136
Test name
Test status
Simulation time 827862780 ps
CPU time 8.7 seconds
Started Jun 22 05:19:42 PM PDT 24
Finished Jun 22 05:19:52 PM PDT 24
Peak memory 220232 kb
Host smart-ae53e059-22d2-4a1b-b1eb-3155e76b7a1b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=798796562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.798796562
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.616927391
Short name T964
Test name
Test status
Simulation time 6064882790 ps
CPU time 29.47 seconds
Started Jun 22 05:19:40 PM PDT 24
Finished Jun 22 05:20:11 PM PDT 24
Peak memory 218684 kb
Host smart-f16c0b1d-c630-4c44-babc-170d43d855dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616927391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.616927391
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3815720493
Short name T69
Test name
Test status
Simulation time 2026426776 ps
CPU time 5.79 seconds
Started Jun 22 05:19:35 PM PDT 24
Finished Jun 22 05:19:41 PM PDT 24
Peak memory 217336 kb
Host smart-330d372f-fda1-4cf7-965c-38fbf7ae10a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815720493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3815720493
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3293027706
Short name T551
Test name
Test status
Simulation time 18713457 ps
CPU time 0.88 seconds
Started Jun 22 05:19:34 PM PDT 24
Finished Jun 22 05:19:36 PM PDT 24
Peak memory 208564 kb
Host smart-fadcfc3e-75d1-484b-8264-0b502876c47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293027706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3293027706
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.874302655
Short name T898
Test name
Test status
Simulation time 107078549 ps
CPU time 0.85 seconds
Started Jun 22 05:19:44 PM PDT 24
Finished Jun 22 05:19:46 PM PDT 24
Peak memory 206852 kb
Host smart-ad40c135-6a19-42aa-850a-946813e5bc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874302655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.874302655
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.928170242
Short name T574
Test name
Test status
Simulation time 144309370 ps
CPU time 0.76 seconds
Started Jun 22 05:19:41 PM PDT 24
Finished Jun 22 05:19:43 PM PDT 24
Peak memory 206852 kb
Host smart-e9f1b3ae-e9fa-494d-9844-d10c031500e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928170242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.928170242
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2845511597
Short name T890
Test name
Test status
Simulation time 1588188651 ps
CPU time 16.12 seconds
Started Jun 22 05:19:35 PM PDT 24
Finished Jun 22 05:19:52 PM PDT 24
Peak memory 233692 kb
Host smart-0882d9a7-98b2-476b-9c61-fb933bef0b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845511597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2845511597
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.4015687322
Short name T425
Test name
Test status
Simulation time 27752783 ps
CPU time 0.74 seconds
Started Jun 22 05:19:39 PM PDT 24
Finished Jun 22 05:19:41 PM PDT 24
Peak memory 206464 kb
Host smart-9d16f3c9-cb99-42fc-a380-3003793b49fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015687322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4015687322
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.480216359
Short name T713
Test name
Test status
Simulation time 4240931737 ps
CPU time 91.82 seconds
Started Jun 22 05:19:42 PM PDT 24
Finished Jun 22 05:21:15 PM PDT 24
Peak memory 273868 kb
Host smart-5ae39db7-86cf-4f9b-8f47-98e378dd7a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480216359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.480216359
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1243853879
Short name T464
Test name
Test status
Simulation time 100358874990 ps
CPU time 86.96 seconds
Started Jun 22 05:19:33 PM PDT 24
Finished Jun 22 05:21:01 PM PDT 24
Peak memory 242128 kb
Host smart-24d2cb8a-bf0f-4291-bf6a-5b5ab403a70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243853879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1243853879
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2494672279
Short name T807
Test name
Test status
Simulation time 3834328295 ps
CPU time 24.22 seconds
Started Jun 22 05:19:43 PM PDT 24
Finished Jun 22 05:20:08 PM PDT 24
Peak memory 250236 kb
Host smart-33b59d6d-53a4-40bb-afb8-8b8947fc4906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494672279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2494672279
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1152403999
Short name T923
Test name
Test status
Simulation time 3359714684 ps
CPU time 48.58 seconds
Started Jun 22 05:19:34 PM PDT 24
Finished Jun 22 05:20:23 PM PDT 24
Peak memory 242060 kb
Host smart-db99d261-2e64-4e6e-8a26-f0e73a880e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152403999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1152403999
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.709651367
Short name T485
Test name
Test status
Simulation time 1377050637 ps
CPU time 5.7 seconds
Started Jun 22 05:19:35 PM PDT 24
Finished Jun 22 05:19:41 PM PDT 24
Peak memory 233900 kb
Host smart-1174d9a3-4146-4d51-af9f-b45283320ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709651367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.709651367
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3192959384
Short name T945
Test name
Test status
Simulation time 249473444 ps
CPU time 8.64 seconds
Started Jun 22 05:19:34 PM PDT 24
Finished Jun 22 05:19:43 PM PDT 24
Peak memory 233712 kb
Host smart-2637a858-c7bc-4ced-a519-baae83f1be21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192959384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3192959384
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3934526922
Short name T855
Test name
Test status
Simulation time 943464953 ps
CPU time 2.95 seconds
Started Jun 22 05:19:46 PM PDT 24
Finished Jun 22 05:19:50 PM PDT 24
Peak memory 233716 kb
Host smart-ea6df357-fb42-4b0f-8afe-d175e8dfe7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934526922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3934526922
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1403058731
Short name T868
Test name
Test status
Simulation time 14486986704 ps
CPU time 13.23 seconds
Started Jun 22 05:19:35 PM PDT 24
Finished Jun 22 05:19:49 PM PDT 24
Peak memory 241892 kb
Host smart-67d3ad17-606c-492e-8ad1-6396730c2498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403058731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1403058731
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.122424001
Short name T673
Test name
Test status
Simulation time 1096924846 ps
CPU time 11.28 seconds
Started Jun 22 05:19:34 PM PDT 24
Finished Jun 22 05:19:46 PM PDT 24
Peak memory 222764 kb
Host smart-da9d8cd6-071f-4812-afdd-28ec7382ca00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=122424001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.122424001
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1251141095
Short name T129
Test name
Test status
Simulation time 7420235024 ps
CPU time 89.62 seconds
Started Jun 22 05:19:53 PM PDT 24
Finished Jun 22 05:21:24 PM PDT 24
Peak memory 250264 kb
Host smart-6a3b7648-2ad3-4389-9180-11aa570fd56a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251141095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1251141095
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.4208685314
Short name T615
Test name
Test status
Simulation time 8671633552 ps
CPU time 32.42 seconds
Started Jun 22 05:19:39 PM PDT 24
Finished Jun 22 05:20:12 PM PDT 24
Peak memory 217480 kb
Host smart-1c364755-72ed-4ef9-a45a-a02a341f0056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208685314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.4208685314
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3260344267
Short name T347
Test name
Test status
Simulation time 31879240618 ps
CPU time 21.03 seconds
Started Jun 22 05:19:35 PM PDT 24
Finished Jun 22 05:19:57 PM PDT 24
Peak memory 217384 kb
Host smart-1d1466f3-abc2-4733-9131-1095bce72475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260344267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3260344267
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1779403822
Short name T522
Test name
Test status
Simulation time 350910203 ps
CPU time 6.67 seconds
Started Jun 22 05:19:34 PM PDT 24
Finished Jun 22 05:19:41 PM PDT 24
Peak memory 217208 kb
Host smart-fcb22273-eba4-477d-b135-b7a0a7c3c106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779403822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1779403822
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.4141207295
Short name T820
Test name
Test status
Simulation time 19631655 ps
CPU time 0.7 seconds
Started Jun 22 05:19:44 PM PDT 24
Finished Jun 22 05:19:47 PM PDT 24
Peak memory 206484 kb
Host smart-bc005275-97c2-48f2-85d2-58b9295f3884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141207295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.4141207295
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3153457965
Short name T9
Test name
Test status
Simulation time 16517228680 ps
CPU time 12.41 seconds
Started Jun 22 05:19:41 PM PDT 24
Finished Jun 22 05:19:54 PM PDT 24
Peak memory 233888 kb
Host smart-3ba9726d-bf5b-4fdc-8b53-db73609933b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153457965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3153457965
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.399799095
Short name T337
Test name
Test status
Simulation time 13892898 ps
CPU time 0.75 seconds
Started Jun 22 05:18:05 PM PDT 24
Finished Jun 22 05:18:06 PM PDT 24
Peak memory 205720 kb
Host smart-447ffd4c-1d6d-4b11-b009-d15ef3c2f906
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399799095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.399799095
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2465704019
Short name T247
Test name
Test status
Simulation time 260909373 ps
CPU time 2.73 seconds
Started Jun 22 05:18:04 PM PDT 24
Finished Jun 22 05:18:08 PM PDT 24
Peak memory 225572 kb
Host smart-8b7eeab0-cb7a-4360-958f-26336437b947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465704019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2465704019
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.814455485
Short name T827
Test name
Test status
Simulation time 72619928 ps
CPU time 0.8 seconds
Started Jun 22 05:17:52 PM PDT 24
Finished Jun 22 05:17:54 PM PDT 24
Peak memory 206456 kb
Host smart-f233cb03-28b8-4bee-99d4-6a49bc104e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814455485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.814455485
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1937130946
Short name T284
Test name
Test status
Simulation time 4521617402 ps
CPU time 78.11 seconds
Started Jun 22 05:18:08 PM PDT 24
Finished Jun 22 05:19:27 PM PDT 24
Peak memory 263856 kb
Host smart-3c1da393-312c-4f5f-862b-a8c07af10245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937130946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1937130946
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3700246175
Short name T617
Test name
Test status
Simulation time 2694268531 ps
CPU time 31.8 seconds
Started Jun 22 05:18:05 PM PDT 24
Finished Jun 22 05:18:38 PM PDT 24
Peak memory 232752 kb
Host smart-a8f81e0f-b58a-4070-993a-f72733608a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700246175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3700246175
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_intercept.900347149
Short name T471
Test name
Test status
Simulation time 638910088 ps
CPU time 8.36 seconds
Started Jun 22 05:17:57 PM PDT 24
Finished Jun 22 05:18:06 PM PDT 24
Peak memory 225508 kb
Host smart-58d254cf-7aa1-4847-96d6-21174177c80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900347149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.900347149
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4213949195
Short name T823
Test name
Test status
Simulation time 88930671 ps
CPU time 2.53 seconds
Started Jun 22 05:18:00 PM PDT 24
Finished Jun 22 05:18:03 PM PDT 24
Peak memory 233456 kb
Host smart-1142aea2-eefe-4828-b3f8-095f95eaea36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213949195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4213949195
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1020193991
Short name T556
Test name
Test status
Simulation time 16860199 ps
CPU time 1.1 seconds
Started Jun 22 05:17:57 PM PDT 24
Finished Jun 22 05:17:59 PM PDT 24
Peak memory 217616 kb
Host smart-8bd6095c-3e4f-4ef1-83b5-fde7f51b6a78
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020193991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1020193991
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.363042104
Short name T270
Test name
Test status
Simulation time 19921616647 ps
CPU time 6.68 seconds
Started Jun 22 05:17:55 PM PDT 24
Finished Jun 22 05:18:02 PM PDT 24
Peak memory 225716 kb
Host smart-a2ec1bf6-5951-4bc9-b799-bf8ef5158e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363042104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
363042104
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3084197661
Short name T630
Test name
Test status
Simulation time 494875573 ps
CPU time 3.76 seconds
Started Jun 22 05:18:00 PM PDT 24
Finished Jun 22 05:18:04 PM PDT 24
Peak memory 233932 kb
Host smart-edf83ba0-010d-4b9a-86eb-b2ce3d9126ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084197661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3084197661
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2768771151
Short name T774
Test name
Test status
Simulation time 16385401538 ps
CPU time 18.97 seconds
Started Jun 22 05:17:59 PM PDT 24
Finished Jun 22 05:18:19 PM PDT 24
Peak memory 221024 kb
Host smart-56f22955-36e3-4708-8677-4f94d19ca4e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2768771151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2768771151
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2418522435
Short name T65
Test name
Test status
Simulation time 35695016 ps
CPU time 1.05 seconds
Started Jun 22 05:17:59 PM PDT 24
Finished Jun 22 05:18:01 PM PDT 24
Peak memory 235844 kb
Host smart-1a81022d-79c4-4352-a1bd-bf8c319451c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418522435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2418522435
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2291746462
Short name T644
Test name
Test status
Simulation time 5046244294 ps
CPU time 14.9 seconds
Started Jun 22 05:17:51 PM PDT 24
Finished Jun 22 05:18:06 PM PDT 24
Peak memory 217724 kb
Host smart-97187167-d702-459e-9f87-08f86fc1a56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291746462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2291746462
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1910489690
Short name T334
Test name
Test status
Simulation time 32544533 ps
CPU time 0.73 seconds
Started Jun 22 05:17:48 PM PDT 24
Finished Jun 22 05:17:50 PM PDT 24
Peak memory 206596 kb
Host smart-02f40013-d728-40be-8ff7-f8b6d8c1435b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910489690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1910489690
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3772853855
Short name T768
Test name
Test status
Simulation time 439643417 ps
CPU time 2.09 seconds
Started Jun 22 05:17:48 PM PDT 24
Finished Jun 22 05:17:50 PM PDT 24
Peak memory 217380 kb
Host smart-230818df-3438-46da-b6d8-473da5214083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772853855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3772853855
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.4203497520
Short name T954
Test name
Test status
Simulation time 46393807 ps
CPU time 0.74 seconds
Started Jun 22 05:17:43 PM PDT 24
Finished Jun 22 05:17:44 PM PDT 24
Peak memory 206880 kb
Host smart-a879c21f-5455-4404-97bc-c49e242a8177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203497520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.4203497520
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1834476641
Short name T587
Test name
Test status
Simulation time 4360126426 ps
CPU time 10.62 seconds
Started Jun 22 05:17:49 PM PDT 24
Finished Jun 22 05:18:00 PM PDT 24
Peak memory 225624 kb
Host smart-14884992-d65c-4215-a522-ea502d452896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834476641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1834476641
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3254110179
Short name T563
Test name
Test status
Simulation time 15305326 ps
CPU time 0.73 seconds
Started Jun 22 05:19:45 PM PDT 24
Finished Jun 22 05:19:48 PM PDT 24
Peak memory 206608 kb
Host smart-b0175152-e833-4271-9ca6-b2a7cc84f1a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254110179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3254110179
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.4119120010
Short name T239
Test name
Test status
Simulation time 57081038 ps
CPU time 2.16 seconds
Started Jun 22 05:19:43 PM PDT 24
Finished Jun 22 05:19:46 PM PDT 24
Peak memory 225540 kb
Host smart-5ac27628-c306-4c12-8c40-c8e98714edef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119120010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.4119120010
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1776197913
Short name T847
Test name
Test status
Simulation time 222244320 ps
CPU time 0.81 seconds
Started Jun 22 05:19:40 PM PDT 24
Finished Jun 22 05:19:41 PM PDT 24
Peak memory 207504 kb
Host smart-31257be3-0141-4fb4-9034-e26295cdac1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776197913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1776197913
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1448173454
Short name T845
Test name
Test status
Simulation time 3995405149 ps
CPU time 30.6 seconds
Started Jun 22 05:19:44 PM PDT 24
Finished Jun 22 05:20:17 PM PDT 24
Peak memory 235756 kb
Host smart-8a48900a-da22-4325-abf2-13ca2bcd6a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448173454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1448173454
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1459769145
Short name T970
Test name
Test status
Simulation time 35568901852 ps
CPU time 207.61 seconds
Started Jun 22 05:19:46 PM PDT 24
Finished Jun 22 05:23:15 PM PDT 24
Peak memory 258480 kb
Host smart-4b7e4f3e-c69f-4331-9bd2-effed5951f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459769145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1459769145
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.537263310
Short name T489
Test name
Test status
Simulation time 20099940404 ps
CPU time 29.8 seconds
Started Jun 22 05:19:53 PM PDT 24
Finished Jun 22 05:20:24 PM PDT 24
Peak memory 241696 kb
Host smart-f9f96cdd-4075-45c4-8c7f-656d9f0b22e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537263310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.537263310
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.467518830
Short name T305
Test name
Test status
Simulation time 1479516925 ps
CPU time 21.94 seconds
Started Jun 22 05:19:42 PM PDT 24
Finished Jun 22 05:20:06 PM PDT 24
Peak memory 225524 kb
Host smart-be3570a4-66fb-4d49-a271-a1ece7b5661f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467518830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.467518830
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1880760778
Short name T675
Test name
Test status
Simulation time 555614543 ps
CPU time 4.18 seconds
Started Jun 22 05:19:44 PM PDT 24
Finished Jun 22 05:19:50 PM PDT 24
Peak memory 220656 kb
Host smart-e06dfe28-3b62-4a65-9fb3-31e436c47590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880760778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1880760778
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3437239793
Short name T734
Test name
Test status
Simulation time 2067563929 ps
CPU time 21.87 seconds
Started Jun 22 05:19:43 PM PDT 24
Finished Jun 22 05:20:07 PM PDT 24
Peak memory 233724 kb
Host smart-2bbec3cc-fea1-4970-b980-5a98fed51365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437239793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3437239793
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.4205737248
Short name T858
Test name
Test status
Simulation time 8299367058 ps
CPU time 23.57 seconds
Started Jun 22 05:19:39 PM PDT 24
Finished Jun 22 05:20:04 PM PDT 24
Peak memory 233888 kb
Host smart-49bb110a-887a-421b-bce4-44c5c6bf10c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205737248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.4205737248
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1286826360
Short name T549
Test name
Test status
Simulation time 623090584 ps
CPU time 5.17 seconds
Started Jun 22 05:19:47 PM PDT 24
Finished Jun 22 05:19:53 PM PDT 24
Peak memory 225548 kb
Host smart-ace3d4e7-6386-4715-ad52-6414bcd58917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286826360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1286826360
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1364078637
Short name T3
Test name
Test status
Simulation time 234390831 ps
CPU time 4.18 seconds
Started Jun 22 05:19:50 PM PDT 24
Finished Jun 22 05:19:55 PM PDT 24
Peak memory 220136 kb
Host smart-11563f6d-17af-4f94-b41d-f340421e66f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1364078637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1364078637
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1458773338
Short name T677
Test name
Test status
Simulation time 172139425573 ps
CPU time 629.44 seconds
Started Jun 22 05:19:44 PM PDT 24
Finished Jun 22 05:30:15 PM PDT 24
Peak memory 273836 kb
Host smart-7f7c1c90-4f5c-4663-bf51-b865652fcabb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458773338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1458773338
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2602646007
Short name T507
Test name
Test status
Simulation time 6826540589 ps
CPU time 16.71 seconds
Started Jun 22 05:19:46 PM PDT 24
Finished Jun 22 05:20:04 PM PDT 24
Peak memory 217588 kb
Host smart-02f58123-9259-4084-a172-4a3fb85039c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602646007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2602646007
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3326147816
Short name T481
Test name
Test status
Simulation time 718874963 ps
CPU time 3.46 seconds
Started Jun 22 05:19:47 PM PDT 24
Finished Jun 22 05:19:52 PM PDT 24
Peak memory 217324 kb
Host smart-cbf4786d-4263-4918-8223-aafe8b4cbe05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326147816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3326147816
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.544877469
Short name T921
Test name
Test status
Simulation time 13852602 ps
CPU time 0.69 seconds
Started Jun 22 05:19:40 PM PDT 24
Finished Jun 22 05:19:42 PM PDT 24
Peak memory 206428 kb
Host smart-8ba3fa76-05b4-4bdc-a674-577a266eda7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544877469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.544877469
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1521605358
Short name T368
Test name
Test status
Simulation time 154413148 ps
CPU time 0.93 seconds
Started Jun 22 05:19:43 PM PDT 24
Finished Jun 22 05:19:46 PM PDT 24
Peak memory 207912 kb
Host smart-d6ed95b1-7dd4-4a57-a04f-7913848c2620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521605358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1521605358
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1525521906
Short name T209
Test name
Test status
Simulation time 4375017740 ps
CPU time 14.66 seconds
Started Jun 22 05:19:44 PM PDT 24
Finished Jun 22 05:20:01 PM PDT 24
Peak memory 233820 kb
Host smart-22b002a6-5bc0-400f-8149-1ec180d61ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525521906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1525521906
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3308220966
Short name T901
Test name
Test status
Simulation time 89537445 ps
CPU time 0.78 seconds
Started Jun 22 05:19:46 PM PDT 24
Finished Jun 22 05:19:48 PM PDT 24
Peak memory 206264 kb
Host smart-c4f4838c-1a1f-49eb-971b-5511de5dee41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308220966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3308220966
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.836560107
Short name T800
Test name
Test status
Simulation time 35375561 ps
CPU time 2.22 seconds
Started Jun 22 05:19:44 PM PDT 24
Finished Jun 22 05:19:48 PM PDT 24
Peak memory 225568 kb
Host smart-d7d07e47-b960-40a8-86fe-71343d04eff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836560107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.836560107
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1885908873
Short name T742
Test name
Test status
Simulation time 15487029 ps
CPU time 0.77 seconds
Started Jun 22 05:19:47 PM PDT 24
Finished Jun 22 05:19:49 PM PDT 24
Peak memory 206768 kb
Host smart-26633f17-7418-4063-85a1-ef93c21a6ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885908873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1885908873
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3784332141
Short name T156
Test name
Test status
Simulation time 42099622167 ps
CPU time 59.24 seconds
Started Jun 22 05:19:45 PM PDT 24
Finished Jun 22 05:20:46 PM PDT 24
Peak memory 237884 kb
Host smart-55e603c7-f989-482b-9ba4-9ce7f92e1154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784332141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3784332141
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.245023535
Short name T26
Test name
Test status
Simulation time 108302739540 ps
CPU time 438.22 seconds
Started Jun 22 05:19:43 PM PDT 24
Finished Jun 22 05:27:03 PM PDT 24
Peak memory 257740 kb
Host smart-ab7d4886-fa50-45ab-977a-716baf5e1bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245023535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.245023535
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2702771736
Short name T788
Test name
Test status
Simulation time 3058448976 ps
CPU time 19.2 seconds
Started Jun 22 05:19:42 PM PDT 24
Finished Jun 22 05:20:03 PM PDT 24
Peak memory 237524 kb
Host smart-3cab7789-e04f-496a-a691-4e200459ee9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702771736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2702771736
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2212648110
Short name T802
Test name
Test status
Simulation time 1279955627 ps
CPU time 5.71 seconds
Started Jun 22 05:19:50 PM PDT 24
Finished Jun 22 05:19:56 PM PDT 24
Peak memory 225484 kb
Host smart-ad4e3335-b799-4719-ba63-867aae074148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212648110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2212648110
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2414698904
Short name T216
Test name
Test status
Simulation time 439957466 ps
CPU time 2.33 seconds
Started Jun 22 05:19:47 PM PDT 24
Finished Jun 22 05:19:50 PM PDT 24
Peak memory 225520 kb
Host smart-4c1b4c22-964b-4720-9677-f5d971571545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414698904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2414698904
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3935779449
Short name T274
Test name
Test status
Simulation time 717529809 ps
CPU time 20.75 seconds
Started Jun 22 05:19:47 PM PDT 24
Finished Jun 22 05:20:09 PM PDT 24
Peak memory 238112 kb
Host smart-1eff2c5e-5640-4c0a-a25b-341caca74f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935779449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3935779449
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2749925609
Short name T50
Test name
Test status
Simulation time 2038946562 ps
CPU time 8.9 seconds
Started Jun 22 05:19:39 PM PDT 24
Finished Jun 22 05:19:49 PM PDT 24
Peak memory 233672 kb
Host smart-7ff7c6fd-e4b8-4375-b01c-e549fbfb8d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749925609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2749925609
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2198126277
Short name T676
Test name
Test status
Simulation time 3934514414 ps
CPU time 6.38 seconds
Started Jun 22 05:19:41 PM PDT 24
Finished Jun 22 05:19:48 PM PDT 24
Peak memory 225688 kb
Host smart-94c3ff92-2074-4855-af0d-b23d64d07ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198126277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2198126277
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1179196416
Short name T654
Test name
Test status
Simulation time 644779273 ps
CPU time 5.69 seconds
Started Jun 22 05:19:44 PM PDT 24
Finished Jun 22 05:19:52 PM PDT 24
Peak memory 224308 kb
Host smart-012c5b8c-a40b-4d15-b469-904de67319d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1179196416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1179196416
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1355955592
Short name T463
Test name
Test status
Simulation time 5122993846 ps
CPU time 7.7 seconds
Started Jun 22 05:19:44 PM PDT 24
Finished Jun 22 05:19:54 PM PDT 24
Peak memory 217344 kb
Host smart-3b55243a-775e-4753-a9af-c7189afaf85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355955592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1355955592
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3917147925
Short name T391
Test name
Test status
Simulation time 1708086738 ps
CPU time 4.87 seconds
Started Jun 22 05:19:40 PM PDT 24
Finished Jun 22 05:19:45 PM PDT 24
Peak memory 217280 kb
Host smart-122deca8-e001-4f91-86b4-49ddf762810f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917147925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3917147925
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3512470406
Short name T611
Test name
Test status
Simulation time 11104885 ps
CPU time 0.76 seconds
Started Jun 22 05:19:53 PM PDT 24
Finished Jun 22 05:19:55 PM PDT 24
Peak memory 206780 kb
Host smart-1f895fcc-5a3a-40ea-8b5a-d6ca913c36c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512470406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3512470406
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2437270284
Short name T878
Test name
Test status
Simulation time 171378913 ps
CPU time 0.88 seconds
Started Jun 22 05:19:39 PM PDT 24
Finished Jun 22 05:19:41 PM PDT 24
Peak memory 206868 kb
Host smart-591c7e58-5d27-4b73-b58a-4fa5c7df5c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437270284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2437270284
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2395276211
Short name T433
Test name
Test status
Simulation time 222424085 ps
CPU time 2.37 seconds
Started Jun 22 05:19:45 PM PDT 24
Finished Jun 22 05:19:49 PM PDT 24
Peak memory 224572 kb
Host smart-4ff431bd-bec5-4ba6-9120-1b19c034d6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395276211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2395276211
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.657339106
Short name T372
Test name
Test status
Simulation time 40175794 ps
CPU time 0.71 seconds
Started Jun 22 05:19:47 PM PDT 24
Finished Jun 22 05:19:50 PM PDT 24
Peak memory 206272 kb
Host smart-2fcb332b-8ca1-4715-bf5b-34649c45560a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657339106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.657339106
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3076501432
Short name T614
Test name
Test status
Simulation time 210707710 ps
CPU time 2.81 seconds
Started Jun 22 05:19:53 PM PDT 24
Finished Jun 22 05:19:57 PM PDT 24
Peak memory 225524 kb
Host smart-c4738b88-9e98-4a57-8ff5-c7cccc235039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076501432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3076501432
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3509513132
Short name T911
Test name
Test status
Simulation time 12709876 ps
CPU time 0.75 seconds
Started Jun 22 05:19:51 PM PDT 24
Finished Jun 22 05:19:52 PM PDT 24
Peak memory 206760 kb
Host smart-b067378a-0fae-4dfe-ba03-8a6eb21c4f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509513132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3509513132
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.24701116
Short name T299
Test name
Test status
Simulation time 13623167681 ps
CPU time 85.04 seconds
Started Jun 22 05:19:45 PM PDT 24
Finished Jun 22 05:21:12 PM PDT 24
Peak memory 258456 kb
Host smart-4a269d2f-9de4-4a71-b30e-2c40c124fa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24701116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.24701116
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3866370861
Short name T131
Test name
Test status
Simulation time 54785714562 ps
CPU time 88.45 seconds
Started Jun 22 05:19:55 PM PDT 24
Finished Jun 22 05:21:24 PM PDT 24
Peak memory 254672 kb
Host smart-698a5a12-7268-45cb-b840-fa821014dcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866370861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3866370861
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3315172141
Short name T546
Test name
Test status
Simulation time 17548637169 ps
CPU time 71.34 seconds
Started Jun 22 05:19:48 PM PDT 24
Finished Jun 22 05:21:01 PM PDT 24
Peak memory 251568 kb
Host smart-08b3b1b3-150e-4803-8084-fe794cfbdbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315172141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3315172141
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3404431134
Short name T82
Test name
Test status
Simulation time 193667546 ps
CPU time 4.46 seconds
Started Jun 22 05:19:57 PM PDT 24
Finished Jun 22 05:20:02 PM PDT 24
Peak memory 225568 kb
Host smart-a8d2f852-c89f-4f88-b80d-246357d017ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404431134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3404431134
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.4293845001
Short name T548
Test name
Test status
Simulation time 2453810636 ps
CPU time 7.09 seconds
Started Jun 22 05:19:45 PM PDT 24
Finished Jun 22 05:19:54 PM PDT 24
Peak memory 225708 kb
Host smart-3f029ebe-4d39-4298-be6b-d8b1d9daf617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293845001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.4293845001
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.484575591
Short name T764
Test name
Test status
Simulation time 37476242985 ps
CPU time 55.93 seconds
Started Jun 22 05:19:50 PM PDT 24
Finished Jun 22 05:20:47 PM PDT 24
Peak memory 242068 kb
Host smart-082bb792-940b-4b01-b8c3-f465eba29b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484575591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.484575591
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.4213334983
Short name T264
Test name
Test status
Simulation time 13417494063 ps
CPU time 19.9 seconds
Started Jun 22 05:19:58 PM PDT 24
Finished Jun 22 05:20:18 PM PDT 24
Peak memory 233856 kb
Host smart-2b689c92-634d-4445-aa9e-bd0e30093cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213334983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.4213334983
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3853562128
Short name T255
Test name
Test status
Simulation time 3930796967 ps
CPU time 10.93 seconds
Started Jun 22 05:19:54 PM PDT 24
Finished Jun 22 05:20:06 PM PDT 24
Peak memory 225572 kb
Host smart-ba08673e-c2a0-4ddb-a98c-5133694fd81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853562128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3853562128
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1237803049
Short name T956
Test name
Test status
Simulation time 151417102 ps
CPU time 3.65 seconds
Started Jun 22 05:19:48 PM PDT 24
Finished Jun 22 05:19:53 PM PDT 24
Peak memory 221612 kb
Host smart-bd3339a7-d946-49a9-b4e8-fd7de7ce3676
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1237803049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1237803049
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2156519508
Short name T557
Test name
Test status
Simulation time 3304835800 ps
CPU time 21.09 seconds
Started Jun 22 05:19:49 PM PDT 24
Finished Jun 22 05:20:11 PM PDT 24
Peak memory 217664 kb
Host smart-22ad52f7-bb7c-4b5e-8910-364b9711b4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156519508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2156519508
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2122053938
Short name T601
Test name
Test status
Simulation time 19120876619 ps
CPU time 10.66 seconds
Started Jun 22 05:19:55 PM PDT 24
Finished Jun 22 05:20:06 PM PDT 24
Peak memory 217504 kb
Host smart-35685280-2aa4-43f6-bc5b-913ed39d20fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122053938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2122053938
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.572005383
Short name T582
Test name
Test status
Simulation time 66896721 ps
CPU time 1.51 seconds
Started Jun 22 05:19:48 PM PDT 24
Finished Jun 22 05:19:51 PM PDT 24
Peak memory 217268 kb
Host smart-eeb80b17-7f4e-469c-8cd6-b3ce4b0040b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572005383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.572005383
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.678096350
Short name T530
Test name
Test status
Simulation time 48105532 ps
CPU time 0.95 seconds
Started Jun 22 05:19:54 PM PDT 24
Finished Jun 22 05:19:55 PM PDT 24
Peak memory 206884 kb
Host smart-2d834e80-8f21-4d59-a4a6-7e1dac8ca773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678096350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.678096350
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3252886610
Short name T598
Test name
Test status
Simulation time 19287506987 ps
CPU time 15.94 seconds
Started Jun 22 05:19:45 PM PDT 24
Finished Jun 22 05:20:03 PM PDT 24
Peak memory 225684 kb
Host smart-2f98e916-eb97-48f9-965d-5915af247bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252886610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3252886610
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.582493636
Short name T736
Test name
Test status
Simulation time 195353274 ps
CPU time 0.73 seconds
Started Jun 22 05:19:48 PM PDT 24
Finished Jun 22 05:19:50 PM PDT 24
Peak memory 206272 kb
Host smart-302c9f21-29c5-4a69-8ddc-a95939368db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582493636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.582493636
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.396192180
Short name T761
Test name
Test status
Simulation time 911117626 ps
CPU time 6.45 seconds
Started Jun 22 05:19:53 PM PDT 24
Finished Jun 22 05:20:00 PM PDT 24
Peak memory 233680 kb
Host smart-2f66c21e-cce0-451c-ac36-c66e53dc1a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396192180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.396192180
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.643017625
Short name T515
Test name
Test status
Simulation time 21349688 ps
CPU time 0.83 seconds
Started Jun 22 05:19:48 PM PDT 24
Finished Jun 22 05:19:50 PM PDT 24
Peak memory 207516 kb
Host smart-402723d7-a885-4a13-b7e7-b5e77b6d6bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643017625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.643017625
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3683273314
Short name T537
Test name
Test status
Simulation time 22118841745 ps
CPU time 28.93 seconds
Started Jun 22 05:19:56 PM PDT 24
Finished Jun 22 05:20:26 PM PDT 24
Peak memory 238620 kb
Host smart-6a373bfa-bdb3-429e-890d-c537dd893c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683273314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3683273314
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.838936708
Short name T197
Test name
Test status
Simulation time 118479480112 ps
CPU time 281.83 seconds
Started Jun 22 05:19:51 PM PDT 24
Finished Jun 22 05:24:33 PM PDT 24
Peak memory 258488 kb
Host smart-918afb9f-a0de-401f-bf8a-098816babff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838936708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.838936708
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2193012696
Short name T848
Test name
Test status
Simulation time 12002095922 ps
CPU time 135.7 seconds
Started Jun 22 05:19:59 PM PDT 24
Finished Jun 22 05:22:15 PM PDT 24
Peak memory 256952 kb
Host smart-3a8f404a-80fd-4424-a60c-87e4e64d723d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193012696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2193012696
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3382025702
Short name T122
Test name
Test status
Simulation time 1298859590 ps
CPU time 12.9 seconds
Started Jun 22 05:19:56 PM PDT 24
Finished Jun 22 05:20:09 PM PDT 24
Peak memory 225568 kb
Host smart-efa40d88-d029-40f1-aad2-de9329eaa209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382025702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3382025702
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.4190988940
Short name T213
Test name
Test status
Simulation time 4182294885 ps
CPU time 13.58 seconds
Started Jun 22 05:19:49 PM PDT 24
Finished Jun 22 05:20:04 PM PDT 24
Peak memory 233904 kb
Host smart-968c3628-2b88-4504-97d8-34c55ba32564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190988940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.4190988940
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3034274185
Short name T258
Test name
Test status
Simulation time 21476093209 ps
CPU time 35.11 seconds
Started Jun 22 05:19:51 PM PDT 24
Finished Jun 22 05:20:26 PM PDT 24
Peak memory 257940 kb
Host smart-69df7fa9-742e-4c24-9ad5-f7b6d6e16b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034274185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3034274185
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2430532741
Short name T472
Test name
Test status
Simulation time 689465923 ps
CPU time 3.75 seconds
Started Jun 22 05:19:47 PM PDT 24
Finished Jun 22 05:19:53 PM PDT 24
Peak memory 225460 kb
Host smart-e4320c20-38b5-4fa0-a6ce-93c815c9ecf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430532741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2430532741
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3900818943
Short name T244
Test name
Test status
Simulation time 1646002631 ps
CPU time 7.32 seconds
Started Jun 22 05:19:49 PM PDT 24
Finished Jun 22 05:19:57 PM PDT 24
Peak memory 233752 kb
Host smart-7f4d15bc-037c-460c-b9e4-38410b8ad181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900818943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3900818943
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.746038154
Short name T137
Test name
Test status
Simulation time 290364170 ps
CPU time 3.37 seconds
Started Jun 22 05:19:53 PM PDT 24
Finished Jun 22 05:19:57 PM PDT 24
Peak memory 219836 kb
Host smart-4ffab8f5-0b5d-4ca0-83a5-e4c726fe031f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=746038154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.746038154
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.568554915
Short name T145
Test name
Test status
Simulation time 34551032927 ps
CPU time 78.9 seconds
Started Jun 22 05:19:53 PM PDT 24
Finished Jun 22 05:21:12 PM PDT 24
Peak memory 250352 kb
Host smart-d6e9811c-19ad-46de-bb0f-9e5181448761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568554915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.568554915
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1897987738
Short name T311
Test name
Test status
Simulation time 9715821856 ps
CPU time 10.87 seconds
Started Jun 22 05:19:47 PM PDT 24
Finished Jun 22 05:19:59 PM PDT 24
Peak memory 217552 kb
Host smart-bb671e9f-c032-443d-8eea-7e18d0560425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897987738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1897987738
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1493397400
Short name T928
Test name
Test status
Simulation time 745244149 ps
CPU time 5.93 seconds
Started Jun 22 05:19:48 PM PDT 24
Finished Jun 22 05:19:55 PM PDT 24
Peak memory 217348 kb
Host smart-00314f71-6f89-49fd-997b-06a4fd308fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493397400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1493397400
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2762723930
Short name T765
Test name
Test status
Simulation time 45961287 ps
CPU time 0.79 seconds
Started Jun 22 05:19:50 PM PDT 24
Finished Jun 22 05:19:51 PM PDT 24
Peak memory 206884 kb
Host smart-c1d06613-9bdc-4e75-9c2e-63e223afba82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762723930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2762723930
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.337803045
Short name T448
Test name
Test status
Simulation time 52189001 ps
CPU time 0.79 seconds
Started Jun 22 05:19:55 PM PDT 24
Finished Jun 22 05:19:56 PM PDT 24
Peak memory 206856 kb
Host smart-2952d9ce-a036-4584-a653-2fde3c68aa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337803045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.337803045
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.295060556
Short name T785
Test name
Test status
Simulation time 6872960496 ps
CPU time 15.53 seconds
Started Jun 22 05:19:54 PM PDT 24
Finished Jun 22 05:20:10 PM PDT 24
Peak memory 233884 kb
Host smart-e6a84246-05fe-488e-a127-851cab374e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295060556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.295060556
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3323555641
Short name T509
Test name
Test status
Simulation time 13643782 ps
CPU time 0.74 seconds
Started Jun 22 05:20:05 PM PDT 24
Finished Jun 22 05:20:06 PM PDT 24
Peak memory 206640 kb
Host smart-41226ee1-d102-4661-a992-1b66b9c06e33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323555641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3323555641
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3376556012
Short name T56
Test name
Test status
Simulation time 1078421744 ps
CPU time 12.19 seconds
Started Jun 22 05:19:55 PM PDT 24
Finished Jun 22 05:20:08 PM PDT 24
Peak memory 225564 kb
Host smart-2153839d-2967-42b3-9ce3-e943a126ff61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376556012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3376556012
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1929342494
Short name T662
Test name
Test status
Simulation time 115788570 ps
CPU time 0.73 seconds
Started Jun 22 05:19:54 PM PDT 24
Finished Jun 22 05:19:56 PM PDT 24
Peak memory 206464 kb
Host smart-c4c34eae-a87b-4d3c-ac90-dec6201ca914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929342494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1929342494
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2154978034
Short name T905
Test name
Test status
Simulation time 34081426 ps
CPU time 0.79 seconds
Started Jun 22 05:19:56 PM PDT 24
Finished Jun 22 05:19:58 PM PDT 24
Peak memory 216808 kb
Host smart-632f3c91-9733-4832-87f3-b2efac9a7447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154978034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2154978034
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3399528028
Short name T11
Test name
Test status
Simulation time 1543051277 ps
CPU time 18.76 seconds
Started Jun 22 05:19:54 PM PDT 24
Finished Jun 22 05:20:14 PM PDT 24
Peak memory 242004 kb
Host smart-42b91264-d2a1-4788-b8b4-36ddd69b2831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399528028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3399528028
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.266756855
Short name T293
Test name
Test status
Simulation time 27227973905 ps
CPU time 193.38 seconds
Started Jun 22 05:19:53 PM PDT 24
Finished Jun 22 05:23:07 PM PDT 24
Peak memory 257436 kb
Host smart-771163c9-f1ef-424e-b2d6-e0bddabc18fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266756855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.266756855
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1830051683
Short name T71
Test name
Test status
Simulation time 417253809 ps
CPU time 5.89 seconds
Started Jun 22 05:19:54 PM PDT 24
Finished Jun 22 05:20:00 PM PDT 24
Peak memory 225580 kb
Host smart-94237f9b-25f9-428f-9615-34c5bfe538cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830051683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1830051683
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.39898710
Short name T731
Test name
Test status
Simulation time 4146567343 ps
CPU time 8.27 seconds
Started Jun 22 05:19:56 PM PDT 24
Finished Jun 22 05:20:05 PM PDT 24
Peak memory 233860 kb
Host smart-3042cd42-f6c5-4030-9ac9-750aae893fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39898710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.39898710
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2265302740
Short name T907
Test name
Test status
Simulation time 21543121056 ps
CPU time 40.97 seconds
Started Jun 22 05:19:56 PM PDT 24
Finished Jun 22 05:20:37 PM PDT 24
Peak memory 241632 kb
Host smart-4793d491-2b07-433c-859f-0ab9b1f2c87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265302740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2265302740
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1167334144
Short name T402
Test name
Test status
Simulation time 68820579 ps
CPU time 2.17 seconds
Started Jun 22 05:19:59 PM PDT 24
Finished Jun 22 05:20:01 PM PDT 24
Peak memory 233536 kb
Host smart-49620df8-5730-49d6-9a8f-4a82a3521e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167334144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1167334144
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.296444201
Short name T189
Test name
Test status
Simulation time 7862739337 ps
CPU time 16.04 seconds
Started Jun 22 05:19:55 PM PDT 24
Finished Jun 22 05:20:12 PM PDT 24
Peak memory 233856 kb
Host smart-f55e2520-65a0-431a-a192-a7b2ce86885a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296444201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.296444201
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2985727319
Short name T859
Test name
Test status
Simulation time 1454148888 ps
CPU time 9.14 seconds
Started Jun 22 05:20:00 PM PDT 24
Finished Jun 22 05:20:09 PM PDT 24
Peak memory 220152 kb
Host smart-c03794ee-6d48-48bc-8431-7dd98afcbd1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2985727319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2985727319
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3527405960
Short name T912
Test name
Test status
Simulation time 2312504952 ps
CPU time 24.11 seconds
Started Jun 22 05:19:58 PM PDT 24
Finished Jun 22 05:20:23 PM PDT 24
Peak memory 220672 kb
Host smart-0e485b2f-87b3-471a-80fa-afb92b51a4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527405960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3527405960
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.540424461
Short name T569
Test name
Test status
Simulation time 955779516 ps
CPU time 4.5 seconds
Started Jun 22 05:19:54 PM PDT 24
Finished Jun 22 05:19:59 PM PDT 24
Peak memory 217284 kb
Host smart-ff027634-ed1c-4116-9ed5-70f4ef1e6ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540424461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.540424461
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2729887836
Short name T732
Test name
Test status
Simulation time 45510659 ps
CPU time 1.04 seconds
Started Jun 22 05:19:53 PM PDT 24
Finished Jun 22 05:19:55 PM PDT 24
Peak memory 208932 kb
Host smart-f2d956d5-4575-4949-9b1a-5bf3f995f261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729887836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2729887836
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2923424554
Short name T842
Test name
Test status
Simulation time 10893080 ps
CPU time 0.69 seconds
Started Jun 22 05:19:58 PM PDT 24
Finished Jun 22 05:19:59 PM PDT 24
Peak memory 206748 kb
Host smart-e2564568-0b29-443b-a87c-bc95af590a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923424554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2923424554
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.290405217
Short name T248
Test name
Test status
Simulation time 37632222431 ps
CPU time 20.15 seconds
Started Jun 22 05:20:00 PM PDT 24
Finished Jun 22 05:20:21 PM PDT 24
Peak memory 225620 kb
Host smart-32aedc6b-dbd3-4816-a886-dd63cf68e673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290405217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.290405217
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2437391419
Short name T719
Test name
Test status
Simulation time 31834663 ps
CPU time 0.77 seconds
Started Jun 22 05:20:00 PM PDT 24
Finished Jun 22 05:20:01 PM PDT 24
Peak memory 205720 kb
Host smart-eb1a6736-a8f1-4c01-9d29-419bb1ab82f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437391419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2437391419
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3671562063
Short name T526
Test name
Test status
Simulation time 549398667 ps
CPU time 5.58 seconds
Started Jun 22 05:20:01 PM PDT 24
Finished Jun 22 05:20:07 PM PDT 24
Peak memory 225452 kb
Host smart-f45c918c-43d5-4613-b10f-62038dc8e6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671562063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3671562063
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.449368609
Short name T320
Test name
Test status
Simulation time 37620553 ps
CPU time 0.83 seconds
Started Jun 22 05:20:03 PM PDT 24
Finished Jun 22 05:20:05 PM PDT 24
Peak memory 207828 kb
Host smart-b0d2de12-20f6-4bff-8f30-3b7c1fa7c15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449368609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.449368609
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2655064638
Short name T370
Test name
Test status
Simulation time 13678423481 ps
CPU time 114.66 seconds
Started Jun 22 05:20:00 PM PDT 24
Finished Jun 22 05:21:55 PM PDT 24
Peak memory 255800 kb
Host smart-d80c1b33-f1bb-45b7-bb36-ad409aac7bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655064638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2655064638
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.4107465472
Short name T482
Test name
Test status
Simulation time 8128747356 ps
CPU time 32.71 seconds
Started Jun 22 05:20:06 PM PDT 24
Finished Jun 22 05:20:39 PM PDT 24
Peak memory 250148 kb
Host smart-b54a5457-c8b7-42d3-a048-30813b5c8187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107465472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.4107465472
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3971332183
Short name T195
Test name
Test status
Simulation time 3280185366 ps
CPU time 43.52 seconds
Started Jun 22 05:20:11 PM PDT 24
Finished Jun 22 05:20:56 PM PDT 24
Peak memory 251988 kb
Host smart-5f7e1d80-b28a-4191-941d-c959cbd928bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971332183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3971332183
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2612818744
Short name T755
Test name
Test status
Simulation time 243024186 ps
CPU time 7.03 seconds
Started Jun 22 05:20:05 PM PDT 24
Finished Jun 22 05:20:13 PM PDT 24
Peak memory 240108 kb
Host smart-a08b365e-4092-48ac-baf7-106f5e6f46a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612818744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2612818744
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3571951074
Short name T5
Test name
Test status
Simulation time 1653306202 ps
CPU time 4.54 seconds
Started Jun 22 05:20:00 PM PDT 24
Finished Jun 22 05:20:06 PM PDT 24
Peak memory 225512 kb
Host smart-c6858456-85f0-4d71-bdf3-e64811841dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571951074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3571951074
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3568585712
Short name T612
Test name
Test status
Simulation time 685423458 ps
CPU time 6.21 seconds
Started Jun 22 05:20:02 PM PDT 24
Finished Jun 22 05:20:09 PM PDT 24
Peak memory 219764 kb
Host smart-568213ce-3524-40fd-8a34-a20f6d2b6608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568585712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3568585712
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2824692277
Short name T178
Test name
Test status
Simulation time 9712740531 ps
CPU time 11.66 seconds
Started Jun 22 05:20:01 PM PDT 24
Finished Jun 22 05:20:13 PM PDT 24
Peak memory 225676 kb
Host smart-15f90cd0-888b-4a6d-83bc-9a9faabdb1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824692277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2824692277
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.169936616
Short name T225
Test name
Test status
Simulation time 3783880423 ps
CPU time 9.98 seconds
Started Jun 22 05:20:00 PM PDT 24
Finished Jun 22 05:20:11 PM PDT 24
Peak memory 241712 kb
Host smart-75f80439-4d81-4695-b8b8-27947f78f899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169936616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.169936616
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.991393268
Short name T851
Test name
Test status
Simulation time 4743345690 ps
CPU time 14.99 seconds
Started Jun 22 05:20:03 PM PDT 24
Finished Jun 22 05:20:18 PM PDT 24
Peak memory 220544 kb
Host smart-28ded6e3-be3f-4e84-90ad-85fbfdbf8c91
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=991393268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.991393268
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.32753557
Short name T291
Test name
Test status
Simulation time 127999932478 ps
CPU time 632.63 seconds
Started Jun 22 05:20:01 PM PDT 24
Finished Jun 22 05:30:34 PM PDT 24
Peak memory 285984 kb
Host smart-0fcd896c-a88f-46bb-8114-c4500891fec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32753557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress
_all.32753557
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.131945582
Short name T963
Test name
Test status
Simulation time 1143280349 ps
CPU time 2.15 seconds
Started Jun 22 05:20:08 PM PDT 24
Finished Jun 22 05:20:11 PM PDT 24
Peak memory 217484 kb
Host smart-e3ad7915-6cf1-42aa-9d25-d02da40bc1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131945582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.131945582
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.932917701
Short name T810
Test name
Test status
Simulation time 118574003 ps
CPU time 1.66 seconds
Started Jun 22 05:20:10 PM PDT 24
Finished Jun 22 05:20:14 PM PDT 24
Peak memory 208708 kb
Host smart-a0c49b1e-b2f4-4ae4-9bfc-c2cff58da803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932917701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.932917701
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1293485748
Short name T939
Test name
Test status
Simulation time 175062842 ps
CPU time 1.79 seconds
Started Jun 22 05:20:02 PM PDT 24
Finished Jun 22 05:20:04 PM PDT 24
Peak memory 217304 kb
Host smart-98314ead-ecc7-40c7-81ab-ab4902e77a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293485748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1293485748
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.188545703
Short name T520
Test name
Test status
Simulation time 246853981 ps
CPU time 1.05 seconds
Started Jun 22 05:20:10 PM PDT 24
Finished Jun 22 05:20:13 PM PDT 24
Peak memory 207808 kb
Host smart-deb629c8-d974-4367-9149-1be0196cdb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188545703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.188545703
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.507170683
Short name T237
Test name
Test status
Simulation time 2124653872 ps
CPU time 5.28 seconds
Started Jun 22 05:20:07 PM PDT 24
Finished Jun 22 05:20:13 PM PDT 24
Peak memory 233736 kb
Host smart-5bd8f28d-1829-46cb-8cfc-9f3fb579b049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507170683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.507170683
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3737140198
Short name T333
Test name
Test status
Simulation time 74391724 ps
CPU time 0.82 seconds
Started Jun 22 05:20:01 PM PDT 24
Finished Jun 22 05:20:03 PM PDT 24
Peak memory 205708 kb
Host smart-4f27c95a-54f7-445a-ade2-084f6746b120
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737140198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3737140198
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2105344887
Short name T476
Test name
Test status
Simulation time 162206426 ps
CPU time 2.83 seconds
Started Jun 22 05:20:06 PM PDT 24
Finished Jun 22 05:20:09 PM PDT 24
Peak memory 233528 kb
Host smart-6934e8be-f882-4b8e-814d-33f11eb2057f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105344887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2105344887
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1230839049
Short name T626
Test name
Test status
Simulation time 14626264 ps
CPU time 0.89 seconds
Started Jun 22 05:20:05 PM PDT 24
Finished Jun 22 05:20:06 PM PDT 24
Peak memory 207492 kb
Host smart-e6eb2663-5b57-4054-a080-dfa734bb91b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230839049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1230839049
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3487990800
Short name T475
Test name
Test status
Simulation time 45806025480 ps
CPU time 115.13 seconds
Started Jun 22 05:20:09 PM PDT 24
Finished Jun 22 05:22:05 PM PDT 24
Peak memory 253800 kb
Host smart-6bec8875-d749-4edb-83eb-f167766015a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487990800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3487990800
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3659550338
Short name T899
Test name
Test status
Simulation time 816226830 ps
CPU time 5.84 seconds
Started Jun 22 05:20:03 PM PDT 24
Finished Jun 22 05:20:10 PM PDT 24
Peak memory 218264 kb
Host smart-f7b8eebb-078f-4ef5-a8c8-8ea2d6703ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659550338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3659550338
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1220174449
Short name T804
Test name
Test status
Simulation time 15943563416 ps
CPU time 42.81 seconds
Started Jun 22 05:20:02 PM PDT 24
Finished Jun 22 05:20:46 PM PDT 24
Peak memory 225664 kb
Host smart-261c2dcb-36d9-4990-85c9-826948e756bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220174449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1220174449
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.4000815548
Short name T554
Test name
Test status
Simulation time 811740031 ps
CPU time 11.99 seconds
Started Jun 22 05:20:07 PM PDT 24
Finished Jun 22 05:20:19 PM PDT 24
Peak memory 225500 kb
Host smart-edb86501-5ebc-4b98-aae1-ba0c4fae19f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000815548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.4000815548
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2413258863
Short name T694
Test name
Test status
Simulation time 739509802 ps
CPU time 3.84 seconds
Started Jun 22 05:20:01 PM PDT 24
Finished Jun 22 05:20:06 PM PDT 24
Peak memory 233764 kb
Host smart-54805cd2-1d7c-41e1-9fd0-8479057d3ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413258863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2413258863
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2664030065
Short name T621
Test name
Test status
Simulation time 3178477855 ps
CPU time 10.4 seconds
Started Jun 22 05:20:09 PM PDT 24
Finished Jun 22 05:20:21 PM PDT 24
Peak memory 233872 kb
Host smart-e20657cc-2787-4196-a822-d34fb4c74833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664030065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2664030065
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3287331410
Short name T52
Test name
Test status
Simulation time 11359705641 ps
CPU time 18.46 seconds
Started Jun 22 05:20:00 PM PDT 24
Finished Jun 22 05:20:19 PM PDT 24
Peak memory 233884 kb
Host smart-6c7fb36a-fdc9-490f-889d-610cb44fafcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287331410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3287331410
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2077975340
Short name T343
Test name
Test status
Simulation time 256914948 ps
CPU time 5.09 seconds
Started Jun 22 05:20:04 PM PDT 24
Finished Jun 22 05:20:10 PM PDT 24
Peak memory 221288 kb
Host smart-c1e61a99-ef7f-49a7-8b7d-1a8d54d67b2b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2077975340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2077975340
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1688381117
Short name T14
Test name
Test status
Simulation time 1108245539 ps
CPU time 30.38 seconds
Started Jun 22 05:20:04 PM PDT 24
Finished Jun 22 05:20:35 PM PDT 24
Peak memory 254808 kb
Host smart-f7d1f672-ba1b-4781-a2cf-d232d9d0c91e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688381117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1688381117
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3727408343
Short name T440
Test name
Test status
Simulation time 7465857275 ps
CPU time 8.5 seconds
Started Jun 22 05:20:03 PM PDT 24
Finished Jun 22 05:20:12 PM PDT 24
Peak memory 217352 kb
Host smart-67b775d1-8094-4a95-a059-ffaea443a68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727408343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3727408343
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3624937406
Short name T699
Test name
Test status
Simulation time 889153404 ps
CPU time 7.23 seconds
Started Jun 22 05:20:08 PM PDT 24
Finished Jun 22 05:20:16 PM PDT 24
Peak memory 217296 kb
Host smart-75cc80c8-3f55-450b-9f5d-8d133bcc4659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624937406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3624937406
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1047983539
Short name T555
Test name
Test status
Simulation time 161899380 ps
CPU time 0.94 seconds
Started Jun 22 05:20:00 PM PDT 24
Finished Jun 22 05:20:02 PM PDT 24
Peak memory 207516 kb
Host smart-732ff71a-e483-4d3d-a592-f5dd88bc0056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047983539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1047983539
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3624400441
Short name T603
Test name
Test status
Simulation time 53869350 ps
CPU time 0.83 seconds
Started Jun 22 05:20:10 PM PDT 24
Finished Jun 22 05:20:13 PM PDT 24
Peak memory 206780 kb
Host smart-7386433a-5edd-408f-a520-2169b81fab03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624400441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3624400441
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2649123890
Short name T585
Test name
Test status
Simulation time 328010392 ps
CPU time 3.14 seconds
Started Jun 22 05:20:02 PM PDT 24
Finished Jun 22 05:20:06 PM PDT 24
Peak memory 225472 kb
Host smart-6241c04b-d67b-476a-90e2-ffafc991045e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649123890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2649123890
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3210592978
Short name T648
Test name
Test status
Simulation time 12988660 ps
CPU time 0.72 seconds
Started Jun 22 05:20:10 PM PDT 24
Finished Jun 22 05:20:13 PM PDT 24
Peak memory 205704 kb
Host smart-baccc994-f434-4e15-a553-98b4ba658a27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210592978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3210592978
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.589224273
Short name T763
Test name
Test status
Simulation time 37194233 ps
CPU time 2.74 seconds
Started Jun 22 05:20:09 PM PDT 24
Finished Jun 22 05:20:14 PM PDT 24
Peak memory 233568 kb
Host smart-5797d386-b7a6-4684-9d06-86e00ed47ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589224273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.589224273
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2368654775
Short name T892
Test name
Test status
Simulation time 24290559 ps
CPU time 0.81 seconds
Started Jun 22 05:20:01 PM PDT 24
Finished Jun 22 05:20:03 PM PDT 24
Peak memory 207492 kb
Host smart-72bef882-eaee-4c19-89e4-1c48527a1767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368654775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2368654775
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2351054330
Short name T228
Test name
Test status
Simulation time 29332948682 ps
CPU time 217.59 seconds
Started Jun 22 05:20:10 PM PDT 24
Finished Jun 22 05:23:50 PM PDT 24
Peak memory 261532 kb
Host smart-04be1143-4893-4c40-9b16-5ddd02e57b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351054330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2351054330
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.4274384993
Short name T289
Test name
Test status
Simulation time 87687937361 ps
CPU time 216.81 seconds
Started Jun 22 05:20:09 PM PDT 24
Finished Jun 22 05:23:48 PM PDT 24
Peak memory 251356 kb
Host smart-7b275089-dd6e-4fcb-959d-86cb3f22fee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274384993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.4274384993
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.4119234889
Short name T418
Test name
Test status
Simulation time 2341028907 ps
CPU time 15.99 seconds
Started Jun 22 05:20:08 PM PDT 24
Finished Jun 22 05:20:26 PM PDT 24
Peak memory 235932 kb
Host smart-e34ba2f4-c92f-41f4-9e84-5ff061b30715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119234889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.4119234889
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3416912538
Short name T531
Test name
Test status
Simulation time 1031555391 ps
CPU time 8.77 seconds
Started Jun 22 05:20:07 PM PDT 24
Finished Jun 22 05:20:17 PM PDT 24
Peak memory 233692 kb
Host smart-d5e88394-5208-4d7d-b477-8a912d473270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416912538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3416912538
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2153392480
Short name T474
Test name
Test status
Simulation time 1052886358 ps
CPU time 8.11 seconds
Started Jun 22 05:20:10 PM PDT 24
Finished Jun 22 05:20:20 PM PDT 24
Peak memory 233684 kb
Host smart-65d16b19-4737-4632-9342-854b91f82419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153392480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2153392480
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2230817470
Short name T730
Test name
Test status
Simulation time 2240672614 ps
CPU time 12.8 seconds
Started Jun 22 05:20:01 PM PDT 24
Finished Jun 22 05:20:15 PM PDT 24
Peak memory 249656 kb
Host smart-fce48976-bd08-467a-ad92-f9a18ef6a70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230817470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2230817470
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1128647466
Short name T205
Test name
Test status
Simulation time 11190910252 ps
CPU time 13.51 seconds
Started Jun 22 05:20:05 PM PDT 24
Finished Jun 22 05:20:19 PM PDT 24
Peak memory 241828 kb
Host smart-cae95e02-79be-453e-8a52-9f674e6b05ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128647466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1128647466
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2220620473
Short name T54
Test name
Test status
Simulation time 462435547 ps
CPU time 3.62 seconds
Started Jun 22 05:20:10 PM PDT 24
Finished Jun 22 05:20:16 PM PDT 24
Peak memory 233636 kb
Host smart-d2faab3b-749a-4ddf-972d-f66455335516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220620473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2220620473
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.691153255
Short name T625
Test name
Test status
Simulation time 886590237 ps
CPU time 11.04 seconds
Started Jun 22 05:20:10 PM PDT 24
Finished Jun 22 05:20:23 PM PDT 24
Peak memory 224016 kb
Host smart-cde37a4b-c73d-4ba7-b665-773809fedea7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=691153255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.691153255
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.353765415
Short name T949
Test name
Test status
Simulation time 61945509432 ps
CPU time 173.6 seconds
Started Jun 22 05:20:07 PM PDT 24
Finished Jun 22 05:23:01 PM PDT 24
Peak memory 274452 kb
Host smart-737dd6bf-ec1c-4317-8e2f-2e7892fec569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353765415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.353765415
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.791280989
Short name T903
Test name
Test status
Simulation time 778601988 ps
CPU time 11.93 seconds
Started Jun 22 05:20:04 PM PDT 24
Finished Jun 22 05:20:17 PM PDT 24
Peak memory 217532 kb
Host smart-21dce3eb-d9ab-46e3-a6fd-8c4c8cea8179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791280989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.791280989
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3416205131
Short name T450
Test name
Test status
Simulation time 4320755054 ps
CPU time 10.75 seconds
Started Jun 22 05:20:00 PM PDT 24
Finished Jun 22 05:20:12 PM PDT 24
Peak memory 217596 kb
Host smart-2785aed5-f577-4a84-8db3-05b6c1e494ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416205131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3416205131
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1744372537
Short name T948
Test name
Test status
Simulation time 26372473 ps
CPU time 0.85 seconds
Started Jun 22 05:20:01 PM PDT 24
Finished Jun 22 05:20:03 PM PDT 24
Peak memory 206848 kb
Host smart-3b1f2d5f-c479-4f21-9d92-11f95ef342f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744372537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1744372537
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.695756573
Short name T568
Test name
Test status
Simulation time 71017595 ps
CPU time 0.94 seconds
Started Jun 22 05:20:09 PM PDT 24
Finished Jun 22 05:20:11 PM PDT 24
Peak memory 206904 kb
Host smart-5edc2600-9d37-4538-bdc2-eecb7264b14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695756573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.695756573
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.911356170
Short name T832
Test name
Test status
Simulation time 3309365740 ps
CPU time 5.55 seconds
Started Jun 22 05:20:09 PM PDT 24
Finished Jun 22 05:20:17 PM PDT 24
Peak memory 225564 kb
Host smart-9d7892dd-b022-49f7-a53f-4b353198318d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911356170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.911356170
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2949800532
Short name T710
Test name
Test status
Simulation time 42430228 ps
CPU time 0.75 seconds
Started Jun 22 05:20:09 PM PDT 24
Finished Jun 22 05:20:11 PM PDT 24
Peak memory 205708 kb
Host smart-75bfa7e4-12d1-46a1-bdf1-b65ed4b84114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949800532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2949800532
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2973375186
Short name T655
Test name
Test status
Simulation time 112552132 ps
CPU time 2.52 seconds
Started Jun 22 05:20:09 PM PDT 24
Finished Jun 22 05:20:13 PM PDT 24
Peak memory 233460 kb
Host smart-e61b4868-83f4-47e9-a3e2-8e809b2120a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973375186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2973375186
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.982613861
Short name T872
Test name
Test status
Simulation time 15316171 ps
CPU time 0.74 seconds
Started Jun 22 05:20:09 PM PDT 24
Finished Jun 22 05:20:12 PM PDT 24
Peak memory 207484 kb
Host smart-464a7961-eda6-4a8d-bbb4-acb90f5a7b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982613861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.982613861
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.381457407
Short name T400
Test name
Test status
Simulation time 17863257423 ps
CPU time 37.11 seconds
Started Jun 22 05:20:08 PM PDT 24
Finished Jun 22 05:20:46 PM PDT 24
Peak memory 242080 kb
Host smart-05d188fd-443e-43a6-8dee-6e1a5ae59205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381457407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.381457407
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.4168872681
Short name T295
Test name
Test status
Simulation time 3042461821 ps
CPU time 39.04 seconds
Started Jun 22 05:20:09 PM PDT 24
Finished Jun 22 05:20:49 PM PDT 24
Peak memory 233860 kb
Host smart-d3ab5cb8-a6b4-44dc-9104-cdecce669923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168872681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.4168872681
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3025387882
Short name T447
Test name
Test status
Simulation time 8748088538 ps
CPU time 115.92 seconds
Started Jun 22 05:20:09 PM PDT 24
Finished Jun 22 05:22:06 PM PDT 24
Peak memory 253744 kb
Host smart-3e60e6b6-5b40-488d-9804-590f68c7694b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025387882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3025387882
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.481821395
Short name T965
Test name
Test status
Simulation time 280180202 ps
CPU time 5.23 seconds
Started Jun 22 05:20:09 PM PDT 24
Finished Jun 22 05:20:15 PM PDT 24
Peak memory 225520 kb
Host smart-d0ba144b-46b2-4025-aab8-582cf75ef87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481821395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.481821395
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3580114456
Short name T279
Test name
Test status
Simulation time 5190645317 ps
CPU time 12.18 seconds
Started Jun 22 05:20:07 PM PDT 24
Finished Jun 22 05:20:20 PM PDT 24
Peak memory 233892 kb
Host smart-43e04ba6-a97d-4e43-a447-547189d2e0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580114456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3580114456
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.611558171
Short name T829
Test name
Test status
Simulation time 8085055022 ps
CPU time 19.52 seconds
Started Jun 22 05:20:09 PM PDT 24
Finished Jun 22 05:20:31 PM PDT 24
Peak memory 235668 kb
Host smart-5ba7e5f9-4b52-4110-bbed-d3b7d836296f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611558171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.611558171
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.118901900
Short name T87
Test name
Test status
Simulation time 57750824990 ps
CPU time 23.21 seconds
Started Jun 22 05:20:08 PM PDT 24
Finished Jun 22 05:20:32 PM PDT 24
Peak memory 233860 kb
Host smart-adf68700-da93-4077-8159-416c7794ae2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118901900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.118901900
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1099632193
Short name T534
Test name
Test status
Simulation time 2802625041 ps
CPU time 10.34 seconds
Started Jun 22 05:20:08 PM PDT 24
Finished Jun 22 05:20:20 PM PDT 24
Peak memory 233892 kb
Host smart-a6c8c960-24f1-4df6-be6a-85f3f5e57759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099632193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1099632193
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1357397009
Short name T803
Test name
Test status
Simulation time 867249497 ps
CPU time 5.66 seconds
Started Jun 22 05:20:09 PM PDT 24
Finished Jun 22 05:20:17 PM PDT 24
Peak memory 224016 kb
Host smart-f17594c7-7d56-4698-b786-f146725f3635
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1357397009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1357397009
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.531974178
Short name T176
Test name
Test status
Simulation time 1997632782 ps
CPU time 16.7 seconds
Started Jun 22 05:20:08 PM PDT 24
Finished Jun 22 05:20:25 PM PDT 24
Peak memory 242028 kb
Host smart-272f56ec-b1be-4885-9f18-aa59ed75388a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531974178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.531974178
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3058298701
Short name T483
Test name
Test status
Simulation time 27445611763 ps
CPU time 23.39 seconds
Started Jun 22 05:20:07 PM PDT 24
Finished Jun 22 05:20:32 PM PDT 24
Peak memory 217440 kb
Host smart-79ba7f35-9ee9-4227-9da8-398fcdadd51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058298701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3058298701
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3580323635
Short name T316
Test name
Test status
Simulation time 1073070588 ps
CPU time 6.85 seconds
Started Jun 22 05:20:10 PM PDT 24
Finished Jun 22 05:20:18 PM PDT 24
Peak memory 217488 kb
Host smart-660cdbdd-5855-40d8-b731-6b2358f8073a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580323635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3580323635
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2206372094
Short name T833
Test name
Test status
Simulation time 161316376 ps
CPU time 3.46 seconds
Started Jun 22 05:20:10 PM PDT 24
Finished Jun 22 05:20:15 PM PDT 24
Peak memory 217384 kb
Host smart-cdfe6ce4-9044-4f3e-a826-a2a114c3e8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206372094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2206372094
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2132090257
Short name T502
Test name
Test status
Simulation time 42291309 ps
CPU time 0.81 seconds
Started Jun 22 05:20:11 PM PDT 24
Finished Jun 22 05:20:13 PM PDT 24
Peak memory 206884 kb
Host smart-abe7dbe3-1b57-4e23-b305-dcee33a2f1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132090257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2132090257
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2084913959
Short name T588
Test name
Test status
Simulation time 44681921191 ps
CPU time 36.39 seconds
Started Jun 22 05:20:10 PM PDT 24
Finished Jun 22 05:20:48 PM PDT 24
Peak memory 233772 kb
Host smart-351a1e28-e7d5-4fa0-886b-8f609c1f0085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084913959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2084913959
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3296102718
Short name T726
Test name
Test status
Simulation time 128454204 ps
CPU time 0.69 seconds
Started Jun 22 05:20:14 PM PDT 24
Finished Jun 22 05:20:15 PM PDT 24
Peak memory 205720 kb
Host smart-3b4cc028-a0a1-4388-b607-057ce96b3f40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296102718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3296102718
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2856567517
Short name T540
Test name
Test status
Simulation time 458762642 ps
CPU time 2.48 seconds
Started Jun 22 05:20:16 PM PDT 24
Finished Jun 22 05:20:19 PM PDT 24
Peak memory 225544 kb
Host smart-75493c42-c955-4f66-be99-4eabb38dcec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856567517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2856567517
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.269799823
Short name T359
Test name
Test status
Simulation time 71365237 ps
CPU time 0.8 seconds
Started Jun 22 05:20:10 PM PDT 24
Finished Jun 22 05:20:13 PM PDT 24
Peak memory 207752 kb
Host smart-6f5831a1-7c25-45f6-9796-30962986a5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269799823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.269799823
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3033800452
Short name T193
Test name
Test status
Simulation time 216654163913 ps
CPU time 452.09 seconds
Started Jun 22 05:20:16 PM PDT 24
Finished Jun 22 05:27:48 PM PDT 24
Peak memory 262520 kb
Host smart-a963af43-c56c-4a65-8846-6cf3ff8f76c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033800452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3033800452
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2167444131
Short name T342
Test name
Test status
Simulation time 18516836 ps
CPU time 0.83 seconds
Started Jun 22 05:20:17 PM PDT 24
Finished Jun 22 05:20:18 PM PDT 24
Peak memory 218256 kb
Host smart-c34bbd8b-e465-4f47-a5cc-c21e6f142dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167444131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2167444131
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3485116549
Short name T457
Test name
Test status
Simulation time 42362837 ps
CPU time 2.87 seconds
Started Jun 22 05:20:14 PM PDT 24
Finished Jun 22 05:20:17 PM PDT 24
Peak memory 225572 kb
Host smart-056df0da-eda2-43dc-8a85-3f74c3a6f065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485116549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3485116549
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1554083020
Short name T183
Test name
Test status
Simulation time 6641775998 ps
CPU time 12.12 seconds
Started Jun 22 05:20:09 PM PDT 24
Finished Jun 22 05:20:23 PM PDT 24
Peak memory 225616 kb
Host smart-11bf29c6-63c1-4216-b673-9a794511610a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554083020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1554083020
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.91083062
Short name T516
Test name
Test status
Simulation time 4143183254 ps
CPU time 11.83 seconds
Started Jun 22 05:20:08 PM PDT 24
Finished Jun 22 05:20:22 PM PDT 24
Peak memory 225684 kb
Host smart-ecc8f51d-91d0-4c3e-a75d-75f46b09f390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91083062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.91083062
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3353819042
Short name T262
Test name
Test status
Simulation time 7130932902 ps
CPU time 18.23 seconds
Started Jun 22 05:20:10 PM PDT 24
Finished Jun 22 05:20:30 PM PDT 24
Peak memory 225692 kb
Host smart-0e58994d-818b-4bb5-abf8-6c1994e71553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353819042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3353819042
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1901998771
Short name T536
Test name
Test status
Simulation time 840411333 ps
CPU time 7.33 seconds
Started Jun 22 05:20:10 PM PDT 24
Finished Jun 22 05:20:19 PM PDT 24
Peak memory 233776 kb
Host smart-0e5618c4-954a-4c34-9dd1-2c04fedcd856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901998771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1901998771
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1140057354
Short name T139
Test name
Test status
Simulation time 609121647 ps
CPU time 4.75 seconds
Started Jun 22 05:20:14 PM PDT 24
Finished Jun 22 05:20:20 PM PDT 24
Peak memory 223996 kb
Host smart-25498202-2458-4a8b-a222-20ef179d9191
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1140057354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1140057354
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.437270545
Short name T460
Test name
Test status
Simulation time 47427310 ps
CPU time 1.01 seconds
Started Jun 22 05:20:17 PM PDT 24
Finished Jun 22 05:20:18 PM PDT 24
Peak memory 208120 kb
Host smart-6ddeb8df-fe5f-463c-baba-359fd8dd7af9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437270545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.437270545
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.4114988830
Short name T937
Test name
Test status
Simulation time 5461804418 ps
CPU time 28.72 seconds
Started Jun 22 05:20:07 PM PDT 24
Finished Jun 22 05:20:36 PM PDT 24
Peak memory 217520 kb
Host smart-2fa7b05c-b258-4192-a67a-6eca1c5acbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114988830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.4114988830
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3064422204
Short name T599
Test name
Test status
Simulation time 2517495499 ps
CPU time 3.72 seconds
Started Jun 22 05:20:08 PM PDT 24
Finished Jun 22 05:20:13 PM PDT 24
Peak memory 217508 kb
Host smart-a1b23f5d-5de2-465e-8fcd-06090b18435e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064422204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3064422204
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3294191056
Short name T723
Test name
Test status
Simulation time 60067460 ps
CPU time 0.93 seconds
Started Jun 22 05:20:09 PM PDT 24
Finished Jun 22 05:20:12 PM PDT 24
Peak memory 208036 kb
Host smart-6b1a14ac-bd2a-49cc-8bed-406cc7b40c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294191056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3294191056
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2265250114
Short name T346
Test name
Test status
Simulation time 36995314 ps
CPU time 0.89 seconds
Started Jun 22 05:20:11 PM PDT 24
Finished Jun 22 05:20:13 PM PDT 24
Peak memory 207100 kb
Host smart-4b8fe516-b674-42ff-98d3-2e685ae77d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265250114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2265250114
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3103840338
Short name T226
Test name
Test status
Simulation time 5195073673 ps
CPU time 15.04 seconds
Started Jun 22 05:20:09 PM PDT 24
Finished Jun 22 05:20:26 PM PDT 24
Peak memory 225692 kb
Host smart-421974b2-3c61-4dc8-bf68-5748c5791043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103840338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3103840338
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2430826373
Short name T657
Test name
Test status
Simulation time 12426121 ps
CPU time 0.72 seconds
Started Jun 22 05:17:58 PM PDT 24
Finished Jun 22 05:17:59 PM PDT 24
Peak memory 206580 kb
Host smart-49fd75cd-c9d0-43cb-a3b1-ab5e5ed853fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430826373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
430826373
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1133103983
Short name T737
Test name
Test status
Simulation time 375283852 ps
CPU time 7.01 seconds
Started Jun 22 05:17:59 PM PDT 24
Finished Jun 22 05:18:06 PM PDT 24
Peak memory 233748 kb
Host smart-fdd7ac83-aafe-4d08-99a3-30636767ac0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133103983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1133103983
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1579591771
Short name T717
Test name
Test status
Simulation time 15095152 ps
CPU time 0.81 seconds
Started Jun 22 05:18:02 PM PDT 24
Finished Jun 22 05:18:03 PM PDT 24
Peak memory 207828 kb
Host smart-a5745215-29ad-4140-99e5-798dd01995a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579591771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1579591771
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.4224604587
Short name T856
Test name
Test status
Simulation time 4742932837 ps
CPU time 32.42 seconds
Started Jun 22 05:18:00 PM PDT 24
Finished Jun 22 05:18:33 PM PDT 24
Peak memory 250500 kb
Host smart-a38a5f98-147f-4a56-82d1-d18822935228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224604587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.4224604587
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2296486305
Short name T157
Test name
Test status
Simulation time 1416374152 ps
CPU time 19.88 seconds
Started Jun 22 05:18:05 PM PDT 24
Finished Jun 22 05:18:25 PM PDT 24
Peak memory 233848 kb
Host smart-25745c5d-367f-4409-a49e-ea9f41242e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296486305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2296486305
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2675139871
Short name T772
Test name
Test status
Simulation time 416549356 ps
CPU time 2.94 seconds
Started Jun 22 05:17:57 PM PDT 24
Finished Jun 22 05:18:00 PM PDT 24
Peak memory 225508 kb
Host smart-d1eb4c57-9f67-4004-b92a-a6add59ddb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675139871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2675139871
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2395681475
Short name T877
Test name
Test status
Simulation time 3118768045 ps
CPU time 10.88 seconds
Started Jun 22 05:18:00 PM PDT 24
Finished Jun 22 05:18:11 PM PDT 24
Peak memory 225552 kb
Host smart-e9c24583-b2c4-4a94-a34b-d249c9fe30f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395681475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2395681475
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2629919836
Short name T191
Test name
Test status
Simulation time 4203600999 ps
CPU time 34.02 seconds
Started Jun 22 05:17:53 PM PDT 24
Finished Jun 22 05:18:27 PM PDT 24
Peak memory 225628 kb
Host smart-d38d5cfd-7061-4517-aabd-84e28b9a1a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629919836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2629919836
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.108773400
Short name T950
Test name
Test status
Simulation time 203500996 ps
CPU time 1.1 seconds
Started Jun 22 05:18:06 PM PDT 24
Finished Jun 22 05:18:08 PM PDT 24
Peak memory 217620 kb
Host smart-36756e67-6224-4c89-bdc5-1d3fc0c72145
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108773400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.108773400
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3652508785
Short name T930
Test name
Test status
Simulation time 4841234192 ps
CPU time 14.75 seconds
Started Jun 22 05:17:50 PM PDT 24
Finished Jun 22 05:18:05 PM PDT 24
Peak memory 234016 kb
Host smart-40ab2cf9-80d4-4fb9-85bf-13fd53f7029b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652508785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3652508785
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.808493987
Short name T254
Test name
Test status
Simulation time 6573411840 ps
CPU time 17.97 seconds
Started Jun 22 05:17:57 PM PDT 24
Finished Jun 22 05:18:15 PM PDT 24
Peak memory 225616 kb
Host smart-d60240c7-9ad9-4f0c-83f6-ee90f94a29c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808493987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.808493987
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1167363650
Short name T138
Test name
Test status
Simulation time 1165395495 ps
CPU time 12.5 seconds
Started Jun 22 05:17:59 PM PDT 24
Finished Jun 22 05:18:12 PM PDT 24
Peak memory 223544 kb
Host smart-f01d5f9a-402f-4e2b-aa64-e260b3d12f12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1167363650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1167363650
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1801384260
Short name T671
Test name
Test status
Simulation time 41472757 ps
CPU time 0.99 seconds
Started Jun 22 05:18:00 PM PDT 24
Finished Jun 22 05:18:02 PM PDT 24
Peak memory 207844 kb
Host smart-d966e73f-3a37-4e45-a542-0d350b6ddb3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801384260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1801384260
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3080001217
Short name T739
Test name
Test status
Simulation time 1120597978 ps
CPU time 11.44 seconds
Started Jun 22 05:18:00 PM PDT 24
Finished Jun 22 05:18:12 PM PDT 24
Peak memory 217544 kb
Host smart-e38826fb-4300-4a06-8e44-eff812e0b28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080001217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3080001217
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.4286014436
Short name T327
Test name
Test status
Simulation time 4321412775 ps
CPU time 6.87 seconds
Started Jun 22 05:17:54 PM PDT 24
Finished Jun 22 05:18:02 PM PDT 24
Peak memory 217508 kb
Host smart-fb4ce048-9527-4428-9c6d-122ec450d2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286014436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.4286014436
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3242942309
Short name T451
Test name
Test status
Simulation time 55480098 ps
CPU time 0.82 seconds
Started Jun 22 05:18:08 PM PDT 24
Finished Jun 22 05:18:10 PM PDT 24
Peak memory 206888 kb
Host smart-0b5edf67-d0c5-4c12-b126-5dc992ac4ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242942309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3242942309
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.4041222659
Short name T330
Test name
Test status
Simulation time 22946948 ps
CPU time 0.73 seconds
Started Jun 22 05:17:48 PM PDT 24
Finished Jun 22 05:17:50 PM PDT 24
Peak memory 206876 kb
Host smart-e3bcdd95-1dc0-4bcd-b64a-a24246434833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041222659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.4041222659
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2459209498
Short name T916
Test name
Test status
Simulation time 2753609006 ps
CPU time 12.94 seconds
Started Jun 22 05:17:56 PM PDT 24
Finished Jun 22 05:18:09 PM PDT 24
Peak memory 236448 kb
Host smart-f9b61de6-471b-4077-acae-e53354f56f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459209498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2459209498
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1734148622
Short name T467
Test name
Test status
Simulation time 13726186 ps
CPU time 0.71 seconds
Started Jun 22 05:18:03 PM PDT 24
Finished Jun 22 05:18:04 PM PDT 24
Peak memory 206628 kb
Host smart-f1603049-47ab-4005-bae1-412156178cc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734148622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
734148622
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1593246286
Short name T887
Test name
Test status
Simulation time 195777543 ps
CPU time 2.47 seconds
Started Jun 22 05:17:54 PM PDT 24
Finished Jun 22 05:17:57 PM PDT 24
Peak memory 225548 kb
Host smart-3a431001-27a6-496c-b7ff-23457f80d7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593246286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1593246286
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2554616720
Short name T437
Test name
Test status
Simulation time 78484314 ps
CPU time 0.79 seconds
Started Jun 22 05:18:06 PM PDT 24
Finished Jun 22 05:18:07 PM PDT 24
Peak memory 207776 kb
Host smart-10ec1aba-f146-465a-ae75-ea67e6df7461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554616720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2554616720
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2088160272
Short name T738
Test name
Test status
Simulation time 5642253588 ps
CPU time 46.47 seconds
Started Jun 22 05:18:08 PM PDT 24
Finished Jun 22 05:18:55 PM PDT 24
Peak memory 238480 kb
Host smart-4a057341-d07e-401d-9a41-782eda5443b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088160272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2088160272
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.722585788
Short name T751
Test name
Test status
Simulation time 26020830250 ps
CPU time 255.58 seconds
Started Jun 22 05:18:03 PM PDT 24
Finished Jun 22 05:22:19 PM PDT 24
Peak memory 253656 kb
Host smart-ec398347-27c2-4794-9bf5-3d3c5acc7e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722585788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.722585788
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.885982205
Short name T218
Test name
Test status
Simulation time 3465840636 ps
CPU time 93.62 seconds
Started Jun 22 05:18:01 PM PDT 24
Finished Jun 22 05:19:35 PM PDT 24
Peak memory 258124 kb
Host smart-2ce9eb38-3d59-4532-b710-406c51e0725a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885982205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
885982205
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2463835908
Short name T852
Test name
Test status
Simulation time 2546115844 ps
CPU time 48.24 seconds
Started Jun 22 05:17:59 PM PDT 24
Finished Jun 22 05:18:48 PM PDT 24
Peak memory 233420 kb
Host smart-f3e6ab47-ad2a-455a-9fcf-09d3646c4acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463835908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2463835908
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.847421795
Short name T57
Test name
Test status
Simulation time 1988155788 ps
CPU time 3.77 seconds
Started Jun 22 05:17:58 PM PDT 24
Finished Jun 22 05:18:02 PM PDT 24
Peak memory 225508 kb
Host smart-ea486c4b-edeb-4212-b9ff-b4a1c4e74288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847421795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.847421795
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3964053650
Short name T37
Test name
Test status
Simulation time 25774502925 ps
CPU time 59.77 seconds
Started Jun 22 05:17:57 PM PDT 24
Finished Jun 22 05:18:57 PM PDT 24
Peak memory 233800 kb
Host smart-ea662c0f-d6e1-4428-ac5f-cc4841268da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964053650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3964053650
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1087384366
Short name T480
Test name
Test status
Simulation time 30673887 ps
CPU time 1.1 seconds
Started Jun 22 05:18:02 PM PDT 24
Finished Jun 22 05:18:04 PM PDT 24
Peak memory 218840 kb
Host smart-058acdfd-3ed9-4694-abbf-b766f89b5f79
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087384366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1087384366
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4116456760
Short name T532
Test name
Test status
Simulation time 476559606 ps
CPU time 5.9 seconds
Started Jun 22 05:18:11 PM PDT 24
Finished Jun 22 05:18:18 PM PDT 24
Peak memory 225496 kb
Host smart-98d07c96-fc3a-4e1e-8dcf-88e7a9179b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116456760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.4116456760
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3630608598
Short name T492
Test name
Test status
Simulation time 1627898254 ps
CPU time 6.36 seconds
Started Jun 22 05:18:04 PM PDT 24
Finished Jun 22 05:18:11 PM PDT 24
Peak memory 225524 kb
Host smart-fed06579-5418-4129-abd1-046886300806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630608598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3630608598
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.895257834
Short name T811
Test name
Test status
Simulation time 7223243300 ps
CPU time 16.09 seconds
Started Jun 22 05:17:55 PM PDT 24
Finished Jun 22 05:18:12 PM PDT 24
Peak memory 224228 kb
Host smart-b4d74918-4502-4d80-b058-b4e2e4be97f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=895257834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.895257834
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2227852843
Short name T47
Test name
Test status
Simulation time 155978971838 ps
CPU time 396.08 seconds
Started Jun 22 05:18:03 PM PDT 24
Finished Jun 22 05:24:40 PM PDT 24
Peak memory 258204 kb
Host smart-50dc8871-f044-472e-ae0c-fd8f1af30325
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227852843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2227852843
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3966205945
Short name T496
Test name
Test status
Simulation time 2527825863 ps
CPU time 25.28 seconds
Started Jun 22 05:17:50 PM PDT 24
Finished Jun 22 05:18:16 PM PDT 24
Peak memory 218860 kb
Host smart-ca80e13c-ef0a-4b00-b49e-3f247d4be684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966205945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3966205945
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1548917002
Short name T622
Test name
Test status
Simulation time 587559339 ps
CPU time 4.39 seconds
Started Jun 22 05:17:57 PM PDT 24
Finished Jun 22 05:18:02 PM PDT 24
Peak memory 217348 kb
Host smart-a8e65802-cb84-4dda-a90c-6645dfb1bf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548917002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1548917002
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.826788415
Short name T27
Test name
Test status
Simulation time 210795495 ps
CPU time 3.01 seconds
Started Jun 22 05:17:59 PM PDT 24
Finished Jun 22 05:18:02 PM PDT 24
Peak memory 216944 kb
Host smart-863b5d6c-c19f-4b51-af17-69d42f1f838e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826788415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.826788415
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1040536403
Short name T58
Test name
Test status
Simulation time 167008624 ps
CPU time 0.93 seconds
Started Jun 22 05:17:56 PM PDT 24
Finished Jun 22 05:17:57 PM PDT 24
Peak memory 206880 kb
Host smart-fc784b79-dfed-4565-916d-961c816823dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040536403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1040536403
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3510441621
Short name T946
Test name
Test status
Simulation time 912903996 ps
CPU time 6.34 seconds
Started Jun 22 05:18:05 PM PDT 24
Finished Jun 22 05:18:12 PM PDT 24
Peak memory 236000 kb
Host smart-b37980dd-1d1e-49d1-9719-17873ebab74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510441621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3510441621
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.944992298
Short name T685
Test name
Test status
Simulation time 40758648 ps
CPU time 0.74 seconds
Started Jun 22 05:18:03 PM PDT 24
Finished Jun 22 05:18:05 PM PDT 24
Peak memory 205684 kb
Host smart-ac89f01e-df5d-4be0-8999-a9253fd0a228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944992298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.944992298
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2011564829
Short name T653
Test name
Test status
Simulation time 131557238 ps
CPU time 3.24 seconds
Started Jun 22 05:17:59 PM PDT 24
Finished Jun 22 05:18:03 PM PDT 24
Peak memory 233676 kb
Host smart-239c9fb3-8a0a-402c-8f75-ab182d931987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011564829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2011564829
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.108790559
Short name T500
Test name
Test status
Simulation time 18599765 ps
CPU time 0.82 seconds
Started Jun 22 05:18:06 PM PDT 24
Finished Jun 22 05:18:08 PM PDT 24
Peak memory 206792 kb
Host smart-4c2b970a-48e4-42bf-b0ad-7d9307e946cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108790559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.108790559
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.4264589304
Short name T24
Test name
Test status
Simulation time 2629177927 ps
CPU time 30.52 seconds
Started Jun 22 05:18:12 PM PDT 24
Finished Jun 22 05:18:43 PM PDT 24
Peak memory 250304 kb
Host smart-57b254f5-3421-4910-8b83-d6d9ad0e6bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264589304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.4264589304
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2576513754
Short name T870
Test name
Test status
Simulation time 6398605237 ps
CPU time 57.58 seconds
Started Jun 22 05:18:08 PM PDT 24
Finished Jun 22 05:19:06 PM PDT 24
Peak memory 250316 kb
Host smart-78d2b41d-fe82-4b46-a450-9caead6a42c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576513754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2576513754
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1272616837
Short name T415
Test name
Test status
Simulation time 4830424192 ps
CPU time 16.78 seconds
Started Jun 22 05:18:07 PM PDT 24
Finished Jun 22 05:18:25 PM PDT 24
Peak memory 240172 kb
Host smart-28193006-622e-4093-bb46-321af2584b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272616837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1272616837
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.205176761
Short name T304
Test name
Test status
Simulation time 7362573208 ps
CPU time 15.69 seconds
Started Jun 22 05:18:04 PM PDT 24
Finished Jun 22 05:18:20 PM PDT 24
Peak memory 225664 kb
Host smart-9054698c-2b24-42a1-9dc0-5491bf20e6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205176761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.205176761
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1424269173
Short name T883
Test name
Test status
Simulation time 1446621411 ps
CPU time 13.04 seconds
Started Jun 22 05:18:16 PM PDT 24
Finished Jun 22 05:18:30 PM PDT 24
Peak memory 225504 kb
Host smart-9819da56-0b0c-4582-9720-18e516dd3e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424269173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1424269173
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2403120384
Short name T670
Test name
Test status
Simulation time 433118783 ps
CPU time 11.23 seconds
Started Jun 22 05:18:09 PM PDT 24
Finished Jun 22 05:18:21 PM PDT 24
Peak memory 241788 kb
Host smart-7c561786-74ad-459a-a173-fada8fa64276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403120384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2403120384
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.259879433
Short name T35
Test name
Test status
Simulation time 165101056 ps
CPU time 1.08 seconds
Started Jun 22 05:18:03 PM PDT 24
Finished Jun 22 05:18:05 PM PDT 24
Peak memory 218840 kb
Host smart-89e937d1-96a3-4c62-a28b-d21b4dc34058
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259879433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.259879433
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1699818092
Short name T194
Test name
Test status
Simulation time 3767274646 ps
CPU time 10.42 seconds
Started Jun 22 05:18:14 PM PDT 24
Finished Jun 22 05:18:25 PM PDT 24
Peak memory 230096 kb
Host smart-a24b0083-98d0-49c4-9c1c-ddeef8dcd0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699818092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1699818092
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.96629931
Short name T240
Test name
Test status
Simulation time 14309871733 ps
CPU time 12.16 seconds
Started Jun 22 05:18:02 PM PDT 24
Finished Jun 22 05:18:15 PM PDT 24
Peak memory 225632 kb
Host smart-3fa3d507-cca4-4d0b-a1b9-ea4438761b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96629931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.96629931
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.988351816
Short name T151
Test name
Test status
Simulation time 1246719084 ps
CPU time 10.08 seconds
Started Jun 22 05:18:07 PM PDT 24
Finished Jun 22 05:18:18 PM PDT 24
Peak memory 221244 kb
Host smart-03bb5926-313c-444c-b6db-341675c328a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=988351816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.988351816
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2656912487
Short name T146
Test name
Test status
Simulation time 51742522901 ps
CPU time 271.1 seconds
Started Jun 22 05:18:06 PM PDT 24
Finished Jun 22 05:22:38 PM PDT 24
Peak memory 256252 kb
Host smart-f44ebacf-93eb-4026-9c09-c81d667462fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656912487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2656912487
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1726117997
Short name T477
Test name
Test status
Simulation time 33437456483 ps
CPU time 20.01 seconds
Started Jun 22 05:18:00 PM PDT 24
Finished Jun 22 05:18:21 PM PDT 24
Peak memory 217668 kb
Host smart-59995ad4-e09f-4e8a-b9c4-3994029017a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726117997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1726117997
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3967238291
Short name T629
Test name
Test status
Simulation time 326829880 ps
CPU time 3.06 seconds
Started Jun 22 05:18:11 PM PDT 24
Finished Jun 22 05:18:15 PM PDT 24
Peak memory 217288 kb
Host smart-3a8a3e55-a9c4-4430-a697-7e97581b784c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967238291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3967238291
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1283237616
Short name T809
Test name
Test status
Simulation time 144687048 ps
CPU time 2.58 seconds
Started Jun 22 05:18:06 PM PDT 24
Finished Jun 22 05:18:09 PM PDT 24
Peak memory 217336 kb
Host smart-1688604e-ae03-4506-b80d-86fecbe23758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283237616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1283237616
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.997661756
Short name T686
Test name
Test status
Simulation time 249269741 ps
CPU time 0.81 seconds
Started Jun 22 05:18:20 PM PDT 24
Finished Jun 22 05:18:21 PM PDT 24
Peak memory 206852 kb
Host smart-64134506-d6dd-4732-9c7e-0d7198cf6db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997661756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.997661756
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.4267114300
Short name T796
Test name
Test status
Simulation time 19720154662 ps
CPU time 16.85 seconds
Started Jun 22 05:18:08 PM PDT 24
Finished Jun 22 05:18:26 PM PDT 24
Peak memory 225620 kb
Host smart-8faaf93e-7397-4a51-99e1-a9b0b515a9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267114300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.4267114300
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1463443629
Short name T452
Test name
Test status
Simulation time 15757658 ps
CPU time 0.69 seconds
Started Jun 22 05:18:07 PM PDT 24
Finished Jun 22 05:18:08 PM PDT 24
Peak memory 206244 kb
Host smart-28e6bb69-8edd-4736-9d0c-55b672308a67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463443629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
463443629
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.917837806
Short name T405
Test name
Test status
Simulation time 282028550 ps
CPU time 2.99 seconds
Started Jun 22 05:18:13 PM PDT 24
Finished Jun 22 05:18:16 PM PDT 24
Peak memory 225572 kb
Host smart-6e0e5622-2c75-46ee-8ebc-8228c0f7a7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917837806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.917837806
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2532564202
Short name T360
Test name
Test status
Simulation time 18857243 ps
CPU time 0.78 seconds
Started Jun 22 05:17:58 PM PDT 24
Finished Jun 22 05:18:00 PM PDT 24
Peak memory 206436 kb
Host smart-34cd8de1-d9df-4886-8bc9-798f29fccec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532564202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2532564202
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2384492831
Short name T200
Test name
Test status
Simulation time 4584824497 ps
CPU time 14.55 seconds
Started Jun 22 05:18:10 PM PDT 24
Finished Jun 22 05:18:25 PM PDT 24
Peak memory 236256 kb
Host smart-59938e0b-d81d-4609-9d1a-9c65da1aedb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384492831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2384492831
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2275798753
Short name T42
Test name
Test status
Simulation time 42529605870 ps
CPU time 197.33 seconds
Started Jun 22 05:18:07 PM PDT 24
Finished Jun 22 05:21:25 PM PDT 24
Peak memory 238056 kb
Host smart-103dfc0a-e5bd-4c0b-be15-9147deead67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275798753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2275798753
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1121768064
Short name T819
Test name
Test status
Simulation time 19134196166 ps
CPU time 106.47 seconds
Started Jun 22 05:18:18 PM PDT 24
Finished Jun 22 05:20:05 PM PDT 24
Peak memory 253244 kb
Host smart-1343969f-cbe9-4673-95eb-d0ddc53caef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121768064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1121768064
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.229480124
Short name T641
Test name
Test status
Simulation time 535837805 ps
CPU time 11.55 seconds
Started Jun 22 05:18:07 PM PDT 24
Finished Jun 22 05:18:19 PM PDT 24
Peak memory 249872 kb
Host smart-1529cc62-9242-4033-9757-029124f1d8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229480124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.229480124
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4111429134
Short name T126
Test name
Test status
Simulation time 31183266450 ps
CPU time 23.52 seconds
Started Jun 22 05:18:13 PM PDT 24
Finished Jun 22 05:18:37 PM PDT 24
Peak memory 233836 kb
Host smart-d8ef4ccc-78be-47f5-8197-6a87ebb80610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111429134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4111429134
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3814915112
Short name T105
Test name
Test status
Simulation time 183227437 ps
CPU time 6.44 seconds
Started Jun 22 05:18:08 PM PDT 24
Finished Jun 22 05:18:15 PM PDT 24
Peak memory 233720 kb
Host smart-824d29bc-7791-4212-8e4a-22e1b039309e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814915112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3814915112
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.2059080850
Short name T561
Test name
Test status
Simulation time 109183678 ps
CPU time 1.11 seconds
Started Jun 22 05:18:00 PM PDT 24
Finished Jun 22 05:18:02 PM PDT 24
Peak memory 217644 kb
Host smart-ed252a87-3892-4d81-90d5-e910c7c3b534
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059080850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.2059080850
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4066854888
Short name T267
Test name
Test status
Simulation time 115908362 ps
CPU time 3.47 seconds
Started Jun 22 05:18:07 PM PDT 24
Finished Jun 22 05:18:12 PM PDT 24
Peak memory 229076 kb
Host smart-207ee4f6-15a7-4d4f-9d75-06de138baa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066854888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.4066854888
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2459243939
Short name T863
Test name
Test status
Simulation time 1054874247 ps
CPU time 7.7 seconds
Started Jun 22 05:18:08 PM PDT 24
Finished Jun 22 05:18:16 PM PDT 24
Peak memory 233772 kb
Host smart-677e320e-69f4-454d-8128-1bddb58bba3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459243939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2459243939
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2636745023
Short name T837
Test name
Test status
Simulation time 2137409111 ps
CPU time 22.26 seconds
Started Jun 22 05:18:13 PM PDT 24
Finished Jun 22 05:18:35 PM PDT 24
Peak memory 221188 kb
Host smart-726d0258-b340-4cfb-bb1a-b2df2e0e7186
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2636745023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2636745023
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3691677919
Short name T49
Test name
Test status
Simulation time 23290621960 ps
CPU time 303.95 seconds
Started Jun 22 05:18:10 PM PDT 24
Finished Jun 22 05:23:14 PM PDT 24
Peak memory 273660 kb
Host smart-7060c59e-f0a5-4f29-8ec6-2e8e4c0fc895
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691677919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3691677919
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2113238145
Short name T383
Test name
Test status
Simulation time 4666920687 ps
CPU time 26.63 seconds
Started Jun 22 05:18:01 PM PDT 24
Finished Jun 22 05:18:28 PM PDT 24
Peak memory 217728 kb
Host smart-1fd9c989-1df7-4ade-b23e-514a05ecac2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113238145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2113238145
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2178520129
Short name T869
Test name
Test status
Simulation time 7936885685 ps
CPU time 11.85 seconds
Started Jun 22 05:18:09 PM PDT 24
Finished Jun 22 05:18:21 PM PDT 24
Peak memory 217492 kb
Host smart-55bea9eb-c232-4a9f-a676-f0d150b72c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178520129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2178520129
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2702892456
Short name T393
Test name
Test status
Simulation time 116593137 ps
CPU time 1.89 seconds
Started Jun 22 05:18:04 PM PDT 24
Finished Jun 22 05:18:07 PM PDT 24
Peak memory 217380 kb
Host smart-a7c9297f-5a6f-4e7b-9c1e-be2ee6dc1ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702892456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2702892456
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1600860199
Short name T896
Test name
Test status
Simulation time 77694957 ps
CPU time 0.96 seconds
Started Jun 22 05:18:08 PM PDT 24
Finished Jun 22 05:18:10 PM PDT 24
Peak memory 206852 kb
Host smart-def3d9c6-0ff4-447d-8728-d837e590a41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600860199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1600860199
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2600432544
Short name T498
Test name
Test status
Simulation time 25703531996 ps
CPU time 20.15 seconds
Started Jun 22 05:18:05 PM PDT 24
Finished Jun 22 05:18:26 PM PDT 24
Peak memory 233776 kb
Host smart-486552a1-4f9b-4639-858e-14e664fd193b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600432544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2600432544
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.4271764588
Short name T831
Test name
Test status
Simulation time 17703534 ps
CPU time 0.72 seconds
Started Jun 22 05:18:06 PM PDT 24
Finished Jun 22 05:18:08 PM PDT 24
Peak memory 206256 kb
Host smart-91dd3498-7519-41c8-98bc-e706adb79dfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271764588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.4
271764588
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2083746725
Short name T776
Test name
Test status
Simulation time 16407573526 ps
CPU time 25.05 seconds
Started Jun 22 05:18:11 PM PDT 24
Finished Jun 22 05:18:36 PM PDT 24
Peak memory 233768 kb
Host smart-572a536a-9b61-4b4b-b85b-e5a2ebb21156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083746725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2083746725
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3976014865
Short name T511
Test name
Test status
Simulation time 16232062 ps
CPU time 0.82 seconds
Started Jun 22 05:18:03 PM PDT 24
Finished Jun 22 05:18:05 PM PDT 24
Peak memory 207468 kb
Host smart-bb4516a2-6583-4123-94e1-5ba78ecbb7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976014865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3976014865
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.804748344
Short name T637
Test name
Test status
Simulation time 41642790 ps
CPU time 0.83 seconds
Started Jun 22 05:18:01 PM PDT 24
Finished Jun 22 05:18:03 PM PDT 24
Peak memory 216800 kb
Host smart-e41f6cdd-bcb2-4211-8872-2cd928d6642e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804748344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.804748344
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.391940963
Short name T656
Test name
Test status
Simulation time 63824057210 ps
CPU time 141.67 seconds
Started Jun 22 05:18:03 PM PDT 24
Finished Jun 22 05:20:26 PM PDT 24
Peak memory 242120 kb
Host smart-5ebeda87-9e0d-46a9-a801-ebe6cb5e89e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391940963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.391940963
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1908578518
Short name T798
Test name
Test status
Simulation time 14812661259 ps
CPU time 67.75 seconds
Started Jun 22 05:18:09 PM PDT 24
Finished Jun 22 05:19:18 PM PDT 24
Peak memory 224812 kb
Host smart-5248e6a8-fc71-4e21-b04d-8f53d2413fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908578518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1908578518
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3028921624
Short name T874
Test name
Test status
Simulation time 577629391 ps
CPU time 3.89 seconds
Started Jun 22 05:18:05 PM PDT 24
Finished Jun 22 05:18:10 PM PDT 24
Peak memory 225504 kb
Host smart-e39e8f97-2e1d-4603-83e1-94e9315f56b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028921624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3028921624
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1098942856
Short name T519
Test name
Test status
Simulation time 2984463279 ps
CPU time 19.58 seconds
Started Jun 22 05:18:08 PM PDT 24
Finished Jun 22 05:18:28 PM PDT 24
Peak memory 241684 kb
Host smart-dc6fd685-aad7-4de9-a3f1-ace169c0d33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098942856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1098942856
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3716149281
Short name T808
Test name
Test status
Simulation time 32664446 ps
CPU time 1.14 seconds
Started Jun 22 05:18:12 PM PDT 24
Finished Jun 22 05:18:14 PM PDT 24
Peak memory 217620 kb
Host smart-40e44dfd-7ffa-40a1-9806-ec294f3bb6b4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716149281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3716149281
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1879925903
Short name T266
Test name
Test status
Simulation time 95875534 ps
CPU time 2.8 seconds
Started Jun 22 05:18:26 PM PDT 24
Finished Jun 22 05:18:30 PM PDT 24
Peak memory 233744 kb
Host smart-43d4481f-3601-4d38-8f55-085a65db2d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879925903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1879925903
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2876051639
Short name T127
Test name
Test status
Simulation time 7974057967 ps
CPU time 21.84 seconds
Started Jun 22 05:18:07 PM PDT 24
Finished Jun 22 05:18:29 PM PDT 24
Peak memory 225696 kb
Host smart-90c335b8-d590-46a2-ab0c-c71c64b45d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876051639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2876051639
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.4159173940
Short name T584
Test name
Test status
Simulation time 1247149661 ps
CPU time 7.47 seconds
Started Jun 22 05:18:13 PM PDT 24
Finished Jun 22 05:18:21 PM PDT 24
Peak memory 222880 kb
Host smart-20beaaee-4d1c-4f16-84a3-c21eede9a1a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4159173940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.4159173940
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2939626238
Short name T750
Test name
Test status
Simulation time 4059807712 ps
CPU time 82.38 seconds
Started Jun 22 05:18:08 PM PDT 24
Finished Jun 22 05:19:31 PM PDT 24
Peak memory 257600 kb
Host smart-35d195ba-c0ae-4c15-84fb-8b1692ec0357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939626238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2939626238
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.4202274347
Short name T461
Test name
Test status
Simulation time 13772012010 ps
CPU time 24.37 seconds
Started Jun 22 05:18:07 PM PDT 24
Finished Jun 22 05:18:32 PM PDT 24
Peak memory 217504 kb
Host smart-77e92dfb-922f-4fe8-baec-aaf009f537ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202274347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4202274347
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.30534047
Short name T746
Test name
Test status
Simulation time 20839550904 ps
CPU time 13.63 seconds
Started Jun 22 05:18:03 PM PDT 24
Finished Jun 22 05:18:18 PM PDT 24
Peak memory 217412 kb
Host smart-6bde766f-68e2-448a-9db0-5f95021a283f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30534047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.30534047
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2105055689
Short name T443
Test name
Test status
Simulation time 136286475 ps
CPU time 0.87 seconds
Started Jun 22 05:18:20 PM PDT 24
Finished Jun 22 05:18:22 PM PDT 24
Peak memory 207900 kb
Host smart-46e5edde-5f1e-4b6c-a4ea-57eb76d9b5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105055689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2105055689
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1127375193
Short name T790
Test name
Test status
Simulation time 130156758 ps
CPU time 0.75 seconds
Started Jun 22 05:18:07 PM PDT 24
Finished Jun 22 05:18:08 PM PDT 24
Peak memory 206872 kb
Host smart-d8562283-37dc-4b2e-8982-baf14b9f3ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127375193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1127375193
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.191297769
Short name T940
Test name
Test status
Simulation time 5752714447 ps
CPU time 14.42 seconds
Started Jun 22 05:18:08 PM PDT 24
Finished Jun 22 05:18:23 PM PDT 24
Peak memory 233824 kb
Host smart-3ff22d1c-fb0e-4c19-bab5-cc11befc8a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191297769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.191297769
Directory /workspace/9.spi_device_upload/latest
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