Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2739229	1			T1	1		T4	1		T5	49711
all_values[1]	2739229	1			T1	1		T4	1		T5	49711
all_values[2]	2739229	1			T1	1		T4	1		T5	49711
all_values[3]	2739229	1			T1	1		T4	1		T5	49711
all_values[4]	2739229	1			T1	1		T4	1		T5	49711
all_values[5]	2739229	1			T1	1		T4	1		T5	49711
all_values[6]	2739229	1			T1	1		T4	1		T5	49711
all_values[7]	2739229	1			T1	1		T4	1		T5	49711

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21289720

1

T1

8

T4

8

T5

397688

auto[1]

624112

1

T6

109

T15

29

T17

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21888602

1

T1

8

T4

8

T5

397176

auto[1]

25230

1

T5

512

T6

77

T13

323

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2630067	1			T1	1		T4	1		T5	49417
all_values[0]	auto[0]	auto[1]	12075	1			T5	294		T6	6		T13	147
all_values[0]	auto[1]	auto[0]	96658	1			T6	9		T15	3		T17	3
all_values[0]	auto[1]	auto[1]	429	1			T6	4		T15	3		T17	1
all_values[1]	auto[0]	auto[0]	2617816	1			T1	1		T4	1		T5	49510
all_values[1]	auto[0]	auto[1]	7424	1			T5	201		T6	1		T13	127
all_values[1]	auto[1]	auto[0]	113355	1			T6	9		T15	2		T19	5
all_values[1]	auto[1]	auto[1]	634	1			T6	11		T15	2		T17	1
all_values[2]	auto[0]	auto[0]	2656612	1			T1	1		T4	1		T5	49694
all_values[2]	auto[0]	auto[1]	2596	1			T5	17		T6	2		T13	49
all_values[2]	auto[1]	auto[0]	79730	1			T6	6		T15	2		T19	4
all_values[2]	auto[1]	auto[1]	291	1			T6	2		T15	1		T17	1
all_values[3]	auto[0]	auto[0]	2669807	1			T1	1		T4	1		T5	49711
all_values[3]	auto[0]	auto[1]	190	1			T6	6		T15	4		T17	3
all_values[3]	auto[1]	auto[0]	69032	1			T6	5		T15	1		T19	6
all_values[3]	auto[1]	auto[1]	200	1			T6	10		T15	1		T22	2
all_values[4]	auto[0]	auto[0]	2696924	1			T1	1		T4	1		T5	49711
all_values[4]	auto[0]	auto[1]	168	1			T6	4		T15	4		T17	2
all_values[4]	auto[1]	auto[0]	41954	1			T6	10		T15	1		T17	1
all_values[4]	auto[1]	auto[1]	183	1			T6	4		T15	1		T17	2
all_values[5]	auto[0]	auto[0]	2685816	1			T1	1		T4	1		T5	49711
all_values[5]	auto[0]	auto[1]	149	1			T6	5		T15	1		T17	2
all_values[5]	auto[1]	auto[0]	53097	1			T6	8		T15	3		T17	2
all_values[5]	auto[1]	auto[1]	167	1			T6	5		T15	3		T17	1
all_values[6]	auto[0]	auto[0]	2652455	1			T1	1		T4	1		T5	49711
all_values[6]	auto[0]	auto[1]	211	1			T6	2		T17	4		T22	1
all_values[6]	auto[1]	auto[0]	86400	1			T6	9		T15	3		T19	4
all_values[6]	auto[1]	auto[1]	163	1			T6	4		T19	1		T20	1
all_values[7]	auto[0]	auto[0]	2657241	1			T1	1		T4	1		T5	49711
all_values[7]	auto[0]	auto[1]	169	1			T6	6		T20	1		T31	6
all_values[7]	auto[1]	auto[0]	81638	1			T6	8		T15	3		T17	1
all_values[7]	auto[1]	auto[1]	181	1			T6	5		T17	3		T20	3