Group : spi_device_env_pkg::spi_device_env_cov::cfg_settings_cg
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Group : spi_device_env_pkg::spi_device_env_cov::cfg_settings_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::cfg_settings_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 4 6 60.00
Crosses 4 3 1 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::cfg_settings_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mailbox_en 2 0 2 100.00 100 1 1 2
cp_rx_order 2 1 1 50.00 100 1 1 2
cp_tx_order 2 1 1 50.00 100 1 1 2
rx_order 2 1 1 50.00 100 1 1 2
tx_order 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::cfg_settings_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_order 4 3 1 25.00 100 1 1 0


Summary for Variable cp_mailbox_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_mailbox_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 56560 1 T5 295 T9 18 T10 446
auto[1] 62357 1 T1 22 T4 24 T5 337


Summary for Variable cp_rx_order

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_rx_order

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 118917 1 T1 22 T4 24 T5 632


Summary for Variable cp_tx_order

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_tx_order

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 118917 1 T1 22 T4 24 T5 632


Summary for Variable rx_order

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for rx_order

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 118917 1 T1 22 T4 24 T5 632


Summary for Variable tx_order

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for tx_order

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 118917 1 T1 22 T4 24 T5 632


Summary for Cross cr_order

Samples crossed: tx_order rx_order
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 3 1 25.00 3


Automatically Generated Cross Bins for cr_order

Element holes
tx_orderrx_orderCOUNTAT LEASTNUMBERSTATUS
[auto[1]] * -- -- 2


Uncovered bins
tx_orderrx_orderCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] 0 1 1


Covered bins
tx_orderrx_orderCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 118917 1 T1 22 T4 24 T5 632

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