Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33483	1			T4	14		T5	103		T7	4
auto[SpiFlashAddrCfg]	6389	1			T5	41		T7	10		T8	4
auto[SpiFlashAddr3b]	7768	1			T5	34		T7	8		T8	2
auto[SpiFlashAddr4b]	6135	1			T1	8		T5	31		T7	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29394

1

T1

8

T4

14

T5

134

auto[1]

24381

1

T5

75

T7

24

T13

74

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28747

1

T1

2

T4

14

T5

120

auto[1]

25028

1

T1

6

T5

89

T7

12

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	37512	1			T4	14		T5	133		T7	10
values[1]	843	1			T5	4		T13	7		T14	4
values[2]	1213	1			T5	3		T7	2		T8	2
values[3]	1107	1			T5	5		T13	5		T14	6
values[4]	1193	1			T5	8		T9	6		T13	4
values[5]	1309	1			T5	2		T13	9		T14	17
values[6]	1178	1			T5	4		T13	5		T14	16
values[7]	1279	1			T1	2		T5	5		T7	4
values[8]	8141	1			T1	6		T5	45		T7	8

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31374

1

T1

8

T4

14

T5

209

auto[1]

22401

1

T13

178

T41

2

T43

73

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

51010

1

T1

8

T4

14

T5

193

write

2765

1

T5

16

T7

2

T13

18

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

15964

1

T1

2

T4

14

T5

73

valids[0x1]

37811

1

T1

6

T5

136

T7

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1268	1			T5	11		T7	2		T13	4
internal_process_ops[0x5a]	1295	1			T5	9		T7	2		T13	7
internal_process_ops[0x05]	22038	1			T5	36		T9	2		T13	27
internal_process_ops[0x35]	1282	1			T5	13		T7	2		T13	8
internal_process_ops[0x15]	1324	1			T5	5		T13	9		T14	8
internal_process_ops[0x03]	902	1			T1	6		T5	6		T9	2
internal_process_ops[0x0b]	963	1			T5	13		T7	4		T8	4
internal_process_ops[0x3b]	946	1			T5	6		T7	4		T8	4
internal_process_ops[0x6b]	929	1			T5	6		T13	1		T14	9
internal_process_ops[0xbb]	824	1			T5	6		T14	7		T44	2
internal_process_ops[0xeb]	957	1			T1	2		T5	3		T8	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52385

1

T1

8

T4

14

T5

202

auto[1]

1390

1

T5

7

T7

2

T13

12

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51797

1

T1

8

T4

14

T5

195

auto[1]

1978

1

T5

14

T13

10

T14

19

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10740

1

T4

14

T5

76

T9

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7460

1

T5

21

T7

4

T14

205

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1981

1

T5

20

T8

4

T9

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1662

1

T5

20

T7

8

T14

16

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2429

1

T5

16

T8

2

T9

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2081

1

T5

14

T7

8

T14

27

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1841

1

T1

8

T5

9

T8

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1658

1

T5

17

T7

2

T14

26

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

121

1

T5

2

T14

1

T16

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

87

1

T5

4

T14

1

T16

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

71

1

T14

2

T15

1

T32

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

125

1

T14

3

T32

5

T17

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

107

1

T5

1

T40

1

T16

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

104

1

T14

8

T40

1

T45

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

94

1

T14

2

T40

1

T17

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

101

1

T7

2

T32

4

T17

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

88

1

T15

1

T17

2

T158

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

90

1

T5

3

T16

2

T32

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

85

1

T5

1

T14

8

T40

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

93

1

T14

1

T16

1

T49

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

86

1

T5

3

T44

4

T32

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

80

1

T14

3

T40

1

T16

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

97

1

T5

2

T15

1

T32

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

93

1

T48

4

T15

1

T16

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7621

1

T13

46

T43

41

T38

61

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6947

1

T13

34

T43

9

T38

94

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1064

1

T13

12

T41

2

T43

6

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

988

1

T13

11

T43

4

T38

14

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1303

1

T13

19

T43

2

T38

22

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1278

1

T13

13

T43

4

T38

17

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

977

1

T13

14

T43

3

T38

18

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

980

1

T13

11

T43

1

T38

19

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

86

1

T13

2

T38

3

T50

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

100

1

T13

2

T38

2

T50

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

67

1

T38

1

T15

3

T77

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

58

1

T38

2

T16

1

T77

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

62

1

T13

1

T77

3

T159

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

88

1

T13

2

T39

1

T50

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

70

1

T15

3

T50

1

T77

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

68

1

T16

4

T71

1

T78

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

90

1

T13

1

T43

1

T50

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

76

1

T38

1

T160

3

T71

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

73

1

T13

1

T43

1

T38

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

82

1

T13

3

T43

1

T38

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

96

1

T38

5

T39

1

T15

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

77

1

T13

5

T15

1

T50

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

82

1

T13

1

T39

2

T15

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

68

1

T16

1

T77

2

T159

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3642	1			T4	14		T5	32		T14	38
auto[0]	values[0]	valids[0x1]	17344	1			T5	101		T7	10		T9	4
auto[0]	values[1]	valids[0x1]	463	1			T5	4		T14	4		T40	6
auto[0]	values[2]	valids[0x0]	479	1			T5	1		T8	2		T14	4
auto[0]	values[2]	valids[0x1]	305	1			T5	2		T7	2		T14	1
auto[0]	values[3]	valids[0x0]	455	1			T5	4		T14	6		T84	2
auto[0]	values[3]	valids[0x1]	242	1			T5	1		T15	2		T40	1
auto[0]	values[4]	valids[0x0]	500	1			T5	2		T14	7		T84	4
auto[0]	values[4]	valids[0x1]	278	1			T5	6		T9	6		T14	6
auto[0]	values[5]	valids[0x0]	537	1			T5	1		T14	14		T15	3
auto[0]	values[5]	valids[0x1]	286	1			T5	1		T14	3		T40	2
auto[0]	values[6]	valids[0x0]	484	1			T5	4		T14	15		T15	2
auto[0]	values[6]	valids[0x1]	279	1			T14	1		T15	1		T16	3
auto[0]	values[7]	valids[0x0]	541	1			T1	2		T5	3		T7	2
auto[0]	values[7]	valids[0x1]	293	1			T5	2		T7	2		T47	4
auto[0]	values[8]	valids[0x0]	3301	1			T5	26		T7	8		T14	34
auto[0]	values[8]	valids[0x1]	1945	1			T1	6		T5	19		T8	4
auto[1]	values[0]	valids[0x0]	2741	1			T13	30		T43	11		T38	45
auto[1]	values[0]	valids[0x1]	13785	1			T13	74		T41	2		T43	46
auto[1]	values[1]	valids[0x1]	380	1			T13	7		T43	1		T38	4
auto[1]	values[2]	valids[0x0]	250	1			T13	1		T38	3		T39	2
auto[1]	values[2]	valids[0x1]	179	1			T13	4		T43	1		T38	5
auto[1]	values[3]	valids[0x0]	255	1			T13	3		T43	1		T38	6
auto[1]	values[3]	valids[0x1]	155	1			T13	2		T43	1		T38	4
auto[1]	values[4]	valids[0x0]	256	1			T13	4		T43	1		T38	2
auto[1]	values[4]	valids[0x1]	159	1			T38	7		T39	2		T15	4
auto[1]	values[5]	valids[0x0]	311	1			T13	4		T38	2		T39	1
auto[1]	values[5]	valids[0x1]	175	1			T13	5		T38	6		T39	1
auto[1]	values[6]	valids[0x0]	263	1			T13	3		T38	8		T39	1
auto[1]	values[6]	valids[0x1]	152	1			T13	2		T38	1		T39	2
auto[1]	values[7]	valids[0x0]	258	1			T13	3		T43	1		T38	3
auto[1]	values[7]	valids[0x1]	187	1			T13	2		T38	1		T39	1
auto[1]	values[8]	valids[0x0]	1691	1			T13	19		T43	6		T38	21
auto[1]	values[8]	valids[0x1]	1204	1			T13	15		T43	4		T38	16