Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3273387

1

T1

4037

T4

1243

T5

14786

auto[1]

20694

1

T5

29

T13

18

T14

378

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1159909

1

T1

4037

T4

1243

T5

66

auto[1]

2134172

1

T5

14749

T13

7672

T14

16503

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	601938	1			T1	1399		T4	317		T5	26
auto[524288:1048575]	434432	1			T1	54		T4	1		T5	520
auto[1048576:1572863]	409343	1			T1	76		T4	63		T5	1009
auto[1572864:2097151]	385132	1			T1	1057		T4	500		T5	2255
auto[2097152:2621439]	392838	1			T1	2		T4	19		T5	3185
auto[2621440:3145727]	311764	1			T1	1157		T4	15		T5	567
auto[3145728:3670015]	356527	1			T1	7		T5	3760		T8	180
auto[3670016:4194303]	402107	1			T1	285		T4	328		T5	3493

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2154254

1

T1

101

T4

77

T5

14814

auto[1]

1139827

1

T1

3936

T4

1166

T5

1

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2890069

1

T1

4037

T4

1239

T5

9279

auto[1]

404012

1

T4

4

T5

5536

T13

435

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	250118	1			T1	1399		T4	317		T5	9
auto[0]	auto[0]	auto[0:524287]	auto[1]	290858	1			T5	7		T13	642		T14	2207
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	153261	1			T1	54		T4	1		T5	5
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	206388	1			T5	1		T13	137		T14	3069
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	133118	1			T1	76		T4	63		T5	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	234588	1			T5	992		T13	512		T14	2367
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	158451	1			T1	1057		T4	496		T5	7
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	181085	1			T5	2246		T13	1054		T14	257
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	127105	1			T1	2		T4	19		T5	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	222093	1			T5	258		T13	513		T14	2644
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	106210	1			T1	1157		T4	15		T5	7
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	157867	1			T5	555		T13	4261		T14	4945
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	103358	1			T1	7		T5	7		T8	180
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	206034	1			T5	3751		T13	129		T14	265
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	115973	1			T1	285		T4	328		T5	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	226288	1			T5	1408		T14	390		T38	135
auto[0]	auto[1]	auto[0:524287]	auto[0]	1561	1			T5	1		T43	4		T38	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	56273	1			T5	1		T43	331		T15	3006
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1070	1			T5	1		T38	4		T39	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	71009	1			T5	512		T38	513		T39	1024
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	3162	1			T5	3		T13	3		T39	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	35717	1			T5	6		T13	257		T39	257
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	455	1			T4	4		T13	2		T15	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	43066	1			T13	29		T15	19		T32	2565
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	282	1			T5	1		T38	1		T15	10
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	41093	1			T5	2919		T38	567		T15	3306
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	803	1			T5	1		T13	1		T38	6
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	43743	1			T38	2		T16	260		T17	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2387	1			T13	7		T39	5		T16	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	42279	1			T13	130		T39	687		T40	2164
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	613	1			T5	3		T38	4		T16	7
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	57079	1			T5	2078		T38	835		T16	3855
auto[1]	auto[0]	auto[0:524287]	auto[0]	237	1			T5	3		T13	1		T43	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2498	1			T5	2		T13	1		T43	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	194	1			T5	1		T13	2		T14	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1886	1			T14	64		T43	7		T38	31
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	227	1			T5	1		T14	5		T32	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2188	1			T5	2		T14	79		T32	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	177	1			T5	2		T13	1		T14	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1517	1			T13	1		T14	29		T39	23
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	194	1			T5	1		T13	1		T14	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1709	1			T5	1		T14	71		T43	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	186	1			T5	1		T13	1		T14	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2426	1			T5	3		T13	2		T14	11
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	226	1			T5	1		T13	1		T14	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1836	1			T5	1		T13	1		T14	97
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	184	1			T14	2		T38	2		T50	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1589	1			T14	8		T38	6		T16	16
auto[1]	auto[1]	auto[0:524287]	auto[0]	47	1			T5	1		T43	1		T17	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	346	1			T5	2		T43	17		T77	2
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	53	1			T38	1		T50	3		T187	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	571	1			T38	1		T50	1		T187	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	47	1			T5	1		T13	1		T39	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	296	1			T5	2		T39	15		T15	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	40	1			T15	1		T32	4		T174	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	341	1			T15	4		T32	101		T79	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	33	1			T5	1		T32	1		T17	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	329	1			T5	2		T32	3		T17	25
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	53	1			T38	2		T16	1		T17	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	476	1			T38	13		T16	3		T17	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	42	1			T13	2		T32	1		T160	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	365	1			T13	3		T32	27		T160	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	42	1			T5	1		T32	1		T159	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	339	1			T32	2		T159	8		T78	20

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1740927	1			T1	101		T4	75		T5	9259
auto[0]	auto[0]	auto[1]	1131868	1			T1	3936		T4	1164		T5	1
auto[0]	auto[1]	auto[0]	393000	1			T4	2		T5	5526		T13	429
auto[0]	auto[1]	auto[1]	7592	1			T4	2		T38	1		T39	1
auto[1]	auto[0]	auto[0]	16975	1			T5	19		T13	12		T14	378
auto[1]	auto[0]	auto[1]	299	1			T43	3		T38	8		T39	1
auto[1]	auto[1]	auto[0]	3352	1			T5	10		T13	5		T43	17
auto[1]	auto[1]	auto[1]	68	1			T13	1		T43	1		T38	3