Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17754

1

T1

8

T4

14

T5

134

auto[1]

13620

1

T5

75

T7

24

T14

290

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4241	1			T5	67		T8	10		T14	101
values[1]	3862	1			T5	43		T14	209		T83	10
values[2]	3712	1			T14	62		T84	10		T15	25
values[3]	4513	1			T4	14		T5	27		T14	90
values[4]	3959	1			T14	37		T88	10		T15	22
values[5]	4048	1			T5	52		T7	24		T47	8
values[6]	3478	1			T5	20		T9	10		T14	70
values[7]	3561	1			T1	8		T14	49		T113	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3850	1			T5	22		T14	36		T97	2
values[1]	3607	1			T14	20		T84	10		T40	29
values[2]	3682	1			T4	14		T5	20		T9	10
values[3]	4152	1			T5	73		T14	50		T15	22
values[4]	3959	1			T14	119		T88	10		T114	14
values[5]	4415	1			T1	8		T5	71		T14	40
values[6]	3849	1			T14	115		T40	23		T56	8
values[7]	3860	1			T5	23		T7	24		T8	10

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	425	1			T14	26		T45	51		T68	16
auto[0]	values[0]	values[1]	317	1			T16	14		T32	67		T45	18
auto[0]	values[0]	values[2]	265	1			T14	12		T183	98		T211	14
auto[0]	values[0]	values[3]	337	1			T5	23		T174	7		T79	10
auto[0]	values[0]	values[4]	190	1			T79	12		T206	14		T177	24
auto[0]	values[0]	values[5]	307	1			T5	22		T16	10		T17	11
auto[0]	values[0]	values[6]	282	1			T40	7		T86	16		T132	12
auto[0]	values[0]	values[7]	456	1			T8	10		T46	10		T17	71
auto[0]	values[1]	values[0]	251	1			T17	56		T174	15		T19	13
auto[0]	values[1]	values[1]	329	1			T16	85		T32	12		T17	11
auto[0]	values[1]	values[2]	198	1			T45	5		T174	14		T67	8
auto[0]	values[1]	values[3]	208	1			T5	11		T197	16		T212	10
auto[0]	values[1]	values[4]	323	1			T114	14		T68	14		T158	20
auto[0]	values[1]	values[5]	364	1			T83	10		T16	16		T202	8
auto[0]	values[1]	values[6]	375	1			T14	30		T32	48		T45	16
auto[0]	values[1]	values[7]	303	1			T5	17		T14	167		T40	7
auto[0]	values[2]	values[0]	392	1			T15	11		T32	21		T174	12
auto[0]	values[2]	values[1]	138	1			T14	6		T32	11		T213	18
auto[0]	values[2]	values[2]	111	1			T185	11		T214	11		T215	2
auto[0]	values[2]	values[3]	148	1			T216	36		T150	16		T217	15
auto[0]	values[2]	values[4]	429	1			T16	12		T158	32		T79	9
auto[0]	values[2]	values[5]	303	1			T45	16		T206	19		T135	4
auto[0]	values[2]	values[6]	339	1			T14	6		T17	9		T68	32
auto[0]	values[2]	values[7]	219	1			T190	90		T195	22		T218	17
auto[0]	values[3]	values[0]	341	1			T183	15		T131	11		T196	32
auto[0]	values[3]	values[1]	379	1			T40	23		T174	9		T68	14
auto[0]	values[3]	values[2]	467	1			T4	14		T40	10		T174	8
auto[0]	values[3]	values[3]	307	1			T5	23		T207	4		T183	14
auto[0]	values[3]	values[4]	238	1			T14	12		T178	18		T45	12
auto[0]	values[3]	values[5]	198	1			T177	16		T219	24		T220	19
auto[0]	values[3]	values[6]	342	1			T17	14		T20	15		T175	6
auto[0]	values[3]	values[7]	249	1			T32	13		T221	4		T199	12
auto[0]	values[4]	values[0]	208	1			T32	9		T17	14		T187	22
auto[0]	values[4]	values[1]	194	1			T67	11		T222	12		T206	27
auto[0]	values[4]	values[2]	196	1			T17	14		T68	12		T183	10
auto[0]	values[4]	values[3]	510	1			T67	93		T68	10		T79	45
auto[0]	values[4]	values[4]	223	1			T88	10		T32	24		T205	15
auto[0]	values[4]	values[5]	392	1			T15	11		T16	14		T32	16
auto[0]	values[4]	values[6]	194	1			T14	12		T56	8		T203	8
auto[0]	values[4]	values[7]	361	1			T45	8		T189	13		T205	10
auto[0]	values[5]	values[0]	137	1			T5	11		T17	5		T183	14
auto[0]	values[5]	values[1]	220	1			T186	14		T45	5		T179	8
auto[0]	values[5]	values[2]	288	1			T44	18		T68	12		T79	15
auto[0]	values[5]	values[3]	234	1			T15	15		T72	4		T183	14
auto[0]	values[5]	values[4]	316	1			T40	12		T45	9		T223	4
auto[0]	values[5]	values[5]	346	1			T5	23		T16	9		T19	10
auto[0]	values[5]	values[6]	242	1			T32	10		T183	29		T205	58
auto[0]	values[5]	values[7]	289	1			T40	13		T45	10		T174	25
auto[0]	values[6]	values[0]	74	1			T97	2		T174	12		T175	10
auto[0]	values[6]	values[1]	227	1			T131	10		T185	8		T33	7
auto[0]	values[6]	values[2]	256	1			T5	4		T9	10		T224	2
auto[0]	values[6]	values[3]	231	1			T14	11		T225	6		T226	16
auto[0]	values[6]	values[4]	154	1			T17	13		T176	4		T175	18
auto[0]	values[6]	values[5]	281	1			T14	15		T17	9		T227	9
auto[0]	values[6]	values[6]	286	1			T16	13		T32	14		T17	7
auto[0]	values[6]	values[7]	312	1			T187	20		T175	16		T184	61
auto[0]	values[7]	values[0]	188	1			T16	6		T19	16		T196	11
auto[0]	values[7]	values[1]	289	1			T17	14		T228	10		T229	12
auto[0]	values[7]	values[2]	340	1			T230	17		T79	12		T19	11
auto[0]	values[7]	values[3]	350	1			T17	10		T79	10		T183	65
auto[0]	values[7]	values[4]	244	1			T14	18		T189	47		T136	9
auto[0]	values[7]	values[5]	167	1			T1	8		T14	13		T40	17
auto[0]	values[7]	values[6]	223	1			T32	14		T174	13		T187	21
auto[0]	values[7]	values[7]	252	1			T113	4		T17	23		T181	20
auto[1]	values[0]	values[0]	118	1			T14	10		T45	11		T68	8
auto[1]	values[0]	values[1]	250	1			T16	6		T32	8		T45	32
auto[1]	values[0]	values[2]	183	1			T14	53		T183	11		T231	16
auto[1]	values[0]	values[3]	243	1			T5	3		T174	13		T79	44
auto[1]	values[0]	values[4]	250	1			T79	8		T206	6		T177	16
auto[1]	values[0]	values[5]	300	1			T5	19		T16	192		T17	9
auto[1]	values[0]	values[6]	117	1			T40	16		T132	8		T184	9
auto[1]	values[0]	values[7]	201	1			T17	8		T174	4		T67	9
auto[1]	values[1]	values[0]	84	1			T17	8		T174	5		T19	7
auto[1]	values[1]	values[1]	173	1			T16	14		T32	8		T17	9
auto[1]	values[1]	values[2]	176	1			T45	27		T174	13		T180	8
auto[1]	values[1]	values[3]	250	1			T5	9		T20	6		T132	24
auto[1]	values[1]	values[4]	211	1			T48	20		T68	6		T158	5
auto[1]	values[1]	values[5]	282	1			T16	4		T45	5		T79	2
auto[1]	values[1]	values[6]	176	1			T14	6		T32	7		T45	11
auto[1]	values[1]	values[7]	159	1			T5	6		T14	6		T40	13
auto[1]	values[2]	values[0]	435	1			T15	14		T32	204		T174	8
auto[1]	values[2]	values[1]	216	1			T14	14		T84	10		T32	12
auto[1]	values[2]	values[2]	84	1			T185	13		T214	10		T33	9
auto[1]	values[2]	values[3]	73	1			T150	23		T217	6		T194	12
auto[1]	values[2]	values[4]	273	1			T16	15		T158	5		T79	11
auto[1]	values[2]	values[5]	297	1			T45	4		T206	7		T232	14
auto[1]	values[2]	values[6]	208	1			T14	36		T17	11		T68	16
auto[1]	values[2]	values[7]	47	1			T190	9		T195	7		T218	7
auto[1]	values[3]	values[0]	319	1			T183	53		T131	9		T196	10
auto[1]	values[3]	values[1]	163	1			T40	6		T174	11		T68	11
auto[1]	values[3]	values[2]	374	1			T40	10		T174	12		T79	8
auto[1]	values[3]	values[3]	325	1			T5	4		T183	48		T177	11
auto[1]	values[3]	values[4]	374	1			T14	78		T45	182		T70	10
auto[1]	values[3]	values[5]	121	1			T177	4		T220	1		T233	10
auto[1]	values[3]	values[6]	206	1			T17	12		T20	5		T175	18
auto[1]	values[3]	values[7]	110	1			T32	7		T199	12		T136	13
auto[1]	values[4]	values[0]	226	1			T32	11		T17	12		T187	22
auto[1]	values[4]	values[1]	155	1			T67	86		T222	8		T206	16
auto[1]	values[4]	values[2]	247	1			T17	6		T68	8		T183	43
auto[1]	values[4]	values[3]	206	1			T67	40		T68	10		T79	10
auto[1]	values[4]	values[4]	154	1			T32	8		T205	37		T184	9
auto[1]	values[4]	values[5]	354	1			T15	11		T16	94		T32	4
auto[1]	values[4]	values[6]	136	1			T14	25		T222	9		T189	25
auto[1]	values[4]	values[7]	203	1			T45	36		T189	10		T205	10
auto[1]	values[5]	values[0]	260	1			T5	11		T17	15		T183	6
auto[1]	values[5]	values[1]	219	1			T45	148		T79	8		T199	6
auto[1]	values[5]	values[2]	240	1			T68	8		T79	8		T132	7
auto[1]	values[5]	values[3]	178	1			T15	7		T183	6		T132	34
auto[1]	values[5]	values[4]	309	1			T40	8		T45	11		T132	6
auto[1]	values[5]	values[5]	240	1			T5	7		T16	121		T19	10
auto[1]	values[5]	values[6]	288	1			T32	10		T234	4		T183	6
auto[1]	values[5]	values[7]	242	1			T7	24		T47	8		T40	7
auto[1]	values[6]	values[0]	143	1			T174	11		T175	11		T206	22
auto[1]	values[6]	values[1]	224	1			T131	10		T185	12		T33	120
auto[1]	values[6]	values[2]	111	1			T5	16		T206	12		T199	8
auto[1]	values[6]	values[3]	342	1			T14	39		T132	47		T205	7
auto[1]	values[6]	values[4]	105	1			T17	7		T175	4		T132	7
auto[1]	values[6]	values[5]	217	1			T14	5		T17	11		T227	11
auto[1]	values[6]	values[6]	292	1			T16	12		T32	6		T17	13
auto[1]	values[6]	values[7]	223	1			T187	2		T175	4		T184	6
auto[1]	values[7]	values[0]	249	1			T16	14		T19	48		T196	21
auto[1]	values[7]	values[1]	114	1			T17	7		T235	10		T195	10
auto[1]	values[7]	values[2]	146	1			T79	8		T19	9		T183	7
auto[1]	values[7]	values[3]	210	1			T17	10		T79	10		T183	12
auto[1]	values[7]	values[4]	166	1			T14	11		T189	8		T136	14
auto[1]	values[7]	values[5]	246	1			T14	7		T40	3		T174	53
auto[1]	values[7]	values[6]	143	1			T32	6		T49	16		T174	7
auto[1]	values[7]	values[7]	234	1			T17	51		T196	73		T204	42