Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2739229	1			T1	1		T4	1		T5	49711
all_pins[1]	2739229	1			T1	1		T4	1		T5	49711
all_pins[2]	2739229	1			T1	1		T4	1		T5	49711
all_pins[3]	2739229	1			T1	1		T4	1		T5	49711
all_pins[4]	2739229	1			T1	1		T4	1		T5	49711
all_pins[5]	2739229	1			T1	1		T4	1		T5	49711
all_pins[6]	2739229	1			T1	1		T4	1		T5	49711
all_pins[7]	2739229	1			T1	1		T4	1		T5	49711

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21825018	1			T1	8		T4	8		T5	397688
values[0x1]	88814	1			T6	45		T15	11		T17	9
transitions[0x0=>0x1]	87652	1			T6	28		T15	10		T17	5
transitions[0x1=>0x0]	87666	1			T6	28		T15	10		T17	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2738769	1			T1	1		T4	1		T5	49711
all_pins[0]	values[0x1]	460	1			T6	4		T15	3		T17	1
all_pins[0]	transitions[0x0=>0x1]	276	1			T15	3		T22	1		T31	4
all_pins[0]	transitions[0x1=>0x0]	498	1			T6	7		T15	2		T19	1
all_pins[1]	values[0x0]	2738547	1			T1	1		T4	1		T5	49711
all_pins[1]	values[0x1]	682	1			T6	11		T15	2		T17	1
all_pins[1]	transitions[0x0=>0x1]	553	1			T6	9		T15	2		T19	1
all_pins[1]	transitions[0x1=>0x0]	173	1			T15	1		T20	1		T22	1
all_pins[2]	values[0x0]	2738927	1			T1	1		T4	1		T5	49711
all_pins[2]	values[0x1]	302	1			T6	2		T15	1		T17	1
all_pins[2]	transitions[0x0=>0x1]	246	1			T15	1		T17	1		T20	1
all_pins[2]	transitions[0x1=>0x0]	144	1			T6	8		T15	1		T22	1
all_pins[3]	values[0x0]	2739029	1			T1	1		T4	1		T5	49711
all_pins[3]	values[0x1]	200	1			T6	10		T15	1		T22	2
all_pins[3]	transitions[0x0=>0x1]	135	1			T6	6		T15	1		T22	2
all_pins[3]	transitions[0x1=>0x0]	118	1			T15	1		T17	2		T20	3
all_pins[4]	values[0x0]	2739046	1			T1	1		T4	1		T5	49711
all_pins[4]	values[0x1]	183	1			T6	4		T15	1		T17	2
all_pins[4]	transitions[0x0=>0x1]	139	1			T6	3		T17	1		T20	2
all_pins[4]	transitions[0x1=>0x0]	996	1			T6	4		T15	2		T19	2
all_pins[5]	values[0x0]	2738189	1			T1	1		T4	1		T5	49711
all_pins[5]	values[0x1]	1040	1			T6	5		T15	3		T17	1
all_pins[5]	transitions[0x0=>0x1]	456	1			T6	3		T15	3		T17	1
all_pins[5]	transitions[0x1=>0x0]	85182	1			T6	2		T19	1		T20	1
all_pins[6]	values[0x0]	2653463	1			T1	1		T4	1		T5	49711
all_pins[6]	values[0x1]	85766	1			T6	4		T19	1		T20	1
all_pins[6]	transitions[0x0=>0x1]	85717	1			T6	4		T19	1		T20	1
all_pins[6]	transitions[0x1=>0x0]	132	1			T6	5		T17	3		T20	3
all_pins[7]	values[0x0]	2739048	1			T1	1		T4	1		T5	49711
all_pins[7]	values[0x1]	181	1			T6	5		T17	3		T20	3
all_pins[7]	transitions[0x0=>0x1]	130	1			T6	3		T17	2		T20	3
all_pins[7]	transitions[0x1=>0x0]	423	1			T6	2		T15	3		T22	1