Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	383	1			T1	2		T5	1		T8	2
auto[ReadAddrCrossIntoMailbox]	264	1			T8	2		T14	4		T114	2
auto[ReadAddrCrossOutOfMailbox]	272	1			T14	3		T40	3		T16	4
auto[ReadAddrCrossAllMailbox]	211	1			T1	4		T8	4		T14	5
auto[ReadAddrOutsideMailbox]	3347	1			T1	2		T5	39		T7	8

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2200

1

T1

4

T5

26

T7

4

auto[1]

2277

1

T1

4

T5

14

T7

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	722	1			T1	6		T5	6		T9	2
read_ops[0x0b]	795	1			T5	13		T7	4		T8	4
read_ops[0x3b]	778	1			T5	6		T7	4		T8	4
read_ops[0x6b]	754	1			T5	6		T14	9		T15	1
read_ops[0xbb]	664	1			T5	6		T14	7		T44	2
read_ops[0xeb]	764	1			T1	2		T5	3		T8	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T1	1		T14	1		T45	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T1	1		T17	1		T174	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T17	1		T67	1		T68	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T45	1		T222	1		T235	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T16	3		T212	1		T67	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	14	1			T212	1		T132	2		T236	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T1	1		T19	1		T205	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T1	1		T45	1		T187	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	282	1			T1	1		T5	3		T9	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	258	1			T1	1		T5	3		T9	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T114	1		T15	1		T32	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T114	1		T79	1		T183	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T17	1		T183	1		T136	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T14	1		T67	1		T68	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T45	1		T174	1		T187	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T40	2		T175	1		T237	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T8	1		T114	1		T174	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T8	1		T14	1		T114	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	300	1			T5	10		T7	2		T8	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	299	1			T5	3		T7	2		T8	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T5	1		T8	1		T32	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T8	1		T16	1		T17	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T16	1		T32	1		T174	3
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T17	1		T45	1		T67	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T40	1		T16	1		T32	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T187	2		T68	1		T183	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T8	1		T14	3		T32	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T8	1		T45	1		T174	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	285	1			T5	2		T7	2		T14	5
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	287	1			T5	3		T7	2		T14	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T14	1		T16	1		T32	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T67	1		T72	1		T191	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T16	2		T67	1		T132	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T14	1		T17	1		T189	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	14	1			T45	1		T175	1		T131	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T17	2		T45	1		T68	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T16	1		T174	1		T175	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T222	1		T132	1		T205	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	269	1			T5	3		T14	1		T40	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	284	1			T5	3		T14	6		T15	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T203	1		T207	1		T79	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T16	2		T174	1		T203	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T114	1		T15	1		T68	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T114	1		T17	1		T174	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T14	2		T174	1		T67	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T17	1		T45	1		T72	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T14	1		T33	1		T236	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T16	1		T45	1		T206	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	230	1			T5	6		T14	1		T44	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	265	1			T14	3		T44	1		T48	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T17	2		T158	1		T132	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T14	1		T174	1		T67	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T8	1		T14	1		T183	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T8	1		T14	1		T32	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T17	2		T19	1		T183	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T14	1		T174	1		T67	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T1	1		T187	1		T67	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T1	1		T174	2		T67	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	295	1			T5	1		T14	2		T46	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	293	1			T5	2		T14	5		T46	1