Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4014	1			T5	45		T8	10		T44	18
values[1]	4102	1			T5	47		T9	10		T14	49
values[2]	4851	1			T5	30		T14	285		T83	10
values[3]	3305	1			T4	14		T7	24		T14	73
values[4]	4022	1			T1	8		T5	20		T40	20
values[5]	4097	1			T5	26		T14	85		T97	2
values[6]	3320	1			T5	41		T14	126		T84	10
values[7]	3663	1			T114	14		T40	29		T32	55

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4218	1			T5	20		T14	36		T47	8
values[1]	4058	1			T1	8		T5	79		T7	24
values[2]	3912	1			T5	20		T14	155		T40	23
values[3]	4017	1			T4	14		T5	20		T14	106
values[4]	3586	1			T5	47		T113	4		T15	22
values[5]	3697	1			T8	10		T14	29		T15	25
values[6]	4166	1			T5	23		T14	57		T83	10
values[7]	3720	1			T14	193		T44	18		T46	10

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30601

1

T1

8

T4

14

T5

202

auto[1]

773

1

T5

7

T7

2

T14

16

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	521	1			T17	20		T45	60		T79	45
auto[0]	values[0]	values[1]	624	1			T5	22		T174	20		T238	24
auto[0]	values[0]	values[2]	340	1			T17	20		T174	20		T86	16
auto[0]	values[0]	values[3]	545	1			T174	20		T187	35		T68	28
auto[0]	values[0]	values[4]	621	1			T15	22		T16	52		T45	47
auto[0]	values[0]	values[5]	494	1			T8	10		T40	20		T17	27
auto[0]	values[0]	values[6]	260	1			T5	23		T187	23		T19	20
auto[0]	values[0]	values[7]	520	1			T44	18		T131	20		T205	20
auto[0]	values[1]	values[0]	455	1			T16	22		T174	20		T158	20
auto[0]	values[1]	values[1]	384	1			T5	25		T9	10		T15	21
auto[0]	values[1]	values[2]	447	1			T5	20		T206	22		T135	4
auto[0]	values[1]	values[3]	593	1			T178	18		T207	4		T19	27
auto[0]	values[1]	values[4]	377	1			T79	53		T184	24		T239	43
auto[0]	values[1]	values[5]	505	1			T14	28		T32	20		T67	20
auto[0]	values[1]	values[6]	898	1			T14	20		T16	130		T17	20
auto[0]	values[1]	values[7]	347	1			T17	46		T45	20		T174	100
auto[0]	values[2]	values[0]	641	1			T32	20		T17	77		T158	25
auto[0]	values[2]	values[1]	685	1			T5	27		T14	41		T227	20
auto[0]	values[2]	values[2]	508	1			T67	94		T79	20		T183	63
auto[0]	values[2]	values[3]	546	1			T14	49		T16	24		T32	20
auto[0]	values[2]	values[4]	514	1			T186	14		T68	20		T136	33
auto[0]	values[2]	values[5]	583	1			T15	25		T16	200		T17	45
auto[0]	values[2]	values[6]	689	1			T83	10		T40	20		T67	20
auto[0]	values[2]	values[7]	566	1			T14	189		T45	16		T19	44
auto[0]	values[3]	values[0]	589	1			T14	36		T47	8		T32	39
auto[0]	values[3]	values[1]	234	1			T7	22		T32	22		T68	24
auto[0]	values[3]	values[2]	533	1			T32	20		T79	23		T183	109
auto[0]	values[3]	values[3]	401	1			T4	14		T88	10		T68	40
auto[0]	values[3]	values[4]	410	1			T16	20		T32	30		T45	20
auto[0]	values[3]	values[5]	457	1			T79	68		T189	23		T87	2
auto[0]	values[3]	values[6]	366	1			T14	36		T17	27		T68	19
auto[0]	values[3]	values[7]	257	1			T175	19		T136	52		T185	20
auto[0]	values[4]	values[0]	422	1			T5	20		T68	25		T237	4
auto[0]	values[4]	values[1]	410	1			T1	8		T40	20		T240	4
auto[0]	values[4]	values[2]	448	1			T191	14		T79	54		T241	6
auto[0]	values[4]	values[3]	441	1			T17	64		T19	41		T242	2
auto[0]	values[4]	values[4]	457	1			T180	4		T230	17		T158	19
auto[0]	values[4]	values[5]	433	1			T32	18		T45	19		T67	41
auto[0]	values[4]	values[6]	680	1			T16	19		T45	152		T67	88
auto[0]	values[4]	values[7]	635	1			T16	106		T45	188		T243	20
auto[0]	values[5]	values[0]	583	1			T56	8		T68	27		T244	4
auto[0]	values[5]	values[1]	592	1			T79	18		T183	20		T206	22
auto[0]	values[5]	values[2]	656	1			T14	61		T40	22		T32	198
auto[0]	values[5]	values[3]	435	1			T14	19		T17	20		T205	31
auto[0]	values[5]	values[4]	501	1			T5	24		T113	4		T19	16
auto[0]	values[5]	values[5]	475	1			T185	20		T214	19		T245	18
auto[0]	values[5]	values[6]	295	1			T97	2		T49	12		T174	20
auto[0]	values[5]	values[7]	440	1			T16	46		T32	95		T176	4
auto[0]	values[6]	values[0]	513	1			T40	20		T202	8		T197	16
auto[0]	values[6]	values[1]	320	1			T174	27		T234	4		T206	45
auto[0]	values[6]	values[2]	418	1			T14	87		T158	20		T136	31
auto[0]	values[6]	values[3]	624	1			T5	20		T14	36		T48	16
auto[0]	values[6]	values[4]	356	1			T5	21		T17	20		T79	40
auto[0]	values[6]	values[5]	217	1			T68	19		T33	20		T233	20
auto[0]	values[6]	values[6]	405	1			T84	10		T45	43		T158	37
auto[0]	values[6]	values[7]	376	1			T46	10		T17	20		T203	8
auto[0]	values[7]	values[0]	404	1			T114	14		T45	32		T183	35
auto[0]	values[7]	values[1]	709	1			T17	19		T45	81		T174	20
auto[0]	values[7]	values[2]	431	1			T67	19		T19	20		T131	53
auto[0]	values[7]	values[3]	341	1			T40	29		T67	42		T19	24
auto[0]	values[7]	values[4]	262	1			T211	14		T34	44		T246	20
auto[0]	values[7]	values[5]	440	1			T174	19		T19	20		T33	81
auto[0]	values[7]	values[6]	469	1			T32	55		T20	18		T175	20
auto[0]	values[7]	values[7]	503	1			T45	27		T187	21		T132	19
auto[1]	values[0]	values[0]	5	1			T45	2		T79	1		T205	2
auto[1]	values[0]	values[1]	15	1			T245	1		T195	4		T247	1
auto[1]	values[0]	values[2]	7	1			T248	1		T193	1		T249	2
auto[1]	values[0]	values[3]	16	1			T187	2		T250	4		T185	3
auto[1]	values[0]	values[4]	17	1			T16	1		T45	3		T187	1
auto[1]	values[0]	values[5]	18	1			T189	1		T196	1		T177	1
auto[1]	values[0]	values[6]	3	1			T205	1		T194	2		-	-
auto[1]	values[0]	values[7]	8	1			T196	1		T248	4		T194	1
auto[1]	values[1]	values[0]	12	1			T16	3		T185	1		T220	1
auto[1]	values[1]	values[1]	13	1			T5	2		T15	1		T171	8
auto[1]	values[1]	values[2]	19	1			T206	3		T177	1		T204	4
auto[1]	values[1]	values[3]	8	1			T19	1		T132	2		T233	1
auto[1]	values[1]	values[4]	10	1			T79	2		T239	1		T251	4
auto[1]	values[1]	values[5]	15	1			T14	1		T222	1		T199	4
auto[1]	values[1]	values[6]	13	1			T132	3		T136	1		T185	2
auto[1]	values[1]	values[7]	6	1			T174	1		T158	2		T252	1
auto[1]	values[2]	values[0]	14	1			T17	2		T19	1		T196	2
auto[1]	values[2]	values[1]	16	1			T5	3		T14	1		T183	1
auto[1]	values[2]	values[2]	20	1			T67	3		T183	1		T194	1
auto[1]	values[2]	values[3]	14	1			T14	1		T16	3		T243	3
auto[1]	values[2]	values[4]	9	1			T194	3		T253	5		T254	1
auto[1]	values[2]	values[5]	12	1			T16	2		T17	2		T190	1
auto[1]	values[2]	values[6]	14	1			T132	2		T205	1		T252	2
auto[1]	values[2]	values[7]	20	1			T14	4		T45	4		T19	2
auto[1]	values[3]	values[0]	5	1			T32	1		T196	3		T193	1
auto[1]	values[3]	values[1]	9	1			T7	2		T32	1		T68	1
auto[1]	values[3]	values[2]	8	1			T184	1		T33	3		T252	1
auto[1]	values[3]	values[3]	3	1			T204	1		T246	1		T255	1
auto[1]	values[3]	values[4]	4	1			T32	2		T195	1		T193	1
auto[1]	values[3]	values[5]	6	1			T79	1		T193	1		T249	2
auto[1]	values[3]	values[6]	13	1			T14	1		T17	3		T68	1
auto[1]	values[3]	values[7]	10	1			T175	1		T136	1		T194	2
auto[1]	values[4]	values[0]	8	1			T185	4		T33	1		T218	2
auto[1]	values[4]	values[1]	6	1			T52	1		T246	2		T54	2
auto[1]	values[4]	values[2]	18	1			T20	1		T256	4		T235	1
auto[1]	values[4]	values[3]	9	1			T132	2		T193	1		T217	2
auto[1]	values[4]	values[4]	13	1			T180	4		T158	1		T177	1
auto[1]	values[4]	values[5]	7	1			T32	2		T45	1		T183	1
auto[1]	values[4]	values[6]	23	1			T16	1		T45	1		T67	4
auto[1]	values[4]	values[7]	12	1			T16	2		T45	6		T189	1
auto[1]	values[5]	values[0]	18	1			T184	1		T204	2		T257	1
auto[1]	values[5]	values[1]	16	1			T79	2		T206	1		T196	2
auto[1]	values[5]	values[2]	24	1			T14	4		T40	1		T32	7
auto[1]	values[5]	values[3]	13	1			T14	1		T258	2		T52	1
auto[1]	values[5]	values[4]	20	1			T5	2		T19	4		T183	1
auto[1]	values[5]	values[5]	19	1			T214	2		T245	2		T150	1
auto[1]	values[5]	values[6]	7	1			T49	4		T175	1		T190	1
auto[1]	values[5]	values[7]	3	1			T259	1		T260	1		T255	1
auto[1]	values[6]	values[0]	11	1			T190	1		T261	2		T262	1
auto[1]	values[6]	values[1]	11	1			T206	4		T177	1		T185	2
auto[1]	values[6]	values[2]	17	1			T14	3		T136	2		T239	1
auto[1]	values[6]	values[3]	15	1			T48	4		T40	1		T17	3
auto[1]	values[6]	values[4]	10	1			T263	3		T54	2		T253	1
auto[1]	values[6]	values[5]	5	1			T68	1		T264	1		T194	2
auto[1]	values[6]	values[6]	16	1			T45	1		T190	4		T265	3
auto[1]	values[6]	values[7]	6	1			T206	2		T33	3		T266	1
auto[1]	values[7]	values[0]	17	1			T175	1		T136	1		T267	2
auto[1]	values[7]	values[1]	14	1			T17	2		T19	2		T131	1
auto[1]	values[7]	values[2]	18	1			T67	1		T196	3		T33	5
auto[1]	values[7]	values[3]	13	1			T67	1		T33	1		T195	3
auto[1]	values[7]	values[4]	5	1			T34	1		T246	2		T249	2
auto[1]	values[7]	values[5]	11	1			T174	1		T33	3		T246	2
auto[1]	values[7]	values[6]	15	1			T20	2		T175	2		T220	2
auto[1]	values[7]	values[7]	11	1			T187	1		T132	1		T239	1