Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1800

1

T5

13

T10

10

T13

11

auto[1]

1774

1

T5

7

T10

10

T13

7

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1887

1

T5

20

T10

20

T13

16

auto[1]

1687

1

T13

2

T24

3

T26

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2839

1

T5

12

T10

12

T13

8

auto[1]

735

1

T5

8

T10

8

T13

10

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	728	1			T5	3		T10	5		T13	4
valid[1]	703	1			T5	3		T10	2		T13	2
valid[2]	743	1			T5	4		T10	5		T13	6
valid[3]	711	1			T5	7		T10	3		T13	1
valid[4]	689	1			T5	3		T10	5		T13	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	121	1			T13	1		T15	3		T50	1
auto[0]	auto[0]	valid[0]	auto[1]	171	1			T13	1		T26	1		T27	6
auto[0]	auto[0]	valid[1]	auto[0]	112	1			T5	2		T10	1		T15	1
auto[0]	auto[0]	valid[1]	auto[1]	173	1			T24	2		T27	3		T30	1
auto[0]	auto[0]	valid[2]	auto[0]	103	1			T5	1		T10	2		T15	2
auto[0]	auto[0]	valid[2]	auto[1]	182	1			T13	1		T27	6		T51	1
auto[0]	auto[0]	valid[3]	auto[0]	134	1			T5	4		T13	1		T15	3
auto[0]	auto[0]	valid[3]	auto[1]	159	1			T27	5		T57	3		T279	1
auto[0]	auto[0]	valid[4]	auto[0]	115	1			T5	1		T10	2		T13	1
auto[0]	auto[0]	valid[4]	auto[1]	165	1			T27	5		T15	2		T51	1
auto[0]	auto[1]	valid[0]	auto[0]	132	1			T10	1		T15	8		T51	3
auto[0]	auto[1]	valid[0]	auto[1]	154	1			T27	5		T51	1		T57	6
auto[0]	auto[1]	valid[1]	auto[0]	109	1			T5	1		T13	1		T15	1
auto[0]	auto[1]	valid[1]	auto[1]	155	1			T26	1		T27	4		T30	1
auto[0]	auto[1]	valid[2]	auto[0]	118	1			T10	2		T26	1		T15	2
auto[0]	auto[1]	valid[2]	auto[1]	194	1			T26	1		T27	2		T28	1
auto[0]	auto[1]	valid[3]	auto[0]	99	1			T5	3		T10	2		T15	4
auto[0]	auto[1]	valid[3]	auto[1]	172	1			T26	1		T27	4		T28	2
auto[0]	auto[1]	valid[4]	auto[0]	109	1			T10	2		T13	2		T26	2
auto[0]	auto[1]	valid[4]	auto[1]	162	1			T24	1		T27	7		T28	1
auto[1]	auto[0]	valid[0]	auto[0]	65	1			T5	2		T10	2		T13	1
auto[1]	auto[0]	valid[1]	auto[0]	73	1			T10	1		T15	2		T51	1
auto[1]	auto[0]	valid[2]	auto[0]	77	1			T5	1		T13	3		T29	1
auto[1]	auto[0]	valid[3]	auto[0]	75	1			T10	1		T15	3		T16	1
auto[1]	auto[0]	valid[4]	auto[0]	75	1			T5	2		T10	1		T13	2
auto[1]	auto[1]	valid[0]	auto[0]	85	1			T5	1		T10	2		T13	1
auto[1]	auto[1]	valid[1]	auto[0]	81	1			T13	1		T15	1		T51	2
auto[1]	auto[1]	valid[2]	auto[0]	69	1			T5	2		T10	1		T13	2
auto[1]	auto[1]	valid[3]	auto[0]	72	1			T15	1		T16	3		T279	3
auto[1]	auto[1]	valid[4]	auto[0]	63	1			T15	5		T50	1		T287	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal