Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	770	1			T6	21		T15	7		T17	4
all_values[1]	770	1			T6	21		T15	7		T17	4
all_values[2]	770	1			T6	21		T15	7		T17	4
all_values[3]	770	1			T6	21		T15	7		T17	4
all_values[4]	770	1			T6	21		T15	7		T17	4
all_values[5]	770	1			T6	21		T15	7		T17	4
all_values[6]	770	1			T6	21		T15	7		T17	4
all_values[7]	770	1			T6	21		T15	7		T17	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3261

1

T6

86

T15

30

T17

20

auto[1]

2899

1

T6

82

T15

26

T17

12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2472

1

T6

68

T15

25

T17

6

auto[1]

3688

1

T6

100

T15

31

T17

26

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3561

1

T6

102

T15

31

T17

14

auto[1]

2599

1

T6

66

T15

25

T17

18

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	145	1			T6	4		T19	2		T20	3
all_values[0]	auto[0]	auto[0]	auto[1]	83	1			T6	4		T22	2		T31	3
all_values[0]	auto[0]	auto[1]	auto[0]	133	1			T6	6		T15	1		T17	2
all_values[0]	auto[0]	auto[1]	auto[1]	66	1			T6	2		T15	2		T31	4
all_values[0]	auto[1]	auto[0]	auto[1]	187	1			T6	3		T15	3		T17	1
all_values[0]	auto[1]	auto[1]	auto[1]	156	1			T6	2		T15	1		T17	1
all_values[1]	auto[0]	auto[0]	auto[0]	153	1			T6	3		T15	1		T17	1
all_values[1]	auto[0]	auto[0]	auto[1]	85	1			T6	1		T15	1		T17	1
all_values[1]	auto[0]	auto[1]	auto[0]	116	1			T6	3		T15	1		T19	1
all_values[1]	auto[0]	auto[1]	auto[1]	85	1			T6	5		T19	1		T20	2
all_values[1]	auto[1]	auto[0]	auto[1]	167	1			T6	1		T15	1		T17	1
all_values[1]	auto[1]	auto[1]	auto[1]	164	1			T6	8		T15	3		T17	1
all_values[2]	auto[0]	auto[0]	auto[0]	157	1			T6	9		T15	2		T20	3
all_values[2]	auto[0]	auto[0]	auto[1]	80	1			T17	2		T20	1		T31	1
all_values[2]	auto[0]	auto[1]	auto[0]	143	1			T6	3		T15	2		T19	1
all_values[2]	auto[0]	auto[1]	auto[1]	70	1			T6	1		T22	1		T31	3
all_values[2]	auto[1]	auto[0]	auto[1]	178	1			T6	8		T15	2		T17	1
all_values[2]	auto[1]	auto[1]	auto[1]	142	1			T15	1		T17	1		T20	2
all_values[3]	auto[0]	auto[0]	auto[0]	150	1			T6	1		T17	1		T19	1
all_values[3]	auto[0]	auto[0]	auto[1]	85	1			T6	3		T15	1		T17	1
all_values[3]	auto[0]	auto[1]	auto[0]	127	1			T6	1		T15	1		T19	1
all_values[3]	auto[0]	auto[1]	auto[1]	86	1			T6	5		T20	1		T22	1
all_values[3]	auto[1]	auto[0]	auto[1]	166	1			T6	10		T15	4		T17	2
all_values[3]	auto[1]	auto[1]	auto[1]	156	1			T6	1		T15	1		T19	2
all_values[4]	auto[0]	auto[0]	auto[0]	160	1			T6	5		T15	1		T19	1
all_values[4]	auto[0]	auto[0]	auto[1]	64	1			T6	3		T15	1		T17	1
all_values[4]	auto[0]	auto[1]	auto[0]	139	1			T6	4		T15	1		T22	3
all_values[4]	auto[0]	auto[1]	auto[1]	83	1			T6	1		T15	1		T17	1
all_values[4]	auto[1]	auto[0]	auto[1]	173	1			T6	1		T15	3		T17	1
all_values[4]	auto[1]	auto[1]	auto[1]	151	1			T6	7		T17	1		T19	2
all_values[5]	auto[0]	auto[0]	auto[0]	246	1			T6	6		T15	1		T20	2
all_values[5]	auto[0]	auto[1]	auto[0]	208	1			T6	5		T15	2		T17	1
all_values[5]	auto[1]	auto[0]	auto[1]	155	1			T6	1		T15	1		T17	2
all_values[5]	auto[1]	auto[1]	auto[1]	161	1			T6	9		T15	3		T17	1
all_values[6]	auto[0]	auto[0]	auto[0]	167	1			T6	7		T15	4		T19	1
all_values[6]	auto[0]	auto[0]	auto[1]	95	1			T6	1		T17	1		T157	1
all_values[6]	auto[0]	auto[1]	auto[0]	134	1			T6	4		T15	3		T19	1
all_values[6]	auto[0]	auto[1]	auto[1]	59	1			T6	1		T31	1		T148	2
all_values[6]	auto[1]	auto[0]	auto[1]	180	1			T6	4		T17	3		T20	1
all_values[6]	auto[1]	auto[1]	auto[1]	135	1			T6	4		T19	2		T20	1
all_values[7]	auto[0]	auto[0]	auto[0]	143	1			T6	3		T15	3		T17	1
all_values[7]	auto[0]	auto[0]	auto[1]	70	1			T6	4		T20	1		T31	2
all_values[7]	auto[0]	auto[1]	auto[0]	151	1			T6	4		T15	2		T19	2
all_values[7]	auto[0]	auto[1]	auto[1]	78	1			T6	3		T17	1		T22	1
all_values[7]	auto[1]	auto[0]	auto[1]	172	1			T6	4		T15	1		T19	1
all_values[7]	auto[1]	auto[1]	auto[1]	156	1			T6	3		T15	1		T17	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal