Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45939

1

T5

423

T10

446

T12

2

auto[1]

17612

1

T13

43

T24

3

T26

32

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46518

1

T5

272

T10

297

T12

1

auto[1]

17033

1

T5

151

T10

149

T12

1

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32806	1			T5	203		T10	224		T12	1
others[1]	5273	1			T5	39		T10	42		T13	20
others[2]	5388	1			T5	31		T10	34		T13	22
others[3]	6057	1			T5	39		T10	51		T13	27
interest[1]	3559	1			T5	26		T10	29		T13	20
interest[4]	21457	1			T5	139		T10	144		T12	1
interest[64]	10468	1			T5	85		T10	66		T12	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14793	1			T5	124		T10	139		T12	1
auto[0]	auto[0]	others[1]	2468	1			T5	25		T10	33		T13	7
auto[0]	auto[0]	others[2]	2532	1			T5	18		T10	24		T13	12
auto[0]	auto[0]	others[3]	2744	1			T5	24		T10	36		T13	15
auto[0]	auto[0]	interest[1]	1598	1			T5	19		T10	20		T13	9
auto[0]	auto[0]	interest[4]	9633	1			T5	82		T10	86		T12	1
auto[0]	auto[0]	interest[64]	4771	1			T5	62		T10	45		T13	30
auto[0]	auto[1]	others[0]	9284	1			T13	26		T24	3		T26	20
auto[0]	auto[1]	others[1]	1395	1			T13	2		T26	3		T27	40
auto[0]	auto[1]	others[2]	1448	1			T13	1		T26	3		T27	45
auto[0]	auto[1]	others[3]	1636	1			T13	2		T26	2		T27	55
auto[0]	auto[1]	interest[1]	979	1			T13	5		T26	1		T27	25
auto[0]	auto[1]	interest[4]	6159	1			T13	16		T24	3		T26	11
auto[0]	auto[1]	interest[64]	2870	1			T13	7		T26	3		T27	87
auto[1]	auto[0]	others[0]	8729	1			T5	79		T10	85		T13	40
auto[1]	auto[0]	others[1]	1410	1			T5	14		T10	9		T13	11
auto[1]	auto[0]	others[2]	1408	1			T5	13		T10	10		T13	9
auto[1]	auto[0]	others[3]	1677	1			T5	15		T10	15		T13	10
auto[1]	auto[0]	interest[1]	982	1			T5	7		T10	9		T13	6
auto[1]	auto[0]	interest[4]	5665	1			T5	57		T10	58		T13	26
auto[1]	auto[0]	interest[64]	2827	1			T5	23		T10	21		T12	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal