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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.44 94.07 98.62 89.36 97.28 95.43 99.25


Total test records in report: 1101
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T156 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.713027587 Jun 23 05:10:02 PM PDT 24 Jun 23 05:10:18 PM PDT 24 941834720 ps
T1012 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2091063351 Jun 23 05:10:24 PM PDT 24 Jun 23 05:10:27 PM PDT 24 318547842 ps
T104 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1034188306 Jun 23 05:10:12 PM PDT 24 Jun 23 05:10:16 PM PDT 24 526029606 ps
T1013 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1389467972 Jun 23 05:10:27 PM PDT 24 Jun 23 05:10:28 PM PDT 24 26855263 ps
T1014 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3805595576 Jun 23 05:10:17 PM PDT 24 Jun 23 05:10:19 PM PDT 24 38982500 ps
T165 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1849745933 Jun 23 05:10:22 PM PDT 24 Jun 23 05:10:32 PM PDT 24 407712125 ps
T1015 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2547707001 Jun 23 05:10:26 PM PDT 24 Jun 23 05:10:30 PM PDT 24 182159944 ps
T125 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1469800111 Jun 23 05:10:02 PM PDT 24 Jun 23 05:10:06 PM PDT 24 104785328 ps
T1016 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3276543633 Jun 23 05:10:08 PM PDT 24 Jun 23 05:10:11 PM PDT 24 117467998 ps
T126 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1995537331 Jun 23 05:10:25 PM PDT 24 Jun 23 05:10:29 PM PDT 24 231640854 ps
T127 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1640600075 Jun 23 05:10:02 PM PDT 24 Jun 23 05:10:35 PM PDT 24 727712365 ps
T1017 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3510676919 Jun 23 05:10:14 PM PDT 24 Jun 23 05:10:23 PM PDT 24 1577729333 ps
T105 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1886655830 Jun 23 05:10:31 PM PDT 24 Jun 23 05:10:36 PM PDT 24 115846794 ps
T1018 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.275757193 Jun 23 05:10:21 PM PDT 24 Jun 23 05:10:23 PM PDT 24 72615495 ps
T163 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3031781934 Jun 23 05:10:23 PM PDT 24 Jun 23 05:10:36 PM PDT 24 818620236 ps
T1019 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3465262892 Jun 23 05:10:28 PM PDT 24 Jun 23 05:10:30 PM PDT 24 38751673 ps
T82 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3885380949 Jun 23 05:10:10 PM PDT 24 Jun 23 05:10:12 PM PDT 24 230808309 ps
T1020 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2568309173 Jun 23 05:10:06 PM PDT 24 Jun 23 05:10:09 PM PDT 24 108815585 ps
T1021 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3686027301 Jun 23 05:10:11 PM PDT 24 Jun 23 05:10:20 PM PDT 24 1054218314 ps
T1022 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1559723451 Jun 23 05:10:16 PM PDT 24 Jun 23 05:10:19 PM PDT 24 363848167 ps
T1023 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3758523523 Jun 23 05:10:17 PM PDT 24 Jun 23 05:10:20 PM PDT 24 87665971 ps
T1024 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.26863008 Jun 23 05:10:29 PM PDT 24 Jun 23 05:10:30 PM PDT 24 14128209 ps
T1025 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3187716268 Jun 23 05:10:16 PM PDT 24 Jun 23 05:10:37 PM PDT 24 966574519 ps
T1026 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2247636721 Jun 23 05:10:21 PM PDT 24 Jun 23 05:10:26 PM PDT 24 224776472 ps
T1027 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2422851257 Jun 23 05:10:22 PM PDT 24 Jun 23 05:10:23 PM PDT 24 79580951 ps
T1028 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4044824217 Jun 23 05:10:21 PM PDT 24 Jun 23 05:10:28 PM PDT 24 217445634 ps
T1029 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2352476364 Jun 23 05:10:14 PM PDT 24 Jun 23 05:10:16 PM PDT 24 100427120 ps
T1030 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2323018916 Jun 23 05:10:11 PM PDT 24 Jun 23 05:10:26 PM PDT 24 406861391 ps
T1031 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3118835880 Jun 23 05:09:58 PM PDT 24 Jun 23 05:09:59 PM PDT 24 63786962 ps
T1032 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1698555607 Jun 23 05:10:16 PM PDT 24 Jun 23 05:10:19 PM PDT 24 67606252 ps
T1033 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2838353039 Jun 23 05:10:11 PM PDT 24 Jun 23 05:10:38 PM PDT 24 24086948081 ps
T1034 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1169009303 Jun 23 05:10:10 PM PDT 24 Jun 23 05:10:13 PM PDT 24 102128418 ps
T1035 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2120819961 Jun 23 05:10:22 PM PDT 24 Jun 23 05:10:24 PM PDT 24 12778447 ps
T1036 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2266966381 Jun 23 05:10:21 PM PDT 24 Jun 23 05:10:25 PM PDT 24 411392281 ps
T162 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4004952168 Jun 23 05:09:59 PM PDT 24 Jun 23 05:10:19 PM PDT 24 803913711 ps
T1037 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1810210643 Jun 23 05:10:02 PM PDT 24 Jun 23 05:10:11 PM PDT 24 951327687 ps
T1038 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3017418633 Jun 23 05:10:04 PM PDT 24 Jun 23 05:10:07 PM PDT 24 208030279 ps
T1039 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2235039218 Jun 23 05:10:16 PM PDT 24 Jun 23 05:10:18 PM PDT 24 75563079 ps
T1040 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.291836623 Jun 23 05:10:04 PM PDT 24 Jun 23 05:10:06 PM PDT 24 43179637 ps
T1041 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1366659152 Jun 23 05:10:28 PM PDT 24 Jun 23 05:10:30 PM PDT 24 22964050 ps
T1042 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3367740418 Jun 23 05:10:25 PM PDT 24 Jun 23 05:10:26 PM PDT 24 25864424 ps
T1043 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.821956698 Jun 23 05:10:22 PM PDT 24 Jun 23 05:10:24 PM PDT 24 78801944 ps
T1044 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2147758276 Jun 23 05:10:08 PM PDT 24 Jun 23 05:10:09 PM PDT 24 13036369 ps
T1045 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.116832297 Jun 23 05:10:07 PM PDT 24 Jun 23 05:10:10 PM PDT 24 202283865 ps
T1046 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2222697422 Jun 23 05:10:24 PM PDT 24 Jun 23 05:10:38 PM PDT 24 2689421709 ps
T1047 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.371761705 Jun 23 05:10:32 PM PDT 24 Jun 23 05:10:33 PM PDT 24 15657903 ps
T1048 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2533167987 Jun 23 05:10:04 PM PDT 24 Jun 23 05:10:07 PM PDT 24 253680545 ps
T1049 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2857123349 Jun 23 05:10:22 PM PDT 24 Jun 23 05:10:24 PM PDT 24 12046922 ps
T1050 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3132196870 Jun 23 05:10:26 PM PDT 24 Jun 23 05:10:28 PM PDT 24 47783687 ps
T1051 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.447754599 Jun 23 05:10:02 PM PDT 24 Jun 23 05:10:10 PM PDT 24 205513868 ps
T1052 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2646490578 Jun 23 05:10:30 PM PDT 24 Jun 23 05:10:32 PM PDT 24 140719572 ps
T1053 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3222950644 Jun 23 05:10:23 PM PDT 24 Jun 23 05:10:25 PM PDT 24 14499946 ps
T1054 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1751926852 Jun 23 05:10:04 PM PDT 24 Jun 23 05:10:09 PM PDT 24 225005203 ps
T1055 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2311836765 Jun 23 05:10:03 PM PDT 24 Jun 23 05:10:07 PM PDT 24 124314054 ps
T1056 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1417289885 Jun 23 05:10:22 PM PDT 24 Jun 23 05:10:26 PM PDT 24 158345646 ps
T1057 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2823226723 Jun 23 05:10:09 PM PDT 24 Jun 23 05:10:10 PM PDT 24 31049309 ps
T1058 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.613341248 Jun 23 05:10:22 PM PDT 24 Jun 23 05:10:25 PM PDT 24 46341920 ps
T1059 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2403118014 Jun 23 05:10:14 PM PDT 24 Jun 23 05:10:19 PM PDT 24 716344724 ps
T1060 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3799934400 Jun 23 05:10:02 PM PDT 24 Jun 23 05:10:06 PM PDT 24 95095143 ps
T1061 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.894316264 Jun 23 05:10:22 PM PDT 24 Jun 23 05:10:26 PM PDT 24 482482434 ps
T161 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.79016982 Jun 23 05:10:03 PM PDT 24 Jun 23 05:10:08 PM PDT 24 204293097 ps
T1062 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2252673122 Jun 23 05:10:20 PM PDT 24 Jun 23 05:10:21 PM PDT 24 13148458 ps
T1063 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.685010386 Jun 23 05:10:27 PM PDT 24 Jun 23 05:10:29 PM PDT 24 27293027 ps
T1064 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3410861068 Jun 23 05:10:04 PM PDT 24 Jun 23 05:10:06 PM PDT 24 13670275 ps
T1065 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2788597583 Jun 23 05:10:01 PM PDT 24 Jun 23 05:10:03 PM PDT 24 11919138 ps
T1066 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3634288263 Jun 23 05:10:18 PM PDT 24 Jun 23 05:10:21 PM PDT 24 98108364 ps
T1067 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1408528535 Jun 23 05:10:09 PM PDT 24 Jun 23 05:10:13 PM PDT 24 97337940 ps
T1068 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2688066121 Jun 23 05:10:03 PM PDT 24 Jun 23 05:10:07 PM PDT 24 408640144 ps
T1069 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1337567628 Jun 23 05:10:23 PM PDT 24 Jun 23 05:10:26 PM PDT 24 38435092 ps
T1070 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.713843044 Jun 23 05:10:21 PM PDT 24 Jun 23 05:10:23 PM PDT 24 38877203 ps
T1071 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.471215590 Jun 23 05:10:17 PM PDT 24 Jun 23 05:10:19 PM PDT 24 175897851 ps
T1072 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4060311103 Jun 23 05:10:23 PM PDT 24 Jun 23 05:10:27 PM PDT 24 76294164 ps
T1073 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1729493033 Jun 23 05:10:22 PM PDT 24 Jun 23 05:10:24 PM PDT 24 14393826 ps
T1074 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4031653635 Jun 23 05:10:03 PM PDT 24 Jun 23 05:10:05 PM PDT 24 32298653 ps
T1075 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1642421108 Jun 23 05:10:09 PM PDT 24 Jun 23 05:10:13 PM PDT 24 217101914 ps
T1076 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.484642829 Jun 23 05:10:16 PM PDT 24 Jun 23 05:10:18 PM PDT 24 30609627 ps
T1077 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1097840272 Jun 23 05:10:01 PM PDT 24 Jun 23 05:10:02 PM PDT 24 77363888 ps
T1078 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.615507742 Jun 23 05:10:28 PM PDT 24 Jun 23 05:10:29 PM PDT 24 13802141 ps
T1079 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.877759493 Jun 23 05:10:22 PM PDT 24 Jun 23 05:10:26 PM PDT 24 108020754 ps
T1080 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4161982813 Jun 23 05:10:10 PM PDT 24 Jun 23 05:10:11 PM PDT 24 22715638 ps
T1081 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.777570477 Jun 23 05:10:09 PM PDT 24 Jun 23 05:10:18 PM PDT 24 607235284 ps
T1082 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.553681571 Jun 23 05:10:03 PM PDT 24 Jun 23 05:10:06 PM PDT 24 114603885 ps
T1083 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2583940844 Jun 23 05:10:15 PM PDT 24 Jun 23 05:10:18 PM PDT 24 85636068 ps
T1084 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.994175423 Jun 23 05:10:09 PM PDT 24 Jun 23 05:10:29 PM PDT 24 1210519711 ps
T1085 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.631497780 Jun 23 05:10:08 PM PDT 24 Jun 23 05:10:11 PM PDT 24 461277551 ps
T1086 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3176001817 Jun 23 05:10:03 PM PDT 24 Jun 23 05:10:05 PM PDT 24 28460174 ps
T1087 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3425064987 Jun 23 05:10:26 PM PDT 24 Jun 23 05:10:27 PM PDT 24 22062366 ps
T1088 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.190643895 Jun 23 05:10:08 PM PDT 24 Jun 23 05:10:10 PM PDT 24 83617529 ps
T1089 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2428042651 Jun 23 05:10:28 PM PDT 24 Jun 23 05:10:29 PM PDT 24 30352109 ps
T1090 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1507070816 Jun 23 05:10:02 PM PDT 24 Jun 23 05:10:37 PM PDT 24 548082572 ps
T1091 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1373975499 Jun 23 05:10:11 PM PDT 24 Jun 23 05:10:16 PM PDT 24 1064606227 ps
T1092 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1857924048 Jun 23 05:10:08 PM PDT 24 Jun 23 05:10:09 PM PDT 24 17557628 ps
T1093 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.916806514 Jun 23 05:10:16 PM PDT 24 Jun 23 05:10:18 PM PDT 24 27562094 ps
T1094 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1878350014 Jun 23 05:10:02 PM PDT 24 Jun 23 05:10:06 PM PDT 24 518116938 ps
T1095 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1544701414 Jun 23 05:10:22 PM PDT 24 Jun 23 05:10:27 PM PDT 24 2386106047 ps
T1096 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1356670182 Jun 23 05:10:01 PM PDT 24 Jun 23 05:10:04 PM PDT 24 45505168 ps
T1097 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3129642621 Jun 23 05:10:13 PM PDT 24 Jun 23 05:10:17 PM PDT 24 241834495 ps
T1098 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3649889649 Jun 23 05:10:12 PM PDT 24 Jun 23 05:10:13 PM PDT 24 12318872 ps
T1099 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3416234038 Jun 23 05:10:22 PM PDT 24 Jun 23 05:10:23 PM PDT 24 46790198 ps
T1100 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.544477617 Jun 23 05:10:09 PM PDT 24 Jun 23 05:10:11 PM PDT 24 59443613 ps
T1101 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.43692792 Jun 23 05:10:02 PM PDT 24 Jun 23 05:10:12 PM PDT 24 117803984 ps

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3635379544
Short name T5
Test name
Test status
Simulation time 44200330567 ps
CPU time 446.03 seconds
Started Jun 23 05:48:02 PM PDT 24
Finished Jun 23 05:55:29 PM PDT 24
Peak memory 254292 kb
Host smart-a85df5d1-d2f4-4655-8333-910940520ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635379544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3635379544
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.324501651
Short name T15
Test name
Test status
Simulation time 37452598639 ps
CPU time 219.57 seconds
Started Jun 23 05:46:55 PM PDT 24
Finished Jun 23 05:50:35 PM PDT 24
Peak memory 264468 kb
Host smart-d18d7ac5-aa71-4169-85f2-9ec673d80167
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324501651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.324501651
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3632602155
Short name T94
Test name
Test status
Simulation time 6732627966 ps
CPU time 22.66 seconds
Started Jun 23 05:10:04 PM PDT 24
Finished Jun 23 05:10:27 PM PDT 24
Peak memory 215392 kb
Host smart-63c4c253-37ab-4dc2-8fb6-93b84def0b1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632602155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3632602155
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.160330676
Short name T17
Test name
Test status
Simulation time 56815137194 ps
CPU time 315.69 seconds
Started Jun 23 05:46:48 PM PDT 24
Finished Jun 23 05:52:04 PM PDT 24
Peak memory 264084 kb
Host smart-9ef16182-f956-470e-86c8-22677d60fc69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160330676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.160330676
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.967444674
Short name T16
Test name
Test status
Simulation time 25173992791 ps
CPU time 143.43 seconds
Started Jun 23 05:46:33 PM PDT 24
Finished Jun 23 05:48:57 PM PDT 24
Peak memory 270756 kb
Host smart-b0370d3b-41c1-4a27-a509-ca01346755e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967444674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.967444674
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3978237102
Short name T63
Test name
Test status
Simulation time 70052337 ps
CPU time 0.73 seconds
Started Jun 23 05:45:49 PM PDT 24
Finished Jun 23 05:45:50 PM PDT 24
Peak memory 217120 kb
Host smart-f4b393c7-9cae-4abf-a5ba-31ce148773f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978237102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3978237102
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3732337164
Short name T136
Test name
Test status
Simulation time 12902229293 ps
CPU time 198.65 seconds
Started Jun 23 05:46:40 PM PDT 24
Finished Jun 23 05:49:59 PM PDT 24
Peak memory 267884 kb
Host smart-cd9f69a0-cb82-45be-815b-e10ec85b13bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732337164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3732337164
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.4211457477
Short name T19
Test name
Test status
Simulation time 205278046167 ps
CPU time 407.95 seconds
Started Jun 23 05:46:57 PM PDT 24
Finished Jun 23 05:53:45 PM PDT 24
Peak memory 266724 kb
Host smart-6b3eb8a7-19ba-488f-a2f9-3be53335578b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211457477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.4211457477
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1331743066
Short name T158
Test name
Test status
Simulation time 4459486098 ps
CPU time 81.25 seconds
Started Jun 23 05:46:54 PM PDT 24
Finished Jun 23 05:48:16 PM PDT 24
Peak memory 250932 kb
Host smart-28201f84-88cc-47dd-897f-d5e6b06d02ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331743066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1331743066
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1715919228
Short name T98
Test name
Test status
Simulation time 213699883 ps
CPU time 3.98 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:28 PM PDT 24
Peak memory 215656 kb
Host smart-cb872466-563a-4498-bb65-4d102c7d3f44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715919228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1715919228
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3415793326
Short name T190
Test name
Test status
Simulation time 4436318117 ps
CPU time 112.43 seconds
Started Jun 23 05:47:24 PM PDT 24
Finished Jun 23 05:49:17 PM PDT 24
Peak memory 269124 kb
Host smart-98c722f5-eaef-49a5-9d15-37bc282c6314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415793326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3415793326
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1748572295
Short name T18
Test name
Test status
Simulation time 71728740 ps
CPU time 1.06 seconds
Started Jun 23 05:46:12 PM PDT 24
Finished Jun 23 05:46:14 PM PDT 24
Peak memory 236372 kb
Host smart-927b38a9-1e7d-479c-bfcc-98b7fa9ab406
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748572295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1748572295
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1508744588
Short name T194
Test name
Test status
Simulation time 70376784894 ps
CPU time 619.09 seconds
Started Jun 23 05:47:19 PM PDT 24
Finished Jun 23 05:57:39 PM PDT 24
Peak memory 286316 kb
Host smart-95760c34-a5ab-423a-a14e-9fae815a1873
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508744588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1508744588
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3494672734
Short name T55
Test name
Test status
Simulation time 8976508089 ps
CPU time 59.21 seconds
Started Jun 23 05:48:09 PM PDT 24
Finished Jun 23 05:49:09 PM PDT 24
Peak memory 233920 kb
Host smart-44dfbc0d-01d9-4708-a9b1-ef83ac4b88c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494672734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3494672734
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1534883954
Short name T13
Test name
Test status
Simulation time 112598513588 ps
CPU time 277.29 seconds
Started Jun 23 05:47:54 PM PDT 24
Finished Jun 23 05:52:32 PM PDT 24
Peak memory 266048 kb
Host smart-90236159-375b-4935-bd2d-8fed947c9a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534883954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1534883954
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3337714880
Short name T67
Test name
Test status
Simulation time 171548102949 ps
CPU time 169.41 seconds
Started Jun 23 05:45:55 PM PDT 24
Finished Jun 23 05:48:45 PM PDT 24
Peak memory 257924 kb
Host smart-912a7ca6-198d-4f0d-9eaf-6dbb19d9f075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337714880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3337714880
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3678944696
Short name T80
Test name
Test status
Simulation time 40379450 ps
CPU time 1.41 seconds
Started Jun 23 05:10:03 PM PDT 24
Finished Jun 23 05:10:06 PM PDT 24
Peak memory 207100 kb
Host smart-65ae5280-2959-4f20-a024-6d2ec822467a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678944696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3678944696
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3331390413
Short name T79
Test name
Test status
Simulation time 205683064060 ps
CPU time 461.43 seconds
Started Jun 23 05:48:33 PM PDT 24
Finished Jun 23 05:56:15 PM PDT 24
Peak memory 273428 kb
Host smart-3b05a04d-aa89-4829-932f-c6fa83672dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331390413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3331390413
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.954700987
Short name T320
Test name
Test status
Simulation time 35501340 ps
CPU time 1.01 seconds
Started Jun 23 05:46:35 PM PDT 24
Finished Jun 23 05:46:37 PM PDT 24
Peak memory 218884 kb
Host smart-7fe0f1df-c541-4787-81d8-245beeb5316e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954700987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.954700987
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1405179063
Short name T217
Test name
Test status
Simulation time 10293787693 ps
CPU time 164.45 seconds
Started Jun 23 05:45:54 PM PDT 24
Finished Jun 23 05:48:39 PM PDT 24
Peak memory 256724 kb
Host smart-4b5e6725-8910-4ac9-8825-ade51ef52686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405179063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1405179063
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1351875913
Short name T177
Test name
Test status
Simulation time 14276768696 ps
CPU time 199.65 seconds
Started Jun 23 05:46:15 PM PDT 24
Finished Jun 23 05:49:35 PM PDT 24
Peak memory 273848 kb
Host smart-9941d91c-e8ce-43e4-a029-e3256ca196c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351875913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1351875913
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.4255682278
Short name T184
Test name
Test status
Simulation time 70387875580 ps
CPU time 500.66 seconds
Started Jun 23 05:47:45 PM PDT 24
Finished Jun 23 05:56:06 PM PDT 24
Peak memory 257256 kb
Host smart-d8474544-1166-44f6-8f5c-217b83abbcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255682278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.4255682278
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1605063008
Short name T246
Test name
Test status
Simulation time 45874986650 ps
CPU time 150.65 seconds
Started Jun 23 05:47:15 PM PDT 24
Finished Jun 23 05:49:46 PM PDT 24
Peak memory 263132 kb
Host smart-67f9195b-e95a-48a6-9981-c10fd5a375da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605063008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1605063008
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3337469238
Short name T32
Test name
Test status
Simulation time 12385691053 ps
CPU time 172.03 seconds
Started Jun 23 05:46:35 PM PDT 24
Finished Jun 23 05:49:28 PM PDT 24
Peak memory 256996 kb
Host smart-2abfb9b9-a586-4798-8d90-48fd70afc706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337469238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3337469238
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1770801277
Short name T300
Test name
Test status
Simulation time 13977991 ps
CPU time 0.72 seconds
Started Jun 23 05:47:01 PM PDT 24
Finished Jun 23 05:47:02 PM PDT 24
Peak memory 205752 kb
Host smart-d5eeca65-3173-40a0-b1cf-817046f3eae9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770801277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1770801277
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2714517466
Short name T22
Test name
Test status
Simulation time 31757254778 ps
CPU time 204.46 seconds
Started Jun 23 05:48:14 PM PDT 24
Finished Jun 23 05:51:39 PM PDT 24
Peak memory 274912 kb
Host smart-4b2c62ae-75f3-48c6-a188-6e35932a1d54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714517466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2714517466
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2294161636
Short name T101
Test name
Test status
Simulation time 157165998 ps
CPU time 4.49 seconds
Started Jun 23 05:10:26 PM PDT 24
Finished Jun 23 05:10:31 PM PDT 24
Peak memory 215320 kb
Host smart-4709a717-35cf-4105-bb82-7cf144b5c67a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294161636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2294161636
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3743735024
Short name T57
Test name
Test status
Simulation time 10588840897 ps
CPU time 10.31 seconds
Started Jun 23 05:46:41 PM PDT 24
Finished Jun 23 05:46:52 PM PDT 24
Peak memory 217448 kb
Host smart-582c63e6-6d2f-45d4-aa95-b1c07fa585a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743735024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3743735024
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.640406684
Short name T14
Test name
Test status
Simulation time 5239568833 ps
CPU time 99.81 seconds
Started Jun 23 05:47:29 PM PDT 24
Finished Jun 23 05:49:09 PM PDT 24
Peak memory 266844 kb
Host smart-be2e54bb-22c7-4fc3-a3a6-543f554b6ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640406684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.640406684
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2025160952
Short name T847
Test name
Test status
Simulation time 11864305959 ps
CPU time 152.54 seconds
Started Jun 23 05:48:16 PM PDT 24
Finished Jun 23 05:50:50 PM PDT 24
Peak memory 257776 kb
Host smart-ea4c72dd-d9d3-4ed5-b9e5-03fb4acc1e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025160952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2025160952
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4004952168
Short name T162
Test name
Test status
Simulation time 803913711 ps
CPU time 18.77 seconds
Started Jun 23 05:09:59 PM PDT 24
Finished Jun 23 05:10:19 PM PDT 24
Peak memory 215412 kb
Host smart-d12f2abc-99e5-4a39-be68-2b3c2a74c236
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004952168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.4004952168
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2321930035
Short name T189
Test name
Test status
Simulation time 47810395603 ps
CPU time 179.84 seconds
Started Jun 23 05:45:54 PM PDT 24
Finished Jun 23 05:48:54 PM PDT 24
Peak memory 256096 kb
Host smart-6973ab7d-70b7-49c7-a0c4-cd2ac00eed7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321930035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2321930035
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2020178699
Short name T164
Test name
Test status
Simulation time 901894934 ps
CPU time 12.94 seconds
Started Jun 23 05:10:18 PM PDT 24
Finished Jun 23 05:10:32 PM PDT 24
Peak memory 215984 kb
Host smart-0335a3a5-c9dd-4c2f-b2da-4654afd1b7a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020178699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2020178699
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2538018856
Short name T193
Test name
Test status
Simulation time 296780327299 ps
CPU time 374.04 seconds
Started Jun 23 05:46:43 PM PDT 24
Finished Jun 23 05:52:58 PM PDT 24
Peak memory 266744 kb
Host smart-1b22b99f-aa8e-4803-a9f8-2c0cdd1a8cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538018856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2538018856
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2151899359
Short name T268
Test name
Test status
Simulation time 2588173949 ps
CPU time 13.68 seconds
Started Jun 23 05:47:18 PM PDT 24
Finished Jun 23 05:47:33 PM PDT 24
Peak memory 235992 kb
Host smart-18b785ac-09a2-4585-a07d-6a8f6c9f6403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151899359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2151899359
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3315158368
Short name T153
Test name
Test status
Simulation time 20233884520 ps
CPU time 204.03 seconds
Started Jun 23 05:47:57 PM PDT 24
Finished Jun 23 05:51:22 PM PDT 24
Peak memory 258172 kb
Host smart-9362a5e2-b4c1-490c-ad52-56326f8604d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315158368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3315158368
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.571434645
Short name T33
Test name
Test status
Simulation time 174014070211 ps
CPU time 226.95 seconds
Started Jun 23 05:48:45 PM PDT 24
Finished Jun 23 05:52:32 PM PDT 24
Peak memory 282532 kb
Host smart-31afd76a-e15e-4d34-a6c6-a7181a4768c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571434645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.571434645
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1589453476
Short name T270
Test name
Test status
Simulation time 2122620570 ps
CPU time 11.93 seconds
Started Jun 23 05:48:48 PM PDT 24
Finished Jun 23 05:49:00 PM PDT 24
Peak memory 250152 kb
Host smart-b0b1b223-d59a-45c3-90cc-91a877644d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589453476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1589453476
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.4274637961
Short name T4
Test name
Test status
Simulation time 716046717 ps
CPU time 5.81 seconds
Started Jun 23 05:47:31 PM PDT 24
Finished Jun 23 05:47:38 PM PDT 24
Peak memory 233788 kb
Host smart-fb040b12-1c3c-4e82-9b7e-58272dcaffe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274637961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.4274637961
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4135396385
Short name T96
Test name
Test status
Simulation time 96172468 ps
CPU time 3.39 seconds
Started Jun 23 05:10:15 PM PDT 24
Finished Jun 23 05:10:19 PM PDT 24
Peak memory 215500 kb
Host smart-9dd7eb52-f110-46da-a55d-f8318e5f8bc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135396385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
4135396385
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.667471641
Short name T114
Test name
Test status
Simulation time 789128514 ps
CPU time 12.43 seconds
Started Jun 23 05:45:50 PM PDT 24
Finished Jun 23 05:46:02 PM PDT 24
Peak memory 241620 kb
Host smart-6bb7d0d3-68aa-415a-abba-a0ef6c386054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667471641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.667471641
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.70928018
Short name T359
Test name
Test status
Simulation time 2171515461 ps
CPU time 50.78 seconds
Started Jun 23 05:46:50 PM PDT 24
Finished Jun 23 05:47:41 PM PDT 24
Peak memory 258244 kb
Host smart-cc121c9f-5000-4906-b515-ec19a9d32181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70928018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.70928018
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1444537706
Short name T665
Test name
Test status
Simulation time 8606516614 ps
CPU time 7.9 seconds
Started Jun 23 05:47:05 PM PDT 24
Finished Jun 23 05:47:14 PM PDT 24
Peak memory 225708 kb
Host smart-0b345062-9fe9-4566-9b89-07eb96e4080b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444537706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1444537706
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2063329756
Short name T168
Test name
Test status
Simulation time 1144536542 ps
CPU time 10.58 seconds
Started Jun 23 05:46:04 PM PDT 24
Finished Jun 23 05:46:15 PM PDT 24
Peak memory 233776 kb
Host smart-030f1d88-5c2f-4434-923f-4a494302b4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063329756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2063329756
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2422080171
Short name T272
Test name
Test status
Simulation time 194884609 ps
CPU time 3.74 seconds
Started Jun 23 05:47:51 PM PDT 24
Finished Jun 23 05:47:55 PM PDT 24
Peak memory 233792 kb
Host smart-3f4da31c-c396-4b0d-ba10-deac3136c2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422080171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2422080171
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.213202536
Short name T253
Test name
Test status
Simulation time 178655767162 ps
CPU time 257.69 seconds
Started Jun 23 05:48:14 PM PDT 24
Finished Jun 23 05:52:33 PM PDT 24
Peak memory 255304 kb
Host smart-6f0ee834-3037-4733-a56c-58d259287b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213202536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.213202536
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3537800304
Short name T260
Test name
Test status
Simulation time 64644754772 ps
CPU time 271.37 seconds
Started Jun 23 05:46:18 PM PDT 24
Finished Jun 23 05:50:50 PM PDT 24
Peak memory 256540 kb
Host smart-15395300-7b8e-4399-b5f4-7ab948504fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537800304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3537800304
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3424596720
Short name T966
Test name
Test status
Simulation time 603721785 ps
CPU time 3.93 seconds
Started Jun 23 05:45:55 PM PDT 24
Finished Jun 23 05:45:59 PM PDT 24
Peak memory 225516 kb
Host smart-d7c7156e-4545-429a-a228-cf8493a61568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424596720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3424596720
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1368143260
Short name T176
Test name
Test status
Simulation time 12682497233 ps
CPU time 24.35 seconds
Started Jun 23 05:47:06 PM PDT 24
Finished Jun 23 05:47:31 PM PDT 24
Peak memory 233872 kb
Host smart-ca2ef5ed-b559-43a3-ad4e-531fc0478ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368143260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1368143260
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1698555607
Short name T1032
Test name
Test status
Simulation time 67606252 ps
CPU time 2.19 seconds
Started Jun 23 05:10:16 PM PDT 24
Finished Jun 23 05:10:19 PM PDT 24
Peak memory 215376 kb
Host smart-6ee70c41-ecf7-4bb2-9b0a-6f7b15225e25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698555607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1698555607
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1810210643
Short name T1037
Test name
Test status
Simulation time 951327687 ps
CPU time 8.32 seconds
Started Jun 23 05:10:02 PM PDT 24
Finished Jun 23 05:10:11 PM PDT 24
Peak memory 215264 kb
Host smart-f895958d-d288-4014-a348-699aae08346c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810210643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1810210643
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2838353039
Short name T1033
Test name
Test status
Simulation time 24086948081 ps
CPU time 26.34 seconds
Started Jun 23 05:10:11 PM PDT 24
Finished Jun 23 05:10:38 PM PDT 24
Peak memory 207172 kb
Host smart-83eeb18f-0d06-4f57-93cd-d830217226ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838353039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2838353039
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1356670182
Short name T1096
Test name
Test status
Simulation time 45505168 ps
CPU time 1.01 seconds
Started Jun 23 05:10:01 PM PDT 24
Finished Jun 23 05:10:04 PM PDT 24
Peak memory 206912 kb
Host smart-c1d4d62f-caaf-441b-97dc-78d88ce5fc98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356670182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1356670182
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2311836765
Short name T1055
Test name
Test status
Simulation time 124314054 ps
CPU time 3 seconds
Started Jun 23 05:10:03 PM PDT 24
Finished Jun 23 05:10:07 PM PDT 24
Peak memory 217628 kb
Host smart-a25cfd42-5b9f-41b8-acb3-f3db3038738f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311836765 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2311836765
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1469800111
Short name T125
Test name
Test status
Simulation time 104785328 ps
CPU time 2.93 seconds
Started Jun 23 05:10:02 PM PDT 24
Finished Jun 23 05:10:06 PM PDT 24
Peak memory 207100 kb
Host smart-953fd6ef-e856-404e-a4e1-78a46db00980
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469800111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
469800111
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3118835880
Short name T1031
Test name
Test status
Simulation time 63786962 ps
CPU time 0.77 seconds
Started Jun 23 05:09:58 PM PDT 24
Finished Jun 23 05:09:59 PM PDT 24
Peak memory 203696 kb
Host smart-6cf8e16e-ee03-43e1-830e-6df2f0f8b66b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118835880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
118835880
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2401705344
Short name T115
Test name
Test status
Simulation time 66033835 ps
CPU time 1.34 seconds
Started Jun 23 05:10:00 PM PDT 24
Finished Jun 23 05:10:02 PM PDT 24
Peak memory 215336 kb
Host smart-5c67ea28-30ff-4c57-b6e9-9ed5421132a7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401705344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2401705344
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2788597583
Short name T1065
Test name
Test status
Simulation time 11919138 ps
CPU time 0.67 seconds
Started Jun 23 05:10:01 PM PDT 24
Finished Jun 23 05:10:03 PM PDT 24
Peak memory 203908 kb
Host smart-bc9e421d-535c-4a01-a5ab-76c62ccfd97e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788597583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2788597583
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.162707559
Short name T999
Test name
Test status
Simulation time 259150377 ps
CPU time 3.03 seconds
Started Jun 23 05:10:05 PM PDT 24
Finished Jun 23 05:10:08 PM PDT 24
Peak memory 215380 kb
Host smart-5d40a990-261d-41e2-ac79-7bb3068c91dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162707559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.162707559
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1354902222
Short name T1000
Test name
Test status
Simulation time 74901070 ps
CPU time 1.68 seconds
Started Jun 23 05:10:00 PM PDT 24
Finished Jun 23 05:10:02 PM PDT 24
Peak memory 215428 kb
Host smart-13c250f1-3d51-48e5-8564-85d4dca9c9a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354902222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
354902222
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2323018916
Short name T1030
Test name
Test status
Simulation time 406861391 ps
CPU time 13.98 seconds
Started Jun 23 05:10:11 PM PDT 24
Finished Jun 23 05:10:26 PM PDT 24
Peak memory 207044 kb
Host smart-222ecf20-4804-4ae7-8f72-650882175c79
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323018916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2323018916
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1507070816
Short name T1090
Test name
Test status
Simulation time 548082572 ps
CPU time 33.51 seconds
Started Jun 23 05:10:02 PM PDT 24
Finished Jun 23 05:10:37 PM PDT 24
Peak memory 207144 kb
Host smart-5ab6535f-9aee-4d15-b53a-d29dfc56d5cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507070816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1507070816
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1680091582
Short name T147
Test name
Test status
Simulation time 849831223 ps
CPU time 3.91 seconds
Started Jun 23 05:10:04 PM PDT 24
Finished Jun 23 05:10:09 PM PDT 24
Peak memory 217016 kb
Host smart-e7653fe7-5709-450f-894f-b8b3bfed01c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680091582 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1680091582
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3672547040
Short name T122
Test name
Test status
Simulation time 35602364 ps
CPU time 2.48 seconds
Started Jun 23 05:10:02 PM PDT 24
Finished Jun 23 05:10:06 PM PDT 24
Peak memory 215368 kb
Host smart-09c5f485-b659-4fde-b1e8-03cebce6f909
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672547040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
672547040
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3410861068
Short name T1064
Test name
Test status
Simulation time 13670275 ps
CPU time 0.76 seconds
Started Jun 23 05:10:04 PM PDT 24
Finished Jun 23 05:10:06 PM PDT 24
Peak memory 204016 kb
Host smart-cd0aa043-1bbb-43d1-9ca2-6fd758a0af02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410861068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
410861068
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2284639149
Short name T118
Test name
Test status
Simulation time 248946040 ps
CPU time 1.97 seconds
Started Jun 23 05:10:03 PM PDT 24
Finished Jun 23 05:10:06 PM PDT 24
Peak memory 215380 kb
Host smart-8ff94662-6343-4b58-9250-2eafc959ef6b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284639149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2284639149
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4031653635
Short name T1074
Test name
Test status
Simulation time 32298653 ps
CPU time 0.66 seconds
Started Jun 23 05:10:03 PM PDT 24
Finished Jun 23 05:10:05 PM PDT 24
Peak memory 203576 kb
Host smart-2aec8e9f-450a-49e2-8b26-98425e49181d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031653635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4031653635
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3516300921
Short name T140
Test name
Test status
Simulation time 1665478014 ps
CPU time 2.75 seconds
Started Jun 23 05:10:03 PM PDT 24
Finished Jun 23 05:10:06 PM PDT 24
Peak memory 215424 kb
Host smart-1b30ca7f-c6c2-4540-89ac-7b1b55983465
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516300921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3516300921
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1878350014
Short name T1094
Test name
Test status
Simulation time 518116938 ps
CPU time 3.34 seconds
Started Jun 23 05:10:02 PM PDT 24
Finished Jun 23 05:10:06 PM PDT 24
Peak memory 215608 kb
Host smart-a7e9123a-4a2b-4421-98a8-e581a82f071c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878350014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
878350014
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3576640718
Short name T109
Test name
Test status
Simulation time 207425791 ps
CPU time 12.87 seconds
Started Jun 23 05:10:10 PM PDT 24
Finished Jun 23 05:10:24 PM PDT 24
Peak memory 215416 kb
Host smart-fd010799-fffb-4b07-bfc3-fe392abd72e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576640718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3576640718
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3758523523
Short name T1023
Test name
Test status
Simulation time 87665971 ps
CPU time 2.81 seconds
Started Jun 23 05:10:17 PM PDT 24
Finished Jun 23 05:10:20 PM PDT 24
Peak memory 217040 kb
Host smart-9bdf9271-f3e7-423d-8c7d-8387dbd1dacf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758523523 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3758523523
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.170671730
Short name T138
Test name
Test status
Simulation time 263292618 ps
CPU time 1.94 seconds
Started Jun 23 05:10:16 PM PDT 24
Finished Jun 23 05:10:19 PM PDT 24
Peak memory 215376 kb
Host smart-854ff980-4882-484e-a553-081900a8e79f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170671730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.170671730
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.484642829
Short name T1076
Test name
Test status
Simulation time 30609627 ps
CPU time 0.74 seconds
Started Jun 23 05:10:16 PM PDT 24
Finished Jun 23 05:10:18 PM PDT 24
Peak memory 203756 kb
Host smart-e9bcfda7-81bf-4629-a0cb-299d330bec5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484642829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.484642829
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4120538897
Short name T1005
Test name
Test status
Simulation time 310772913 ps
CPU time 4.19 seconds
Started Jun 23 05:10:15 PM PDT 24
Finished Jun 23 05:10:19 PM PDT 24
Peak memory 215408 kb
Host smart-d482f441-f4cd-4427-961d-8998b3b6a61f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120538897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4120538897
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.428536344
Short name T92
Test name
Test status
Simulation time 126609289 ps
CPU time 3.74 seconds
Started Jun 23 05:10:15 PM PDT 24
Finished Jun 23 05:10:20 PM PDT 24
Peak memory 215520 kb
Host smart-df267a0d-c7e2-4a90-a6a6-9160f55ea2e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428536344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.428536344
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4281006298
Short name T89
Test name
Test status
Simulation time 898953324 ps
CPU time 21.98 seconds
Started Jun 23 05:10:17 PM PDT 24
Finished Jun 23 05:10:39 PM PDT 24
Peak memory 215544 kb
Host smart-c58ecede-1546-43aa-a4a2-e7f981ebb7a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281006298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4281006298
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.471215590
Short name T1071
Test name
Test status
Simulation time 175897851 ps
CPU time 1.69 seconds
Started Jun 23 05:10:17 PM PDT 24
Finished Jun 23 05:10:19 PM PDT 24
Peak memory 215288 kb
Host smart-c4668550-27bc-495e-90f9-c6c2586fe0d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471215590 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.471215590
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2235039218
Short name T1039
Test name
Test status
Simulation time 75563079 ps
CPU time 1.97 seconds
Started Jun 23 05:10:16 PM PDT 24
Finished Jun 23 05:10:18 PM PDT 24
Peak memory 215356 kb
Host smart-11958dd7-6668-41df-af2c-215f35f8a3b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235039218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2235039218
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1485925580
Short name T1006
Test name
Test status
Simulation time 13682276 ps
CPU time 0.71 seconds
Started Jun 23 05:10:18 PM PDT 24
Finished Jun 23 05:10:19 PM PDT 24
Peak memory 203624 kb
Host smart-b1011611-4da5-4888-a643-61aa6a820f72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485925580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1485925580
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3634288263
Short name T1066
Test name
Test status
Simulation time 98108364 ps
CPU time 2.78 seconds
Started Jun 23 05:10:18 PM PDT 24
Finished Jun 23 05:10:21 PM PDT 24
Peak memory 215348 kb
Host smart-36573511-09e5-4e90-a60a-29470ef8835b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634288263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3634288263
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.781471991
Short name T93
Test name
Test status
Simulation time 200573543 ps
CPU time 6.42 seconds
Started Jun 23 05:10:18 PM PDT 24
Finished Jun 23 05:10:25 PM PDT 24
Peak memory 215316 kb
Host smart-c76b06fe-a2a7-4a5c-b397-e0df27b051ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781471991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.781471991
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2378964893
Short name T1010
Test name
Test status
Simulation time 110677640 ps
CPU time 4.15 seconds
Started Jun 23 05:10:16 PM PDT 24
Finished Jun 23 05:10:20 PM PDT 24
Peak memory 217308 kb
Host smart-200f2e00-fdc5-4b56-b704-98d145578f03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378964893 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2378964893
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3805595576
Short name T1014
Test name
Test status
Simulation time 38982500 ps
CPU time 1.4 seconds
Started Jun 23 05:10:17 PM PDT 24
Finished Jun 23 05:10:19 PM PDT 24
Peak memory 207164 kb
Host smart-04d1fd37-e57d-4307-a2f0-a18a47d0e44e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805595576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3805595576
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.645374940
Short name T991
Test name
Test status
Simulation time 42417754 ps
CPU time 0.77 seconds
Started Jun 23 05:10:18 PM PDT 24
Finished Jun 23 05:10:19 PM PDT 24
Peak memory 203680 kb
Host smart-5adc8d3b-f766-48c3-970a-68b9bc92e318
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645374940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.645374940
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1755749697
Short name T142
Test name
Test status
Simulation time 43451662 ps
CPU time 2.75 seconds
Started Jun 23 05:10:20 PM PDT 24
Finished Jun 23 05:10:23 PM PDT 24
Peak memory 215372 kb
Host smart-5a118403-61c4-4eba-9505-b20fbcdb9dac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755749697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1755749697
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3119465290
Short name T110
Test name
Test status
Simulation time 212748553 ps
CPU time 6.8 seconds
Started Jun 23 05:10:16 PM PDT 24
Finished Jun 23 05:10:24 PM PDT 24
Peak memory 215476 kb
Host smart-22d137fe-4da8-4881-8a73-3f772b4ef3fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119465290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3119465290
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.613341248
Short name T1058
Test name
Test status
Simulation time 46341920 ps
CPU time 1.58 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:25 PM PDT 24
Peak memory 215696 kb
Host smart-be93617b-83b5-4664-8ca9-c64afebe7624
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613341248 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.613341248
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2375505471
Short name T120
Test name
Test status
Simulation time 45972720 ps
CPU time 1.37 seconds
Started Jun 23 05:10:17 PM PDT 24
Finished Jun 23 05:10:19 PM PDT 24
Peak memory 207116 kb
Host smart-bbfbc6f8-513c-4b06-8477-dc7405c07acc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375505471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2375505471
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1422299893
Short name T981
Test name
Test status
Simulation time 22151489 ps
CPU time 0.71 seconds
Started Jun 23 05:10:15 PM PDT 24
Finished Jun 23 05:10:16 PM PDT 24
Peak memory 203596 kb
Host smart-6b367bd5-0dca-493d-b831-7577be62618b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422299893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1422299893
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3077877080
Short name T993
Test name
Test status
Simulation time 432848142 ps
CPU time 2.95 seconds
Started Jun 23 05:10:20 PM PDT 24
Finished Jun 23 05:10:23 PM PDT 24
Peak memory 215336 kb
Host smart-6759371f-11d9-4f79-931f-ecd85d02984d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077877080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3077877080
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2247636721
Short name T1026
Test name
Test status
Simulation time 224776472 ps
CPU time 4.99 seconds
Started Jun 23 05:10:21 PM PDT 24
Finished Jun 23 05:10:26 PM PDT 24
Peak memory 215456 kb
Host smart-88d4b01e-23b3-4a45-8160-7e0cd7d87614
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247636721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2247636721
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4060311103
Short name T1072
Test name
Test status
Simulation time 76294164 ps
CPU time 2.58 seconds
Started Jun 23 05:10:23 PM PDT 24
Finished Jun 23 05:10:27 PM PDT 24
Peak memory 216468 kb
Host smart-2a4db95d-1a22-4c02-b949-895f542f3ae0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060311103 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.4060311103
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.821956698
Short name T1043
Test name
Test status
Simulation time 78801944 ps
CPU time 1.34 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:24 PM PDT 24
Peak memory 206992 kb
Host smart-369f0902-0afd-4b99-ae52-e77bcf08a8d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821956698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.821956698
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.713843044
Short name T1070
Test name
Test status
Simulation time 38877203 ps
CPU time 0.69 seconds
Started Jun 23 05:10:21 PM PDT 24
Finished Jun 23 05:10:23 PM PDT 24
Peak memory 204008 kb
Host smart-ba4ea9c3-7bd6-4c8c-b15a-7a8ec221b217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713843044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.713843044
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.894316264
Short name T1061
Test name
Test status
Simulation time 482482434 ps
CPU time 3.07 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:26 PM PDT 24
Peak memory 215420 kb
Host smart-9e8f5bd1-a2c2-485e-98f2-1a6a31733865
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894316264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.894316264
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1965166557
Short name T91
Test name
Test status
Simulation time 124613859 ps
CPU time 3.53 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:26 PM PDT 24
Peak memory 215412 kb
Host smart-a3b28fe6-0198-4eaf-a56c-ad2347631799
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965166557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1965166557
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2222697422
Short name T1046
Test name
Test status
Simulation time 2689421709 ps
CPU time 13.85 seconds
Started Jun 23 05:10:24 PM PDT 24
Finished Jun 23 05:10:38 PM PDT 24
Peak memory 215368 kb
Host smart-18505d96-e90f-4fc5-adc6-96788ba3eb54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222697422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2222697422
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.920382205
Short name T1011
Test name
Test status
Simulation time 51268911 ps
CPU time 1.9 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:25 PM PDT 24
Peak memory 215280 kb
Host smart-39360a41-4be6-4f07-b5c4-73d9f8dc8546
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920382205 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.920382205
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1337567628
Short name T1069
Test name
Test status
Simulation time 38435092 ps
CPU time 1.95 seconds
Started Jun 23 05:10:23 PM PDT 24
Finished Jun 23 05:10:26 PM PDT 24
Peak memory 215312 kb
Host smart-86effdb2-81c7-431a-83d3-1af394a16a4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337567628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1337567628
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1588895664
Short name T988
Test name
Test status
Simulation time 15006441 ps
CPU time 0.71 seconds
Started Jun 23 05:10:20 PM PDT 24
Finished Jun 23 05:10:21 PM PDT 24
Peak memory 204028 kb
Host smart-204886e2-3a73-48a8-8593-8d8c5bf7b1e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588895664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1588895664
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2589807433
Short name T139
Test name
Test status
Simulation time 145623346 ps
CPU time 1.94 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:25 PM PDT 24
Peak memory 215412 kb
Host smart-65062ac1-ffdd-48f7-b7c4-45220fa733e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589807433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2589807433
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2700766694
Short name T102
Test name
Test status
Simulation time 167640433 ps
CPU time 3.92 seconds
Started Jun 23 05:10:23 PM PDT 24
Finished Jun 23 05:10:28 PM PDT 24
Peak memory 215484 kb
Host smart-027c23e1-dd82-450b-ae05-467fc37f2552
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700766694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2700766694
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.648619910
Short name T146
Test name
Test status
Simulation time 2900802721 ps
CPU time 16.78 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:39 PM PDT 24
Peak memory 223604 kb
Host smart-3b0bbf5e-29da-491c-b4a0-cf8bd6fcb042
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648619910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.648619910
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2547707001
Short name T1015
Test name
Test status
Simulation time 182159944 ps
CPU time 3.51 seconds
Started Jun 23 05:10:26 PM PDT 24
Finished Jun 23 05:10:30 PM PDT 24
Peak memory 218324 kb
Host smart-5608ee08-7788-4106-bbcd-4be048a17895
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547707001 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2547707001
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4091494477
Short name T117
Test name
Test status
Simulation time 64009795 ps
CPU time 1.25 seconds
Started Jun 23 05:10:27 PM PDT 24
Finished Jun 23 05:10:29 PM PDT 24
Peak memory 207036 kb
Host smart-77200cd1-0250-4b36-8df5-867b077d7e43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091494477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
4091494477
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1729493033
Short name T1073
Test name
Test status
Simulation time 14393826 ps
CPU time 0.71 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:24 PM PDT 24
Peak memory 203700 kb
Host smart-ec9ec9c8-492e-462b-8fe1-f8549ee75a1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729493033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1729493033
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2266966381
Short name T1036
Test name
Test status
Simulation time 411392281 ps
CPU time 3.8 seconds
Started Jun 23 05:10:21 PM PDT 24
Finished Jun 23 05:10:25 PM PDT 24
Peak memory 215352 kb
Host smart-79f8f539-fbcd-47b4-8c75-d19e3562f5de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266966381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2266966381
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1849745933
Short name T165
Test name
Test status
Simulation time 407712125 ps
CPU time 8.18 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:32 PM PDT 24
Peak memory 215864 kb
Host smart-a4b0f6b1-6993-446a-956c-7a90ab3d699a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849745933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1849745933
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2091063351
Short name T1012
Test name
Test status
Simulation time 318547842 ps
CPU time 2.8 seconds
Started Jun 23 05:10:24 PM PDT 24
Finished Jun 23 05:10:27 PM PDT 24
Peak memory 216408 kb
Host smart-81068788-be42-400c-a2cb-b546df4b9ca1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091063351 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2091063351
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1232684447
Short name T119
Test name
Test status
Simulation time 73504444 ps
CPU time 1.81 seconds
Started Jun 23 05:10:21 PM PDT 24
Finished Jun 23 05:10:24 PM PDT 24
Peak memory 206976 kb
Host smart-74d885f6-b5ef-4647-a026-33c0cbbc875e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232684447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1232684447
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2422851257
Short name T1027
Test name
Test status
Simulation time 79580951 ps
CPU time 0.73 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:23 PM PDT 24
Peak memory 203764 kb
Host smart-67218527-a7d0-4b81-8a95-8c456a3d1fdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422851257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2422851257
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1544701414
Short name T1095
Test name
Test status
Simulation time 2386106047 ps
CPU time 4.18 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:27 PM PDT 24
Peak memory 215572 kb
Host smart-f9f018f1-df2f-4c77-8718-ff74d305486a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544701414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1544701414
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.4044824217
Short name T1028
Test name
Test status
Simulation time 217445634 ps
CPU time 6.67 seconds
Started Jun 23 05:10:21 PM PDT 24
Finished Jun 23 05:10:28 PM PDT 24
Peak memory 215476 kb
Host smart-392a65eb-e3a6-4327-9a58-138c3155f632
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044824217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.4044824217
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1417289885
Short name T1056
Test name
Test status
Simulation time 158345646 ps
CPU time 2.59 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:26 PM PDT 24
Peak memory 216528 kb
Host smart-1cee0213-1fb5-4733-936a-6b4369119bd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417289885 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1417289885
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1995537331
Short name T126
Test name
Test status
Simulation time 231640854 ps
CPU time 3.01 seconds
Started Jun 23 05:10:25 PM PDT 24
Finished Jun 23 05:10:29 PM PDT 24
Peak memory 215364 kb
Host smart-dd5262a0-d0b8-4ecb-92ae-8fe3370d1717
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995537331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1995537331
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1389467972
Short name T1013
Test name
Test status
Simulation time 26855263 ps
CPU time 0.74 seconds
Started Jun 23 05:10:27 PM PDT 24
Finished Jun 23 05:10:28 PM PDT 24
Peak memory 203716 kb
Host smart-61253b83-5548-42c0-8243-9c6c9ba707b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389467972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1389467972
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2612123820
Short name T137
Test name
Test status
Simulation time 148406222 ps
CPU time 3.08 seconds
Started Jun 23 05:10:26 PM PDT 24
Finished Jun 23 05:10:30 PM PDT 24
Peak memory 215412 kb
Host smart-0fb98500-7a19-430e-93a1-6d5587fee28a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612123820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2612123820
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1886655830
Short name T105
Test name
Test status
Simulation time 115846794 ps
CPU time 4.11 seconds
Started Jun 23 05:10:31 PM PDT 24
Finished Jun 23 05:10:36 PM PDT 24
Peak memory 219560 kb
Host smart-e051fe44-c91e-4582-bb43-83ca4e78fc1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886655830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1886655830
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1297578004
Short name T103
Test name
Test status
Simulation time 559367690 ps
CPU time 6.46 seconds
Started Jun 23 05:10:27 PM PDT 24
Finished Jun 23 05:10:34 PM PDT 24
Peak memory 215872 kb
Host smart-f2e89ff7-9009-47f5-b0d3-2aef21d8d75f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297578004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1297578004
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2517110778
Short name T90
Test name
Test status
Simulation time 58527610 ps
CPU time 1.62 seconds
Started Jun 23 05:10:20 PM PDT 24
Finished Jun 23 05:10:22 PM PDT 24
Peak memory 215416 kb
Host smart-023aad27-c0d7-440e-b58c-d7267f08d3ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517110778 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2517110778
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.877759493
Short name T1079
Test name
Test status
Simulation time 108020754 ps
CPU time 2.64 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:26 PM PDT 24
Peak memory 215364 kb
Host smart-620d0215-6164-4b4f-9290-25b2da59415d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877759493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.877759493
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2548639656
Short name T985
Test name
Test status
Simulation time 15899970 ps
CPU time 0.7 seconds
Started Jun 23 05:10:26 PM PDT 24
Finished Jun 23 05:10:27 PM PDT 24
Peak memory 203608 kb
Host smart-4f61b843-9e90-463f-943d-380f1478cb07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548639656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2548639656
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3708544031
Short name T986
Test name
Test status
Simulation time 164057207 ps
CPU time 4.16 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:27 PM PDT 24
Peak memory 215292 kb
Host smart-1b40fc29-f79c-44e3-a0a8-3ca09b24111d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708544031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3708544031
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1998423357
Short name T1002
Test name
Test status
Simulation time 106720266 ps
CPU time 1.9 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:25 PM PDT 24
Peak memory 215604 kb
Host smart-f7d7218a-ebfd-486f-a087-f217426ca1c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998423357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1998423357
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3031781934
Short name T163
Test name
Test status
Simulation time 818620236 ps
CPU time 12.67 seconds
Started Jun 23 05:10:23 PM PDT 24
Finished Jun 23 05:10:36 PM PDT 24
Peak memory 215816 kb
Host smart-7660bcf6-0182-461c-99cf-a17924536ca4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031781934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3031781934
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.43692792
Short name T1101
Test name
Test status
Simulation time 117803984 ps
CPU time 8.22 seconds
Started Jun 23 05:10:02 PM PDT 24
Finished Jun 23 05:10:12 PM PDT 24
Peak memory 207072 kb
Host smart-0e910d73-a3da-49fa-a8aa-e9db6cce81a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43692792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_
aliasing.43692792
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.713027587
Short name T156
Test name
Test status
Simulation time 941834720 ps
CPU time 14.81 seconds
Started Jun 23 05:10:02 PM PDT 24
Finished Jun 23 05:10:18 PM PDT 24
Peak memory 207032 kb
Host smart-a405ce54-1411-497f-b811-3f86e2e9aeff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713027587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.713027587
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2835438035
Short name T81
Test name
Test status
Simulation time 82428665 ps
CPU time 1.36 seconds
Started Jun 23 05:10:02 PM PDT 24
Finished Jun 23 05:10:05 PM PDT 24
Peak memory 207080 kb
Host smart-5d3b8885-27e8-4d1c-a88f-c1307b2158e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835438035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2835438035
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1751926852
Short name T1054
Test name
Test status
Simulation time 225005203 ps
CPU time 3.73 seconds
Started Jun 23 05:10:04 PM PDT 24
Finished Jun 23 05:10:09 PM PDT 24
Peak memory 217840 kb
Host smart-6668e544-1590-4e10-9702-559438d10b63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751926852 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1751926852
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3799934400
Short name T1060
Test name
Test status
Simulation time 95095143 ps
CPU time 2.42 seconds
Started Jun 23 05:10:02 PM PDT 24
Finished Jun 23 05:10:06 PM PDT 24
Peak memory 215528 kb
Host smart-97a89396-30a7-4c9f-8555-93afd0dcc9f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799934400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
799934400
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.846984773
Short name T983
Test name
Test status
Simulation time 118418026 ps
CPU time 0.82 seconds
Started Jun 23 05:10:04 PM PDT 24
Finished Jun 23 05:10:05 PM PDT 24
Peak memory 203684 kb
Host smart-5686b096-f4df-4371-a748-cc24e3946fbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846984773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.846984773
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3017418633
Short name T1038
Test name
Test status
Simulation time 208030279 ps
CPU time 1.97 seconds
Started Jun 23 05:10:04 PM PDT 24
Finished Jun 23 05:10:07 PM PDT 24
Peak memory 215636 kb
Host smart-6df48b97-2eb8-4938-9cf0-17a84c082a81
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017418633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3017418633
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3176001817
Short name T1086
Test name
Test status
Simulation time 28460174 ps
CPU time 0.68 seconds
Started Jun 23 05:10:03 PM PDT 24
Finished Jun 23 05:10:05 PM PDT 24
Peak memory 203844 kb
Host smart-cb89e6f3-4e33-4b60-9b92-401e664617fe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176001817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3176001817
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2568309173
Short name T1020
Test name
Test status
Simulation time 108815585 ps
CPU time 3.02 seconds
Started Jun 23 05:10:06 PM PDT 24
Finished Jun 23 05:10:09 PM PDT 24
Peak memory 215448 kb
Host smart-551fd309-a48b-442a-8dc9-e17f233ab816
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568309173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2568309173
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.79016982
Short name T161
Test name
Test status
Simulation time 204293097 ps
CPU time 3.27 seconds
Started Jun 23 05:10:03 PM PDT 24
Finished Jun 23 05:10:08 PM PDT 24
Peak memory 215512 kb
Host smart-945f1577-89dc-4038-8110-c7de1bbffe2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79016982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.79016982
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2857123349
Short name T1049
Test name
Test status
Simulation time 12046922 ps
CPU time 0.69 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:24 PM PDT 24
Peak memory 203620 kb
Host smart-5c5f66c7-39d9-40b7-a5db-348b7810355d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857123349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2857123349
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2252673122
Short name T1062
Test name
Test status
Simulation time 13148458 ps
CPU time 0.76 seconds
Started Jun 23 05:10:20 PM PDT 24
Finished Jun 23 05:10:21 PM PDT 24
Peak memory 203764 kb
Host smart-8d0fe5fc-0d8e-44ac-b736-9761ba08995c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252673122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2252673122
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.275757193
Short name T1018
Test name
Test status
Simulation time 72615495 ps
CPU time 0.75 seconds
Started Jun 23 05:10:21 PM PDT 24
Finished Jun 23 05:10:23 PM PDT 24
Peak memory 203732 kb
Host smart-66413948-c9cf-4143-a918-cfba5d5731e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275757193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.275757193
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1087718416
Short name T1009
Test name
Test status
Simulation time 12185485 ps
CPU time 0.72 seconds
Started Jun 23 05:10:27 PM PDT 24
Finished Jun 23 05:10:28 PM PDT 24
Peak memory 203608 kb
Host smart-288d165f-4083-46dd-aacc-9fb6bf531280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087718416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1087718416
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3416234038
Short name T1099
Test name
Test status
Simulation time 46790198 ps
CPU time 0.77 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:23 PM PDT 24
Peak memory 204016 kb
Host smart-d03f828c-5fef-471d-8edd-083779735818
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416234038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3416234038
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3425064987
Short name T1087
Test name
Test status
Simulation time 22062366 ps
CPU time 0.7 seconds
Started Jun 23 05:10:26 PM PDT 24
Finished Jun 23 05:10:27 PM PDT 24
Peak memory 203676 kb
Host smart-f1522958-7319-4aa6-882f-9372162b6749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425064987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3425064987
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2120819961
Short name T1035
Test name
Test status
Simulation time 12778447 ps
CPU time 0.73 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:24 PM PDT 24
Peak memory 203848 kb
Host smart-ae488997-39fa-40fc-8d45-a54059986dac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120819961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2120819961
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3367740418
Short name T1042
Test name
Test status
Simulation time 25864424 ps
CPU time 0.73 seconds
Started Jun 23 05:10:25 PM PDT 24
Finished Jun 23 05:10:26 PM PDT 24
Peak memory 203764 kb
Host smart-c48037bc-bfbc-4f69-a5f3-f02a97c888d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367740418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3367740418
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3222950644
Short name T1053
Test name
Test status
Simulation time 14499946 ps
CPU time 0.78 seconds
Started Jun 23 05:10:23 PM PDT 24
Finished Jun 23 05:10:25 PM PDT 24
Peak memory 203736 kb
Host smart-4018ae62-acbc-4a4c-9f80-22638fb7d579
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222950644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3222950644
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2372291573
Short name T994
Test name
Test status
Simulation time 13510680 ps
CPU time 0.78 seconds
Started Jun 23 05:10:22 PM PDT 24
Finished Jun 23 05:10:24 PM PDT 24
Peak memory 203936 kb
Host smart-0f4e5c3d-34d7-41ae-8f2e-9a9ae3347e83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372291573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2372291573
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2045810715
Short name T124
Test name
Test status
Simulation time 4119882924 ps
CPU time 22.37 seconds
Started Jun 23 05:10:09 PM PDT 24
Finished Jun 23 05:10:31 PM PDT 24
Peak memory 215388 kb
Host smart-edf66805-71e8-4d1e-b749-4917dc328cd4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045810715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2045810715
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1640600075
Short name T127
Test name
Test status
Simulation time 727712365 ps
CPU time 31.52 seconds
Started Jun 23 05:10:02 PM PDT 24
Finished Jun 23 05:10:35 PM PDT 24
Peak memory 215220 kb
Host smart-fc25a909-35ef-45d7-8e68-573861cbae89
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640600075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1640600075
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.553681571
Short name T1082
Test name
Test status
Simulation time 114603885 ps
CPU time 1.16 seconds
Started Jun 23 05:10:03 PM PDT 24
Finished Jun 23 05:10:06 PM PDT 24
Peak memory 207068 kb
Host smart-9fd0cffd-9b5d-414c-a6ce-cff10cce49a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553681571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.553681571
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1138689872
Short name T108
Test name
Test status
Simulation time 81197578 ps
CPU time 1.69 seconds
Started Jun 23 05:10:13 PM PDT 24
Finished Jun 23 05:10:15 PM PDT 24
Peak memory 215804 kb
Host smart-c75b5827-b265-4e57-bc4b-1d55f4d4dd03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138689872 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1138689872
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2533167987
Short name T1048
Test name
Test status
Simulation time 253680545 ps
CPU time 2.11 seconds
Started Jun 23 05:10:04 PM PDT 24
Finished Jun 23 05:10:07 PM PDT 24
Peak memory 207004 kb
Host smart-c7b13537-346e-4ee3-9a1b-69e2c20a2899
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533167987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
533167987
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.291836623
Short name T1040
Test name
Test status
Simulation time 43179637 ps
CPU time 0.74 seconds
Started Jun 23 05:10:04 PM PDT 24
Finished Jun 23 05:10:06 PM PDT 24
Peak memory 203952 kb
Host smart-2a1f00b7-cc15-4d3c-b27a-7de35fcc122e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291836623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.291836623
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1097840272
Short name T1077
Test name
Test status
Simulation time 77363888 ps
CPU time 1.56 seconds
Started Jun 23 05:10:01 PM PDT 24
Finished Jun 23 05:10:02 PM PDT 24
Peak memory 215324 kb
Host smart-5c445186-1dad-4c8e-8113-f185b029bea9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097840272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1097840272
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.368112540
Short name T1001
Test name
Test status
Simulation time 12980529 ps
CPU time 0.67 seconds
Started Jun 23 05:10:04 PM PDT 24
Finished Jun 23 05:10:06 PM PDT 24
Peak memory 203620 kb
Host smart-f28c0a47-824e-4ec6-acfb-2d4422082cf4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368112540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.368112540
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3316045065
Short name T141
Test name
Test status
Simulation time 983266645 ps
CPU time 1.83 seconds
Started Jun 23 05:10:11 PM PDT 24
Finished Jun 23 05:10:14 PM PDT 24
Peak memory 215340 kb
Host smart-4c18f3c1-edb8-4548-bd0a-9da8eff40dac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316045065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3316045065
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2688066121
Short name T1068
Test name
Test status
Simulation time 408640144 ps
CPU time 2.99 seconds
Started Jun 23 05:10:03 PM PDT 24
Finished Jun 23 05:10:07 PM PDT 24
Peak memory 215572 kb
Host smart-c6ff20b8-e3be-474d-9db5-30562d20bbf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688066121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
688066121
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.447754599
Short name T1051
Test name
Test status
Simulation time 205513868 ps
CPU time 6.43 seconds
Started Jun 23 05:10:02 PM PDT 24
Finished Jun 23 05:10:10 PM PDT 24
Peak memory 215416 kb
Host smart-31e7c622-2c59-4a97-a05e-fbd405eb6c6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447754599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.447754599
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3135984845
Short name T989
Test name
Test status
Simulation time 16547981 ps
CPU time 0.78 seconds
Started Jun 23 05:10:29 PM PDT 24
Finished Jun 23 05:10:30 PM PDT 24
Peak memory 203956 kb
Host smart-1550279e-0bfc-4241-8701-51f5639faadb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135984845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3135984845
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3465262892
Short name T1019
Test name
Test status
Simulation time 38751673 ps
CPU time 0.67 seconds
Started Jun 23 05:10:28 PM PDT 24
Finished Jun 23 05:10:30 PM PDT 24
Peak memory 203672 kb
Host smart-32a855ff-6fc8-4fe6-86e1-0005ca3b0678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465262892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3465262892
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3132196870
Short name T1050
Test name
Test status
Simulation time 47783687 ps
CPU time 0.77 seconds
Started Jun 23 05:10:26 PM PDT 24
Finished Jun 23 05:10:28 PM PDT 24
Peak memory 203704 kb
Host smart-7e621a5d-3375-4c8f-99bd-5999d66fe362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132196870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3132196870
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.26863008
Short name T1024
Test name
Test status
Simulation time 14128209 ps
CPU time 0.72 seconds
Started Jun 23 05:10:29 PM PDT 24
Finished Jun 23 05:10:30 PM PDT 24
Peak memory 203756 kb
Host smart-e2eed3f7-cffc-4317-8ff8-662a3ae2ed0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26863008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.26863008
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2497982944
Short name T987
Test name
Test status
Simulation time 43393262 ps
CPU time 0.79 seconds
Started Jun 23 05:10:32 PM PDT 24
Finished Jun 23 05:10:33 PM PDT 24
Peak memory 203780 kb
Host smart-a172a0a8-95d9-46db-9a1a-314b4bd68f9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497982944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2497982944
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.685010386
Short name T1063
Test name
Test status
Simulation time 27293027 ps
CPU time 0.75 seconds
Started Jun 23 05:10:27 PM PDT 24
Finished Jun 23 05:10:29 PM PDT 24
Peak memory 203756 kb
Host smart-e5fd16f3-b6ea-448d-bb69-95c1e6a00ade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685010386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.685010386
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3793409248
Short name T1004
Test name
Test status
Simulation time 20835362 ps
CPU time 0.72 seconds
Started Jun 23 05:10:31 PM PDT 24
Finished Jun 23 05:10:32 PM PDT 24
Peak memory 203972 kb
Host smart-869a52ec-bd9d-43cf-8619-48a161eb6beb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793409248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3793409248
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3556695071
Short name T980
Test name
Test status
Simulation time 142831821 ps
CPU time 0.77 seconds
Started Jun 23 05:10:27 PM PDT 24
Finished Jun 23 05:10:29 PM PDT 24
Peak memory 203896 kb
Host smart-00b0c681-1c3f-463a-80ef-9cd27e234cd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556695071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3556695071
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3812933909
Short name T997
Test name
Test status
Simulation time 13604446 ps
CPU time 0.71 seconds
Started Jun 23 05:10:28 PM PDT 24
Finished Jun 23 05:10:30 PM PDT 24
Peak memory 203712 kb
Host smart-f845fdc9-5a13-49f2-9e90-e985eaee9713
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812933909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3812933909
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.553739882
Short name T992
Test name
Test status
Simulation time 15970782 ps
CPU time 0.74 seconds
Started Jun 23 05:10:28 PM PDT 24
Finished Jun 23 05:10:30 PM PDT 24
Peak memory 203684 kb
Host smart-7854891b-9151-49ef-8746-8d5c3ddff39f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553739882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.553739882
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3510676919
Short name T1017
Test name
Test status
Simulation time 1577729333 ps
CPU time 8.3 seconds
Started Jun 23 05:10:14 PM PDT 24
Finished Jun 23 05:10:23 PM PDT 24
Peak memory 215260 kb
Host smart-72b25d2e-fce7-454c-b570-121c1ddb7942
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510676919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3510676919
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2689497271
Short name T123
Test name
Test status
Simulation time 188696112 ps
CPU time 12.52 seconds
Started Jun 23 05:10:13 PM PDT 24
Finished Jun 23 05:10:27 PM PDT 24
Peak memory 216448 kb
Host smart-8cff8699-c2fc-4e1c-9814-c29ed541e598
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689497271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2689497271
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3885380949
Short name T82
Test name
Test status
Simulation time 230808309 ps
CPU time 1.04 seconds
Started Jun 23 05:10:10 PM PDT 24
Finished Jun 23 05:10:12 PM PDT 24
Peak memory 206932 kb
Host smart-f52ec580-e13d-498c-ace4-b0b1035b1ede
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885380949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3885380949
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1408528535
Short name T1067
Test name
Test status
Simulation time 97337940 ps
CPU time 3.64 seconds
Started Jun 23 05:10:09 PM PDT 24
Finished Jun 23 05:10:13 PM PDT 24
Peak memory 217024 kb
Host smart-01d4198b-7831-4643-bf2d-a59242a80611
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408528535 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1408528535
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1207092162
Short name T121
Test name
Test status
Simulation time 70560700 ps
CPU time 2.12 seconds
Started Jun 23 05:10:11 PM PDT 24
Finished Jun 23 05:10:14 PM PDT 24
Peak memory 215244 kb
Host smart-e88bc9e6-faeb-4d17-9dfd-84dfc3497e84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207092162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
207092162
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2147758276
Short name T1044
Test name
Test status
Simulation time 13036369 ps
CPU time 0.73 seconds
Started Jun 23 05:10:08 PM PDT 24
Finished Jun 23 05:10:09 PM PDT 24
Peak memory 204016 kb
Host smart-dbe7008d-733c-4f83-ad18-00b05b80c190
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147758276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
147758276
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.190643895
Short name T1088
Test name
Test status
Simulation time 83617529 ps
CPU time 2.04 seconds
Started Jun 23 05:10:08 PM PDT 24
Finished Jun 23 05:10:10 PM PDT 24
Peak memory 215420 kb
Host smart-a939ffbd-fa3d-4be0-8ee6-30c059459505
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190643895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.190643895
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4161982813
Short name T1080
Test name
Test status
Simulation time 22715638 ps
CPU time 0.66 seconds
Started Jun 23 05:10:10 PM PDT 24
Finished Jun 23 05:10:11 PM PDT 24
Peak memory 203532 kb
Host smart-eba93b5d-9fe0-4b65-bdab-6dc8c1968d83
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161982813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4161982813
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3022805044
Short name T990
Test name
Test status
Simulation time 60051281 ps
CPU time 3.51 seconds
Started Jun 23 05:10:13 PM PDT 24
Finished Jun 23 05:10:17 PM PDT 24
Peak memory 216484 kb
Host smart-dc03ccee-bb86-4916-84e9-2a27edef402d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022805044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3022805044
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3940786849
Short name T100
Test name
Test status
Simulation time 71138742 ps
CPU time 2.3 seconds
Started Jun 23 05:10:11 PM PDT 24
Finished Jun 23 05:10:15 PM PDT 24
Peak memory 215520 kb
Host smart-b654cabe-9061-47d4-a4b1-de4fc939ba9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940786849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
940786849
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.994175423
Short name T1084
Test name
Test status
Simulation time 1210519711 ps
CPU time 18.6 seconds
Started Jun 23 05:10:09 PM PDT 24
Finished Jun 23 05:10:29 PM PDT 24
Peak memory 222380 kb
Host smart-127435c0-f22c-4990-8ef0-521963b7da84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994175423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.994175423
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1366659152
Short name T1041
Test name
Test status
Simulation time 22964050 ps
CPU time 0.68 seconds
Started Jun 23 05:10:28 PM PDT 24
Finished Jun 23 05:10:30 PM PDT 24
Peak memory 203604 kb
Host smart-4c4d81b3-513a-454c-ac1e-d503dd9d6025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366659152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1366659152
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.615507742
Short name T1078
Test name
Test status
Simulation time 13802141 ps
CPU time 0.8 seconds
Started Jun 23 05:10:28 PM PDT 24
Finished Jun 23 05:10:29 PM PDT 24
Peak memory 204016 kb
Host smart-70d33877-b697-4209-a425-b38306e66528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615507742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.615507742
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.587915432
Short name T978
Test name
Test status
Simulation time 42110669 ps
CPU time 0.76 seconds
Started Jun 23 05:10:28 PM PDT 24
Finished Jun 23 05:10:29 PM PDT 24
Peak memory 203752 kb
Host smart-ae8df49f-3868-462a-acaf-e882f9fd7050
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587915432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.587915432
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.736331113
Short name T984
Test name
Test status
Simulation time 14684044 ps
CPU time 0.75 seconds
Started Jun 23 05:10:30 PM PDT 24
Finished Jun 23 05:10:31 PM PDT 24
Peak memory 204020 kb
Host smart-6c3620a3-b94c-4214-8968-710e3b4ff0a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736331113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.736331113
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2973461610
Short name T996
Test name
Test status
Simulation time 33254731 ps
CPU time 0.7 seconds
Started Jun 23 05:10:28 PM PDT 24
Finished Jun 23 05:10:29 PM PDT 24
Peak memory 203712 kb
Host smart-df26a63e-8e3d-4137-8000-278110bd3c69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973461610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2973461610
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2646490578
Short name T1052
Test name
Test status
Simulation time 140719572 ps
CPU time 0.76 seconds
Started Jun 23 05:10:30 PM PDT 24
Finished Jun 23 05:10:32 PM PDT 24
Peak memory 203676 kb
Host smart-66258eb5-a3e5-4825-a6e0-09d7b0ae9862
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646490578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2646490578
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.371761705
Short name T1047
Test name
Test status
Simulation time 15657903 ps
CPU time 0.78 seconds
Started Jun 23 05:10:32 PM PDT 24
Finished Jun 23 05:10:33 PM PDT 24
Peak memory 203772 kb
Host smart-a62db6b8-e79a-4aed-98fb-2c262e19ad86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371761705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.371761705
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3147578385
Short name T1003
Test name
Test status
Simulation time 16332381 ps
CPU time 0.77 seconds
Started Jun 23 05:10:28 PM PDT 24
Finished Jun 23 05:10:29 PM PDT 24
Peak memory 204016 kb
Host smart-b68e7915-51cc-48e6-9018-20ceb6d3148e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147578385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3147578385
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.113700781
Short name T979
Test name
Test status
Simulation time 12980551 ps
CPU time 0.78 seconds
Started Jun 23 05:10:32 PM PDT 24
Finished Jun 23 05:10:33 PM PDT 24
Peak memory 204036 kb
Host smart-8dd63ebb-d885-41bc-a90a-9665618df0bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113700781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.113700781
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2428042651
Short name T1089
Test name
Test status
Simulation time 30352109 ps
CPU time 0.78 seconds
Started Jun 23 05:10:28 PM PDT 24
Finished Jun 23 05:10:29 PM PDT 24
Peak memory 203752 kb
Host smart-ed44458a-803c-4626-a1a4-e164a01774d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428042651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2428042651
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1622674993
Short name T95
Test name
Test status
Simulation time 247747803 ps
CPU time 1.84 seconds
Started Jun 23 05:10:11 PM PDT 24
Finished Jun 23 05:10:14 PM PDT 24
Peak memory 215392 kb
Host smart-7fcf5146-1e95-4fc0-ab94-dfe80b7e6996
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622674993 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1622674993
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1169009303
Short name T1034
Test name
Test status
Simulation time 102128418 ps
CPU time 2 seconds
Started Jun 23 05:10:10 PM PDT 24
Finished Jun 23 05:10:13 PM PDT 24
Peak memory 215308 kb
Host smart-ea83c7ec-f5c5-4937-85ba-845bb5f3044a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169009303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
169009303
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2823226723
Short name T1057
Test name
Test status
Simulation time 31049309 ps
CPU time 0.76 seconds
Started Jun 23 05:10:09 PM PDT 24
Finished Jun 23 05:10:10 PM PDT 24
Peak memory 203776 kb
Host smart-1caca3e4-a84d-41ef-bd53-bae5bd6be15e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823226723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
823226723
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3129642621
Short name T1097
Test name
Test status
Simulation time 241834495 ps
CPU time 4.03 seconds
Started Jun 23 05:10:13 PM PDT 24
Finished Jun 23 05:10:17 PM PDT 24
Peak memory 215480 kb
Host smart-561786d2-dab2-4cc9-9d0c-facfcf837270
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129642621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3129642621
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3276543633
Short name T1016
Test name
Test status
Simulation time 117467998 ps
CPU time 1.93 seconds
Started Jun 23 05:10:08 PM PDT 24
Finished Jun 23 05:10:11 PM PDT 24
Peak memory 216540 kb
Host smart-8ab69c61-276f-42e9-a31b-f63360469ae0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276543633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
276543633
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3686027301
Short name T1021
Test name
Test status
Simulation time 1054218314 ps
CPU time 8.46 seconds
Started Jun 23 05:10:11 PM PDT 24
Finished Jun 23 05:10:20 PM PDT 24
Peak memory 215320 kb
Host smart-8f01d22e-c257-4f4f-a7e7-a4621770648c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686027301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3686027301
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3073632011
Short name T106
Test name
Test status
Simulation time 726285191 ps
CPU time 3.98 seconds
Started Jun 23 05:10:12 PM PDT 24
Finished Jun 23 05:10:17 PM PDT 24
Peak memory 217392 kb
Host smart-fa730a50-80af-4e24-af64-64401de1616a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073632011 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3073632011
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2352476364
Short name T1029
Test name
Test status
Simulation time 100427120 ps
CPU time 1.79 seconds
Started Jun 23 05:10:14 PM PDT 24
Finished Jun 23 05:10:16 PM PDT 24
Peak memory 215248 kb
Host smart-11d44f71-2bdb-4108-9e49-24d85fb08454
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352476364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
352476364
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3649889649
Short name T1098
Test name
Test status
Simulation time 12318872 ps
CPU time 0.7 seconds
Started Jun 23 05:10:12 PM PDT 24
Finished Jun 23 05:10:13 PM PDT 24
Peak memory 203676 kb
Host smart-b5d25fd6-7e74-43ee-9472-17f5dfa19263
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649889649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
649889649
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1642421108
Short name T1075
Test name
Test status
Simulation time 217101914 ps
CPU time 3.93 seconds
Started Jun 23 05:10:09 PM PDT 24
Finished Jun 23 05:10:13 PM PDT 24
Peak memory 215384 kb
Host smart-09ce2238-6dfb-4990-89b1-8d9ae14250d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642421108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1642421108
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1034188306
Short name T104
Test name
Test status
Simulation time 526029606 ps
CPU time 3.38 seconds
Started Jun 23 05:10:12 PM PDT 24
Finished Jun 23 05:10:16 PM PDT 24
Peak memory 215524 kb
Host smart-76f78557-74aa-4667-94c4-b85e79c4e2c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034188306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
034188306
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.777570477
Short name T1081
Test name
Test status
Simulation time 607235284 ps
CPU time 8.34 seconds
Started Jun 23 05:10:09 PM PDT 24
Finished Jun 23 05:10:18 PM PDT 24
Peak memory 215708 kb
Host smart-3a39a6bb-4213-4bca-a4d9-221545ebace2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777570477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.777570477
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.116832297
Short name T1045
Test name
Test status
Simulation time 202283865 ps
CPU time 2.55 seconds
Started Jun 23 05:10:07 PM PDT 24
Finished Jun 23 05:10:10 PM PDT 24
Peak memory 217516 kb
Host smart-67d71556-141e-46fd-9b24-a317a9e45e81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116832297 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.116832297
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2529073577
Short name T116
Test name
Test status
Simulation time 284458009 ps
CPU time 1.96 seconds
Started Jun 23 05:10:09 PM PDT 24
Finished Jun 23 05:10:12 PM PDT 24
Peak memory 207100 kb
Host smart-9fdfe56b-ca53-41a8-9ccd-20e89baa8dcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529073577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
529073577
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1857924048
Short name T1092
Test name
Test status
Simulation time 17557628 ps
CPU time 0.71 seconds
Started Jun 23 05:10:08 PM PDT 24
Finished Jun 23 05:10:09 PM PDT 24
Peak memory 203632 kb
Host smart-a107aac2-99d8-424f-939e-bdcaca0a0f3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857924048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
857924048
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.631497780
Short name T1085
Test name
Test status
Simulation time 461277551 ps
CPU time 2.92 seconds
Started Jun 23 05:10:08 PM PDT 24
Finished Jun 23 05:10:11 PM PDT 24
Peak memory 215288 kb
Host smart-d9774072-66a7-42ae-9c6e-706977da919f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631497780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.631497780
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.544477617
Short name T1100
Test name
Test status
Simulation time 59443613 ps
CPU time 1.81 seconds
Started Jun 23 05:10:09 PM PDT 24
Finished Jun 23 05:10:11 PM PDT 24
Peak memory 215412 kb
Host smart-f48cf04c-d155-41a6-ba78-32db7f5c00d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544477617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.544477617
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4080754506
Short name T107
Test name
Test status
Simulation time 293762387 ps
CPU time 17.72 seconds
Started Jun 23 05:10:13 PM PDT 24
Finished Jun 23 05:10:31 PM PDT 24
Peak memory 215368 kb
Host smart-bfba70a6-0096-4d59-890a-79708fb98eb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080754506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.4080754506
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.916806514
Short name T1093
Test name
Test status
Simulation time 27562094 ps
CPU time 1.75 seconds
Started Jun 23 05:10:16 PM PDT 24
Finished Jun 23 05:10:18 PM PDT 24
Peak memory 215380 kb
Host smart-3113d9f8-9811-448d-b7a6-8bc96ebf3720
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916806514 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.916806514
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1142594280
Short name T1008
Test name
Test status
Simulation time 103499043 ps
CPU time 1.87 seconds
Started Jun 23 05:10:09 PM PDT 24
Finished Jun 23 05:10:12 PM PDT 24
Peak memory 215220 kb
Host smart-67ca1a32-c5cc-4a5a-b8a0-25f7585a69d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142594280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
142594280
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2365940172
Short name T982
Test name
Test status
Simulation time 58290586 ps
CPU time 0.82 seconds
Started Jun 23 05:10:08 PM PDT 24
Finished Jun 23 05:10:09 PM PDT 24
Peak memory 203764 kb
Host smart-6be74b7b-4bbc-48ea-8291-3ffe5aa653bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365940172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
365940172
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2403118014
Short name T1059
Test name
Test status
Simulation time 716344724 ps
CPU time 4.02 seconds
Started Jun 23 05:10:14 PM PDT 24
Finished Jun 23 05:10:19 PM PDT 24
Peak memory 215300 kb
Host smart-c4270c0a-d2ba-441d-8501-995408b52c6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403118014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2403118014
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1373975499
Short name T1091
Test name
Test status
Simulation time 1064606227 ps
CPU time 4.82 seconds
Started Jun 23 05:10:11 PM PDT 24
Finished Jun 23 05:10:16 PM PDT 24
Peak memory 215388 kb
Host smart-9ed5f2ae-6f28-4510-898b-8e591c6fb43c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373975499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
373975499
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.188408506
Short name T998
Test name
Test status
Simulation time 176753956 ps
CPU time 6.63 seconds
Started Jun 23 05:10:09 PM PDT 24
Finished Jun 23 05:10:17 PM PDT 24
Peak memory 215364 kb
Host smart-44a0dfb4-6cc0-458a-bc94-1fbe79181902
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188408506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.188408506
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1559723451
Short name T1022
Test name
Test status
Simulation time 363848167 ps
CPU time 2.91 seconds
Started Jun 23 05:10:16 PM PDT 24
Finished Jun 23 05:10:19 PM PDT 24
Peak memory 216784 kb
Host smart-1e8b820f-34c7-4940-94bc-b9ac0fd9487e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559723451 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1559723451
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2583940844
Short name T1083
Test name
Test status
Simulation time 85636068 ps
CPU time 2.66 seconds
Started Jun 23 05:10:15 PM PDT 24
Finished Jun 23 05:10:18 PM PDT 24
Peak memory 215320 kb
Host smart-bfcfbd9d-9643-4a75-9bfc-e799ea6467e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583940844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
583940844
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1016514932
Short name T1007
Test name
Test status
Simulation time 32339028 ps
CPU time 0.76 seconds
Started Jun 23 05:10:17 PM PDT 24
Finished Jun 23 05:10:18 PM PDT 24
Peak memory 203936 kb
Host smart-566ca192-6db1-4d04-8d38-34ca847f539f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016514932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
016514932
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3401899506
Short name T995
Test name
Test status
Simulation time 59432756 ps
CPU time 3.63 seconds
Started Jun 23 05:10:19 PM PDT 24
Finished Jun 23 05:10:23 PM PDT 24
Peak memory 215380 kb
Host smart-1ce6b7a2-6970-4eba-8d16-97f44b3c4a62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401899506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3401899506
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2524808964
Short name T99
Test name
Test status
Simulation time 53817490 ps
CPU time 3.27 seconds
Started Jun 23 05:10:15 PM PDT 24
Finished Jun 23 05:10:20 PM PDT 24
Peak memory 216452 kb
Host smart-651c00b7-e0ab-4321-b551-e853cb40f062
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524808964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
524808964
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3187716268
Short name T1025
Test name
Test status
Simulation time 966574519 ps
CPU time 20.12 seconds
Started Jun 23 05:10:16 PM PDT 24
Finished Jun 23 05:10:37 PM PDT 24
Peak memory 215404 kb
Host smart-632241a5-ed2c-4f98-adea-128969e1e1c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187716268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3187716268
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3182593815
Short name T839
Test name
Test status
Simulation time 15619131 ps
CPU time 0.75 seconds
Started Jun 23 05:45:51 PM PDT 24
Finished Jun 23 05:45:52 PM PDT 24
Peak memory 206648 kb
Host smart-7c1cdf54-1323-4f49-937c-5bb2b98cef66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182593815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
182593815
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1177704353
Short name T471
Test name
Test status
Simulation time 100381217 ps
CPU time 2.88 seconds
Started Jun 23 05:45:55 PM PDT 24
Finished Jun 23 05:45:58 PM PDT 24
Peak memory 233744 kb
Host smart-c0d5e028-8948-4141-b516-cff641ff3ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177704353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1177704353
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1433920217
Short name T292
Test name
Test status
Simulation time 18349783 ps
CPU time 0.86 seconds
Started Jun 23 05:45:46 PM PDT 24
Finished Jun 23 05:45:48 PM PDT 24
Peak memory 207508 kb
Host smart-6a4a75bb-2f90-4f39-87db-677a0c0fde60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433920217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1433920217
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.4004208366
Short name T249
Test name
Test status
Simulation time 148110085007 ps
CPU time 523.86 seconds
Started Jun 23 05:45:51 PM PDT 24
Finished Jun 23 05:54:35 PM PDT 24
Peak memory 266728 kb
Host smart-41da4165-98f8-43e1-9291-5ea5d8945a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004208366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.4004208366
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1272278150
Short name T553
Test name
Test status
Simulation time 184818876 ps
CPU time 3.25 seconds
Started Jun 23 05:45:48 PM PDT 24
Finished Jun 23 05:45:52 PM PDT 24
Peak memory 225608 kb
Host smart-a630b99f-c278-4e10-94d0-28bd801d246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272278150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1272278150
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.76555288
Short name T579
Test name
Test status
Simulation time 117963454 ps
CPU time 1.02 seconds
Started Jun 23 05:45:47 PM PDT 24
Finished Jun 23 05:45:48 PM PDT 24
Peak memory 218856 kb
Host smart-7c164d05-bea6-4efc-b41f-c98190044199
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76555288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.76555288
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3167081357
Short name T522
Test name
Test status
Simulation time 10770810334 ps
CPU time 22.11 seconds
Started Jun 23 05:45:47 PM PDT 24
Finished Jun 23 05:46:10 PM PDT 24
Peak memory 225636 kb
Host smart-38ff0c61-3d42-4266-8b41-9eaa4bfc5caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167081357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3167081357
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1719670484
Short name T369
Test name
Test status
Simulation time 1738660019 ps
CPU time 6.45 seconds
Started Jun 23 05:45:49 PM PDT 24
Finished Jun 23 05:45:55 PM PDT 24
Peak memory 233764 kb
Host smart-1288da22-04ba-481c-be34-e05bcd841c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719670484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1719670484
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1392448114
Short name T309
Test name
Test status
Simulation time 4033863385 ps
CPU time 7.74 seconds
Started Jun 23 05:45:56 PM PDT 24
Finished Jun 23 05:46:05 PM PDT 24
Peak memory 223212 kb
Host smart-6b1ca1cd-eec3-48d9-8e92-d0836e5d2665
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1392448114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1392448114
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.267029615
Short name T64
Test name
Test status
Simulation time 34492059 ps
CPU time 0.98 seconds
Started Jun 23 05:45:54 PM PDT 24
Finished Jun 23 05:45:56 PM PDT 24
Peak memory 236440 kb
Host smart-b5863f31-7b6f-4cf5-8d3c-331f28d63167
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267029615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.267029615
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3703312446
Short name T152
Test name
Test status
Simulation time 842888007 ps
CPU time 7.86 seconds
Started Jun 23 05:45:51 PM PDT 24
Finished Jun 23 05:45:59 PM PDT 24
Peak memory 218660 kb
Host smart-a62775f0-b927-4b63-abd7-74dad9d1ef2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703312446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3703312446
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2225514632
Short name T481
Test name
Test status
Simulation time 16703065035 ps
CPU time 25.15 seconds
Started Jun 23 05:45:45 PM PDT 24
Finished Jun 23 05:46:11 PM PDT 24
Peak memory 217452 kb
Host smart-c06ff8e4-fd0e-4d88-86b9-4de425d07758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225514632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2225514632
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.4037169886
Short name T573
Test name
Test status
Simulation time 829333172 ps
CPU time 5.27 seconds
Started Jun 23 05:45:50 PM PDT 24
Finished Jun 23 05:45:55 PM PDT 24
Peak memory 217224 kb
Host smart-478439b8-f791-4370-b12b-cd9ed4967113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037169886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.4037169886
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4158251164
Short name T584
Test name
Test status
Simulation time 259993838 ps
CPU time 5.04 seconds
Started Jun 23 05:45:47 PM PDT 24
Finished Jun 23 05:45:53 PM PDT 24
Peak memory 217588 kb
Host smart-64ff3529-3206-46e7-9b50-cfdf5195cc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158251164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4158251164
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1991290105
Short name T855
Test name
Test status
Simulation time 43523846 ps
CPU time 0.71 seconds
Started Jun 23 05:45:45 PM PDT 24
Finished Jun 23 05:45:46 PM PDT 24
Peak memory 206904 kb
Host smart-f8f2faeb-ca3d-4d88-b50b-0437d5e5fba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991290105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1991290105
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1822854213
Short name T453
Test name
Test status
Simulation time 1248614091 ps
CPU time 6.31 seconds
Started Jun 23 05:45:56 PM PDT 24
Finished Jun 23 05:46:02 PM PDT 24
Peak memory 225600 kb
Host smart-ee99aba1-61a0-468c-bca0-0863b4e5f212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822854213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1822854213
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.649743457
Short name T518
Test name
Test status
Simulation time 13978215 ps
CPU time 0.75 seconds
Started Jun 23 05:45:58 PM PDT 24
Finished Jun 23 05:45:59 PM PDT 24
Peak memory 205708 kb
Host smart-845b285c-4e6d-4d41-a9a7-6d2f22619717
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649743457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.649743457
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1853653330
Short name T965
Test name
Test status
Simulation time 583161635 ps
CPU time 4.54 seconds
Started Jun 23 05:45:55 PM PDT 24
Finished Jun 23 05:46:00 PM PDT 24
Peak memory 225720 kb
Host smart-9469f3d9-621a-483d-8aef-c7de73283464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853653330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1853653330
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.546192721
Short name T363
Test name
Test status
Simulation time 14287795 ps
CPU time 0.75 seconds
Started Jun 23 05:45:54 PM PDT 24
Finished Jun 23 05:45:55 PM PDT 24
Peak memory 206816 kb
Host smart-a81e0392-7118-4ae5-81dd-d2213789e17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546192721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.546192721
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.707151013
Short name T227
Test name
Test status
Simulation time 4211549775 ps
CPU time 27.34 seconds
Started Jun 23 05:45:56 PM PDT 24
Finished Jun 23 05:46:24 PM PDT 24
Peak memory 222768 kb
Host smart-d6391712-948c-4fd3-bece-0c76156690bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707151013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.707151013
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.367350623
Short name T245
Test name
Test status
Simulation time 129008169758 ps
CPU time 78.88 seconds
Started Jun 23 05:45:57 PM PDT 24
Finished Jun 23 05:47:16 PM PDT 24
Peak memory 250268 kb
Host smart-885d1150-6a65-4be9-b156-9603a818675f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367350623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
367350623
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3575601296
Short name T271
Test name
Test status
Simulation time 611573650 ps
CPU time 5.8 seconds
Started Jun 23 05:45:58 PM PDT 24
Finished Jun 23 05:46:05 PM PDT 24
Peak memory 233668 kb
Host smart-83617a65-7689-4d20-b6fb-d3332684aeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575601296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3575601296
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3265944181
Short name T631
Test name
Test status
Simulation time 1910476053 ps
CPU time 7.66 seconds
Started Jun 23 05:45:58 PM PDT 24
Finished Jun 23 05:46:06 PM PDT 24
Peak memory 225484 kb
Host smart-07679382-127f-425e-aeae-ceed1c8b8d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265944181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3265944181
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3366006636
Short name T709
Test name
Test status
Simulation time 13718769326 ps
CPU time 24.53 seconds
Started Jun 23 05:45:56 PM PDT 24
Finished Jun 23 05:46:21 PM PDT 24
Peak memory 242064 kb
Host smart-7de6a06d-e2b5-43bc-b108-f374d002bd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366006636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3366006636
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1095231299
Short name T756
Test name
Test status
Simulation time 28011821 ps
CPU time 1.08 seconds
Started Jun 23 05:45:54 PM PDT 24
Finished Jun 23 05:45:56 PM PDT 24
Peak memory 217640 kb
Host smart-f66ab452-49cb-4777-9b5c-f4ce5335fb9c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095231299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1095231299
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3562810428
Short name T373
Test name
Test status
Simulation time 1179665178 ps
CPU time 8.62 seconds
Started Jun 23 05:45:57 PM PDT 24
Finished Jun 23 05:46:06 PM PDT 24
Peak memory 241512 kb
Host smart-64c37fd5-aefd-4ad2-935e-55b936a31921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562810428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3562810428
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3901324353
Short name T509
Test name
Test status
Simulation time 273393093 ps
CPU time 3.13 seconds
Started Jun 23 05:46:01 PM PDT 24
Finished Jun 23 05:46:04 PM PDT 24
Peak memory 233792 kb
Host smart-9219b961-80d8-4a1b-94df-fc84ef59fe42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901324353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3901324353
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.211789680
Short name T425
Test name
Test status
Simulation time 135189908 ps
CPU time 3.97 seconds
Started Jun 23 05:45:59 PM PDT 24
Finished Jun 23 05:46:03 PM PDT 24
Peak memory 224200 kb
Host smart-9a5a68cd-296f-4314-9e02-00310494617b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=211789680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.211789680
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.4217767881
Short name T21
Test name
Test status
Simulation time 85218996 ps
CPU time 1.13 seconds
Started Jun 23 05:45:56 PM PDT 24
Finished Jun 23 05:45:58 PM PDT 24
Peak memory 236336 kb
Host smart-35754143-ee4b-4bfb-acf1-ddf61c706a79
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217767881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4217767881
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.4074438769
Short name T725
Test name
Test status
Simulation time 11771414571 ps
CPU time 44.08 seconds
Started Jun 23 05:45:56 PM PDT 24
Finished Jun 23 05:46:40 PM PDT 24
Peak memory 225748 kb
Host smart-2ff2425c-37e4-4634-b247-9de326451bd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074438769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.4074438769
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3047930089
Short name T511
Test name
Test status
Simulation time 332766190 ps
CPU time 2.73 seconds
Started Jun 23 05:45:54 PM PDT 24
Finished Jun 23 05:45:57 PM PDT 24
Peak memory 217412 kb
Host smart-7be3c5e2-9af6-4651-9df5-3d402a2a60dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047930089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3047930089
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.383447475
Short name T457
Test name
Test status
Simulation time 2461618949 ps
CPU time 2.75 seconds
Started Jun 23 05:45:52 PM PDT 24
Finished Jun 23 05:45:55 PM PDT 24
Peak memory 209048 kb
Host smart-470b7051-07a8-4fb2-9a10-534b26ebeba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383447475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.383447475
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2970067277
Short name T344
Test name
Test status
Simulation time 253332217 ps
CPU time 1.87 seconds
Started Jun 23 05:46:01 PM PDT 24
Finished Jun 23 05:46:03 PM PDT 24
Peak memory 217372 kb
Host smart-5c316257-5f57-4df4-919e-a0273e01c77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970067277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2970067277
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1679414254
Short name T646
Test name
Test status
Simulation time 375014635 ps
CPU time 0.99 seconds
Started Jun 23 05:45:56 PM PDT 24
Finished Jun 23 05:45:58 PM PDT 24
Peak memory 206900 kb
Host smart-18c94998-ce1c-4275-b72a-581c95b6ec21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679414254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1679414254
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2148657451
Short name T230
Test name
Test status
Simulation time 1555990663 ps
CPU time 7.59 seconds
Started Jun 23 05:45:59 PM PDT 24
Finished Jun 23 05:46:07 PM PDT 24
Peak memory 233716 kb
Host smart-ad46580f-f2d0-43f3-949d-456c059ce7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148657451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2148657451
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1368281335
Short name T339
Test name
Test status
Simulation time 13479909 ps
CPU time 0.7 seconds
Started Jun 23 05:46:37 PM PDT 24
Finished Jun 23 05:46:39 PM PDT 24
Peak memory 205648 kb
Host smart-57240c2f-fc00-4192-8a61-28ad26bf87e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368281335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1368281335
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.4280378822
Short name T211
Test name
Test status
Simulation time 1430175382 ps
CPU time 18.65 seconds
Started Jun 23 05:46:47 PM PDT 24
Finished Jun 23 05:47:06 PM PDT 24
Peak memory 225540 kb
Host smart-05de8651-48a1-48b1-bc97-593347b43916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280378822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.4280378822
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2071683798
Short name T752
Test name
Test status
Simulation time 165937257 ps
CPU time 0.78 seconds
Started Jun 23 05:46:35 PM PDT 24
Finished Jun 23 05:46:37 PM PDT 24
Peak memory 207520 kb
Host smart-38b612af-1494-4ce3-bc31-dccf696d365b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071683798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2071683798
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.4262419546
Short name T683
Test name
Test status
Simulation time 8733243513 ps
CPU time 59.73 seconds
Started Jun 23 05:46:48 PM PDT 24
Finished Jun 23 05:47:48 PM PDT 24
Peak memory 251416 kb
Host smart-43e552ec-2d66-457f-9e0e-be42dc960833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262419546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.4262419546
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.4099256409
Short name T132
Test name
Test status
Simulation time 79676792241 ps
CPU time 312.47 seconds
Started Jun 23 05:46:40 PM PDT 24
Finished Jun 23 05:51:53 PM PDT 24
Peak memory 274608 kb
Host smart-cca07c7d-9ff8-40e9-a486-f15793e1b167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099256409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.4099256409
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3682733223
Short name T864
Test name
Test status
Simulation time 197247486 ps
CPU time 3.15 seconds
Started Jun 23 05:46:40 PM PDT 24
Finished Jun 23 05:46:43 PM PDT 24
Peak memory 233768 kb
Host smart-5d2583a0-0560-47df-b41d-189cb505c2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682733223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3682733223
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3685022163
Short name T787
Test name
Test status
Simulation time 101446663 ps
CPU time 3.44 seconds
Started Jun 23 05:46:35 PM PDT 24
Finished Jun 23 05:46:39 PM PDT 24
Peak memory 225612 kb
Host smart-f3b58388-2023-4ad0-9f97-0b3f68add7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685022163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3685022163
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1906794496
Short name T390
Test name
Test status
Simulation time 23534514712 ps
CPU time 55.17 seconds
Started Jun 23 05:46:41 PM PDT 24
Finished Jun 23 05:47:37 PM PDT 24
Peak memory 241744 kb
Host smart-2fa95c56-edca-4999-b6c9-dc322cf211bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906794496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1906794496
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2758481850
Short name T953
Test name
Test status
Simulation time 382624551 ps
CPU time 3.52 seconds
Started Jun 23 05:46:41 PM PDT 24
Finished Jun 23 05:46:45 PM PDT 24
Peak memory 225480 kb
Host smart-eb3a4c56-4e80-45cc-bfdb-272e1be0d063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758481850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2758481850
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1984997913
Short name T534
Test name
Test status
Simulation time 273915583 ps
CPU time 2.73 seconds
Started Jun 23 05:46:36 PM PDT 24
Finished Jun 23 05:46:40 PM PDT 24
Peak memory 233800 kb
Host smart-f353f79c-a917-458e-b90a-f5c527a791b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984997913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1984997913
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3248591572
Short name T635
Test name
Test status
Simulation time 72342282 ps
CPU time 3.74 seconds
Started Jun 23 05:46:43 PM PDT 24
Finished Jun 23 05:46:47 PM PDT 24
Peak memory 224200 kb
Host smart-5117b45d-ffee-470a-afed-893c099e3f0c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3248591572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3248591572
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.376705641
Short name T805
Test name
Test status
Simulation time 12336806325 ps
CPU time 55.13 seconds
Started Jun 23 05:46:40 PM PDT 24
Finished Jun 23 05:47:35 PM PDT 24
Peak memory 257836 kb
Host smart-e068da33-203b-4ed0-b2cd-c4227e4a67a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376705641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.376705641
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3779915007
Short name T961
Test name
Test status
Simulation time 3950381692 ps
CPU time 24.36 seconds
Started Jun 23 05:46:38 PM PDT 24
Finished Jun 23 05:47:03 PM PDT 24
Peak memory 217488 kb
Host smart-c5fc8c71-adb2-4db1-baea-a19ad331b3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779915007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3779915007
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.22580168
Short name T449
Test name
Test status
Simulation time 1308777892 ps
CPU time 7.83 seconds
Started Jun 23 05:46:38 PM PDT 24
Finished Jun 23 05:46:47 PM PDT 24
Peak memory 217376 kb
Host smart-1e8c7746-ec1d-4c71-a2e1-2206b608cee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22580168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.22580168
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1648951164
Short name T766
Test name
Test status
Simulation time 18116543 ps
CPU time 1.01 seconds
Started Jun 23 05:46:35 PM PDT 24
Finished Jun 23 05:46:37 PM PDT 24
Peak memory 208732 kb
Host smart-1141a970-a9e3-4833-b72d-7b8ad9c878c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648951164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1648951164
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.917215279
Short name T918
Test name
Test status
Simulation time 26540726 ps
CPU time 0.67 seconds
Started Jun 23 05:46:38 PM PDT 24
Finished Jun 23 05:46:40 PM PDT 24
Peak memory 206544 kb
Host smart-5cefcee1-87ce-408f-b2d7-4d1cc99c1a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917215279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.917215279
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1895091410
Short name T399
Test name
Test status
Simulation time 142854363 ps
CPU time 2.26 seconds
Started Jun 23 05:46:41 PM PDT 24
Finished Jun 23 05:46:44 PM PDT 24
Peak memory 224524 kb
Host smart-4044008c-68b9-4c61-a75d-f27cc291b881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895091410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1895091410
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3249683756
Short name T296
Test name
Test status
Simulation time 89341358 ps
CPU time 0.7 seconds
Started Jun 23 05:46:45 PM PDT 24
Finished Jun 23 05:46:46 PM PDT 24
Peak memory 206800 kb
Host smart-c3e6e5c5-a7c9-4a61-bd6d-a35bdcfad466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249683756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3249683756
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2883713926
Short name T169
Test name
Test status
Simulation time 410206595 ps
CPU time 2.33 seconds
Started Jun 23 05:46:47 PM PDT 24
Finished Jun 23 05:46:50 PM PDT 24
Peak memory 225576 kb
Host smart-15466cda-a898-44a4-acfb-976614b86ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883713926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2883713926
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4229428211
Short name T490
Test name
Test status
Simulation time 52716623 ps
CPU time 0.74 seconds
Started Jun 23 05:46:39 PM PDT 24
Finished Jun 23 05:46:41 PM PDT 24
Peak memory 207432 kb
Host smart-16b78038-9db5-4fc3-8d09-a262b1ac9233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229428211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4229428211
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2307684835
Short name T442
Test name
Test status
Simulation time 1392831889 ps
CPU time 13.11 seconds
Started Jun 23 05:46:44 PM PDT 24
Finished Jun 23 05:46:57 PM PDT 24
Peak memory 237944 kb
Host smart-92c8d8a9-086a-4053-bf98-ec42b49fdc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307684835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2307684835
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.465746813
Short name T913
Test name
Test status
Simulation time 22823229121 ps
CPU time 97.3 seconds
Started Jun 23 05:46:46 PM PDT 24
Finished Jun 23 05:48:24 PM PDT 24
Peak memory 253356 kb
Host smart-31c28a9d-e70c-4e8d-82eb-137adcb2332e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465746813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.465746813
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1674615073
Short name T543
Test name
Test status
Simulation time 7160763903 ps
CPU time 16.05 seconds
Started Jun 23 05:46:47 PM PDT 24
Finished Jun 23 05:47:04 PM PDT 24
Peak memory 225708 kb
Host smart-ab7b5ed0-aa09-4da7-8351-f9ee8d48ba36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674615073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1674615073
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3368801644
Short name T775
Test name
Test status
Simulation time 831767432 ps
CPU time 5.09 seconds
Started Jun 23 05:46:46 PM PDT 24
Finished Jun 23 05:46:52 PM PDT 24
Peak memory 233804 kb
Host smart-2de61b7c-de0b-494c-bd52-0dd04f801a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368801644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3368801644
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1213755778
Short name T715
Test name
Test status
Simulation time 5138572607 ps
CPU time 11.75 seconds
Started Jun 23 05:46:44 PM PDT 24
Finished Jun 23 05:46:56 PM PDT 24
Peak memory 233880 kb
Host smart-4bc40fa0-157e-4847-883b-9c775c12378b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213755778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1213755778
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.192698369
Short name T606
Test name
Test status
Simulation time 82090928 ps
CPU time 1.09 seconds
Started Jun 23 05:46:45 PM PDT 24
Finished Jun 23 05:46:47 PM PDT 24
Peak memory 217828 kb
Host smart-eed626d7-1c9e-42d4-8adc-099db9464e5b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192698369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.192698369
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.990090405
Short name T956
Test name
Test status
Simulation time 715329470 ps
CPU time 5.61 seconds
Started Jun 23 05:46:46 PM PDT 24
Finished Jun 23 05:46:52 PM PDT 24
Peak memory 241752 kb
Host smart-ac36587e-ebdc-4e74-9d79-bb1f982eaf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990090405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.990090405
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1500117177
Short name T866
Test name
Test status
Simulation time 15408241651 ps
CPU time 14.48 seconds
Started Jun 23 05:46:41 PM PDT 24
Finished Jun 23 05:46:56 PM PDT 24
Peak memory 225496 kb
Host smart-8c622db1-2cf3-4630-afd4-57783a69029b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500117177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1500117177
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3910651896
Short name T426
Test name
Test status
Simulation time 915491663 ps
CPU time 3.71 seconds
Started Jun 23 05:46:48 PM PDT 24
Finished Jun 23 05:46:52 PM PDT 24
Peak memory 221520 kb
Host smart-073ca928-eb31-4ff9-9bd3-d5f839589955
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3910651896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3910651896
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1806263042
Short name T443
Test name
Test status
Simulation time 6937149648 ps
CPU time 29.04 seconds
Started Jun 23 05:46:42 PM PDT 24
Finished Jun 23 05:47:11 PM PDT 24
Peak memory 217476 kb
Host smart-8633ca22-4f3a-4fac-a7ea-5b7a8d7010d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806263042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1806263042
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1179862246
Short name T731
Test name
Test status
Simulation time 31661767 ps
CPU time 0.91 seconds
Started Jun 23 05:46:40 PM PDT 24
Finished Jun 23 05:46:41 PM PDT 24
Peak memory 208060 kb
Host smart-7037ff09-cb3b-4f37-a98d-29b4669ea87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179862246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1179862246
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2190453950
Short name T438
Test name
Test status
Simulation time 487342374 ps
CPU time 0.9 seconds
Started Jun 23 05:46:45 PM PDT 24
Finished Jun 23 05:46:46 PM PDT 24
Peak memory 206888 kb
Host smart-b8d96e82-2858-4a61-84c8-7aed54f27ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190453950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2190453950
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.953180810
Short name T652
Test name
Test status
Simulation time 3025790543 ps
CPU time 10.3 seconds
Started Jun 23 05:46:45 PM PDT 24
Finished Jun 23 05:46:55 PM PDT 24
Peak memory 225676 kb
Host smart-1231b493-193d-41fd-b876-b9370e608a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953180810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.953180810
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2979320976
Short name T888
Test name
Test status
Simulation time 12965765 ps
CPU time 0.71 seconds
Started Jun 23 05:46:47 PM PDT 24
Finished Jun 23 05:46:49 PM PDT 24
Peak memory 205684 kb
Host smart-60567140-c161-40ab-9f29-50728d5a51c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979320976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2979320976
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3922386667
Short name T718
Test name
Test status
Simulation time 93425103 ps
CPU time 2.24 seconds
Started Jun 23 05:46:53 PM PDT 24
Finished Jun 23 05:46:56 PM PDT 24
Peak memory 225588 kb
Host smart-9fabf335-0168-4779-8298-280596424811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922386667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3922386667
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.502491162
Short name T658
Test name
Test status
Simulation time 31562837 ps
CPU time 0.8 seconds
Started Jun 23 05:46:43 PM PDT 24
Finished Jun 23 05:46:44 PM PDT 24
Peak memory 207508 kb
Host smart-1429dc5b-d692-4144-aecf-e7ffbcef4b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502491162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.502491162
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2339823674
Short name T647
Test name
Test status
Simulation time 5062130054 ps
CPU time 47.46 seconds
Started Jun 23 05:46:51 PM PDT 24
Finished Jun 23 05:47:39 PM PDT 24
Peak memory 251900 kb
Host smart-8bba7e3d-d060-40ac-afdd-6c5146f4a8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339823674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2339823674
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3859191870
Short name T195
Test name
Test status
Simulation time 45232407373 ps
CPU time 197.86 seconds
Started Jun 23 05:46:50 PM PDT 24
Finished Jun 23 05:50:09 PM PDT 24
Peak memory 268576 kb
Host smart-572f5881-ec74-4d21-b0b2-26204f943cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859191870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3859191870
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.930039956
Short name T546
Test name
Test status
Simulation time 122207172 ps
CPU time 2.66 seconds
Started Jun 23 05:46:50 PM PDT 24
Finished Jun 23 05:46:53 PM PDT 24
Peak memory 218444 kb
Host smart-3b911591-23c2-4892-90e7-573de52ea536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930039956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.930039956
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3599338528
Short name T111
Test name
Test status
Simulation time 9304398470 ps
CPU time 19.04 seconds
Started Jun 23 05:46:48 PM PDT 24
Finished Jun 23 05:47:08 PM PDT 24
Peak memory 240640 kb
Host smart-589372f7-1192-4c32-ac5a-49f7dbb2c698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599338528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3599338528
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.437016963
Short name T207
Test name
Test status
Simulation time 2977857133 ps
CPU time 33.26 seconds
Started Jun 23 05:46:48 PM PDT 24
Finished Jun 23 05:47:21 PM PDT 24
Peak memory 225672 kb
Host smart-cc6fd35e-1aa5-43fc-9927-60e0a0d17f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437016963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.437016963
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1318880062
Short name T412
Test name
Test status
Simulation time 216320230 ps
CPU time 5.94 seconds
Started Jun 23 05:46:47 PM PDT 24
Finished Jun 23 05:46:53 PM PDT 24
Peak memory 225716 kb
Host smart-0082724d-65f7-4f8c-93cc-7aeb618d8222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318880062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1318880062
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.4183683121
Short name T935
Test name
Test status
Simulation time 24888661 ps
CPU time 1.01 seconds
Started Jun 23 05:46:48 PM PDT 24
Finished Jun 23 05:46:49 PM PDT 24
Peak memory 217628 kb
Host smart-b7528386-8111-4ca1-8516-751de513a916
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183683121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.4183683121
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3973356084
Short name T231
Test name
Test status
Simulation time 7149620690 ps
CPU time 22.45 seconds
Started Jun 23 05:46:47 PM PDT 24
Finished Jun 23 05:47:10 PM PDT 24
Peak memory 233904 kb
Host smart-457824a6-92d6-48f3-811f-830dac699d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973356084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3973356084
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3681421210
Short name T791
Test name
Test status
Simulation time 1372341837 ps
CPU time 8.44 seconds
Started Jun 23 05:46:45 PM PDT 24
Finished Jun 23 05:46:54 PM PDT 24
Peak memory 233772 kb
Host smart-75496a45-e32d-4640-94ed-efc146deb20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681421210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3681421210
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4102589725
Short name T312
Test name
Test status
Simulation time 282479196 ps
CPU time 3.24 seconds
Started Jun 23 05:46:53 PM PDT 24
Finished Jun 23 05:46:57 PM PDT 24
Peak memory 220260 kb
Host smart-7a692c17-800b-461c-bf45-9b85462ee005
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4102589725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4102589725
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.4091346930
Short name T155
Test name
Test status
Simulation time 46818245 ps
CPU time 0.99 seconds
Started Jun 23 05:46:47 PM PDT 24
Finished Jun 23 05:46:48 PM PDT 24
Peak memory 207580 kb
Host smart-5fe2ee23-40c9-4256-8897-c00c8060b46f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091346930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.4091346930
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.4227975352
Short name T611
Test name
Test status
Simulation time 12223739206 ps
CPU time 63.25 seconds
Started Jun 23 05:46:47 PM PDT 24
Finished Jun 23 05:47:51 PM PDT 24
Peak memory 217468 kb
Host smart-dc2cab37-dc24-4694-8057-23d110fee6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227975352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.4227975352
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2478954879
Short name T968
Test name
Test status
Simulation time 12244134139 ps
CPU time 17.46 seconds
Started Jun 23 05:46:46 PM PDT 24
Finished Jun 23 05:47:04 PM PDT 24
Peak memory 217544 kb
Host smart-3a2dd83d-8e73-4918-b6a1-94130968f543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478954879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2478954879
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1858862776
Short name T748
Test name
Test status
Simulation time 93832472 ps
CPU time 1.52 seconds
Started Jun 23 05:46:45 PM PDT 24
Finished Jun 23 05:46:47 PM PDT 24
Peak memory 217336 kb
Host smart-97c64384-6c18-49d9-b013-a1ed5d01f7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858862776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1858862776
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.813956821
Short name T763
Test name
Test status
Simulation time 87060659 ps
CPU time 0.79 seconds
Started Jun 23 05:46:46 PM PDT 24
Finished Jun 23 05:46:47 PM PDT 24
Peak memory 206912 kb
Host smart-89b371d2-aff6-4427-8fa8-0e709a5478c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813956821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.813956821
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2966752994
Short name T530
Test name
Test status
Simulation time 686673836 ps
CPU time 2.34 seconds
Started Jun 23 05:46:51 PM PDT 24
Finished Jun 23 05:46:54 PM PDT 24
Peak memory 225236 kb
Host smart-d66299cb-d861-4e5e-887a-bd647090af96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966752994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2966752994
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.884096266
Short name T859
Test name
Test status
Simulation time 12994097 ps
CPU time 0.83 seconds
Started Jun 23 05:46:47 PM PDT 24
Finished Jun 23 05:46:48 PM PDT 24
Peak memory 205744 kb
Host smart-a77e4567-48a1-46af-8d77-f44c65ec4cc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884096266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.884096266
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2282233543
Short name T771
Test name
Test status
Simulation time 626448451 ps
CPU time 3.91 seconds
Started Jun 23 05:46:51 PM PDT 24
Finished Jun 23 05:46:55 PM PDT 24
Peak memory 225516 kb
Host smart-50f0c41c-452a-425a-a241-a2a8fa39616d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282233543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2282233543
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.333565789
Short name T328
Test name
Test status
Simulation time 38307539 ps
CPU time 0.82 seconds
Started Jun 23 05:46:51 PM PDT 24
Finished Jun 23 05:46:53 PM PDT 24
Peak memory 207524 kb
Host smart-5a4213f8-90aa-42e0-87b2-5fdd12368f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333565789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.333565789
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1744369456
Short name T774
Test name
Test status
Simulation time 366824618 ps
CPU time 6.61 seconds
Started Jun 23 05:46:49 PM PDT 24
Finished Jun 23 05:46:56 PM PDT 24
Peak memory 225516 kb
Host smart-22de09d7-ecae-494e-92c7-b139abb90850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744369456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1744369456
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.641498455
Short name T346
Test name
Test status
Simulation time 8549827223 ps
CPU time 65.3 seconds
Started Jun 23 05:46:52 PM PDT 24
Finished Jun 23 05:47:57 PM PDT 24
Peak memory 232152 kb
Host smart-8dc353dd-3eac-4d38-9315-7caee592eecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641498455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.641498455
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1376684203
Short name T575
Test name
Test status
Simulation time 11054259457 ps
CPU time 35.78 seconds
Started Jun 23 05:46:49 PM PDT 24
Finished Jun 23 05:47:25 PM PDT 24
Peak memory 241984 kb
Host smart-db8754d7-43d9-4264-a813-aa742e822288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376684203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1376684203
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.121193179
Short name T609
Test name
Test status
Simulation time 972293858 ps
CPU time 11.85 seconds
Started Jun 23 05:46:49 PM PDT 24
Finished Jun 23 05:47:01 PM PDT 24
Peak memory 225544 kb
Host smart-6e1469b7-4c8d-4968-9fb0-b93119c0078d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121193179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.121193179
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2318203775
Short name T639
Test name
Test status
Simulation time 4341775685 ps
CPU time 31.21 seconds
Started Jun 23 05:46:53 PM PDT 24
Finished Jun 23 05:47:25 PM PDT 24
Peak memory 241656 kb
Host smart-c6f8d16d-10ec-4138-8859-eaacecf08baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318203775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2318203775
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.305008512
Short name T358
Test name
Test status
Simulation time 149402165 ps
CPU time 1.07 seconds
Started Jun 23 05:46:50 PM PDT 24
Finished Jun 23 05:46:52 PM PDT 24
Peak memory 217620 kb
Host smart-b3e53f35-c1b9-4261-80cd-6c18f25e7a73
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305008512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.305008512
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2733779585
Short name T386
Test name
Test status
Simulation time 16326055125 ps
CPU time 13.68 seconds
Started Jun 23 05:46:49 PM PDT 24
Finished Jun 23 05:47:03 PM PDT 24
Peak memory 225724 kb
Host smart-3b80e48c-4447-4655-873b-4814c4680209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733779585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2733779585
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2208388068
Short name T914
Test name
Test status
Simulation time 328559235 ps
CPU time 2.58 seconds
Started Jun 23 05:46:51 PM PDT 24
Finished Jun 23 05:46:54 PM PDT 24
Peak memory 233668 kb
Host smart-6b09fa51-ba5b-4738-81c1-a53dbfdd24e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208388068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2208388068
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1925825697
Short name T971
Test name
Test status
Simulation time 10205572228 ps
CPU time 9.18 seconds
Started Jun 23 05:46:53 PM PDT 24
Finished Jun 23 05:47:03 PM PDT 24
Peak memory 220084 kb
Host smart-74b7f5dc-d4c7-412d-9447-ea4b419848d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1925825697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1925825697
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2368391870
Short name T946
Test name
Test status
Simulation time 32369935972 ps
CPU time 309.53 seconds
Started Jun 23 05:46:50 PM PDT 24
Finished Jun 23 05:52:00 PM PDT 24
Peak memory 254272 kb
Host smart-e19de75f-7b65-4de4-9942-d80ec059f727
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368391870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2368391870
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2534740729
Short name T279
Test name
Test status
Simulation time 22217666883 ps
CPU time 46.44 seconds
Started Jun 23 05:46:54 PM PDT 24
Finished Jun 23 05:47:41 PM PDT 24
Peak memory 217420 kb
Host smart-597bc0d3-c7af-49af-bfb0-736650016533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534740729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2534740729
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.4067955070
Short name T586
Test name
Test status
Simulation time 766320201 ps
CPU time 4.27 seconds
Started Jun 23 05:46:50 PM PDT 24
Finished Jun 23 05:46:55 PM PDT 24
Peak memory 217396 kb
Host smart-1f5cc588-d894-4e3a-86ea-4aed2e7c7734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067955070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.4067955070
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2775515994
Short name T503
Test name
Test status
Simulation time 180089830 ps
CPU time 1.34 seconds
Started Jun 23 05:46:50 PM PDT 24
Finished Jun 23 05:46:51 PM PDT 24
Peak memory 217344 kb
Host smart-8025bb79-1f76-4422-a724-e55d2756af63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775515994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2775515994
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.45412002
Short name T505
Test name
Test status
Simulation time 168220644 ps
CPU time 0.88 seconds
Started Jun 23 05:46:53 PM PDT 24
Finished Jun 23 05:46:54 PM PDT 24
Peak memory 207448 kb
Host smart-41b233e4-e23a-41a2-8152-30672fbc1867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45412002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.45412002
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2934233292
Short name T747
Test name
Test status
Simulation time 1132077604 ps
CPU time 4.85 seconds
Started Jun 23 05:46:50 PM PDT 24
Finished Jun 23 05:46:56 PM PDT 24
Peak memory 233656 kb
Host smart-4dfcb56b-f65d-404d-8779-54ef98994a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934233292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2934233292
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2829050613
Short name T323
Test name
Test status
Simulation time 207083008 ps
CPU time 0.71 seconds
Started Jun 23 05:46:52 PM PDT 24
Finished Jun 23 05:46:53 PM PDT 24
Peak memory 206316 kb
Host smart-1d9b9fac-773d-4e87-935f-d563c6bb2968
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829050613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2829050613
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.927684687
Short name T856
Test name
Test status
Simulation time 11478156181 ps
CPU time 22.32 seconds
Started Jun 23 05:46:55 PM PDT 24
Finished Jun 23 05:47:18 PM PDT 24
Peak memory 225660 kb
Host smart-5840d1bb-c653-4755-a736-b846a5ded243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927684687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.927684687
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3381985190
Short name T717
Test name
Test status
Simulation time 19623332 ps
CPU time 0.81 seconds
Started Jun 23 05:46:49 PM PDT 24
Finished Jun 23 05:46:50 PM PDT 24
Peak memory 207864 kb
Host smart-53d45fd8-1073-4730-ba07-18b4239b1d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381985190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3381985190
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3091303859
Short name T362
Test name
Test status
Simulation time 10270357832 ps
CPU time 37.64 seconds
Started Jun 23 05:46:54 PM PDT 24
Finished Jun 23 05:47:32 PM PDT 24
Peak memory 221404 kb
Host smart-cc05475f-22c7-4317-9f5a-4a5973bff93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091303859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3091303859
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.122436378
Short name T524
Test name
Test status
Simulation time 11840009727 ps
CPU time 98.38 seconds
Started Jun 23 05:46:57 PM PDT 24
Finished Jun 23 05:48:36 PM PDT 24
Peak memory 250356 kb
Host smart-1f7dfc5c-3307-41cc-badd-08ef8f6bc6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122436378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.122436378
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3632263925
Short name T423
Test name
Test status
Simulation time 802942869 ps
CPU time 7.09 seconds
Started Jun 23 05:46:56 PM PDT 24
Finished Jun 23 05:47:03 PM PDT 24
Peak memory 233724 kb
Host smart-d518dbad-8626-4343-8f8a-b14ac8120156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632263925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3632263925
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.728814425
Short name T583
Test name
Test status
Simulation time 2249921206 ps
CPU time 6.21 seconds
Started Jun 23 05:46:54 PM PDT 24
Finished Jun 23 05:47:01 PM PDT 24
Peak memory 225640 kb
Host smart-a21ebb8a-b199-4f42-9959-66458ff9b2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728814425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.728814425
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3916435097
Short name T173
Test name
Test status
Simulation time 71325139969 ps
CPU time 161.15 seconds
Started Jun 23 05:46:55 PM PDT 24
Finished Jun 23 05:49:37 PM PDT 24
Peak memory 250080 kb
Host smart-53bdf760-3a4d-4c7c-bcd3-9793c35344f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916435097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3916435097
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2165919325
Short name T36
Test name
Test status
Simulation time 89164586 ps
CPU time 1.01 seconds
Started Jun 23 05:46:54 PM PDT 24
Finished Jun 23 05:46:55 PM PDT 24
Peak memory 218796 kb
Host smart-5e7d2777-f20b-4b5f-afaa-e6a379fdce3d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165919325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2165919325
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2399915678
Short name T47
Test name
Test status
Simulation time 4557954949 ps
CPU time 4.03 seconds
Started Jun 23 05:46:53 PM PDT 24
Finished Jun 23 05:46:57 PM PDT 24
Peak memory 233852 kb
Host smart-4b8cc044-9f2f-4d60-9d32-914e992408a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399915678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2399915678
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3460521989
Short name T202
Test name
Test status
Simulation time 1269559632 ps
CPU time 6.83 seconds
Started Jun 23 05:46:55 PM PDT 24
Finished Jun 23 05:47:02 PM PDT 24
Peak memory 233788 kb
Host smart-ddee9dec-b31b-42ac-9672-7d92c98ecb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460521989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3460521989
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2386530860
Short name T818
Test name
Test status
Simulation time 282511018 ps
CPU time 4.55 seconds
Started Jun 23 05:46:53 PM PDT 24
Finished Jun 23 05:46:58 PM PDT 24
Peak memory 224088 kb
Host smart-77b60603-9392-4319-9056-e3254f1ed3e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2386530860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2386530860
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3131388273
Short name T285
Test name
Test status
Simulation time 27078510949 ps
CPU time 39.37 seconds
Started Jun 23 05:46:54 PM PDT 24
Finished Jun 23 05:47:34 PM PDT 24
Peak memory 217524 kb
Host smart-ddf54754-66e6-4c66-afca-9692ab7e2ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131388273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3131388273
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3898081321
Short name T550
Test name
Test status
Simulation time 36549441 ps
CPU time 0.72 seconds
Started Jun 23 05:46:54 PM PDT 24
Finished Jun 23 05:46:55 PM PDT 24
Peak memory 206636 kb
Host smart-bdc43ab1-9f4c-44e7-b3df-b7c6b8181c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898081321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3898081321
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2699065718
Short name T434
Test name
Test status
Simulation time 94418616 ps
CPU time 1.01 seconds
Started Jun 23 05:46:57 PM PDT 24
Finished Jun 23 05:46:58 PM PDT 24
Peak memory 208472 kb
Host smart-737ad429-95c5-4dbf-b2a6-21c1f32e4f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699065718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2699065718
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3961772644
Short name T898
Test name
Test status
Simulation time 213169685 ps
CPU time 0.86 seconds
Started Jun 23 05:46:56 PM PDT 24
Finished Jun 23 05:46:57 PM PDT 24
Peak memory 206888 kb
Host smart-eb7aaa88-329b-4088-a888-734f3715fdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961772644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3961772644
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2147295223
Short name T469
Test name
Test status
Simulation time 8785262693 ps
CPU time 8.83 seconds
Started Jun 23 05:46:54 PM PDT 24
Finished Jun 23 05:47:04 PM PDT 24
Peak memory 225652 kb
Host smart-38132087-a59c-4387-8972-f0be9c23be71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147295223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2147295223
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.441485088
Short name T521
Test name
Test status
Simulation time 6032308651 ps
CPU time 4.52 seconds
Started Jun 23 05:46:57 PM PDT 24
Finished Jun 23 05:47:02 PM PDT 24
Peak memory 233872 kb
Host smart-f8512a62-eab7-48bf-bede-0ce2ff1888e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441485088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.441485088
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1317088756
Short name T921
Test name
Test status
Simulation time 66363569 ps
CPU time 0.81 seconds
Started Jun 23 05:46:54 PM PDT 24
Finished Jun 23 05:46:55 PM PDT 24
Peak memory 207524 kb
Host smart-4b11af76-6cf3-49b2-94f4-01c181877d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317088756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1317088756
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3402545221
Short name T555
Test name
Test status
Simulation time 5437228572 ps
CPU time 64.02 seconds
Started Jun 23 05:47:03 PM PDT 24
Finished Jun 23 05:48:07 PM PDT 24
Peak memory 242116 kb
Host smart-7c4731ad-c040-403d-91b2-f9dc6cbe0c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402545221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3402545221
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.704662620
Short name T174
Test name
Test status
Simulation time 26889602048 ps
CPU time 268.47 seconds
Started Jun 23 05:46:57 PM PDT 24
Finished Jun 23 05:51:26 PM PDT 24
Peak memory 251384 kb
Host smart-4e17a742-2a48-441e-9852-d055268c3d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704662620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.704662620
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2446138689
Short name T741
Test name
Test status
Simulation time 8468432452 ps
CPU time 44.36 seconds
Started Jun 23 05:46:57 PM PDT 24
Finished Jun 23 05:47:42 PM PDT 24
Peak memory 251416 kb
Host smart-e462507e-86e2-451d-8d1f-d78df4647918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446138689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2446138689
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1377834946
Short name T872
Test name
Test status
Simulation time 2088172978 ps
CPU time 4.21 seconds
Started Jun 23 05:47:04 PM PDT 24
Finished Jun 23 05:47:09 PM PDT 24
Peak memory 233768 kb
Host smart-d4190ac2-67c6-43d4-bb81-77d82996d626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377834946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1377834946
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1033306698
Short name T456
Test name
Test status
Simulation time 280157961 ps
CPU time 2.88 seconds
Started Jun 23 05:46:59 PM PDT 24
Finished Jun 23 05:47:02 PM PDT 24
Peak memory 225568 kb
Host smart-f42b9961-d773-44e2-8a2e-bdce62a13ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033306698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1033306698
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1886837560
Short name T302
Test name
Test status
Simulation time 68218482 ps
CPU time 2.59 seconds
Started Jun 23 05:47:03 PM PDT 24
Finished Jun 23 05:47:06 PM PDT 24
Peak memory 233792 kb
Host smart-7b713186-61c2-4ae0-9306-f78b252cb10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886837560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1886837560
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1891022498
Short name T622
Test name
Test status
Simulation time 161715458 ps
CPU time 1.03 seconds
Started Jun 23 05:46:59 PM PDT 24
Finished Jun 23 05:47:00 PM PDT 24
Peak memory 217620 kb
Host smart-0e9dc46b-69d8-4347-a8a7-4497b8bcdc9d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891022498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1891022498
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2307245742
Short name T361
Test name
Test status
Simulation time 292351064 ps
CPU time 3.36 seconds
Started Jun 23 05:46:59 PM PDT 24
Finished Jun 23 05:47:03 PM PDT 24
Peak memory 233792 kb
Host smart-689c46c9-82e7-4b99-9d2d-b27d585dcadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307245742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2307245742
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3648105654
Short name T409
Test name
Test status
Simulation time 1227247364 ps
CPU time 9.39 seconds
Started Jun 23 05:47:00 PM PDT 24
Finished Jun 23 05:47:09 PM PDT 24
Peak memory 233808 kb
Host smart-8fe8fd5a-1bd8-4f94-aa34-d57105fdd28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648105654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3648105654
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1951155490
Short name T785
Test name
Test status
Simulation time 1108845658 ps
CPU time 5.41 seconds
Started Jun 23 05:47:02 PM PDT 24
Finished Jun 23 05:47:08 PM PDT 24
Peak memory 220012 kb
Host smart-4d5c6576-cf4e-4319-b96b-ebb249240797
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1951155490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1951155490
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.918217064
Short name T26
Test name
Test status
Simulation time 904778559 ps
CPU time 9.48 seconds
Started Jun 23 05:46:58 PM PDT 24
Finished Jun 23 05:47:07 PM PDT 24
Peak memory 217396 kb
Host smart-415a25cc-228a-47d4-9afe-63e8e55f3dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918217064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.918217064
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.319498671
Short name T495
Test name
Test status
Simulation time 2483251588 ps
CPU time 9.73 seconds
Started Jun 23 05:47:01 PM PDT 24
Finished Jun 23 05:47:11 PM PDT 24
Peak memory 217536 kb
Host smart-5d50bbdd-148a-40f0-81c6-20269a1dcae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319498671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.319498671
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1018138537
Short name T551
Test name
Test status
Simulation time 257195124 ps
CPU time 1.05 seconds
Started Jun 23 05:47:03 PM PDT 24
Finished Jun 23 05:47:05 PM PDT 24
Peak memory 208952 kb
Host smart-16a30dbf-5858-4abf-8956-5c1ad8a53993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018138537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1018138537
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2166547512
Short name T455
Test name
Test status
Simulation time 85722317 ps
CPU time 0.8 seconds
Started Jun 23 05:46:59 PM PDT 24
Finished Jun 23 05:47:00 PM PDT 24
Peak memory 206876 kb
Host smart-6ca51745-89ab-4585-a771-ad7924508a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166547512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2166547512
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3889169626
Short name T560
Test name
Test status
Simulation time 2576874531 ps
CPU time 6.98 seconds
Started Jun 23 05:47:02 PM PDT 24
Finished Jun 23 05:47:09 PM PDT 24
Peak memory 241964 kb
Host smart-8ed67b91-2be2-4f15-a488-dc387b7bc1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889169626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3889169626
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.4292683485
Short name T729
Test name
Test status
Simulation time 14573268 ps
CPU time 0.69 seconds
Started Jun 23 05:47:02 PM PDT 24
Finished Jun 23 05:47:03 PM PDT 24
Peak memory 206640 kb
Host smart-d159e284-1e7d-4850-8740-25b1e0649c0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292683485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
4292683485
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1379044221
Short name T445
Test name
Test status
Simulation time 1099035401 ps
CPU time 5.38 seconds
Started Jun 23 05:47:08 PM PDT 24
Finished Jun 23 05:47:14 PM PDT 24
Peak memory 225572 kb
Host smart-f21e533e-5cf0-4852-b6dd-3cd28f109dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379044221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1379044221
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.917347070
Short name T633
Test name
Test status
Simulation time 13978841 ps
CPU time 0.72 seconds
Started Jun 23 05:46:56 PM PDT 24
Finished Jun 23 05:46:57 PM PDT 24
Peak memory 206832 kb
Host smart-fe216fec-332f-4bcb-b54d-d10890b67904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917347070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.917347070
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1208486673
Short name T243
Test name
Test status
Simulation time 3276305081 ps
CPU time 20.57 seconds
Started Jun 23 05:47:04 PM PDT 24
Finished Jun 23 05:47:25 PM PDT 24
Peak memory 233876 kb
Host smart-c37476cd-5e8e-45d0-9524-de59d33b7f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208486673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1208486673
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2834935326
Short name T574
Test name
Test status
Simulation time 78467330898 ps
CPU time 374.38 seconds
Started Jun 23 05:47:03 PM PDT 24
Finished Jun 23 05:53:18 PM PDT 24
Peak memory 253908 kb
Host smart-02e8f493-bf9b-4164-a481-e2fb5e85d319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834935326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2834935326
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2531254184
Short name T187
Test name
Test status
Simulation time 67089483286 ps
CPU time 173.18 seconds
Started Jun 23 05:47:05 PM PDT 24
Finished Jun 23 05:49:58 PM PDT 24
Peak memory 258388 kb
Host smart-ff63b563-d1a2-4a2b-bf99-1e14ab976ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531254184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2531254184
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.4039069688
Short name T592
Test name
Test status
Simulation time 32102368 ps
CPU time 2.61 seconds
Started Jun 23 05:47:06 PM PDT 24
Finished Jun 23 05:47:09 PM PDT 24
Peak memory 225524 kb
Host smart-037b3feb-e1e9-44f6-b89b-e0bff0fd3237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039069688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.4039069688
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.191691588
Short name T977
Test name
Test status
Simulation time 9725856821 ps
CPU time 19.53 seconds
Started Jun 23 05:47:04 PM PDT 24
Finished Jun 23 05:47:25 PM PDT 24
Peak memory 233936 kb
Host smart-371e5445-7bb2-4874-b5fb-772af207a7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191691588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.191691588
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.4216702592
Short name T342
Test name
Test status
Simulation time 50961256 ps
CPU time 1.08 seconds
Started Jun 23 05:47:04 PM PDT 24
Finished Jun 23 05:47:06 PM PDT 24
Peak memory 218840 kb
Host smart-5f238bf1-5027-454e-a892-19c21801ba63
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216702592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.4216702592
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3634682202
Short name T46
Test name
Test status
Simulation time 20065323707 ps
CPU time 16.21 seconds
Started Jun 23 05:47:05 PM PDT 24
Finished Jun 23 05:47:22 PM PDT 24
Peak memory 233804 kb
Host smart-11feb8eb-9e1b-475a-be56-79a36b153ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634682202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3634682202
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1013061028
Short name T501
Test name
Test status
Simulation time 1265573649 ps
CPU time 5.17 seconds
Started Jun 23 05:47:03 PM PDT 24
Finished Jun 23 05:47:09 PM PDT 24
Peak memory 223560 kb
Host smart-102273ee-df01-495f-948a-bb062deb7f4a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1013061028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1013061028
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1515097489
Short name T884
Test name
Test status
Simulation time 9419058008 ps
CPU time 145.45 seconds
Started Jun 23 05:47:05 PM PDT 24
Finished Jun 23 05:49:31 PM PDT 24
Peak memory 263048 kb
Host smart-08d5b6bf-5549-4175-b94b-227162721dc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515097489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1515097489
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3193904351
Short name T381
Test name
Test status
Simulation time 2326988535 ps
CPU time 7.19 seconds
Started Jun 23 05:47:03 PM PDT 24
Finished Jun 23 05:47:11 PM PDT 24
Peak memory 217672 kb
Host smart-f0f6099a-bb8c-48e2-a8c4-1e3c5152f6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193904351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3193904351
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1879725585
Short name T589
Test name
Test status
Simulation time 3250895414 ps
CPU time 6.06 seconds
Started Jun 23 05:46:59 PM PDT 24
Finished Jun 23 05:47:05 PM PDT 24
Peak memory 217496 kb
Host smart-54b3f297-6354-4e93-8614-9e1d2b4429e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879725585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1879725585
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2719674873
Short name T444
Test name
Test status
Simulation time 11279702 ps
CPU time 0.72 seconds
Started Jun 23 05:47:07 PM PDT 24
Finished Jun 23 05:47:08 PM PDT 24
Peak memory 206908 kb
Host smart-7bd10792-925a-409e-80ea-7002f29a29e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719674873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2719674873
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3604351684
Short name T76
Test name
Test status
Simulation time 37014528 ps
CPU time 0.77 seconds
Started Jun 23 05:47:03 PM PDT 24
Finished Jun 23 05:47:04 PM PDT 24
Peak memory 206544 kb
Host smart-73267901-c948-4954-b879-40f77d35830b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604351684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3604351684
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3804268212
Short name T392
Test name
Test status
Simulation time 364675805 ps
CPU time 2.44 seconds
Started Jun 23 05:47:02 PM PDT 24
Finished Jun 23 05:47:05 PM PDT 24
Peak memory 224464 kb
Host smart-3fe5821b-cb1c-48f8-8254-636a54d37733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804268212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3804268212
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2872850421
Short name T976
Test name
Test status
Simulation time 41354616 ps
CPU time 0.71 seconds
Started Jun 23 05:47:14 PM PDT 24
Finished Jun 23 05:47:16 PM PDT 24
Peak memory 205756 kb
Host smart-e8c16d2f-a96a-45c0-87be-9f22f4b2cfa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872850421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2872850421
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3021016844
Short name T360
Test name
Test status
Simulation time 66810246 ps
CPU time 3.04 seconds
Started Jun 23 05:47:18 PM PDT 24
Finished Jun 23 05:47:22 PM PDT 24
Peak memory 233792 kb
Host smart-74623394-76c4-4209-acaf-243474e047b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021016844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3021016844
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.246363389
Short name T447
Test name
Test status
Simulation time 68775171 ps
CPU time 0.81 seconds
Started Jun 23 05:47:06 PM PDT 24
Finished Jun 23 05:47:08 PM PDT 24
Peak memory 207884 kb
Host smart-c926de75-5a18-4f2d-a241-96c939ca639c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246363389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.246363389
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.303484002
Short name T916
Test name
Test status
Simulation time 2540681893 ps
CPU time 54.86 seconds
Started Jun 23 05:47:17 PM PDT 24
Finished Jun 23 05:48:13 PM PDT 24
Peak memory 250552 kb
Host smart-c18a16ab-27b7-4e36-996d-fd7c4e425636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303484002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.303484002
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3270831412
Short name T591
Test name
Test status
Simulation time 330655124 ps
CPU time 2.87 seconds
Started Jun 23 05:47:20 PM PDT 24
Finished Jun 23 05:47:23 PM PDT 24
Peak memory 218488 kb
Host smart-0d95bbee-eac4-42c9-9523-102ff46c7503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270831412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3270831412
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2814693293
Short name T53
Test name
Test status
Simulation time 86530057430 ps
CPU time 792.02 seconds
Started Jun 23 05:47:14 PM PDT 24
Finished Jun 23 06:00:27 PM PDT 24
Peak memory 266252 kb
Host smart-f3fe3dce-35d3-423b-aa7a-df8d98a5f795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814693293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2814693293
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2369327030
Short name T730
Test name
Test status
Simulation time 4548773350 ps
CPU time 12.67 seconds
Started Jun 23 05:47:18 PM PDT 24
Finished Jun 23 05:47:31 PM PDT 24
Peak memory 233920 kb
Host smart-175b0c3a-67ab-4926-b61b-f894951592b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369327030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2369327030
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3180323003
Short name T408
Test name
Test status
Simulation time 11892763252 ps
CPU time 45.32 seconds
Started Jun 23 05:47:15 PM PDT 24
Finished Jun 23 05:48:01 PM PDT 24
Peak memory 250240 kb
Host smart-8a538dbf-4b36-4243-aa27-fafb4103abe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180323003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3180323003
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3580545896
Short name T37
Test name
Test status
Simulation time 123037503 ps
CPU time 1.07 seconds
Started Jun 23 05:47:04 PM PDT 24
Finished Jun 23 05:47:05 PM PDT 24
Peak memory 217640 kb
Host smart-93dfdb2e-e0e8-4e86-b2e4-0b178b513977
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580545896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3580545896
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2042806027
Short name T911
Test name
Test status
Simulation time 114367682 ps
CPU time 2.95 seconds
Started Jun 23 05:47:17 PM PDT 24
Finished Jun 23 05:47:21 PM PDT 24
Peak memory 233752 kb
Host smart-0be6d87c-a2ed-428f-8ea4-6ab775975f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042806027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2042806027
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2845863664
Short name T853
Test name
Test status
Simulation time 589121990 ps
CPU time 2.82 seconds
Started Jun 23 05:47:15 PM PDT 24
Finished Jun 23 05:47:18 PM PDT 24
Peak memory 233804 kb
Host smart-1655284f-3cd4-40b0-8622-eb495ec72953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845863664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2845863664
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2770749730
Short name T440
Test name
Test status
Simulation time 2584878069 ps
CPU time 20.42 seconds
Started Jun 23 05:47:13 PM PDT 24
Finished Jun 23 05:47:34 PM PDT 24
Peak memory 220408 kb
Host smart-a28f4448-899e-426c-96b6-32edba950527
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2770749730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2770749730
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.758244470
Short name T248
Test name
Test status
Simulation time 3693580573 ps
CPU time 45.1 seconds
Started Jun 23 05:47:16 PM PDT 24
Finished Jun 23 05:48:02 PM PDT 24
Peak memory 250316 kb
Host smart-3deba072-9464-4a5c-8815-509e0eea1835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758244470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.758244470
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.866536910
Short name T491
Test name
Test status
Simulation time 309275902 ps
CPU time 2.04 seconds
Started Jun 23 05:47:04 PM PDT 24
Finished Jun 23 05:47:06 PM PDT 24
Peak memory 217400 kb
Host smart-bef43fa0-32fb-4373-b8c4-bc81cfcf3c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866536910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.866536910
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1082253142
Short name T934
Test name
Test status
Simulation time 1003281723 ps
CPU time 4.87 seconds
Started Jun 23 05:47:04 PM PDT 24
Finished Jun 23 05:47:09 PM PDT 24
Peak memory 217404 kb
Host smart-81a0442d-9417-4e16-b339-96ad72712763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082253142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1082253142
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2130198047
Short name T608
Test name
Test status
Simulation time 901027628 ps
CPU time 3.06 seconds
Started Jun 23 05:47:19 PM PDT 24
Finished Jun 23 05:47:23 PM PDT 24
Peak memory 217568 kb
Host smart-1a9ed9b8-eab5-4161-b96e-6854a07069c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130198047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2130198047
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3062076229
Short name T542
Test name
Test status
Simulation time 75557310 ps
CPU time 0.81 seconds
Started Jun 23 05:47:04 PM PDT 24
Finished Jun 23 05:47:06 PM PDT 24
Peak memory 206888 kb
Host smart-a098e133-e7fb-4c8e-b2ee-775decaf79f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062076229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3062076229
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2091093714
Short name T499
Test name
Test status
Simulation time 2833761356 ps
CPU time 5.58 seconds
Started Jun 23 05:47:20 PM PDT 24
Finished Jun 23 05:47:26 PM PDT 24
Peak memory 225720 kb
Host smart-fd09c59b-8f85-4a6d-9c74-d73ef5bcebe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091093714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2091093714
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.245150318
Short name T62
Test name
Test status
Simulation time 38825070 ps
CPU time 0.72 seconds
Started Jun 23 05:47:16 PM PDT 24
Finished Jun 23 05:47:17 PM PDT 24
Peak memory 205720 kb
Host smart-0973f03c-2aa1-4540-8885-1f9a10596533
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245150318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.245150318
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4136354535
Short name T554
Test name
Test status
Simulation time 540680538 ps
CPU time 2.71 seconds
Started Jun 23 05:47:15 PM PDT 24
Finished Jun 23 05:47:19 PM PDT 24
Peak memory 225564 kb
Host smart-9e2923c6-203d-426d-b386-88cc40db8677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136354535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4136354535
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3961809123
Short name T345
Test name
Test status
Simulation time 15680756 ps
CPU time 0.82 seconds
Started Jun 23 05:47:13 PM PDT 24
Finished Jun 23 05:47:14 PM PDT 24
Peak memory 206432 kb
Host smart-40091dd6-92ca-4e21-bd74-fe7c1ff1f6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961809123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3961809123
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3934153618
Short name T78
Test name
Test status
Simulation time 31790039591 ps
CPU time 71.28 seconds
Started Jun 23 05:47:16 PM PDT 24
Finished Jun 23 05:48:27 PM PDT 24
Peak memory 260496 kb
Host smart-b42098a1-8c38-4d32-89d1-314cd5e1592c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934153618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3934153618
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1311031481
Short name T640
Test name
Test status
Simulation time 8055115744 ps
CPU time 125.65 seconds
Started Jun 23 05:47:15 PM PDT 24
Finished Jun 23 05:49:21 PM PDT 24
Peak memory 267000 kb
Host smart-315cb029-5e28-4846-8d75-8df5e64ea555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311031481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1311031481
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.718930772
Short name T276
Test name
Test status
Simulation time 2127023668 ps
CPU time 11.37 seconds
Started Jun 23 05:47:15 PM PDT 24
Finished Jun 23 05:47:27 PM PDT 24
Peak memory 233808 kb
Host smart-f431bdc8-80c8-4ca1-9af9-bda305cc9469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718930772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.718930772
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1279698371
Short name T191
Test name
Test status
Simulation time 4839509778 ps
CPU time 13.49 seconds
Started Jun 23 05:47:16 PM PDT 24
Finished Jun 23 05:47:30 PM PDT 24
Peak memory 233900 kb
Host smart-f9c55b83-b56e-45b7-a671-c5ff778dbfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279698371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1279698371
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.442310748
Short name T972
Test name
Test status
Simulation time 211116258 ps
CPU time 3.88 seconds
Started Jun 23 05:47:17 PM PDT 24
Finished Jun 23 05:47:21 PM PDT 24
Peak memory 225528 kb
Host smart-81205b21-39db-4f0e-9df2-ce74a07d4a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442310748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.442310748
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1592794800
Short name T952
Test name
Test status
Simulation time 61712111 ps
CPU time 0.97 seconds
Started Jun 23 05:47:16 PM PDT 24
Finished Jun 23 05:47:17 PM PDT 24
Peak memory 217612 kb
Host smart-0931514d-0e0a-4356-a16b-1d87a5d02af5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592794800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1592794800
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.4230620856
Short name T941
Test name
Test status
Simulation time 3055321198 ps
CPU time 9.99 seconds
Started Jun 23 05:47:16 PM PDT 24
Finished Jun 23 05:47:27 PM PDT 24
Peak memory 225640 kb
Host smart-8782e55b-6ece-4c85-9e2e-6be15d5c382c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230620856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.4230620856
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3647075850
Short name T588
Test name
Test status
Simulation time 4531351116 ps
CPU time 14.78 seconds
Started Jun 23 05:47:16 PM PDT 24
Finished Jun 23 05:47:32 PM PDT 24
Peak memory 225716 kb
Host smart-ee1c28cb-b7e3-4cdc-a273-b9bdb7640b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647075850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3647075850
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.310968048
Short name T315
Test name
Test status
Simulation time 941546260 ps
CPU time 7.77 seconds
Started Jun 23 05:47:18 PM PDT 24
Finished Jun 23 05:47:27 PM PDT 24
Peak memory 223004 kb
Host smart-bffc991b-b927-4bd1-8d2b-def8672cae4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=310968048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.310968048
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2576426149
Short name T31
Test name
Test status
Simulation time 21743584382 ps
CPU time 20.86 seconds
Started Jun 23 05:47:16 PM PDT 24
Finished Jun 23 05:47:38 PM PDT 24
Peak memory 225720 kb
Host smart-933d1f15-a12d-4639-bed7-00442ec77ce3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576426149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2576426149
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2665040759
Short name T867
Test name
Test status
Simulation time 2115820286 ps
CPU time 17.96 seconds
Started Jun 23 05:47:17 PM PDT 24
Finished Jun 23 05:47:36 PM PDT 24
Peak memory 220128 kb
Host smart-396d7c7b-c8bb-4a4e-bd4c-68efce36234c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665040759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2665040759
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.4288350511
Short name T703
Test name
Test status
Simulation time 1168727275 ps
CPU time 2.3 seconds
Started Jun 23 05:47:15 PM PDT 24
Finished Jun 23 05:47:17 PM PDT 24
Peak memory 217412 kb
Host smart-45d7c5c7-cb2d-4c7a-859d-230e6828bb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288350511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.4288350511
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.4174226211
Short name T436
Test name
Test status
Simulation time 311619818 ps
CPU time 2.53 seconds
Started Jun 23 05:47:17 PM PDT 24
Finished Jun 23 05:47:20 PM PDT 24
Peak memory 217704 kb
Host smart-ba821443-9590-458a-a229-f4ae6cacb3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174226211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.4174226211
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1689650653
Short name T338
Test name
Test status
Simulation time 37063274 ps
CPU time 0.71 seconds
Started Jun 23 05:47:15 PM PDT 24
Finished Jun 23 05:47:17 PM PDT 24
Peak memory 206904 kb
Host smart-b88e7584-2f17-42ab-a7ec-15161479fee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689650653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1689650653
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.997214629
Short name T768
Test name
Test status
Simulation time 29865529173 ps
CPU time 23.22 seconds
Started Jun 23 05:47:17 PM PDT 24
Finished Jun 23 05:47:41 PM PDT 24
Peak memory 225640 kb
Host smart-166b65f0-e32c-4a16-9b3d-c10cb1123df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997214629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.997214629
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3271107882
Short name T538
Test name
Test status
Simulation time 109358381 ps
CPU time 0.74 seconds
Started Jun 23 05:47:16 PM PDT 24
Finished Jun 23 05:47:18 PM PDT 24
Peak memory 206652 kb
Host smart-103a4bec-c043-4091-9322-33e90631cbb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271107882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3271107882
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3363131873
Short name T794
Test name
Test status
Simulation time 183700935 ps
CPU time 3.05 seconds
Started Jun 23 05:47:17 PM PDT 24
Finished Jun 23 05:47:21 PM PDT 24
Peak memory 225604 kb
Host smart-66d731e5-34f7-4579-bfc8-5f8106f578a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363131873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3363131873
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.4155064599
Short name T353
Test name
Test status
Simulation time 42731296 ps
CPU time 0.79 seconds
Started Jun 23 05:47:14 PM PDT 24
Finished Jun 23 05:47:16 PM PDT 24
Peak memory 207484 kb
Host smart-cfc803e4-6973-4a41-8fce-34acebeb7bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155064599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.4155064599
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2267957241
Short name T247
Test name
Test status
Simulation time 21735576463 ps
CPU time 76.55 seconds
Started Jun 23 05:47:19 PM PDT 24
Finished Jun 23 05:48:36 PM PDT 24
Peak memory 256536 kb
Host smart-e5661947-177a-43f7-af10-f9af48fd2e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267957241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2267957241
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1845023032
Short name T804
Test name
Test status
Simulation time 57933557578 ps
CPU time 138.35 seconds
Started Jun 23 05:47:16 PM PDT 24
Finished Jun 23 05:49:35 PM PDT 24
Peak memory 255792 kb
Host smart-92f341b3-acb8-4b29-906a-34e402b5804e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845023032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1845023032
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1015151545
Short name T185
Test name
Test status
Simulation time 91246911841 ps
CPU time 266.56 seconds
Started Jun 23 05:47:13 PM PDT 24
Finished Jun 23 05:51:40 PM PDT 24
Peak memory 266912 kb
Host smart-e3743777-7085-400e-81ae-ba18502031b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015151545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1015151545
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.21456368
Short name T954
Test name
Test status
Simulation time 1248978085 ps
CPU time 4.08 seconds
Started Jun 23 05:47:14 PM PDT 24
Finished Jun 23 05:47:19 PM PDT 24
Peak memory 233812 kb
Host smart-0598cb26-8b3f-430d-84c3-359911431178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21456368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.21456368
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2664638576
Short name T668
Test name
Test status
Simulation time 240090804 ps
CPU time 2.62 seconds
Started Jun 23 05:47:17 PM PDT 24
Finished Jun 23 05:47:21 PM PDT 24
Peak memory 225516 kb
Host smart-4c4a3a5a-4287-4a24-b1d6-1a59d82a564f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664638576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2664638576
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.117404456
Short name T237
Test name
Test status
Simulation time 226892932 ps
CPU time 4.1 seconds
Started Jun 23 05:47:20 PM PDT 24
Finished Jun 23 05:47:25 PM PDT 24
Peak memory 225532 kb
Host smart-1b9917d1-00b8-4145-b832-04a2e8c3cb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117404456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.117404456
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3772768898
Short name T964
Test name
Test status
Simulation time 24900172 ps
CPU time 1.06 seconds
Started Jun 23 05:47:19 PM PDT 24
Finished Jun 23 05:47:21 PM PDT 24
Peak memory 217608 kb
Host smart-1dd3536c-1da7-4b7b-a55a-504dbbc2e783
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772768898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3772768898
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1921194117
Short name T632
Test name
Test status
Simulation time 5570368957 ps
CPU time 7.32 seconds
Started Jun 23 05:47:18 PM PDT 24
Finished Jun 23 05:47:26 PM PDT 24
Peak memory 233844 kb
Host smart-14f68707-4be5-4542-99f0-7a1a2b0bb375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921194117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1921194117
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3817451958
Short name T406
Test name
Test status
Simulation time 771149041 ps
CPU time 2.89 seconds
Started Jun 23 05:47:16 PM PDT 24
Finished Jun 23 05:47:20 PM PDT 24
Peak memory 225584 kb
Host smart-96d1605e-7404-483f-b414-25b1c69b5fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817451958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3817451958
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4097423160
Short name T942
Test name
Test status
Simulation time 1413526976 ps
CPU time 8.54 seconds
Started Jun 23 05:47:17 PM PDT 24
Finished Jun 23 05:47:26 PM PDT 24
Peak memory 221188 kb
Host smart-25b4a4b8-1b11-4ce6-907f-519f27a715ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4097423160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4097423160
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3567950588
Short name T151
Test name
Test status
Simulation time 106482420 ps
CPU time 1.07 seconds
Started Jun 23 05:47:18 PM PDT 24
Finished Jun 23 05:47:20 PM PDT 24
Peak memory 208344 kb
Host smart-0ee37bba-5705-4d39-a93f-cdd4c34be909
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567950588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3567950588
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3794766100
Short name T316
Test name
Test status
Simulation time 18615743338 ps
CPU time 13.5 seconds
Started Jun 23 05:47:17 PM PDT 24
Finished Jun 23 05:47:31 PM PDT 24
Peak memory 217532 kb
Host smart-ccde5139-9dbe-4c72-bb4d-d8c484897fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794766100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3794766100
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.4078568624
Short name T565
Test name
Test status
Simulation time 3496189554 ps
CPU time 8.24 seconds
Started Jun 23 05:47:17 PM PDT 24
Finished Jun 23 05:47:26 PM PDT 24
Peak memory 217448 kb
Host smart-123440f0-541f-40d2-909f-27ccdfe1c180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078568624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.4078568624
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2335026110
Short name T301
Test name
Test status
Simulation time 159233027 ps
CPU time 4.05 seconds
Started Jun 23 05:47:15 PM PDT 24
Finished Jun 23 05:47:19 PM PDT 24
Peak memory 217480 kb
Host smart-35a1403b-086e-4cc9-bde5-0d3234a0b74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335026110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2335026110
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2068186422
Short name T324
Test name
Test status
Simulation time 17984382 ps
CPU time 0.74 seconds
Started Jun 23 05:47:16 PM PDT 24
Finished Jun 23 05:47:17 PM PDT 24
Peak memory 206916 kb
Host smart-887a407f-029d-4cfa-805b-c475d5d5ca78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068186422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2068186422
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1991053867
Short name T226
Test name
Test status
Simulation time 1580613534 ps
CPU time 9.15 seconds
Started Jun 23 05:47:15 PM PDT 24
Finished Jun 23 05:47:25 PM PDT 24
Peak memory 233736 kb
Host smart-5059816c-14ba-4340-a77f-40f4a5b53443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991053867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1991053867
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2066844207
Short name T307
Test name
Test status
Simulation time 27901249 ps
CPU time 0.76 seconds
Started Jun 23 05:46:07 PM PDT 24
Finished Jun 23 05:46:08 PM PDT 24
Peak memory 206644 kb
Host smart-ce88aeb8-43f8-41ca-b572-f3581b56f236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066844207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
066844207
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2429980282
Short name T690
Test name
Test status
Simulation time 60399373 ps
CPU time 0.82 seconds
Started Jun 23 05:45:58 PM PDT 24
Finished Jun 23 05:46:00 PM PDT 24
Peak memory 207744 kb
Host smart-068251a4-430c-48d2-b6b8-cd9a96332e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429980282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2429980282
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2050869881
Short name T895
Test name
Test status
Simulation time 135981519608 ps
CPU time 484.55 seconds
Started Jun 23 05:46:01 PM PDT 24
Finished Jun 23 05:54:06 PM PDT 24
Peak memory 266656 kb
Host smart-22169e09-9866-479a-8b24-a9ba52eda90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050869881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2050869881
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1076195229
Short name T77
Test name
Test status
Simulation time 37607882798 ps
CPU time 310.04 seconds
Started Jun 23 05:46:03 PM PDT 24
Finished Jun 23 05:51:14 PM PDT 24
Peak memory 255048 kb
Host smart-97339afa-e59a-435d-a333-8cf8cf9daeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076195229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1076195229
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.393352780
Short name T808
Test name
Test status
Simulation time 26127107868 ps
CPU time 98.19 seconds
Started Jun 23 05:46:01 PM PDT 24
Finished Jun 23 05:47:41 PM PDT 24
Peak memory 250348 kb
Host smart-955a1336-104e-4a3b-9733-34eb3beb6a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393352780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
393352780
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1875357381
Short name T812
Test name
Test status
Simulation time 639994373 ps
CPU time 7.11 seconds
Started Jun 23 05:46:03 PM PDT 24
Finished Jun 23 05:46:10 PM PDT 24
Peak memory 233772 kb
Host smart-66eeb6cc-d908-44f7-ac10-7ce03c110c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875357381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1875357381
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1870856693
Short name T595
Test name
Test status
Simulation time 2163461276 ps
CPU time 20.25 seconds
Started Jun 23 05:46:02 PM PDT 24
Finished Jun 23 05:46:23 PM PDT 24
Peak memory 233860 kb
Host smart-96a5d678-132b-481b-a0f8-b4640a8a19f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870856693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1870856693
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2288068484
Short name T830
Test name
Test status
Simulation time 14874836096 ps
CPU time 36.85 seconds
Started Jun 23 05:46:02 PM PDT 24
Finished Jun 23 05:46:39 PM PDT 24
Peak memory 233916 kb
Host smart-cf6a2124-198b-4232-a0e2-e12a962a01dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288068484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2288068484
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.462118596
Short name T387
Test name
Test status
Simulation time 61523357 ps
CPU time 1.09 seconds
Started Jun 23 05:45:55 PM PDT 24
Finished Jun 23 05:45:57 PM PDT 24
Peak memory 217664 kb
Host smart-38f76e25-2dd5-4155-ba4e-d9b88f807e67
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462118596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.462118596
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.235905320
Short name T256
Test name
Test status
Simulation time 206570814 ps
CPU time 5.49 seconds
Started Jun 23 05:46:00 PM PDT 24
Finished Jun 23 05:46:06 PM PDT 24
Peak memory 233748 kb
Host smart-d2f4bed5-7193-4a44-b9a9-986472b9ad85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235905320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
235905320
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3703635051
Short name T400
Test name
Test status
Simulation time 825376890 ps
CPU time 2.33 seconds
Started Jun 23 05:46:01 PM PDT 24
Finished Jun 23 05:46:05 PM PDT 24
Peak memory 224208 kb
Host smart-a6e6ca0a-6118-4917-959e-e40948f227ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703635051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3703635051
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3033611536
Short name T331
Test name
Test status
Simulation time 794714446 ps
CPU time 5.17 seconds
Started Jun 23 05:46:00 PM PDT 24
Finished Jun 23 05:46:05 PM PDT 24
Peak memory 223984 kb
Host smart-22cb15bd-406d-4b57-ba61-e4d1e7b6071a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3033611536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3033611536
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1697443159
Short name T65
Test name
Test status
Simulation time 120386481 ps
CPU time 1.19 seconds
Started Jun 23 05:46:01 PM PDT 24
Finished Jun 23 05:46:02 PM PDT 24
Peak memory 236312 kb
Host smart-01a6e2cb-5fe7-4347-b024-aeaa0131e425
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697443159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1697443159
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.721073337
Short name T258
Test name
Test status
Simulation time 17693925740 ps
CPU time 62.28 seconds
Started Jun 23 05:46:01 PM PDT 24
Finished Jun 23 05:47:04 PM PDT 24
Peak memory 251688 kb
Host smart-76d96f48-882c-473e-921d-b90865d8dd4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721073337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.721073337
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.269223804
Short name T944
Test name
Test status
Simulation time 56655673 ps
CPU time 0.74 seconds
Started Jun 23 05:46:00 PM PDT 24
Finished Jun 23 05:46:02 PM PDT 24
Peak memory 206644 kb
Host smart-c1f30018-345b-40f6-b2cf-17654bade3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269223804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.269223804
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2317260603
Short name T450
Test name
Test status
Simulation time 8745935234 ps
CPU time 7.09 seconds
Started Jun 23 05:45:59 PM PDT 24
Finished Jun 23 05:46:07 PM PDT 24
Peak memory 217556 kb
Host smart-50f15745-4a87-4ed5-bbbb-f92485eef785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317260603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2317260603
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.17137994
Short name T478
Test name
Test status
Simulation time 25692054 ps
CPU time 0.92 seconds
Started Jun 23 05:45:59 PM PDT 24
Finished Jun 23 05:46:00 PM PDT 24
Peak memory 208300 kb
Host smart-90ba5d16-d228-4938-975f-66b89317c5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17137994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.17137994
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.208853144
Short name T786
Test name
Test status
Simulation time 23270636 ps
CPU time 0.78 seconds
Started Jun 23 05:46:02 PM PDT 24
Finished Jun 23 05:46:03 PM PDT 24
Peak memory 206912 kb
Host smart-7ddce69f-27b2-4f5e-b88e-89bdbbc72afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208853144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.208853144
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1501394114
Short name T904
Test name
Test status
Simulation time 1761327040 ps
CPU time 7.67 seconds
Started Jun 23 05:46:03 PM PDT 24
Finished Jun 23 05:46:11 PM PDT 24
Peak memory 225592 kb
Host smart-efdc5649-c575-4760-855f-59510307ba6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501394114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1501394114
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1889676316
Short name T506
Test name
Test status
Simulation time 31876889 ps
CPU time 0.79 seconds
Started Jun 23 05:47:20 PM PDT 24
Finished Jun 23 05:47:21 PM PDT 24
Peak memory 205696 kb
Host smart-b956b3eb-cb36-48a7-8ffd-6f41acfa110c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889676316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1889676316
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3743762754
Short name T482
Test name
Test status
Simulation time 680726525 ps
CPU time 3.68 seconds
Started Jun 23 05:47:21 PM PDT 24
Finished Jun 23 05:47:25 PM PDT 24
Peak memory 233776 kb
Host smart-2751ce12-cc45-4e8a-aebd-a4c071c194e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743762754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3743762754
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.325196648
Short name T973
Test name
Test status
Simulation time 20137466 ps
CPU time 0.73 seconds
Started Jun 23 05:47:18 PM PDT 24
Finished Jun 23 05:47:19 PM PDT 24
Peak memory 206500 kb
Host smart-5f4a264d-4d51-42cb-8330-2133dc735edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325196648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.325196648
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3351833156
Short name T159
Test name
Test status
Simulation time 105003832514 ps
CPU time 208.73 seconds
Started Jun 23 05:47:19 PM PDT 24
Finished Jun 23 05:50:49 PM PDT 24
Peak memory 251328 kb
Host smart-2ce02c15-2bfe-413f-8cdd-47b02a08d430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351833156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3351833156
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1030835616
Short name T607
Test name
Test status
Simulation time 12758006200 ps
CPU time 65.94 seconds
Started Jun 23 05:47:18 PM PDT 24
Finished Jun 23 05:48:24 PM PDT 24
Peak memory 254820 kb
Host smart-7be2ec65-4b44-46f7-8d4c-f87665a4cdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030835616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1030835616
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.4257635857
Short name T630
Test name
Test status
Simulation time 2852823976 ps
CPU time 26.33 seconds
Started Jun 23 05:47:18 PM PDT 24
Finished Jun 23 05:47:45 PM PDT 24
Peak memory 232996 kb
Host smart-e688afef-e699-441d-9ac2-6aee1e87ac8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257635857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.4257635857
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3082220707
Short name T655
Test name
Test status
Simulation time 105046613 ps
CPU time 3.84 seconds
Started Jun 23 05:47:20 PM PDT 24
Finished Jun 23 05:47:24 PM PDT 24
Peak memory 233716 kb
Host smart-13fd3517-96cd-41df-9b14-45041b5fdac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082220707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3082220707
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4105164958
Short name T751
Test name
Test status
Simulation time 930971471 ps
CPU time 4.67 seconds
Started Jun 23 05:47:25 PM PDT 24
Finished Jun 23 05:47:30 PM PDT 24
Peak memory 233692 kb
Host smart-239d30a3-5cf2-4445-a364-10b6daae1579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105164958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4105164958
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1530271702
Short name T641
Test name
Test status
Simulation time 2235574407 ps
CPU time 15.28 seconds
Started Jun 23 05:47:19 PM PDT 24
Finished Jun 23 05:47:35 PM PDT 24
Peak memory 225720 kb
Host smart-5c2e4bbb-4957-4033-bc46-f6ce5d7d5f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530271702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1530271702
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2949747497
Short name T761
Test name
Test status
Simulation time 38052037 ps
CPU time 2.5 seconds
Started Jun 23 05:47:21 PM PDT 24
Finished Jun 23 05:47:24 PM PDT 24
Peak memory 233544 kb
Host smart-9bc1dd9d-7b66-4a9f-8388-def0d2b06bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949747497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2949747497
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.344333524
Short name T497
Test name
Test status
Simulation time 134393151 ps
CPU time 2.18 seconds
Started Jun 23 05:47:22 PM PDT 24
Finished Jun 23 05:47:24 PM PDT 24
Peak memory 225604 kb
Host smart-d5e860c4-bf65-4645-ac0b-928e72ebe2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344333524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.344333524
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.79834563
Short name T396
Test name
Test status
Simulation time 301054942 ps
CPU time 4.31 seconds
Started Jun 23 05:47:18 PM PDT 24
Finished Jun 23 05:47:24 PM PDT 24
Peak memory 219928 kb
Host smart-3beb2257-c9e7-4b99-8184-a7b58af6ddad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=79834563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direc
t.79834563
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3394201370
Short name T417
Test name
Test status
Simulation time 1453634969 ps
CPU time 8.36 seconds
Started Jun 23 05:47:16 PM PDT 24
Finished Jun 23 05:47:25 PM PDT 24
Peak memory 217328 kb
Host smart-0abc3a2d-173d-42e0-8b27-be4dadeaf76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394201370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3394201370
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3474441328
Short name T871
Test name
Test status
Simulation time 5256715059 ps
CPU time 3.7 seconds
Started Jun 23 05:47:16 PM PDT 24
Finished Jun 23 05:47:20 PM PDT 24
Peak memory 217300 kb
Host smart-e2427223-473c-4528-825b-a8c081359104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474441328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3474441328
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3914534443
Short name T516
Test name
Test status
Simulation time 198110481 ps
CPU time 3.35 seconds
Started Jun 23 05:47:21 PM PDT 24
Finished Jun 23 05:47:25 PM PDT 24
Peak memory 217404 kb
Host smart-01131d9b-69aa-4e6d-9fae-98ebdf2cfd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914534443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3914534443
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2169856207
Short name T667
Test name
Test status
Simulation time 61951705 ps
CPU time 0.93 seconds
Started Jun 23 05:47:17 PM PDT 24
Finished Jun 23 05:47:18 PM PDT 24
Peak memory 206816 kb
Host smart-f2dadbcd-dff4-4816-96cb-2a484b6dee9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169856207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2169856207
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.13621791
Short name T948
Test name
Test status
Simulation time 171125574 ps
CPU time 2.45 seconds
Started Jun 23 05:47:20 PM PDT 24
Finished Jun 23 05:47:23 PM PDT 24
Peak memory 233528 kb
Host smart-09ec49ea-b0f0-4979-adb0-12bef2046732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13621791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.13621791
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1652828770
Short name T3
Test name
Test status
Simulation time 17673650 ps
CPU time 0.71 seconds
Started Jun 23 05:47:29 PM PDT 24
Finished Jun 23 05:47:31 PM PDT 24
Peak memory 205920 kb
Host smart-ad34ba28-3fa4-4f18-9dd6-79cb8b6c1a4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652828770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1652828770
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.4046326775
Short name T561
Test name
Test status
Simulation time 1517460739 ps
CPU time 17.16 seconds
Started Jun 23 05:47:29 PM PDT 24
Finished Jun 23 05:47:47 PM PDT 24
Peak memory 233868 kb
Host smart-0bcbd502-0736-44ac-8fd8-23ac966bf100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046326775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.4046326775
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2060538219
Short name T769
Test name
Test status
Simulation time 32266717 ps
CPU time 0.76 seconds
Started Jun 23 05:47:20 PM PDT 24
Finished Jun 23 05:47:21 PM PDT 24
Peak memory 206452 kb
Host smart-96e596bd-acd0-409c-aada-cc4f5013b518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060538219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2060538219
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.894169221
Short name T466
Test name
Test status
Simulation time 2551978145 ps
CPU time 18.07 seconds
Started Jun 23 05:47:23 PM PDT 24
Finished Jun 23 05:47:41 PM PDT 24
Peak memory 239208 kb
Host smart-149ae68e-b67c-47cd-a44d-d7680c8e77e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894169221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.894169221
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2367091070
Short name T547
Test name
Test status
Simulation time 21599126537 ps
CPU time 71.76 seconds
Started Jun 23 05:47:24 PM PDT 24
Finished Jun 23 05:48:36 PM PDT 24
Peak memory 250584 kb
Host smart-ce957ae9-bad6-4c89-93f2-a163d5d84f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367091070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2367091070
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.4050864272
Short name T936
Test name
Test status
Simulation time 2628857870 ps
CPU time 57.55 seconds
Started Jun 23 05:47:23 PM PDT 24
Finished Jun 23 05:48:21 PM PDT 24
Peak memory 266356 kb
Host smart-42575617-f30e-47a1-93ed-2bd261f36ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050864272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.4050864272
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2515409443
Short name T278
Test name
Test status
Simulation time 1059234910 ps
CPU time 9.23 seconds
Started Jun 23 05:47:28 PM PDT 24
Finished Jun 23 05:47:37 PM PDT 24
Peak memory 233680 kb
Host smart-bfad7a8e-53f9-4659-a892-cae750a42fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515409443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2515409443
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3870443660
Short name T909
Test name
Test status
Simulation time 645437605 ps
CPU time 3 seconds
Started Jun 23 05:47:20 PM PDT 24
Finished Jun 23 05:47:23 PM PDT 24
Peak memory 225540 kb
Host smart-eff00bfa-092e-437c-90b0-279c4caaf5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870443660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3870443660
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2249093932
Short name T802
Test name
Test status
Simulation time 12257714138 ps
CPU time 97.24 seconds
Started Jun 23 05:47:18 PM PDT 24
Finished Jun 23 05:48:56 PM PDT 24
Peak memory 241796 kb
Host smart-a99f5087-4a34-4d60-b096-1850b755ba86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249093932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2249093932
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.4012893410
Short name T250
Test name
Test status
Simulation time 293442761 ps
CPU time 4.76 seconds
Started Jun 23 05:47:23 PM PDT 24
Finished Jun 23 05:47:28 PM PDT 24
Peak memory 233732 kb
Host smart-ee9f23a5-1d66-4514-a9a8-c4fe8faab0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012893410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.4012893410
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1879241085
Short name T186
Test name
Test status
Simulation time 21254693476 ps
CPU time 11.09 seconds
Started Jun 23 05:47:20 PM PDT 24
Finished Jun 23 05:47:32 PM PDT 24
Peak memory 233812 kb
Host smart-e5f98cdb-aaad-4d60-a0ca-ed556a914267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879241085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1879241085
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2951488697
Short name T809
Test name
Test status
Simulation time 272284107 ps
CPU time 4.76 seconds
Started Jun 23 05:47:27 PM PDT 24
Finished Jun 23 05:47:32 PM PDT 24
Peak memory 223072 kb
Host smart-ffad6999-09ce-41df-9a43-b93a2406994c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2951488697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2951488697
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.112120455
Short name T602
Test name
Test status
Simulation time 197972698 ps
CPU time 1.07 seconds
Started Jun 23 05:47:22 PM PDT 24
Finished Jun 23 05:47:23 PM PDT 24
Peak memory 208176 kb
Host smart-de5d081f-fbf3-409e-8a8c-295e6759e3bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112120455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.112120455
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.879329531
Short name T852
Test name
Test status
Simulation time 7395384842 ps
CPU time 35.8 seconds
Started Jun 23 05:47:19 PM PDT 24
Finished Jun 23 05:47:56 PM PDT 24
Peak memory 217504 kb
Host smart-b326da15-8fd2-40de-a60d-dd6cdcacae84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879329531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.879329531
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2499755761
Short name T686
Test name
Test status
Simulation time 10790754495 ps
CPU time 7.32 seconds
Started Jun 23 05:47:24 PM PDT 24
Finished Jun 23 05:47:31 PM PDT 24
Peak memory 217320 kb
Host smart-1f3f1704-f3b4-4b6a-8fc7-88bfcfd057cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499755761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2499755761
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1945621002
Short name T12
Test name
Test status
Simulation time 102067089 ps
CPU time 1.36 seconds
Started Jun 23 05:47:24 PM PDT 24
Finished Jun 23 05:47:25 PM PDT 24
Peak memory 208992 kb
Host smart-e007bfd1-ed76-462b-b40f-b542660f7af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945621002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1945621002
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3019262733
Short name T887
Test name
Test status
Simulation time 59628276 ps
CPU time 0.84 seconds
Started Jun 23 05:47:18 PM PDT 24
Finished Jun 23 05:47:20 PM PDT 24
Peak memory 206804 kb
Host smart-fa49a176-2184-4c5c-9349-a05764374ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019262733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3019262733
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.4194210582
Short name T244
Test name
Test status
Simulation time 850085640 ps
CPU time 5.83 seconds
Started Jun 23 05:47:19 PM PDT 24
Finished Jun 23 05:47:25 PM PDT 24
Peak memory 233764 kb
Host smart-bb2c28dc-8371-4e77-9a3b-f14d2c56ea03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194210582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4194210582
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1873278167
Short name T894
Test name
Test status
Simulation time 92134329 ps
CPU time 0.71 seconds
Started Jun 23 05:47:30 PM PDT 24
Finished Jun 23 05:47:32 PM PDT 24
Peak memory 206232 kb
Host smart-fb63ae2b-2a76-4e55-813f-2bb2be2e4951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873278167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1873278167
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2606010208
Short name T571
Test name
Test status
Simulation time 902217435 ps
CPU time 6.4 seconds
Started Jun 23 05:47:25 PM PDT 24
Finished Jun 23 05:47:32 PM PDT 24
Peak memory 225600 kb
Host smart-b8e615e8-8f2a-4595-a025-a00992ba34db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606010208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2606010208
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3346885613
Short name T564
Test name
Test status
Simulation time 34790100 ps
CPU time 0.75 seconds
Started Jun 23 05:47:25 PM PDT 24
Finished Jun 23 05:47:26 PM PDT 24
Peak memory 207524 kb
Host smart-387cc7f8-b047-46a6-a51a-7eb095a5ff4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346885613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3346885613
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.353614172
Short name T960
Test name
Test status
Simulation time 4007859633 ps
CPU time 51.4 seconds
Started Jun 23 05:47:22 PM PDT 24
Finished Jun 23 05:48:14 PM PDT 24
Peak memory 250344 kb
Host smart-39bebe42-533d-4428-a644-35224732ead0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353614172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.353614172
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2228682631
Short name T377
Test name
Test status
Simulation time 319305358 ps
CPU time 4.6 seconds
Started Jun 23 05:47:27 PM PDT 24
Finished Jun 23 05:47:32 PM PDT 24
Peak memory 233788 kb
Host smart-c7399d7f-1567-4057-8d5c-3c1f1e3d0e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228682631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2228682631
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2626277569
Short name T732
Test name
Test status
Simulation time 607054378 ps
CPU time 3.34 seconds
Started Jun 23 05:47:26 PM PDT 24
Finished Jun 23 05:47:30 PM PDT 24
Peak memory 233800 kb
Host smart-5add40d5-5047-4573-bacd-a778f1489cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626277569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2626277569
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2971318407
Short name T198
Test name
Test status
Simulation time 336661457 ps
CPU time 9.3 seconds
Started Jun 23 05:47:25 PM PDT 24
Finished Jun 23 05:47:35 PM PDT 24
Peak memory 233740 kb
Host smart-26bac3e8-50ac-43aa-8c76-f3bf0be3328a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971318407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2971318407
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2712879901
Short name T70
Test name
Test status
Simulation time 4735820892 ps
CPU time 19.17 seconds
Started Jun 23 05:47:25 PM PDT 24
Finished Jun 23 05:47:45 PM PDT 24
Peak memory 250108 kb
Host smart-09eaee5d-e4a6-4d4d-bcb9-4a978020f95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712879901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2712879901
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2491706231
Short name T685
Test name
Test status
Simulation time 636981377 ps
CPU time 6.7 seconds
Started Jun 23 05:47:23 PM PDT 24
Finished Jun 23 05:47:30 PM PDT 24
Peak memory 241840 kb
Host smart-d2dd6fa8-84e9-42c9-8cd7-306a299a5fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491706231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2491706231
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3123124452
Short name T945
Test name
Test status
Simulation time 1163112402 ps
CPU time 4.41 seconds
Started Jun 23 05:47:27 PM PDT 24
Finished Jun 23 05:47:32 PM PDT 24
Peak memory 222864 kb
Host smart-9e55402f-9881-45c4-9c21-1b474c6c0772
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3123124452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3123124452
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3094868485
Short name T726
Test name
Test status
Simulation time 7315827423 ps
CPU time 41.51 seconds
Started Jun 23 05:47:25 PM PDT 24
Finished Jun 23 05:48:07 PM PDT 24
Peak memory 225700 kb
Host smart-ce4648d4-93ce-4d30-a24a-56c14ea9d75f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094868485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3094868485
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1573934793
Short name T597
Test name
Test status
Simulation time 32936031 ps
CPU time 0.73 seconds
Started Jun 23 05:47:24 PM PDT 24
Finished Jun 23 05:47:25 PM PDT 24
Peak memory 206656 kb
Host smart-021f8273-b52c-4e07-8d6c-b0f50ae66839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573934793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1573934793
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2183671446
Short name T332
Test name
Test status
Simulation time 7960234447 ps
CPU time 20.28 seconds
Started Jun 23 05:47:26 PM PDT 24
Finished Jun 23 05:47:47 PM PDT 24
Peak memory 217440 kb
Host smart-7a29fdfb-c38d-4687-ac0a-755cbd5ef047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183671446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2183671446
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1935332875
Short name T293
Test name
Test status
Simulation time 94865199 ps
CPU time 1.81 seconds
Started Jun 23 05:47:21 PM PDT 24
Finished Jun 23 05:47:23 PM PDT 24
Peak memory 217288 kb
Host smart-2628bf71-8c13-47b8-91dc-086a6c968e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935332875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1935332875
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1710160076
Short name T28
Test name
Test status
Simulation time 114038320 ps
CPU time 1 seconds
Started Jun 23 05:47:26 PM PDT 24
Finished Jun 23 05:47:27 PM PDT 24
Peak memory 206924 kb
Host smart-c00c2622-b4d4-4dfd-874e-2ec599ab61e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710160076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1710160076
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1255397620
Short name T487
Test name
Test status
Simulation time 118429104 ps
CPU time 3.17 seconds
Started Jun 23 05:47:26 PM PDT 24
Finished Jun 23 05:47:29 PM PDT 24
Peak memory 233788 kb
Host smart-88325654-a592-4d36-9de2-da9b31a0cf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255397620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1255397620
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.784083788
Short name T617
Test name
Test status
Simulation time 11553743 ps
CPU time 0.81 seconds
Started Jun 23 05:47:33 PM PDT 24
Finished Jun 23 05:47:34 PM PDT 24
Peak memory 205720 kb
Host smart-1f2e5018-f7e4-4116-8857-7bf51f30733b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784083788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.784083788
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.862601658
Short name T844
Test name
Test status
Simulation time 28636228 ps
CPU time 0.77 seconds
Started Jun 23 05:47:29 PM PDT 24
Finished Jun 23 05:47:30 PM PDT 24
Peak memory 207792 kb
Host smart-88a2a454-5916-480e-8693-1619faa7bc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862601658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.862601658
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3092889914
Short name T367
Test name
Test status
Simulation time 52795130285 ps
CPU time 110.53 seconds
Started Jun 23 05:47:30 PM PDT 24
Finished Jun 23 05:49:22 PM PDT 24
Peak memory 256408 kb
Host smart-f56ed938-3c0f-4e10-a305-b37563e02d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092889914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3092889914
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1256993228
Short name T970
Test name
Test status
Simulation time 30943882360 ps
CPU time 98.02 seconds
Started Jun 23 05:47:29 PM PDT 24
Finished Jun 23 05:49:08 PM PDT 24
Peak memory 250332 kb
Host smart-076ffbe7-c871-42fc-a18d-4b8dae04ac0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256993228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1256993228
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1547834194
Short name T870
Test name
Test status
Simulation time 257517758568 ps
CPU time 127.08 seconds
Started Jun 23 05:47:30 PM PDT 24
Finished Jun 23 05:49:38 PM PDT 24
Peak memory 251808 kb
Host smart-32bf0448-1010-4797-9cd4-80d023830663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547834194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1547834194
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.926208339
Short name T144
Test name
Test status
Simulation time 407210994 ps
CPU time 9.34 seconds
Started Jun 23 05:47:30 PM PDT 24
Finished Jun 23 05:47:40 PM PDT 24
Peak memory 255632 kb
Host smart-d5e8f6c4-9df8-4beb-b4b3-be3e769e97e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926208339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.926208339
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2537158266
Short name T905
Test name
Test status
Simulation time 1742785619 ps
CPU time 6.94 seconds
Started Jun 23 05:47:26 PM PDT 24
Finished Jun 23 05:47:34 PM PDT 24
Peak memory 233780 kb
Host smart-88327af7-1333-4242-9fa9-5f10047fae9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537158266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2537158266
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1173224562
Short name T88
Test name
Test status
Simulation time 13232217544 ps
CPU time 155.32 seconds
Started Jun 23 05:47:34 PM PDT 24
Finished Jun 23 05:50:10 PM PDT 24
Peak memory 241096 kb
Host smart-9f284930-18b4-47fa-8af6-30d34c663184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173224562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1173224562
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.493333904
Short name T49
Test name
Test status
Simulation time 5394729885 ps
CPU time 10.77 seconds
Started Jun 23 05:47:32 PM PDT 24
Finished Jun 23 05:47:44 PM PDT 24
Peak memory 240792 kb
Host smart-aafdfd90-ac82-479d-b479-1435b93d76e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493333904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.493333904
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1954641247
Short name T223
Test name
Test status
Simulation time 267838129 ps
CPU time 2.25 seconds
Started Jun 23 05:47:29 PM PDT 24
Finished Jun 23 05:47:31 PM PDT 24
Peak memory 225500 kb
Host smart-2d799881-7c5d-4fdf-abe9-f0191d8dccf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954641247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1954641247
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.490291147
Short name T753
Test name
Test status
Simulation time 384263052 ps
CPU time 4.1 seconds
Started Jun 23 05:47:33 PM PDT 24
Finished Jun 23 05:47:37 PM PDT 24
Peak memory 224172 kb
Host smart-f8751498-55cc-40b5-8417-317361fea809
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=490291147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.490291147
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1481119599
Short name T157
Test name
Test status
Simulation time 89912937 ps
CPU time 1.21 seconds
Started Jun 23 05:47:33 PM PDT 24
Finished Jun 23 05:47:35 PM PDT 24
Peak memory 207924 kb
Host smart-11c99066-5e1d-4db4-afc2-fc560dd89e24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481119599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1481119599
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3943303706
Short name T283
Test name
Test status
Simulation time 10167875283 ps
CPU time 13.19 seconds
Started Jun 23 05:47:29 PM PDT 24
Finished Jun 23 05:47:43 PM PDT 24
Peak memory 217612 kb
Host smart-ce7dc7cf-cd5f-460c-9a03-59867a511d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943303706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3943303706
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1462896181
Short name T30
Test name
Test status
Simulation time 730714444 ps
CPU time 1.91 seconds
Started Jun 23 05:47:27 PM PDT 24
Finished Jun 23 05:47:30 PM PDT 24
Peak memory 208972 kb
Host smart-24d4245b-28dd-4f4e-a747-7edd82950d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462896181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1462896181
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.582425165
Short name T566
Test name
Test status
Simulation time 202240680 ps
CPU time 8.84 seconds
Started Jun 23 05:47:34 PM PDT 24
Finished Jun 23 05:47:43 PM PDT 24
Peak memory 217356 kb
Host smart-b8f49039-0fb7-4bea-851a-8863d5241c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582425165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.582425165
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2929329380
Short name T326
Test name
Test status
Simulation time 110275900 ps
CPU time 1.04 seconds
Started Jun 23 05:47:29 PM PDT 24
Finished Jun 23 05:47:31 PM PDT 24
Peak memory 207176 kb
Host smart-1c7e0219-62dc-4ec0-a736-db03d6f3ed66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929329380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2929329380
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3615748598
Short name T792
Test name
Test status
Simulation time 732736776 ps
CPU time 5.52 seconds
Started Jun 23 05:47:33 PM PDT 24
Finished Jun 23 05:47:39 PM PDT 24
Peak memory 233748 kb
Host smart-4de9ca0b-4651-4eeb-a759-b4f0d49d34a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615748598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3615748598
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.4220741505
Short name T311
Test name
Test status
Simulation time 68352779 ps
CPU time 0.67 seconds
Started Jun 23 05:47:36 PM PDT 24
Finished Jun 23 05:47:37 PM PDT 24
Peak memory 206560 kb
Host smart-bd288c10-50c5-49b9-a37d-03e0a50cdd19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220741505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
4220741505
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.870328362
Short name T799
Test name
Test status
Simulation time 177506514 ps
CPU time 3.57 seconds
Started Jun 23 05:47:31 PM PDT 24
Finished Jun 23 05:47:35 PM PDT 24
Peak memory 233684 kb
Host smart-24452eaa-d53e-418e-970e-9d5de81f3556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870328362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.870328362
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2784333169
Short name T789
Test name
Test status
Simulation time 53528056 ps
CPU time 0.81 seconds
Started Jun 23 05:47:30 PM PDT 24
Finished Jun 23 05:47:31 PM PDT 24
Peak memory 207496 kb
Host smart-66b618c7-ba3d-4c39-8e7d-9262198be59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784333169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2784333169
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.803035666
Short name T682
Test name
Test status
Simulation time 6565680848 ps
CPU time 17.8 seconds
Started Jun 23 05:47:32 PM PDT 24
Finished Jun 23 05:47:50 PM PDT 24
Peak memory 237204 kb
Host smart-44383b5d-fd22-4d71-833a-c76d476b1c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803035666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.803035666
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1277407956
Short name T167
Test name
Test status
Simulation time 3519743338 ps
CPU time 34.38 seconds
Started Jun 23 05:47:33 PM PDT 24
Finished Jun 23 05:48:08 PM PDT 24
Peak memory 242288 kb
Host smart-3015537f-b044-4032-9b84-a80431c87ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277407956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1277407956
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2881399583
Short name T476
Test name
Test status
Simulation time 2329637070 ps
CPU time 20.68 seconds
Started Jun 23 05:47:33 PM PDT 24
Finished Jun 23 05:47:54 PM PDT 24
Peak memory 218748 kb
Host smart-8cd5f7bc-87f4-4b00-8146-d7cb23aab81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881399583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2881399583
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1889356592
Short name T74
Test name
Test status
Simulation time 335872618 ps
CPU time 9.5 seconds
Started Jun 23 05:47:35 PM PDT 24
Finished Jun 23 05:47:45 PM PDT 24
Peak memory 250144 kb
Host smart-a095d7e0-51d4-498b-8467-85fc7fcd6264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889356592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1889356592
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2987822626
Short name T242
Test name
Test status
Simulation time 120513409 ps
CPU time 3.68 seconds
Started Jun 23 05:47:33 PM PDT 24
Finished Jun 23 05:47:38 PM PDT 24
Peak memory 233764 kb
Host smart-d098769e-c2ec-49cf-bf20-5c8d46b4660b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987822626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2987822626
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3648349168
Short name T783
Test name
Test status
Simulation time 6662583107 ps
CPU time 24.5 seconds
Started Jun 23 05:47:33 PM PDT 24
Finished Jun 23 05:47:58 PM PDT 24
Peak memory 250128 kb
Host smart-08c7143d-7356-4397-b51f-892d98028df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648349168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3648349168
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1943171034
Short name T857
Test name
Test status
Simulation time 530385057 ps
CPU time 2.53 seconds
Started Jun 23 05:47:30 PM PDT 24
Finished Jun 23 05:47:34 PM PDT 24
Peak memory 225464 kb
Host smart-401b4ee1-abdf-4ea6-adc0-f80532c8eb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943171034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1943171034
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1097007069
Short name T882
Test name
Test status
Simulation time 17649482506 ps
CPU time 44.34 seconds
Started Jun 23 05:47:34 PM PDT 24
Finished Jun 23 05:48:19 PM PDT 24
Peak memory 225604 kb
Host smart-90f8a01b-f96e-498e-959c-637ad084f684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097007069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1097007069
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3671788864
Short name T11
Test name
Test status
Simulation time 5153147435 ps
CPU time 6.65 seconds
Started Jun 23 05:47:34 PM PDT 24
Finished Jun 23 05:47:41 PM PDT 24
Peak memory 224292 kb
Host smart-9a80903c-ca25-476f-afee-985db6b15569
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3671788864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3671788864
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2454199939
Short name T526
Test name
Test status
Simulation time 11866929733 ps
CPU time 99.63 seconds
Started Jun 23 05:47:32 PM PDT 24
Finished Jun 23 05:49:12 PM PDT 24
Peak memory 250380 kb
Host smart-476786d3-754b-410f-b617-830c93a0e893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454199939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2454199939
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3460510124
Short name T10
Test name
Test status
Simulation time 6347574993 ps
CPU time 27.55 seconds
Started Jun 23 05:47:29 PM PDT 24
Finished Jun 23 05:47:58 PM PDT 24
Peak memory 217576 kb
Host smart-741451df-e808-49c6-88ea-5cae99200a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460510124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3460510124
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3362663802
Short name T798
Test name
Test status
Simulation time 1969436725 ps
CPU time 7.47 seconds
Started Jun 23 05:47:27 PM PDT 24
Finished Jun 23 05:47:35 PM PDT 24
Peak memory 217256 kb
Host smart-532b87fe-6e97-4f1a-b08f-63bdac4d4976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362663802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3362663802
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.844921097
Short name T834
Test name
Test status
Simulation time 302223506 ps
CPU time 3.77 seconds
Started Jun 23 05:47:32 PM PDT 24
Finished Jun 23 05:47:36 PM PDT 24
Peak memory 217340 kb
Host smart-91e480af-aa52-40d6-be84-e0089936fde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844921097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.844921097
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3558345115
Short name T313
Test name
Test status
Simulation time 434853077 ps
CPU time 0.93 seconds
Started Jun 23 05:47:30 PM PDT 24
Finished Jun 23 05:47:31 PM PDT 24
Peak memory 206936 kb
Host smart-f3e51157-7139-49fb-9cbf-42b32a9e336f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558345115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3558345115
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2987650625
Short name T835
Test name
Test status
Simulation time 151479286 ps
CPU time 2.06 seconds
Started Jun 23 05:47:30 PM PDT 24
Finished Jun 23 05:47:32 PM PDT 24
Peak memory 225180 kb
Host smart-0ee60e6f-abd5-4b3b-8b7d-9c194cd98010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987650625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2987650625
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2124997119
Short name T496
Test name
Test status
Simulation time 11435629 ps
CPU time 0.74 seconds
Started Jun 23 05:47:39 PM PDT 24
Finished Jun 23 05:47:40 PM PDT 24
Peak memory 206264 kb
Host smart-40d1941e-3138-4070-8aac-e8eabf15f324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124997119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2124997119
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2197350871
Short name T638
Test name
Test status
Simulation time 473350205 ps
CPU time 2.42 seconds
Started Jun 23 05:47:38 PM PDT 24
Finished Jun 23 05:47:41 PM PDT 24
Peak memory 225460 kb
Host smart-62bca10e-2545-491c-af4a-211ba5ac2ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197350871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2197350871
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2930683736
Short name T519
Test name
Test status
Simulation time 71479341 ps
CPU time 0.79 seconds
Started Jun 23 05:47:35 PM PDT 24
Finished Jun 23 05:47:37 PM PDT 24
Peak memory 207860 kb
Host smart-98ccdb4d-774a-48e2-ba9e-122ea5982a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930683736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2930683736
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.369757562
Short name T134
Test name
Test status
Simulation time 2336417254 ps
CPU time 17.85 seconds
Started Jun 23 05:47:43 PM PDT 24
Finished Jun 23 05:48:01 PM PDT 24
Peak memory 242100 kb
Host smart-3d7951a7-f7a4-46bf-85b5-d91fa0143ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369757562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.369757562
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2960713942
Short name T868
Test name
Test status
Simulation time 88023477830 ps
CPU time 224.81 seconds
Started Jun 23 05:47:40 PM PDT 24
Finished Jun 23 05:51:26 PM PDT 24
Peak memory 250372 kb
Host smart-32469822-fc1a-4a96-a5d2-99f48c26bebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960713942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2960713942
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3077132898
Short name T251
Test name
Test status
Simulation time 46933761813 ps
CPU time 486.91 seconds
Started Jun 23 05:47:40 PM PDT 24
Finished Jun 23 05:55:48 PM PDT 24
Peak memory 267584 kb
Host smart-0a47dcbd-3331-4e14-887c-d70ffdf7eceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077132898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3077132898
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2878138953
Short name T693
Test name
Test status
Simulation time 195304956 ps
CPU time 4 seconds
Started Jun 23 05:47:39 PM PDT 24
Finished Jun 23 05:47:43 PM PDT 24
Peak memory 225592 kb
Host smart-fc62b001-15e9-4d62-b9f0-bec5da7885b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878138953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2878138953
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3483180103
Short name T660
Test name
Test status
Simulation time 1869731012 ps
CPU time 7.46 seconds
Started Jun 23 05:47:33 PM PDT 24
Finished Jun 23 05:47:41 PM PDT 24
Peak memory 233768 kb
Host smart-f9f71589-1767-4ae9-9217-f273546c3daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483180103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3483180103
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.749854676
Short name T494
Test name
Test status
Simulation time 105122377 ps
CPU time 2.35 seconds
Started Jun 23 05:47:40 PM PDT 24
Finished Jun 23 05:47:43 PM PDT 24
Peak memory 224248 kb
Host smart-d423b39e-32c1-4d56-988c-1f1471a2f400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749854676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.749854676
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.628883181
Short name T900
Test name
Test status
Simulation time 449090586 ps
CPU time 5.22 seconds
Started Jun 23 05:47:36 PM PDT 24
Finished Jun 23 05:47:42 PM PDT 24
Peak memory 233768 kb
Host smart-2822d84a-69e7-46f8-97e1-21f8c6b4c1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628883181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.628883181
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1006446009
Short name T719
Test name
Test status
Simulation time 769030398 ps
CPU time 8.94 seconds
Started Jun 23 05:47:30 PM PDT 24
Finished Jun 23 05:47:40 PM PDT 24
Peak memory 241768 kb
Host smart-a3e83871-2945-4f01-807e-4352899b023a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006446009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1006446009
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3043733081
Short name T389
Test name
Test status
Simulation time 1715977571 ps
CPU time 4.62 seconds
Started Jun 23 05:47:40 PM PDT 24
Finished Jun 23 05:47:44 PM PDT 24
Peak memory 223672 kb
Host smart-81324cfa-524f-471f-b93d-7c7e522249c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3043733081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3043733081
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1410621083
Short name T148
Test name
Test status
Simulation time 25045082092 ps
CPU time 52.35 seconds
Started Jun 23 05:47:41 PM PDT 24
Finished Jun 23 05:48:34 PM PDT 24
Peak memory 242032 kb
Host smart-7003fa37-7307-4faa-9cfc-018fd89950aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410621083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1410621083
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.4196027183
Short name T280
Test name
Test status
Simulation time 4403358974 ps
CPU time 27.93 seconds
Started Jun 23 05:47:34 PM PDT 24
Finished Jun 23 05:48:02 PM PDT 24
Peak memory 217472 kb
Host smart-050e2731-971c-4bcd-972c-576279265ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196027183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.4196027183
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3266142742
Short name T395
Test name
Test status
Simulation time 3037499945 ps
CPU time 5.72 seconds
Started Jun 23 05:47:36 PM PDT 24
Finished Jun 23 05:47:42 PM PDT 24
Peak memory 217472 kb
Host smart-79be3031-1d3d-48fe-9397-d3c40da7aa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266142742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3266142742
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2787983219
Short name T394
Test name
Test status
Simulation time 316545119 ps
CPU time 2.62 seconds
Started Jun 23 05:47:32 PM PDT 24
Finished Jun 23 05:47:35 PM PDT 24
Peak memory 217268 kb
Host smart-6ee36d1f-0c1c-48dc-93f1-5275dbb03800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787983219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2787983219
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2657744896
Short name T616
Test name
Test status
Simulation time 79935693 ps
CPU time 0.98 seconds
Started Jun 23 05:47:35 PM PDT 24
Finished Jun 23 05:47:36 PM PDT 24
Peak memory 207888 kb
Host smart-aa8d9b63-afe1-4142-8c19-bec29175839a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657744896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2657744896
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.822229874
Short name T559
Test name
Test status
Simulation time 377859653 ps
CPU time 3.18 seconds
Started Jun 23 05:47:40 PM PDT 24
Finished Jun 23 05:47:44 PM PDT 24
Peak memory 225560 kb
Host smart-dfe3cad5-4898-46cb-a81c-c92ec4ff8ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822229874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.822229874
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.497370584
Short name T963
Test name
Test status
Simulation time 23735470 ps
CPU time 0.74 seconds
Started Jun 23 05:47:48 PM PDT 24
Finished Jun 23 05:47:50 PM PDT 24
Peak memory 206264 kb
Host smart-d4dfcf7c-bed7-4c03-b22c-7c561002a32e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497370584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.497370584
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2572547612
Short name T372
Test name
Test status
Simulation time 2936106709 ps
CPU time 8.92 seconds
Started Jun 23 05:47:40 PM PDT 24
Finished Jun 23 05:47:50 PM PDT 24
Peak memory 225708 kb
Host smart-7a2d9bc8-9991-4eb7-9f28-8cbbaeef33a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572547612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2572547612
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3754004119
Short name T714
Test name
Test status
Simulation time 14099189 ps
CPU time 0.76 seconds
Started Jun 23 05:47:40 PM PDT 24
Finished Jun 23 05:47:42 PM PDT 24
Peak memory 207872 kb
Host smart-a5028704-0a9e-4d7a-9ab6-761e5b363faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754004119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3754004119
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.4144712077
Short name T371
Test name
Test status
Simulation time 2642573268 ps
CPU time 22.13 seconds
Started Jun 23 05:47:40 PM PDT 24
Finished Jun 23 05:48:03 PM PDT 24
Peak memory 233852 kb
Host smart-3b483346-a32c-4c2d-9ae5-79d1419a5850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144712077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.4144712077
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3794323762
Short name T925
Test name
Test status
Simulation time 2702550095 ps
CPU time 41.51 seconds
Started Jun 23 05:47:42 PM PDT 24
Finished Jun 23 05:48:24 PM PDT 24
Peak memory 251204 kb
Host smart-2dd18650-5eba-4667-9183-277243117d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794323762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3794323762
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3339257669
Short name T265
Test name
Test status
Simulation time 31085802832 ps
CPU time 187.43 seconds
Started Jun 23 05:47:43 PM PDT 24
Finished Jun 23 05:50:51 PM PDT 24
Peak memory 249752 kb
Host smart-a017d7bc-0d5b-4e29-beb7-817073092292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339257669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3339257669
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1801336735
Short name T831
Test name
Test status
Simulation time 11719774749 ps
CPU time 15.84 seconds
Started Jun 23 05:47:45 PM PDT 24
Finished Jun 23 05:48:01 PM PDT 24
Peak memory 225604 kb
Host smart-c76c9fc4-b692-4934-b451-282319b50856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801336735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1801336735
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2703935305
Short name T883
Test name
Test status
Simulation time 90783063066 ps
CPU time 46.96 seconds
Started Jun 23 05:47:37 PM PDT 24
Finished Jun 23 05:48:24 PM PDT 24
Peak memory 225572 kb
Host smart-d3a03bb5-2cc6-4ea5-9e6c-d24fd2817f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703935305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2703935305
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.220564388
Short name T221
Test name
Test status
Simulation time 469471889 ps
CPU time 13.24 seconds
Started Jun 23 05:47:48 PM PDT 24
Finished Jun 23 05:48:02 PM PDT 24
Peak memory 240528 kb
Host smart-45f799ac-105c-4253-b84b-15ee7c57201d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220564388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.220564388
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.804377542
Short name T470
Test name
Test status
Simulation time 703223568 ps
CPU time 4.73 seconds
Started Jun 23 05:47:40 PM PDT 24
Finished Jun 23 05:47:45 PM PDT 24
Peak memory 233764 kb
Host smart-9b8de306-c043-44af-8e4a-305511a01066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804377542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.804377542
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1113708022
Short name T483
Test name
Test status
Simulation time 9142444054 ps
CPU time 13.01 seconds
Started Jun 23 05:47:38 PM PDT 24
Finished Jun 23 05:47:52 PM PDT 24
Peak memory 233880 kb
Host smart-d0397218-ece8-43ce-9188-30e3bbf2809d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113708022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1113708022
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2252722675
Short name T42
Test name
Test status
Simulation time 145642957 ps
CPU time 3.43 seconds
Started Jun 23 05:47:43 PM PDT 24
Finished Jun 23 05:47:47 PM PDT 24
Peak memory 223476 kb
Host smart-f0b7e5b2-914b-4615-a4c2-7c9694d8b2fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2252722675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2252722675
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.191859880
Short name T666
Test name
Test status
Simulation time 222387467 ps
CPU time 1.08 seconds
Started Jun 23 05:47:48 PM PDT 24
Finished Jun 23 05:47:49 PM PDT 24
Peak memory 207960 kb
Host smart-916c6512-5a51-4820-94dd-6965995ae3b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191859880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.191859880
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1323212760
Short name T504
Test name
Test status
Simulation time 12217560230 ps
CPU time 34.47 seconds
Started Jun 23 05:47:48 PM PDT 24
Finished Jun 23 05:48:23 PM PDT 24
Peak memory 217444 kb
Host smart-e32e985a-3f1f-4a59-a736-7ffe2b1a35b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323212760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1323212760
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2395426361
Short name T689
Test name
Test status
Simulation time 779522695 ps
CPU time 3.84 seconds
Started Jun 23 05:47:41 PM PDT 24
Finished Jun 23 05:47:45 PM PDT 24
Peak memory 217376 kb
Host smart-4abc138b-2d2e-4c60-8c06-48561e5f438e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395426361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2395426361
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1115989471
Short name T355
Test name
Test status
Simulation time 138859799 ps
CPU time 1.44 seconds
Started Jun 23 05:47:37 PM PDT 24
Finished Jun 23 05:47:39 PM PDT 24
Peak memory 217336 kb
Host smart-bef85e39-0742-4039-9f36-64c5386e29fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115989471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1115989471
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1378663305
Short name T461
Test name
Test status
Simulation time 89634551 ps
CPU time 0.96 seconds
Started Jun 23 05:47:39 PM PDT 24
Finished Jun 23 05:47:41 PM PDT 24
Peak memory 207340 kb
Host smart-96cd4ae2-16f1-4d52-9be5-4c71a927c834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378663305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1378663305
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1223586502
Short name T241
Test name
Test status
Simulation time 2402688801 ps
CPU time 9.51 seconds
Started Jun 23 05:47:47 PM PDT 24
Finished Jun 23 05:47:57 PM PDT 24
Peak memory 233904 kb
Host smart-dda5fe59-0f0d-419f-9401-677d823cc0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223586502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1223586502
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2488521962
Short name T549
Test name
Test status
Simulation time 13402022 ps
CPU time 0.72 seconds
Started Jun 23 05:47:48 PM PDT 24
Finished Jun 23 05:47:50 PM PDT 24
Peak memory 206632 kb
Host smart-a0d0e7e5-67c6-498f-9522-51330e34fb81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488521962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2488521962
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.687983279
Short name T877
Test name
Test status
Simulation time 271475014 ps
CPU time 2.98 seconds
Started Jun 23 05:47:43 PM PDT 24
Finished Jun 23 05:47:47 PM PDT 24
Peak memory 233788 kb
Host smart-6bdfba8b-4d9b-4c19-b2cd-5fd53363d3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687983279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.687983279
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3477004047
Short name T650
Test name
Test status
Simulation time 16665706 ps
CPU time 0.76 seconds
Started Jun 23 05:47:44 PM PDT 24
Finished Jun 23 05:47:45 PM PDT 24
Peak memory 206528 kb
Host smart-ac8105b1-e85b-49d0-9fe7-4e34a2ab3190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477004047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3477004047
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.422779472
Short name T734
Test name
Test status
Simulation time 17683306961 ps
CPU time 70.41 seconds
Started Jun 23 05:47:48 PM PDT 24
Finished Jun 23 05:48:59 PM PDT 24
Peak memory 256312 kb
Host smart-dce98ab1-d80c-40c6-acf6-07e371456335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422779472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.422779472
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2872164576
Short name T767
Test name
Test status
Simulation time 129496654397 ps
CPU time 328.93 seconds
Started Jun 23 05:47:46 PM PDT 24
Finished Jun 23 05:53:15 PM PDT 24
Peak memory 254936 kb
Host smart-9b129d37-cf7c-4749-be31-6ee5e742d0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872164576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2872164576
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1321543910
Short name T910
Test name
Test status
Simulation time 1038531651 ps
CPU time 11.32 seconds
Started Jun 23 05:47:44 PM PDT 24
Finished Jun 23 05:47:56 PM PDT 24
Peak memory 225548 kb
Host smart-5597e783-1a31-4b5c-a9b9-634a2b7e37a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321543910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1321543910
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1356874805
Short name T706
Test name
Test status
Simulation time 12804473872 ps
CPU time 36.67 seconds
Started Jun 23 05:47:42 PM PDT 24
Finished Jun 23 05:48:19 PM PDT 24
Peak memory 241688 kb
Host smart-5326991f-7abd-47ec-af61-a42d8ab93547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356874805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1356874805
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1937248986
Short name T807
Test name
Test status
Simulation time 755297642 ps
CPU time 6.6 seconds
Started Jun 23 05:47:45 PM PDT 24
Finished Jun 23 05:47:52 PM PDT 24
Peak memory 241900 kb
Host smart-040ed48d-08ab-4e7b-b696-9e55aff8cd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937248986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1937248986
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.329702129
Short name T219
Test name
Test status
Simulation time 8708197946 ps
CPU time 16.21 seconds
Started Jun 23 05:47:46 PM PDT 24
Finished Jun 23 05:48:03 PM PDT 24
Peak memory 233804 kb
Host smart-0b796293-a28b-4090-b2e0-abc361e1e11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329702129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.329702129
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.394407019
Short name T710
Test name
Test status
Simulation time 249345840 ps
CPU time 3.51 seconds
Started Jun 23 05:47:51 PM PDT 24
Finished Jun 23 05:47:55 PM PDT 24
Peak memory 220476 kb
Host smart-d300ff47-b316-4b77-8a50-ec95ec296870
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=394407019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.394407019
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2954373032
Short name T696
Test name
Test status
Simulation time 280971380203 ps
CPU time 261.75 seconds
Started Jun 23 05:47:43 PM PDT 24
Finished Jun 23 05:52:05 PM PDT 24
Peak memory 254776 kb
Host smart-d67b37a8-cacf-4a98-9cbb-07739f10e729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954373032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2954373032
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.547766066
Short name T876
Test name
Test status
Simulation time 3686348635 ps
CPU time 18.53 seconds
Started Jun 23 05:47:43 PM PDT 24
Finished Jun 23 05:48:02 PM PDT 24
Peak memory 217488 kb
Host smart-d3c41163-0261-46e6-994b-29e8c7e56f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547766066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.547766066
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1917801104
Short name T458
Test name
Test status
Simulation time 22194598097 ps
CPU time 15.95 seconds
Started Jun 23 05:47:40 PM PDT 24
Finished Jun 23 05:47:56 PM PDT 24
Peak memory 217484 kb
Host smart-4a70ecd9-40b3-4681-9628-594c15e26850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917801104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1917801104
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1664876021
Short name T480
Test name
Test status
Simulation time 35784095 ps
CPU time 1.67 seconds
Started Jun 23 05:47:40 PM PDT 24
Finished Jun 23 05:47:43 PM PDT 24
Peak memory 217288 kb
Host smart-4fb0ef7a-5422-4a5e-89cb-3c356acbaf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664876021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1664876021
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2541411544
Short name T762
Test name
Test status
Simulation time 105837353 ps
CPU time 0.8 seconds
Started Jun 23 05:47:44 PM PDT 24
Finished Jun 23 05:47:45 PM PDT 24
Peak memory 206792 kb
Host smart-1705a023-a320-4850-9ed2-99efde801df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541411544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2541411544
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.655449266
Short name T599
Test name
Test status
Simulation time 177526798 ps
CPU time 2.39 seconds
Started Jun 23 05:47:44 PM PDT 24
Finished Jun 23 05:47:46 PM PDT 24
Peak memory 233772 kb
Host smart-533784ca-aea7-42dd-9a22-8cf303a69da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655449266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.655449266
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3902363953
Short name T745
Test name
Test status
Simulation time 42885396 ps
CPU time 0.71 seconds
Started Jun 23 05:47:50 PM PDT 24
Finished Jun 23 05:47:52 PM PDT 24
Peak memory 206652 kb
Host smart-8eb50d0d-ea0b-45e1-bda3-63b13ae38d0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902363953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3902363953
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1202461181
Short name T329
Test name
Test status
Simulation time 312990572 ps
CPU time 6.22 seconds
Started Jun 23 05:47:44 PM PDT 24
Finished Jun 23 05:47:50 PM PDT 24
Peak memory 233604 kb
Host smart-43df69b8-e4ab-4421-9d94-8698f31a4a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202461181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1202461181
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2473510703
Short name T790
Test name
Test status
Simulation time 167692429 ps
CPU time 0.77 seconds
Started Jun 23 05:47:43 PM PDT 24
Finished Jun 23 05:47:44 PM PDT 24
Peak memory 208020 kb
Host smart-53cb2a34-50c9-4cbc-9f89-a0e9ed60a42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473510703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2473510703
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3497888350
Short name T930
Test name
Test status
Simulation time 4314823980 ps
CPU time 42.86 seconds
Started Jun 23 05:47:53 PM PDT 24
Finished Jun 23 05:48:37 PM PDT 24
Peak memory 251696 kb
Host smart-b986aa76-7409-4b79-bdc3-9d0477eae652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497888350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3497888350
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3371343346
Short name T699
Test name
Test status
Simulation time 4007573712 ps
CPU time 80.34 seconds
Started Jun 23 05:47:48 PM PDT 24
Finished Jun 23 05:49:08 PM PDT 24
Peak memory 258544 kb
Host smart-9657383d-50c2-4e5d-b3e2-027247e5314b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371343346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3371343346
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3755931962
Short name T352
Test name
Test status
Simulation time 8779280678 ps
CPU time 64.41 seconds
Started Jun 23 05:47:48 PM PDT 24
Finished Jun 23 05:48:52 PM PDT 24
Peak memory 251632 kb
Host smart-4e719c08-10bb-48ff-a45c-635da60c23ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755931962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3755931962
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1827136659
Short name T486
Test name
Test status
Simulation time 95458299 ps
CPU time 2.58 seconds
Started Jun 23 05:47:52 PM PDT 24
Finished Jun 23 05:47:56 PM PDT 24
Peak memory 225532 kb
Host smart-0dfd0a40-6252-47ba-a32b-d05449b1d7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827136659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1827136659
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2013830004
Short name T548
Test name
Test status
Simulation time 4713576174 ps
CPU time 9.8 seconds
Started Jun 23 05:47:45 PM PDT 24
Finished Jun 23 05:47:55 PM PDT 24
Peak memory 225624 kb
Host smart-25f06100-32cc-4e0d-8ffb-cf92b3ca22f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013830004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2013830004
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2603863404
Short name T203
Test name
Test status
Simulation time 730394280 ps
CPU time 12.9 seconds
Started Jun 23 05:47:44 PM PDT 24
Finished Jun 23 05:47:57 PM PDT 24
Peak memory 233648 kb
Host smart-42b96fd1-7ff9-4dcb-a105-a0242d228498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603863404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2603863404
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3905795989
Short name T712
Test name
Test status
Simulation time 62947401164 ps
CPU time 19.65 seconds
Started Jun 23 05:47:46 PM PDT 24
Finished Jun 23 05:48:06 PM PDT 24
Peak memory 241804 kb
Host smart-88f76a35-3300-41c2-89b5-fc4a5f04553a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905795989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3905795989
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3317803737
Short name T464
Test name
Test status
Simulation time 5169827838 ps
CPU time 8.5 seconds
Started Jun 23 05:47:45 PM PDT 24
Finished Jun 23 05:47:54 PM PDT 24
Peak memory 225672 kb
Host smart-78f1da67-4f34-47dd-9bdf-161dd4f6a8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317803737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3317803737
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2460302029
Short name T637
Test name
Test status
Simulation time 1556941577 ps
CPU time 4.15 seconds
Started Jun 23 05:47:49 PM PDT 24
Finished Jun 23 05:47:54 PM PDT 24
Peak memory 224184 kb
Host smart-1f98cec9-5f0c-491e-aab2-56f30c62a412
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2460302029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2460302029
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3825926697
Short name T264
Test name
Test status
Simulation time 15688551420 ps
CPU time 104.51 seconds
Started Jun 23 05:47:50 PM PDT 24
Finished Jun 23 05:49:35 PM PDT 24
Peak memory 270872 kb
Host smart-3f1a587c-6723-4a94-9d50-ed9fc6eace5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825926697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3825926697
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1554308982
Short name T402
Test name
Test status
Simulation time 6342011005 ps
CPU time 19.47 seconds
Started Jun 23 05:47:43 PM PDT 24
Finished Jun 23 05:48:03 PM PDT 24
Peak memory 217536 kb
Host smart-273f4b93-0bc5-49b7-a278-0f4dcf319d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554308982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1554308982
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.117230085
Short name T716
Test name
Test status
Simulation time 1320151004 ps
CPU time 5.86 seconds
Started Jun 23 05:47:51 PM PDT 24
Finished Jun 23 05:47:57 PM PDT 24
Peak memory 217328 kb
Host smart-b59abcd1-bd0c-4c27-929e-6a0325cb9e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117230085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.117230085
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1423213375
Short name T421
Test name
Test status
Simulation time 853769183 ps
CPU time 10.18 seconds
Started Jun 23 05:47:46 PM PDT 24
Finished Jun 23 05:47:57 PM PDT 24
Peak memory 217488 kb
Host smart-cadb8c87-44d2-4fd5-8cc9-f4223f82a3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423213375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1423213375
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.818830714
Short name T298
Test name
Test status
Simulation time 23618183 ps
CPU time 0.77 seconds
Started Jun 23 05:47:41 PM PDT 24
Finished Jun 23 05:47:43 PM PDT 24
Peak memory 206900 kb
Host smart-a8983554-9636-41c0-b8bf-e4e7037e2709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818830714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.818830714
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.363425853
Short name T216
Test name
Test status
Simulation time 7595509528 ps
CPU time 14.42 seconds
Started Jun 23 05:47:45 PM PDT 24
Finished Jun 23 05:48:00 PM PDT 24
Peak memory 234908 kb
Host smart-c5a7e6e8-14cd-468b-b924-8f651b6e5859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363425853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.363425853
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3265802581
Short name T527
Test name
Test status
Simulation time 14457655 ps
CPU time 0.72 seconds
Started Jun 23 05:47:53 PM PDT 24
Finished Jun 23 05:47:54 PM PDT 24
Peak memory 205744 kb
Host smart-ebaa1629-346c-440e-95dd-1c4751650817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265802581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3265802581
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.579472960
Short name T962
Test name
Test status
Simulation time 3981018887 ps
CPU time 6.62 seconds
Started Jun 23 05:47:57 PM PDT 24
Finished Jun 23 05:48:04 PM PDT 24
Peak memory 225720 kb
Host smart-8efc1a99-8a06-47e2-a682-147f33f596c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579472960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.579472960
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1251436312
Short name T356
Test name
Test status
Simulation time 70832094 ps
CPU time 0.79 seconds
Started Jun 23 05:47:50 PM PDT 24
Finished Jun 23 05:47:51 PM PDT 24
Peak memory 206520 kb
Host smart-03f54f53-560e-4511-b67a-e42e976d6637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251436312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1251436312
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1069191976
Short name T926
Test name
Test status
Simulation time 18792581966 ps
CPU time 194.14 seconds
Started Jun 23 05:47:55 PM PDT 24
Finished Jun 23 05:51:10 PM PDT 24
Peak memory 250368 kb
Host smart-b9800573-5c19-4e29-969e-05ef3bb5fe79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069191976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1069191976
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.4227163870
Short name T758
Test name
Test status
Simulation time 5060777981 ps
CPU time 49.62 seconds
Started Jun 23 05:47:52 PM PDT 24
Finished Jun 23 05:48:43 PM PDT 24
Peak memory 235132 kb
Host smart-8a8fbada-a83a-45ef-baed-eedd00b7651e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227163870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.4227163870
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.926403060
Short name T179
Test name
Test status
Simulation time 1421840290 ps
CPU time 14.45 seconds
Started Jun 23 05:47:52 PM PDT 24
Finished Jun 23 05:48:08 PM PDT 24
Peak memory 241956 kb
Host smart-a56d3783-0a2f-45ba-a991-7eb84a1a936a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926403060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.926403060
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2348366126
Short name T975
Test name
Test status
Simulation time 373950336 ps
CPU time 7.48 seconds
Started Jun 23 05:47:55 PM PDT 24
Finished Jun 23 05:48:03 PM PDT 24
Peak memory 225536 kb
Host smart-ab952250-d71f-4293-8fc3-c5060509e9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348366126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2348366126
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1583229636
Short name T692
Test name
Test status
Simulation time 7902841003 ps
CPU time 7.93 seconds
Started Jun 23 05:47:51 PM PDT 24
Finished Jun 23 05:47:59 PM PDT 24
Peak memory 233780 kb
Host smart-429dcf9f-4726-4ead-b622-a02edf862bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583229636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1583229636
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3794465711
Short name T594
Test name
Test status
Simulation time 12022628923 ps
CPU time 26.34 seconds
Started Jun 23 05:47:56 PM PDT 24
Finished Jun 23 05:48:22 PM PDT 24
Peak memory 225636 kb
Host smart-0421af47-e529-47ca-b009-d7bbd3750927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794465711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3794465711
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1289453625
Short name T541
Test name
Test status
Simulation time 271341352 ps
CPU time 3.73 seconds
Started Jun 23 05:47:54 PM PDT 24
Finished Jun 23 05:47:58 PM PDT 24
Peak memory 223960 kb
Host smart-bbe29ffc-13e6-4841-b337-f41ad9588d23
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1289453625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1289453625
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.287861418
Short name T563
Test name
Test status
Simulation time 13001491111 ps
CPU time 12.93 seconds
Started Jun 23 05:47:55 PM PDT 24
Finished Jun 23 05:48:08 PM PDT 24
Peak memory 225644 kb
Host smart-b4e02298-dcc2-413c-986c-93f6ba8a9231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287861418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.287861418
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.315350890
Short name T51
Test name
Test status
Simulation time 40209799111 ps
CPU time 45.64 seconds
Started Jun 23 05:47:48 PM PDT 24
Finished Jun 23 05:48:34 PM PDT 24
Peak memory 217480 kb
Host smart-9e77a346-2c1e-434b-8a62-cf083b001a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315350890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.315350890
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1239692592
Short name T437
Test name
Test status
Simulation time 539697500 ps
CPU time 2.71 seconds
Started Jun 23 05:47:50 PM PDT 24
Finished Jun 23 05:47:54 PM PDT 24
Peak memory 217408 kb
Host smart-69ad80cf-dce4-46ef-8fa8-aba1e03576dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239692592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1239692592
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3228679908
Short name T879
Test name
Test status
Simulation time 26265729 ps
CPU time 1.07 seconds
Started Jun 23 05:47:52 PM PDT 24
Finished Jun 23 05:47:54 PM PDT 24
Peak memory 208956 kb
Host smart-5cf6613a-134f-4ad6-b45a-cb4a956e1448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228679908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3228679908
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2029809669
Short name T319
Test name
Test status
Simulation time 86823817 ps
CPU time 0.91 seconds
Started Jun 23 05:47:50 PM PDT 24
Finished Jun 23 05:47:51 PM PDT 24
Peak memory 206912 kb
Host smart-1e7e8547-2a80-47fc-a024-700aa13381ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029809669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2029809669
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3002702504
Short name T208
Test name
Test status
Simulation time 2741352920 ps
CPU time 7.4 seconds
Started Jun 23 05:47:53 PM PDT 24
Finished Jun 23 05:48:01 PM PDT 24
Peak memory 233888 kb
Host smart-c602b2ab-6ffe-4529-9916-387d3b67fe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002702504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3002702504
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.320655798
Short name T940
Test name
Test status
Simulation time 17549891 ps
CPU time 0.7 seconds
Started Jun 23 05:46:13 PM PDT 24
Finished Jun 23 05:46:14 PM PDT 24
Peak memory 206340 kb
Host smart-0d062f52-6523-4163-83ac-f7c9916be0fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320655798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.320655798
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2606570887
Short name T773
Test name
Test status
Simulation time 1986228150 ps
CPU time 5.72 seconds
Started Jun 23 05:46:12 PM PDT 24
Finished Jun 23 05:46:19 PM PDT 24
Peak memory 225528 kb
Host smart-0a83a9a8-1e31-4463-b084-0dd3d6526e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606570887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2606570887
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2654387190
Short name T620
Test name
Test status
Simulation time 74671823 ps
CPU time 0.77 seconds
Started Jun 23 05:46:07 PM PDT 24
Finished Jun 23 05:46:08 PM PDT 24
Peak memory 206496 kb
Host smart-e20b5928-cab3-4a6f-a669-5ff5debec0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654387190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2654387190
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.630897847
Short name T552
Test name
Test status
Simulation time 9931375388 ps
CPU time 16.83 seconds
Started Jun 23 05:46:12 PM PDT 24
Finished Jun 23 05:46:29 PM PDT 24
Peak memory 238148 kb
Host smart-3d646492-e144-49fe-b010-e8a4af3db223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630897847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.630897847
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2956936394
Short name T368
Test name
Test status
Simulation time 214312869528 ps
CPU time 98.42 seconds
Started Jun 23 05:46:15 PM PDT 24
Finished Jun 23 05:47:54 PM PDT 24
Peak memory 239312 kb
Host smart-867b5fd6-c7cd-4470-8a71-e10754e17142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956936394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2956936394
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.96130208
Short name T257
Test name
Test status
Simulation time 3678890649 ps
CPU time 83.14 seconds
Started Jun 23 05:46:10 PM PDT 24
Finished Jun 23 05:47:34 PM PDT 24
Peak memory 257448 kb
Host smart-e99496c6-d161-4981-94b6-d20360f9391b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96130208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.96130208
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1122443073
Short name T365
Test name
Test status
Simulation time 189056483 ps
CPU time 2.76 seconds
Started Jun 23 05:46:17 PM PDT 24
Finished Jun 23 05:46:20 PM PDT 24
Peak memory 233812 kb
Host smart-76637f45-5b3b-4680-b38f-fa7bd7ab976d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122443073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1122443073
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2371672344
Short name T535
Test name
Test status
Simulation time 107464846 ps
CPU time 2.44 seconds
Started Jun 23 05:46:05 PM PDT 24
Finished Jun 23 05:46:08 PM PDT 24
Peak memory 219688 kb
Host smart-3d5805ab-64a6-404d-a1d2-e244cdffa69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371672344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2371672344
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3905747197
Short name T236
Test name
Test status
Simulation time 30630570471 ps
CPU time 80.14 seconds
Started Jun 23 05:46:09 PM PDT 24
Finished Jun 23 05:47:30 PM PDT 24
Peak memory 225712 kb
Host smart-3ed19a2d-018d-4e2c-be85-bb0f2d77778c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905747197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3905747197
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3062675464
Short name T128
Test name
Test status
Simulation time 30328992 ps
CPU time 0.96 seconds
Started Jun 23 05:46:08 PM PDT 24
Finished Jun 23 05:46:10 PM PDT 24
Peak memory 218880 kb
Host smart-0bcf628e-ea78-4e75-92c0-48b1bfa62d2f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062675464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3062675464
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.803331090
Short name T463
Test name
Test status
Simulation time 173698152 ps
CPU time 2.21 seconds
Started Jun 23 05:46:09 PM PDT 24
Finished Jun 23 05:46:12 PM PDT 24
Peak memory 224820 kb
Host smart-3fd1edd5-c687-49b6-8070-fb1d8b3249ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803331090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
803331090
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3508598584
Short name T429
Test name
Test status
Simulation time 483753853 ps
CPU time 4.43 seconds
Started Jun 23 05:46:09 PM PDT 24
Finished Jun 23 05:46:14 PM PDT 24
Peak memory 235880 kb
Host smart-662a1637-e7ea-42b3-9454-31f6e90274da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508598584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3508598584
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3364870944
Short name T432
Test name
Test status
Simulation time 5779610294 ps
CPU time 16.38 seconds
Started Jun 23 05:46:10 PM PDT 24
Finished Jun 23 05:46:27 PM PDT 24
Peak memory 224264 kb
Host smart-3ad95a11-dfa2-4b98-87c7-efc607cf287d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3364870944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3364870944
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.996398471
Short name T733
Test name
Test status
Simulation time 6859461129 ps
CPU time 18.05 seconds
Started Jun 23 05:46:08 PM PDT 24
Finished Jun 23 05:46:27 PM PDT 24
Peak memory 217500 kb
Host smart-645c88ee-b72e-4f22-a178-4efb5330a429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996398471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.996398471
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2736340231
Short name T707
Test name
Test status
Simulation time 8413656220 ps
CPU time 3.19 seconds
Started Jun 23 05:46:09 PM PDT 24
Finished Jun 23 05:46:13 PM PDT 24
Peak memory 217528 kb
Host smart-93a2a25a-132f-4556-9969-d7b43ad2c1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736340231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2736340231
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2115011213
Short name T642
Test name
Test status
Simulation time 22935918 ps
CPU time 0.7 seconds
Started Jun 23 05:46:07 PM PDT 24
Finished Jun 23 05:46:08 PM PDT 24
Peak memory 206560 kb
Host smart-259dd824-8cf0-472a-aca0-25feb65e5e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115011213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2115011213
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.223703348
Short name T950
Test name
Test status
Simulation time 50574559 ps
CPU time 0.76 seconds
Started Jun 23 05:46:09 PM PDT 24
Finished Jun 23 05:46:10 PM PDT 24
Peak memory 206912 kb
Host smart-03904e14-a22b-44bd-a499-7fbe049b7113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223703348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.223703348
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3756823285
Short name T825
Test name
Test status
Simulation time 830392801 ps
CPU time 3.93 seconds
Started Jun 23 05:46:11 PM PDT 24
Finished Jun 23 05:46:15 PM PDT 24
Peak memory 233800 kb
Host smart-1ae306b6-5dd0-4166-9699-5d9c384cc0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756823285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3756823285
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.4158228284
Short name T489
Test name
Test status
Simulation time 23718150 ps
CPU time 0.73 seconds
Started Jun 23 05:48:00 PM PDT 24
Finished Jun 23 05:48:01 PM PDT 24
Peak memory 206284 kb
Host smart-62332de3-d6b0-4668-abe0-cf8fa7b9fb01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158228284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
4158228284
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1565175316
Short name T431
Test name
Test status
Simulation time 207404413 ps
CPU time 2.29 seconds
Started Jun 23 05:47:54 PM PDT 24
Finished Jun 23 05:47:57 PM PDT 24
Peak memory 225600 kb
Host smart-3a2754bb-e874-4757-a148-89f1059d0e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565175316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1565175316
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1931304848
Short name T605
Test name
Test status
Simulation time 51267911 ps
CPU time 0.87 seconds
Started Jun 23 05:47:59 PM PDT 24
Finished Jun 23 05:48:01 PM PDT 24
Peak memory 206492 kb
Host smart-97ad9e0f-9750-4bd3-b874-b8370153c37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931304848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1931304848
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3799998540
Short name T760
Test name
Test status
Simulation time 7070675104 ps
CPU time 67.4 seconds
Started Jun 23 05:48:10 PM PDT 24
Finished Jun 23 05:49:18 PM PDT 24
Peak memory 256124 kb
Host smart-eb2c606c-3e43-4c30-832c-832838a0ad6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799998540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3799998540
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1955396310
Short name T906
Test name
Test status
Simulation time 4532461016 ps
CPU time 53.83 seconds
Started Jun 23 05:48:00 PM PDT 24
Finished Jun 23 05:48:55 PM PDT 24
Peak memory 237044 kb
Host smart-524a5e96-3994-41ff-8a7d-723f61d3dec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955396310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1955396310
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1186120599
Short name T262
Test name
Test status
Simulation time 161410725958 ps
CPU time 152.6 seconds
Started Jun 23 05:48:01 PM PDT 24
Finished Jun 23 05:50:34 PM PDT 24
Peak memory 255604 kb
Host smart-cd927800-50c4-4a09-a1da-dc0308138a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186120599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1186120599
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.299675526
Short name T492
Test name
Test status
Simulation time 979213346 ps
CPU time 6.9 seconds
Started Jun 23 05:47:53 PM PDT 24
Finished Jun 23 05:48:00 PM PDT 24
Peak memory 233708 kb
Host smart-c6bbfc23-6c97-4d4a-9a19-ba62ea5ee55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299675526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.299675526
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1906390879
Short name T675
Test name
Test status
Simulation time 745330915 ps
CPU time 9.32 seconds
Started Jun 23 05:47:56 PM PDT 24
Finished Jun 23 05:48:06 PM PDT 24
Peak memory 225552 kb
Host smart-f954968b-2d32-4aeb-8384-bd167c3e5703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906390879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1906390879
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2249784333
Short name T713
Test name
Test status
Simulation time 21742286766 ps
CPU time 18.15 seconds
Started Jun 23 05:47:55 PM PDT 24
Finished Jun 23 05:48:14 PM PDT 24
Peak memory 225648 kb
Host smart-49e9acc8-688f-4dec-bb7e-76c469da5eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249784333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2249784333
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2627788751
Short name T590
Test name
Test status
Simulation time 31224884635 ps
CPU time 21.07 seconds
Started Jun 23 05:47:52 PM PDT 24
Finished Jun 23 05:48:13 PM PDT 24
Peak memory 233872 kb
Host smart-103f5cbc-cbc1-447e-8cd4-a9d672069edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627788751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2627788751
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2587748426
Short name T600
Test name
Test status
Simulation time 9709123148 ps
CPU time 14.9 seconds
Started Jun 23 05:47:55 PM PDT 24
Finished Jun 23 05:48:11 PM PDT 24
Peak memory 233900 kb
Host smart-a9df6c2f-6592-4df4-aaf6-4f67b88c81c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587748426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2587748426
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.806663981
Short name T539
Test name
Test status
Simulation time 599401619 ps
CPU time 6.69 seconds
Started Jun 23 05:47:59 PM PDT 24
Finished Jun 23 05:48:06 PM PDT 24
Peak memory 223288 kb
Host smart-c14052c1-80de-4ccc-8da3-299c35d199a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=806663981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.806663981
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3662758810
Short name T73
Test name
Test status
Simulation time 650907394 ps
CPU time 3.53 seconds
Started Jun 23 05:47:55 PM PDT 24
Finished Jun 23 05:47:59 PM PDT 24
Peak memory 217348 kb
Host smart-6572c0c6-efed-4875-9a22-1abe1576967e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662758810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3662758810
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2312252656
Short name T299
Test name
Test status
Simulation time 5516666391 ps
CPU time 13.9 seconds
Started Jun 23 05:47:54 PM PDT 24
Finished Jun 23 05:48:09 PM PDT 24
Peak memory 217512 kb
Host smart-2c59477a-5ea1-48ea-9332-f4aff078edd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312252656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2312252656
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1397366027
Short name T793
Test name
Test status
Simulation time 21155360 ps
CPU time 0.73 seconds
Started Jun 23 05:47:51 PM PDT 24
Finished Jun 23 05:47:52 PM PDT 24
Peak memory 206564 kb
Host smart-1086b3e5-6315-4b50-b22e-0a8316776854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397366027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1397366027
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3258377538
Short name T874
Test name
Test status
Simulation time 107250541 ps
CPU time 0.84 seconds
Started Jun 23 05:47:53 PM PDT 24
Finished Jun 23 05:47:55 PM PDT 24
Peak memory 206944 kb
Host smart-fc2753eb-e106-4ef8-a207-621a82bfff51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258377538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3258377538
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.541003577
Short name T341
Test name
Test status
Simulation time 9967690603 ps
CPU time 25.95 seconds
Started Jun 23 05:47:56 PM PDT 24
Finished Jun 23 05:48:22 PM PDT 24
Peak memory 225620 kb
Host smart-06a96626-aa21-4c1f-8f76-7987f6366504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541003577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.541003577
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.500379979
Short name T513
Test name
Test status
Simulation time 31094637 ps
CPU time 0.73 seconds
Started Jun 23 05:47:59 PM PDT 24
Finished Jun 23 05:48:01 PM PDT 24
Peak memory 206300 kb
Host smart-463c9ec7-1361-403c-924b-dba04421f6af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500379979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.500379979
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3544488276
Short name T488
Test name
Test status
Simulation time 717821238 ps
CPU time 7.03 seconds
Started Jun 23 05:47:56 PM PDT 24
Finished Jun 23 05:48:03 PM PDT 24
Peak memory 233736 kb
Host smart-79ffcac2-2ff5-4483-b657-6b981c39d08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544488276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3544488276
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3603219791
Short name T759
Test name
Test status
Simulation time 15793359 ps
CPU time 0.79 seconds
Started Jun 23 05:47:58 PM PDT 24
Finished Jun 23 05:47:59 PM PDT 24
Peak memory 207812 kb
Host smart-db57ae19-399c-4de5-9f25-404f8ea32f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603219791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3603219791
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2925351146
Short name T806
Test name
Test status
Simulation time 178241530116 ps
CPU time 252.58 seconds
Started Jun 23 05:48:00 PM PDT 24
Finished Jun 23 05:52:14 PM PDT 24
Peak memory 250596 kb
Host smart-e7fa9c82-1405-4970-b95c-79ac1bb9cb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925351146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2925351146
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3955504931
Short name T204
Test name
Test status
Simulation time 188829564478 ps
CPU time 306.28 seconds
Started Jun 23 05:48:11 PM PDT 24
Finished Jun 23 05:53:18 PM PDT 24
Peak memory 274080 kb
Host smart-5739aa40-e44c-496c-800b-7e869c860657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955504931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3955504931
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2763295694
Short name T672
Test name
Test status
Simulation time 15955457233 ps
CPU time 53 seconds
Started Jun 23 05:48:11 PM PDT 24
Finished Jun 23 05:49:05 PM PDT 24
Peak memory 250380 kb
Host smart-0522cedf-c5af-4bef-a8e1-e498fb4a0339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763295694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2763295694
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3331776857
Short name T41
Test name
Test status
Simulation time 589779179 ps
CPU time 7.38 seconds
Started Jun 23 05:48:02 PM PDT 24
Finished Jun 23 05:48:11 PM PDT 24
Peak memory 225588 kb
Host smart-e3ce78b9-e27c-4815-8f5d-729521c01364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331776857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3331776857
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3199133354
Short name T397
Test name
Test status
Simulation time 1379712035 ps
CPU time 3.46 seconds
Started Jun 23 05:47:57 PM PDT 24
Finished Jun 23 05:48:01 PM PDT 24
Peak memory 225548 kb
Host smart-489caf31-40b8-4b92-94d4-96731324c91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199133354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3199133354
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3403558523
Short name T467
Test name
Test status
Simulation time 4481313301 ps
CPU time 42.66 seconds
Started Jun 23 05:47:59 PM PDT 24
Finished Jun 23 05:48:42 PM PDT 24
Peak memory 233848 kb
Host smart-95b29a6c-6241-4ff1-b6b5-929c3b8dd485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403558523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3403558523
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.541772651
Short name T623
Test name
Test status
Simulation time 2800546895 ps
CPU time 10.62 seconds
Started Jun 23 05:47:59 PM PDT 24
Finished Jun 23 05:48:10 PM PDT 24
Peak memory 233872 kb
Host smart-27b421f3-9bb0-4621-b992-4135f84e04b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541772651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.541772651
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.510826289
Short name T757
Test name
Test status
Simulation time 1782272519 ps
CPU time 10.31 seconds
Started Jun 23 05:48:10 PM PDT 24
Finished Jun 23 05:48:21 PM PDT 24
Peak memory 225504 kb
Host smart-a3ae7747-884d-465c-9ddf-690e7a5f9bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510826289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.510826289
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1822029799
Short name T112
Test name
Test status
Simulation time 1025365617 ps
CPU time 5.18 seconds
Started Jun 23 05:47:59 PM PDT 24
Finished Jun 23 05:48:05 PM PDT 24
Peak memory 223592 kb
Host smart-d6a41713-73ed-44cb-a861-658c0609eb8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1822029799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1822029799
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.4111599179
Short name T578
Test name
Test status
Simulation time 23771832601 ps
CPU time 143.69 seconds
Started Jun 23 05:48:11 PM PDT 24
Finished Jun 23 05:50:36 PM PDT 24
Peak memory 241272 kb
Host smart-e8c9a85c-df3a-4119-a87e-43d3e5cec48f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111599179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.4111599179
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3148891588
Short name T837
Test name
Test status
Simulation time 20117328 ps
CPU time 0.76 seconds
Started Jun 23 05:47:59 PM PDT 24
Finished Jun 23 05:48:01 PM PDT 24
Peak memory 206652 kb
Host smart-3dd68038-4cf0-4b33-881c-809dd4f0b372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148891588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3148891588
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.4052499219
Short name T880
Test name
Test status
Simulation time 2705176303 ps
CPU time 8.31 seconds
Started Jun 23 05:48:09 PM PDT 24
Finished Jun 23 05:48:18 PM PDT 24
Peak memory 217456 kb
Host smart-e1106e17-a539-45e4-a923-b6c33da51cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052499219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.4052499219
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.370677074
Short name T404
Test name
Test status
Simulation time 67410835 ps
CPU time 0.93 seconds
Started Jun 23 05:47:59 PM PDT 24
Finished Jun 23 05:48:01 PM PDT 24
Peak memory 208256 kb
Host smart-ae097776-c1f5-4e53-ad8d-5820ca414d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370677074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.370677074
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.560437536
Short name T532
Test name
Test status
Simulation time 335529739 ps
CPU time 1 seconds
Started Jun 23 05:47:59 PM PDT 24
Finished Jun 23 05:48:01 PM PDT 24
Peak memory 207208 kb
Host smart-7e4bbb75-26bd-4dc3-8ca1-95f76ed1f710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560437536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.560437536
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1308981544
Short name T433
Test name
Test status
Simulation time 1830567467 ps
CPU time 9.43 seconds
Started Jun 23 05:48:02 PM PDT 24
Finished Jun 23 05:48:12 PM PDT 24
Peak memory 225536 kb
Host smart-ef02cf6d-7fbf-45e0-803f-ef09df79e51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308981544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1308981544
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3965082281
Short name T61
Test name
Test status
Simulation time 28155384 ps
CPU time 0.69 seconds
Started Jun 23 05:48:03 PM PDT 24
Finished Jun 23 05:48:05 PM PDT 24
Peak memory 206304 kb
Host smart-8fa85f60-8f20-4ba2-a360-97fa8e763c61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965082281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3965082281
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2166933869
Short name T612
Test name
Test status
Simulation time 152761183 ps
CPU time 3.04 seconds
Started Jun 23 05:48:04 PM PDT 24
Finished Jun 23 05:48:07 PM PDT 24
Peak memory 225568 kb
Host smart-b42789bd-707d-4c6b-95e7-7c7e5bf3bb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166933869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2166933869
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1882444874
Short name T603
Test name
Test status
Simulation time 17993608 ps
CPU time 0.74 seconds
Started Jun 23 05:48:11 PM PDT 24
Finished Jun 23 05:48:13 PM PDT 24
Peak memory 206408 kb
Host smart-0684cbfe-9c50-4ff2-bf53-fae9f77732e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882444874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1882444874
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.244127870
Short name T291
Test name
Test status
Simulation time 17042633 ps
CPU time 0.8 seconds
Started Jun 23 05:48:05 PM PDT 24
Finished Jun 23 05:48:06 PM PDT 24
Peak memory 216872 kb
Host smart-42022866-1eed-4c02-b019-632ef931df29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244127870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.244127870
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1043965928
Short name T708
Test name
Test status
Simulation time 9662709189 ps
CPU time 52.43 seconds
Started Jun 23 05:48:06 PM PDT 24
Finished Jun 23 05:48:58 PM PDT 24
Peak memory 238912 kb
Host smart-0df822a7-3964-4d30-9bc2-9ccf2bf3fd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043965928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1043965928
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.268771813
Short name T957
Test name
Test status
Simulation time 2141780804 ps
CPU time 6.14 seconds
Started Jun 23 05:48:05 PM PDT 24
Finished Jun 23 05:48:12 PM PDT 24
Peak memory 225600 kb
Host smart-b492676a-5db5-48ca-8de8-cdbec89c2151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268771813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.268771813
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3959889357
Short name T215
Test name
Test status
Simulation time 3795124383 ps
CPU time 5.04 seconds
Started Jun 23 05:48:11 PM PDT 24
Finished Jun 23 05:48:17 PM PDT 24
Peak memory 225572 kb
Host smart-993b8d18-101c-4fa5-838e-d39b314fe60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959889357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3959889357
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.597813567
Short name T72
Test name
Test status
Simulation time 3029658672 ps
CPU time 18.66 seconds
Started Jun 23 05:47:58 PM PDT 24
Finished Jun 23 05:48:18 PM PDT 24
Peak memory 233916 kb
Host smart-c582509f-aa0d-4748-88a6-4cd7a1f21c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597813567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.597813567
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2123167806
Short name T644
Test name
Test status
Simulation time 2478805168 ps
CPU time 3.92 seconds
Started Jun 23 05:47:59 PM PDT 24
Finished Jun 23 05:48:04 PM PDT 24
Peak memory 233852 kb
Host smart-e83d77ce-0323-4cab-80a3-9158ccfb01f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123167806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2123167806
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2608542717
Short name T97
Test name
Test status
Simulation time 1055520863 ps
CPU time 3.19 seconds
Started Jun 23 05:47:57 PM PDT 24
Finished Jun 23 05:48:01 PM PDT 24
Peak memory 225484 kb
Host smart-4763bc1d-8743-455a-8672-c7990d8817d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608542717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2608542717
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1414357546
Short name T780
Test name
Test status
Simulation time 7300293199 ps
CPU time 16.04 seconds
Started Jun 23 05:48:07 PM PDT 24
Finished Jun 23 05:48:23 PM PDT 24
Peak memory 223716 kb
Host smart-1a02d0bf-6337-4e29-a5cd-a9178236f9cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1414357546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1414357546
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2961151244
Short name T235
Test name
Test status
Simulation time 95287164153 ps
CPU time 374.98 seconds
Started Jun 23 05:48:11 PM PDT 24
Finished Jun 23 05:54:26 PM PDT 24
Peak memory 266684 kb
Host smart-34cb60cf-59a1-4022-a36b-a0f803485c41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961151244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2961151244
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1783995930
Short name T873
Test name
Test status
Simulation time 1574745330 ps
CPU time 14.92 seconds
Started Jun 23 05:48:11 PM PDT 24
Finished Jun 23 05:48:27 PM PDT 24
Peak memory 217588 kb
Host smart-66ddc071-005c-497c-b45d-970c968b57fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783995930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1783995930
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1386667844
Short name T890
Test name
Test status
Simulation time 18758035815 ps
CPU time 16.82 seconds
Started Jun 23 05:48:11 PM PDT 24
Finished Jun 23 05:48:29 PM PDT 24
Peak memory 217476 kb
Host smart-970a5a92-e937-4c92-b51a-8b64f51543f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386667844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1386667844
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2698374999
Short name T801
Test name
Test status
Simulation time 709297580 ps
CPU time 4.3 seconds
Started Jun 23 05:48:11 PM PDT 24
Finished Jun 23 05:48:16 PM PDT 24
Peak memory 217428 kb
Host smart-07dcdfec-4e3f-4c16-abd2-7898213533f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698374999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2698374999
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2295466754
Short name T881
Test name
Test status
Simulation time 80813708 ps
CPU time 0.91 seconds
Started Jun 23 05:47:56 PM PDT 24
Finished Jun 23 05:47:57 PM PDT 24
Peak memory 206912 kb
Host smart-119f0957-dcab-425c-a8f2-94066bd45746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295466754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2295466754
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2306473189
Short name T240
Test name
Test status
Simulation time 917654910 ps
CPU time 3.54 seconds
Started Jun 23 05:48:02 PM PDT 24
Finished Jun 23 05:48:07 PM PDT 24
Peak memory 225500 kb
Host smart-82fb8a87-11cf-4f52-a2eb-a4854a13d6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306473189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2306473189
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.109234065
Short name T407
Test name
Test status
Simulation time 21351673 ps
CPU time 0.78 seconds
Started Jun 23 05:48:05 PM PDT 24
Finished Jun 23 05:48:07 PM PDT 24
Peak memory 206212 kb
Host smart-509b50f0-0699-4acc-b444-f39dbcc19f8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109234065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.109234065
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3694338341
Short name T537
Test name
Test status
Simulation time 101243726 ps
CPU time 2.1 seconds
Started Jun 23 05:48:05 PM PDT 24
Finished Jun 23 05:48:07 PM PDT 24
Peak memory 225248 kb
Host smart-321ae572-ed48-4c3f-9466-1ff18728b355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694338341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3694338341
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3458028968
Short name T556
Test name
Test status
Simulation time 36396360 ps
CPU time 0.75 seconds
Started Jun 23 05:48:11 PM PDT 24
Finished Jun 23 05:48:12 PM PDT 24
Peak memory 207792 kb
Host smart-aeff12fe-110e-425d-95a3-89657f9b9f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458028968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3458028968
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.237130548
Short name T43
Test name
Test status
Simulation time 4171193770 ps
CPU time 32.63 seconds
Started Jun 23 05:48:10 PM PDT 24
Finished Jun 23 05:48:44 PM PDT 24
Peak memory 235904 kb
Host smart-5d56679f-cf39-4dd3-a99e-c450942accf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237130548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.237130548
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.4266836101
Short name T131
Test name
Test status
Simulation time 32386090670 ps
CPU time 297.47 seconds
Started Jun 23 05:48:02 PM PDT 24
Finished Jun 23 05:53:00 PM PDT 24
Peak memory 242108 kb
Host smart-eafc4d85-7317-407d-a9c4-7f0f1ff3392e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266836101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.4266836101
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2781814294
Short name T71
Test name
Test status
Simulation time 14329972651 ps
CPU time 115.6 seconds
Started Jun 23 05:48:04 PM PDT 24
Finished Jun 23 05:50:00 PM PDT 24
Peak memory 251448 kb
Host smart-e6d5e501-3b99-4a0b-bdeb-e4b4b167b391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781814294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2781814294
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.769754281
Short name T750
Test name
Test status
Simulation time 305724795 ps
CPU time 6.72 seconds
Started Jun 23 05:48:08 PM PDT 24
Finished Jun 23 05:48:15 PM PDT 24
Peak memory 225552 kb
Host smart-a66abb4d-2821-4775-b5cb-221a63f737d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769754281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.769754281
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1239837316
Short name T828
Test name
Test status
Simulation time 628767146 ps
CPU time 3.07 seconds
Started Jun 23 05:48:03 PM PDT 24
Finished Jun 23 05:48:07 PM PDT 24
Peak memory 233800 kb
Host smart-ea71ee15-c0d6-47ee-9a14-9bd393e765bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239837316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1239837316
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.4206870433
Short name T517
Test name
Test status
Simulation time 7891726776 ps
CPU time 103.22 seconds
Started Jun 23 05:48:02 PM PDT 24
Finished Jun 23 05:49:46 PM PDT 24
Peak memory 225608 kb
Host smart-37f731f1-2e6c-4db8-9bea-9c30863dabe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206870433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.4206870433
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2431740961
Short name T378
Test name
Test status
Simulation time 1722881150 ps
CPU time 5.08 seconds
Started Jun 23 05:48:02 PM PDT 24
Finished Jun 23 05:48:08 PM PDT 24
Peak memory 233704 kb
Host smart-419d765f-52e3-41d1-8e6c-9c34a947ccea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431740961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2431740961
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.871218269
Short name T182
Test name
Test status
Simulation time 1864547883 ps
CPU time 8.25 seconds
Started Jun 23 05:48:03 PM PDT 24
Finished Jun 23 05:48:12 PM PDT 24
Peak memory 233784 kb
Host smart-01b339ae-f224-4c1b-839e-fc3bcd4816b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871218269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.871218269
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1839760527
Short name T937
Test name
Test status
Simulation time 2429015158 ps
CPU time 13.74 seconds
Started Jun 23 05:48:11 PM PDT 24
Finished Jun 23 05:48:26 PM PDT 24
Peak memory 224060 kb
Host smart-0ef7ec64-d853-4b54-ad52-fb0372c8c3f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1839760527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1839760527
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.875841245
Short name T820
Test name
Test status
Simulation time 339726197750 ps
CPU time 566.06 seconds
Started Jun 23 05:48:04 PM PDT 24
Finished Jun 23 05:57:30 PM PDT 24
Peak memory 261244 kb
Host smart-cea47449-2888-44e8-a4f9-4b44ac036037
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875841245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.875841245
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2000790876
Short name T281
Test name
Test status
Simulation time 11967920688 ps
CPU time 28.65 seconds
Started Jun 23 05:48:05 PM PDT 24
Finished Jun 23 05:48:34 PM PDT 24
Peak memory 217520 kb
Host smart-9f774a62-0c00-41be-ac37-47eb338ebb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000790876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2000790876
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3106404692
Short name T468
Test name
Test status
Simulation time 235130437 ps
CPU time 1.97 seconds
Started Jun 23 05:48:04 PM PDT 24
Finished Jun 23 05:48:06 PM PDT 24
Peak memory 208832 kb
Host smart-bcaf8c29-e319-48ba-8cef-88a95fcfeb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106404692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3106404692
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.565240586
Short name T129
Test name
Test status
Simulation time 29454394 ps
CPU time 0.93 seconds
Started Jun 23 05:48:02 PM PDT 24
Finished Jun 23 05:48:04 PM PDT 24
Peak memory 207948 kb
Host smart-c0d4e4a5-ad53-41c6-92d7-41ce0d4b2694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565240586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.565240586
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.967852623
Short name T958
Test name
Test status
Simulation time 65682768 ps
CPU time 0.88 seconds
Started Jun 23 05:48:05 PM PDT 24
Finished Jun 23 05:48:06 PM PDT 24
Peak memory 206916 kb
Host smart-9a2e4cb2-b555-4669-aa30-f567f45b897d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967852623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.967852623
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3123155463
Short name T624
Test name
Test status
Simulation time 4893441176 ps
CPU time 6.02 seconds
Started Jun 23 05:48:07 PM PDT 24
Finished Jun 23 05:48:14 PM PDT 24
Peak memory 225720 kb
Host smart-2def688d-11a6-4c1f-93fe-0aead0cdd8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123155463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3123155463
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.142341766
Short name T845
Test name
Test status
Simulation time 14523133 ps
CPU time 0.77 seconds
Started Jun 23 05:48:08 PM PDT 24
Finished Jun 23 05:48:09 PM PDT 24
Peak memory 206272 kb
Host smart-c3134cdc-ee53-4213-ac36-a5513c46435a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142341766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.142341766
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1120861882
Short name T166
Test name
Test status
Simulation time 786219654 ps
CPU time 7.94 seconds
Started Jun 23 05:48:10 PM PDT 24
Finished Jun 23 05:48:19 PM PDT 24
Peak memory 233768 kb
Host smart-3a605dbf-d7ce-403a-870c-6d713c3550c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120861882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1120861882
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3447189822
Short name T69
Test name
Test status
Simulation time 69861054 ps
CPU time 0.81 seconds
Started Jun 23 05:48:06 PM PDT 24
Finished Jun 23 05:48:08 PM PDT 24
Peak memory 207516 kb
Host smart-3257006d-b060-43f1-b762-a6fc26776712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447189822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3447189822
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3130343452
Short name T170
Test name
Test status
Simulation time 24745193269 ps
CPU time 158.21 seconds
Started Jun 23 05:48:07 PM PDT 24
Finished Jun 23 05:50:46 PM PDT 24
Peak memory 256596 kb
Host smart-a705a8a9-b043-4c3b-8727-91d07bf2d52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130343452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3130343452
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1170964561
Short name T220
Test name
Test status
Simulation time 8224352877 ps
CPU time 113.12 seconds
Started Jun 23 05:48:08 PM PDT 24
Finished Jun 23 05:50:02 PM PDT 24
Peak memory 251508 kb
Host smart-e17fb9e0-a4bc-44c6-af1d-002209e1be97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170964561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1170964561
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3766754697
Short name T502
Test name
Test status
Simulation time 29737420939 ps
CPU time 303.11 seconds
Started Jun 23 05:48:06 PM PDT 24
Finished Jun 23 05:53:10 PM PDT 24
Peak memory 251336 kb
Host smart-b418fd64-0f65-48dc-ac53-b16d7a6cb726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766754697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3766754697
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1473121718
Short name T684
Test name
Test status
Simulation time 6494260252 ps
CPU time 10.71 seconds
Started Jun 23 05:48:13 PM PDT 24
Finished Jun 23 05:48:24 PM PDT 24
Peak memory 225728 kb
Host smart-20cd62c9-caa3-4ef3-bb9b-21754c136330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473121718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1473121718
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.481521065
Short name T749
Test name
Test status
Simulation time 17840546067 ps
CPU time 28.86 seconds
Started Jun 23 05:48:10 PM PDT 24
Finished Jun 23 05:48:40 PM PDT 24
Peak memory 225664 kb
Host smart-3b405b75-0f38-4a69-81f9-cdaaf9e9654f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481521065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.481521065
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3061762772
Short name T878
Test name
Test status
Simulation time 4644942683 ps
CPU time 14.46 seconds
Started Jun 23 05:48:06 PM PDT 24
Finished Jun 23 05:48:21 PM PDT 24
Peak memory 234080 kb
Host smart-df1fdb3a-b9de-405d-a167-fc187a4a4263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061762772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3061762772
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.512750838
Short name T902
Test name
Test status
Simulation time 3423672847 ps
CPU time 15.57 seconds
Started Jun 23 05:48:07 PM PDT 24
Finished Jun 23 05:48:23 PM PDT 24
Peak memory 242004 kb
Host smart-0047e70d-e689-4e41-a37e-3567fe4df3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512750838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.512750838
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.136804914
Short name T907
Test name
Test status
Simulation time 7577523208 ps
CPU time 19.43 seconds
Started Jun 23 05:48:14 PM PDT 24
Finished Jun 23 05:48:34 PM PDT 24
Peak memory 220532 kb
Host smart-3ec5ce1a-8c3d-448d-9812-505601f81491
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=136804914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.136804914
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1167716411
Short name T917
Test name
Test status
Simulation time 229807819396 ps
CPU time 611.56 seconds
Started Jun 23 05:48:12 PM PDT 24
Finished Jun 23 05:58:24 PM PDT 24
Peak memory 269896 kb
Host smart-35f58b70-3321-4d4b-ad54-83dd5eaafc0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167716411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1167716411
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.820198465
Short name T649
Test name
Test status
Simulation time 999120183 ps
CPU time 10.68 seconds
Started Jun 23 05:48:02 PM PDT 24
Finished Jun 23 05:48:14 PM PDT 24
Peak memory 217328 kb
Host smart-80303b4c-b950-4915-9e66-0264e3ed1562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820198465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.820198465
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3365265768
Short name T721
Test name
Test status
Simulation time 9888656025 ps
CPU time 14.56 seconds
Started Jun 23 05:48:02 PM PDT 24
Finished Jun 23 05:48:18 PM PDT 24
Peak memory 217424 kb
Host smart-55a5884d-be47-4e0d-8798-1978f3904af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365265768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3365265768
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2721100935
Short name T711
Test name
Test status
Simulation time 547535788 ps
CPU time 2.17 seconds
Started Jun 23 05:48:12 PM PDT 24
Finished Jun 23 05:48:15 PM PDT 24
Peak memory 209364 kb
Host smart-552e1204-95be-4d3f-b121-39c828d64855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721100935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2721100935
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1566403243
Short name T817
Test name
Test status
Simulation time 33195231 ps
CPU time 0.82 seconds
Started Jun 23 05:48:07 PM PDT 24
Finished Jun 23 05:48:08 PM PDT 24
Peak memory 206920 kb
Host smart-864d9c8e-de1a-4bb3-96da-fd3e50cb45d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566403243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1566403243
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1943912653
Short name T832
Test name
Test status
Simulation time 2682522939 ps
CPU time 4.46 seconds
Started Jun 23 05:48:11 PM PDT 24
Finished Jun 23 05:48:16 PM PDT 24
Peak memory 225720 kb
Host smart-7e732e40-0304-46b5-969d-6d8a62f98fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943912653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1943912653
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2650671348
Short name T770
Test name
Test status
Simulation time 53009837 ps
CPU time 0.72 seconds
Started Jun 23 05:48:15 PM PDT 24
Finished Jun 23 05:48:16 PM PDT 24
Peak memory 206660 kb
Host smart-4828f263-9808-4b0e-bfd0-9f34bb83deda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650671348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2650671348
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2599015837
Short name T507
Test name
Test status
Simulation time 522770891 ps
CPU time 3.02 seconds
Started Jun 23 05:48:08 PM PDT 24
Finished Jun 23 05:48:12 PM PDT 24
Peak memory 225472 kb
Host smart-0b6b2b3b-7e9b-47c3-bcac-cfcf9ceaec21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599015837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2599015837
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2212986631
Short name T587
Test name
Test status
Simulation time 55144749 ps
CPU time 0.78 seconds
Started Jun 23 05:48:11 PM PDT 24
Finished Jun 23 05:48:13 PM PDT 24
Peak memory 207780 kb
Host smart-fe5b007e-2e4a-47a6-a8ca-b89a0c7b75ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212986631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2212986631
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1755570737
Short name T737
Test name
Test status
Simulation time 57106871 ps
CPU time 0.96 seconds
Started Jun 23 05:48:10 PM PDT 24
Finished Jun 23 05:48:11 PM PDT 24
Peak memory 217064 kb
Host smart-3689a3c3-fa78-41fc-8c34-384ff9aecc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755570737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1755570737
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1939111501
Short name T567
Test name
Test status
Simulation time 753938311 ps
CPU time 20.06 seconds
Started Jun 23 05:48:08 PM PDT 24
Finished Jun 23 05:48:29 PM PDT 24
Peak memory 242004 kb
Host smart-7ccdfd4e-41ef-4789-8457-0faf749f7f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939111501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1939111501
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.4071941054
Short name T645
Test name
Test status
Simulation time 1572883637 ps
CPU time 14.81 seconds
Started Jun 23 05:48:13 PM PDT 24
Finished Jun 23 05:48:28 PM PDT 24
Peak memory 225652 kb
Host smart-56ea56e6-b60e-4013-a35c-ff1e4bff3e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071941054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.4071941054
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1590954969
Short name T145
Test name
Test status
Simulation time 177279249 ps
CPU time 4.21 seconds
Started Jun 23 05:48:11 PM PDT 24
Finished Jun 23 05:48:16 PM PDT 24
Peak memory 233808 kb
Host smart-565af4aa-2871-4b0c-9672-d3e5904e3fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590954969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1590954969
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2289336579
Short name T722
Test name
Test status
Simulation time 349984475 ps
CPU time 5.49 seconds
Started Jun 23 05:48:14 PM PDT 24
Finished Jun 23 05:48:20 PM PDT 24
Peak memory 233808 kb
Host smart-c0021e83-c7fb-4c9e-af32-34c31bd0a203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289336579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2289336579
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3828945739
Short name T322
Test name
Test status
Simulation time 26864053493 ps
CPU time 85.75 seconds
Started Jun 23 05:48:09 PM PDT 24
Finished Jun 23 05:49:35 PM PDT 24
Peak memory 234168 kb
Host smart-d74089da-8b8a-4fc2-8c1d-a6b4b3f3bc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828945739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3828945739
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.276697734
Short name T84
Test name
Test status
Simulation time 4214237760 ps
CPU time 9.61 seconds
Started Jun 23 05:48:12 PM PDT 24
Finished Jun 23 05:48:22 PM PDT 24
Peak memory 233856 kb
Host smart-ba1a795e-a78e-4a87-8728-530151e44a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276697734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.276697734
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3042992285
Short name T744
Test name
Test status
Simulation time 311835852 ps
CPU time 3.65 seconds
Started Jun 23 05:48:11 PM PDT 24
Finished Jun 23 05:48:15 PM PDT 24
Peak memory 225488 kb
Host smart-ba518fbf-711b-434a-b438-a91f15e564ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042992285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3042992285
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.926206625
Short name T325
Test name
Test status
Simulation time 1363461715 ps
CPU time 5.1 seconds
Started Jun 23 05:48:06 PM PDT 24
Finished Jun 23 05:48:12 PM PDT 24
Peak memory 220304 kb
Host smart-3cbf3cde-ae35-4568-99c5-35c487fb536d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=926206625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.926206625
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.610796233
Short name T6
Test name
Test status
Simulation time 39351781 ps
CPU time 0.98 seconds
Started Jun 23 05:48:24 PM PDT 24
Finished Jun 23 05:48:25 PM PDT 24
Peak memory 208080 kb
Host smart-f30b2e11-6de9-474c-8dca-017501d1a79f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610796233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.610796233
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.178628023
Short name T472
Test name
Test status
Simulation time 4655400049 ps
CPU time 32.51 seconds
Started Jun 23 05:48:10 PM PDT 24
Finished Jun 23 05:48:43 PM PDT 24
Peak memory 217544 kb
Host smart-9039f490-b538-439e-85ec-8bd05a43d098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178628023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.178628023
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3016768370
Short name T540
Test name
Test status
Simulation time 3766884497 ps
CPU time 7.68 seconds
Started Jun 23 05:48:06 PM PDT 24
Finished Jun 23 05:48:14 PM PDT 24
Peak memory 217540 kb
Host smart-446574e5-46cb-4b00-a51d-e80dc1cc4d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016768370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3016768370
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3522540306
Short name T25
Test name
Test status
Simulation time 25574731 ps
CPU time 0.77 seconds
Started Jun 23 05:48:12 PM PDT 24
Finished Jun 23 05:48:13 PM PDT 24
Peak memory 206884 kb
Host smart-d65ad36e-d2a8-4ec2-a6d0-49059cb623f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522540306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3522540306
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3019919511
Short name T702
Test name
Test status
Simulation time 269196694 ps
CPU time 0.92 seconds
Started Jun 23 05:48:09 PM PDT 24
Finished Jun 23 05:48:11 PM PDT 24
Peak memory 206904 kb
Host smart-21bed98c-41cd-482f-a839-f8679c7ed1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019919511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3019919511
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2366463256
Short name T379
Test name
Test status
Simulation time 416895465 ps
CPU time 3.78 seconds
Started Jun 23 05:48:07 PM PDT 24
Finished Jun 23 05:48:12 PM PDT 24
Peak memory 228964 kb
Host smart-6568c777-dc12-48ce-a042-5d5d0247e4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366463256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2366463256
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.605715093
Short name T869
Test name
Test status
Simulation time 12256711 ps
CPU time 0.75 seconds
Started Jun 23 05:48:13 PM PDT 24
Finished Jun 23 05:48:14 PM PDT 24
Peak memory 206320 kb
Host smart-74c8e4a9-fe77-4aa4-8c24-0a7abfecd202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605715093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.605715093
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.956697606
Short name T938
Test name
Test status
Simulation time 266779156 ps
CPU time 5.42 seconds
Started Jun 23 05:48:10 PM PDT 24
Finished Jun 23 05:48:16 PM PDT 24
Peak memory 233772 kb
Host smart-0061429d-be54-44c4-85c7-ec03c38c9491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956697606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.956697606
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2992506945
Short name T841
Test name
Test status
Simulation time 12723904 ps
CPU time 0.74 seconds
Started Jun 23 05:48:16 PM PDT 24
Finished Jun 23 05:48:18 PM PDT 24
Peak memory 206492 kb
Host smart-1f378f77-0375-45e7-9e6c-e10b9c7993c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992506945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2992506945
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2206200090
Short name T723
Test name
Test status
Simulation time 314980541311 ps
CPU time 198.92 seconds
Started Jun 23 05:48:15 PM PDT 24
Finished Jun 23 05:51:34 PM PDT 24
Peak memory 269016 kb
Host smart-d6c51963-db59-4f91-a029-1bdad7f76bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206200090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2206200090
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1772757188
Short name T610
Test name
Test status
Simulation time 7278178427 ps
CPU time 78.95 seconds
Started Jun 23 05:48:24 PM PDT 24
Finished Jun 23 05:49:43 PM PDT 24
Peak memory 257340 kb
Host smart-1df08573-5931-49e3-8701-92ca2e40ef57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772757188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1772757188
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.4020244601
Short name T428
Test name
Test status
Simulation time 3872393862 ps
CPU time 14.79 seconds
Started Jun 23 05:48:24 PM PDT 24
Finished Jun 23 05:48:40 PM PDT 24
Peak memory 233860 kb
Host smart-d1f1a866-a8cc-4000-9790-0a3930db5e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020244601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.4020244601
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3874149762
Short name T776
Test name
Test status
Simulation time 326591627 ps
CPU time 5.57 seconds
Started Jun 23 05:48:17 PM PDT 24
Finished Jun 23 05:48:23 PM PDT 24
Peak memory 225432 kb
Host smart-a66c4f4c-41b7-4b20-8efa-e75a325c488c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874149762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3874149762
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.370155172
Short name T172
Test name
Test status
Simulation time 4840773426 ps
CPU time 44.91 seconds
Started Jun 23 05:48:16 PM PDT 24
Finished Jun 23 05:49:02 PM PDT 24
Peak memory 234108 kb
Host smart-2e289e9d-4ca2-4fe1-9e37-47e8169f3a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370155172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.370155172
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1215856852
Short name T528
Test name
Test status
Simulation time 167990340 ps
CPU time 3.91 seconds
Started Jun 23 05:48:13 PM PDT 24
Finished Jun 23 05:48:18 PM PDT 24
Peak memory 233796 kb
Host smart-d859759c-b995-4744-bb3f-0219b3067e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215856852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1215856852
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3290852471
Short name T581
Test name
Test status
Simulation time 381504769 ps
CPU time 4.77 seconds
Started Jun 23 05:48:11 PM PDT 24
Finished Jun 23 05:48:17 PM PDT 24
Peak memory 225616 kb
Host smart-97ab20df-aa4d-4930-9914-c031fe704588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290852471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3290852471
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3422296774
Short name T143
Test name
Test status
Simulation time 844839995 ps
CPU time 4.02 seconds
Started Jun 23 05:48:23 PM PDT 24
Finished Jun 23 05:48:28 PM PDT 24
Peak memory 223604 kb
Host smart-dfc4d443-6b6e-4d5c-a76b-3d6cb5154f01
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3422296774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3422296774
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3449610032
Short name T287
Test name
Test status
Simulation time 3806505047 ps
CPU time 30.33 seconds
Started Jun 23 05:48:15 PM PDT 24
Finished Jun 23 05:48:46 PM PDT 24
Peak memory 217812 kb
Host smart-760cf8a0-9a5b-487f-b6e7-96a119765cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449610032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3449610032
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1194556529
Short name T742
Test name
Test status
Simulation time 1335299948 ps
CPU time 7.1 seconds
Started Jun 23 05:48:15 PM PDT 24
Finished Jun 23 05:48:22 PM PDT 24
Peak memory 217348 kb
Host smart-8646ffb4-c5f6-456b-89f9-a75e520b61e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194556529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1194556529
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1953000183
Short name T621
Test name
Test status
Simulation time 224202658 ps
CPU time 1.33 seconds
Started Jun 23 05:48:15 PM PDT 24
Finished Jun 23 05:48:17 PM PDT 24
Peak memory 217348 kb
Host smart-5c0edaa1-a0f9-4c50-98d6-e32dad84f73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953000183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1953000183
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1565016655
Short name T405
Test name
Test status
Simulation time 370629407 ps
CPU time 0.95 seconds
Started Jun 23 05:48:15 PM PDT 24
Finished Jun 23 05:48:17 PM PDT 24
Peak memory 206896 kb
Host smart-ecf1ad89-371f-4206-ba8b-0a930927b9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565016655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1565016655
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1762872479
Short name T939
Test name
Test status
Simulation time 19648113817 ps
CPU time 10.29 seconds
Started Jun 23 05:48:13 PM PDT 24
Finished Jun 23 05:48:24 PM PDT 24
Peak memory 225628 kb
Host smart-5cb742dc-69f3-4dfa-ad8a-725876a391b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762872479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1762872479
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3661547351
Short name T305
Test name
Test status
Simulation time 12591400 ps
CPU time 0.7 seconds
Started Jun 23 05:48:15 PM PDT 24
Finished Jun 23 05:48:16 PM PDT 24
Peak memory 206328 kb
Host smart-96ac939e-6bd6-4e53-8f34-81b1f12d0c23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661547351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3661547351
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3204339773
Short name T819
Test name
Test status
Simulation time 436401010 ps
CPU time 2.67 seconds
Started Jun 23 05:48:13 PM PDT 24
Finished Jun 23 05:48:16 PM PDT 24
Peak memory 233680 kb
Host smart-9685ab48-b8d4-4817-b7a0-f71066895375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204339773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3204339773
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2851128622
Short name T23
Test name
Test status
Simulation time 106762873 ps
CPU time 0.8 seconds
Started Jun 23 05:48:10 PM PDT 24
Finished Jun 23 05:48:11 PM PDT 24
Peak memory 207472 kb
Host smart-50dc89c2-5da3-4247-80d1-95c86b04b9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851128622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2851128622
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.4253586346
Short name T160
Test name
Test status
Simulation time 216090812601 ps
CPU time 223.84 seconds
Started Jun 23 05:48:19 PM PDT 24
Finished Jun 23 05:52:04 PM PDT 24
Peak memory 250316 kb
Host smart-903345e0-149b-4875-bb1c-9b65cbda1a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253586346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.4253586346
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3194250186
Short name T572
Test name
Test status
Simulation time 325669757298 ps
CPU time 224.53 seconds
Started Jun 23 05:48:20 PM PDT 24
Finished Jun 23 05:52:05 PM PDT 24
Peak memory 257584 kb
Host smart-b365be85-7d97-45ae-9d93-1e5e8ff19c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194250186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3194250186
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1279266969
Short name T254
Test name
Test status
Simulation time 2509838989 ps
CPU time 48.09 seconds
Started Jun 23 05:48:20 PM PDT 24
Finished Jun 23 05:49:09 PM PDT 24
Peak memory 233848 kb
Host smart-f3691f98-3f82-4cb2-81dc-a8bd40d9bd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279266969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1279266969
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.636977963
Short name T680
Test name
Test status
Simulation time 1202881479 ps
CPU time 7.54 seconds
Started Jun 23 05:48:20 PM PDT 24
Finished Jun 23 05:48:28 PM PDT 24
Peak memory 241968 kb
Host smart-2798cd2d-d640-44c1-a5b3-3a626b3b2996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636977963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.636977963
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3857220079
Short name T224
Test name
Test status
Simulation time 528730425 ps
CPU time 5.83 seconds
Started Jun 23 05:48:23 PM PDT 24
Finished Jun 23 05:48:30 PM PDT 24
Peak memory 233824 kb
Host smart-4a6bbfc9-828e-4241-89b7-2230c98f9c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857220079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3857220079
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3014208149
Short name T803
Test name
Test status
Simulation time 54217390 ps
CPU time 2.54 seconds
Started Jun 23 05:48:12 PM PDT 24
Finished Jun 23 05:48:15 PM PDT 24
Peak memory 233716 kb
Host smart-ff04d0aa-b62e-40e1-a7b8-2c268b31f7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014208149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3014208149
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.592482714
Short name T670
Test name
Test status
Simulation time 657626471 ps
CPU time 7.51 seconds
Started Jun 23 05:48:16 PM PDT 24
Finished Jun 23 05:48:24 PM PDT 24
Peak memory 233684 kb
Host smart-ebb3792f-605d-46ad-960a-f296ae85e7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592482714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.592482714
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1771437467
Short name T694
Test name
Test status
Simulation time 184514238 ps
CPU time 5.37 seconds
Started Jun 23 05:48:12 PM PDT 24
Finished Jun 23 05:48:18 PM PDT 24
Peak memory 241504 kb
Host smart-9eedbd08-400f-45db-85e0-f8e1f80f5c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771437467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1771437467
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3584146912
Short name T473
Test name
Test status
Simulation time 1331157442 ps
CPU time 8.65 seconds
Started Jun 23 05:48:20 PM PDT 24
Finished Jun 23 05:48:29 PM PDT 24
Peak memory 223536 kb
Host smart-f9463084-3dd0-4281-a33d-4e4a679335d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3584146912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3584146912
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.163968142
Short name T154
Test name
Test status
Simulation time 79462953682 ps
CPU time 662.99 seconds
Started Jun 23 05:48:19 PM PDT 24
Finished Jun 23 05:59:22 PM PDT 24
Peak memory 267752 kb
Host smart-212d80a8-430c-4b8e-a023-65edf62c0e3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163968142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.163968142
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3542023150
Short name T875
Test name
Test status
Simulation time 11632224217 ps
CPU time 31.21 seconds
Started Jun 23 05:48:12 PM PDT 24
Finished Jun 23 05:48:44 PM PDT 24
Peak memory 217436 kb
Host smart-d39e6769-2ca1-4457-ab48-ea5ca83c0374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542023150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3542023150
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1016290540
Short name T430
Test name
Test status
Simulation time 1742391052 ps
CPU time 9.9 seconds
Started Jun 23 05:48:16 PM PDT 24
Finished Jun 23 05:48:27 PM PDT 24
Peak memory 217412 kb
Host smart-37855b64-875b-4eeb-b45e-113d39cc0028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016290540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1016290540
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2579215442
Short name T656
Test name
Test status
Simulation time 43378486 ps
CPU time 0.89 seconds
Started Jun 23 05:48:24 PM PDT 24
Finished Jun 23 05:48:26 PM PDT 24
Peak memory 207592 kb
Host smart-b191f047-6117-4e00-854e-7c383445cc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579215442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2579215442
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.918477866
Short name T321
Test name
Test status
Simulation time 90224588 ps
CPU time 0.85 seconds
Started Jun 23 05:48:25 PM PDT 24
Finished Jun 23 05:48:26 PM PDT 24
Peak memory 206924 kb
Host smart-9a9333bf-8b4b-4aa7-8d50-f2babea37d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918477866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.918477866
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1631142059
Short name T113
Test name
Test status
Simulation time 1046129344 ps
CPU time 2.87 seconds
Started Jun 23 05:48:10 PM PDT 24
Finished Jun 23 05:48:13 PM PDT 24
Peak memory 233776 kb
Host smart-6d7f97f0-cb49-4281-9a4c-9588ee39439e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631142059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1631142059
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2535066660
Short name T697
Test name
Test status
Simulation time 15308382 ps
CPU time 0.68 seconds
Started Jun 23 05:48:15 PM PDT 24
Finished Jun 23 05:48:17 PM PDT 24
Peak memory 206268 kb
Host smart-ca38f909-b873-4ce9-a4a3-1e370256296c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535066660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2535066660
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3749876807
Short name T374
Test name
Test status
Simulation time 137135406 ps
CPU time 4.56 seconds
Started Jun 23 05:48:16 PM PDT 24
Finished Jun 23 05:48:22 PM PDT 24
Peak memory 233772 kb
Host smart-df2faf21-b2e2-412f-920b-f9f4fc2c8612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749876807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3749876807
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.4190041047
Short name T796
Test name
Test status
Simulation time 25970483 ps
CPU time 0.75 seconds
Started Jun 23 05:48:18 PM PDT 24
Finished Jun 23 05:48:20 PM PDT 24
Peak memory 207508 kb
Host smart-6c1ecddc-10f7-4f52-b8df-ed45c64d92fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190041047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.4190041047
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2344977929
Short name T777
Test name
Test status
Simulation time 7924811088 ps
CPU time 55.52 seconds
Started Jun 23 05:48:16 PM PDT 24
Finished Jun 23 05:49:12 PM PDT 24
Peak memory 257604 kb
Host smart-8db17bae-bac2-4ec4-9f9c-7f1b0eba13f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344977929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2344977929
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3157939685
Short name T317
Test name
Test status
Simulation time 9306601550 ps
CPU time 85.42 seconds
Started Jun 23 05:48:20 PM PDT 24
Finished Jun 23 05:49:46 PM PDT 24
Peak memory 250252 kb
Host smart-36b97ad4-0194-43db-965f-90a16c10a239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157939685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3157939685
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.872087531
Short name T199
Test name
Test status
Simulation time 39151432987 ps
CPU time 415.33 seconds
Started Jun 23 05:48:23 PM PDT 24
Finished Jun 23 05:55:19 PM PDT 24
Peak memory 258140 kb
Host smart-21b604d2-d3ac-4507-8788-5e444fc14e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872087531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.872087531
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2104411986
Short name T85
Test name
Test status
Simulation time 815267213 ps
CPU time 7.45 seconds
Started Jun 23 05:48:14 PM PDT 24
Finished Jun 23 05:48:22 PM PDT 24
Peak memory 242536 kb
Host smart-c9b11c93-d340-4a77-a492-e16aa7873344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104411986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2104411986
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3878161257
Short name T210
Test name
Test status
Simulation time 11246161858 ps
CPU time 27.09 seconds
Started Jun 23 05:48:17 PM PDT 24
Finished Jun 23 05:48:45 PM PDT 24
Peak memory 233924 kb
Host smart-fcf8334d-f461-466a-a5eb-54550ec13c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878161257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3878161257
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.527010886
Short name T529
Test name
Test status
Simulation time 7024714440 ps
CPU time 5.03 seconds
Started Jun 23 05:48:16 PM PDT 24
Finished Jun 23 05:48:21 PM PDT 24
Peak memory 225608 kb
Host smart-96942ce3-73cd-4c0d-a9c1-181dbef074a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527010886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.527010886
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1714722509
Short name T232
Test name
Test status
Simulation time 5281604962 ps
CPU time 12.75 seconds
Started Jun 23 05:48:19 PM PDT 24
Finished Jun 23 05:48:32 PM PDT 24
Peak memory 234904 kb
Host smart-a82e0d32-847c-4240-b1e3-e5a4994766b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714722509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1714722509
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.614738090
Short name T44
Test name
Test status
Simulation time 120783528475 ps
CPU time 43.1 seconds
Started Jun 23 05:48:20 PM PDT 24
Finished Jun 23 05:49:04 PM PDT 24
Peak memory 250232 kb
Host smart-4dc542d2-b280-4de1-863a-d31824b11c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614738090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.614738090
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.4160151256
Short name T618
Test name
Test status
Simulation time 117668731 ps
CPU time 3.91 seconds
Started Jun 23 05:48:20 PM PDT 24
Finished Jun 23 05:48:25 PM PDT 24
Peak memory 220668 kb
Host smart-0cb368e7-af6b-433b-988d-578695184996
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4160151256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.4160151256
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1179619803
Short name T922
Test name
Test status
Simulation time 31527675147 ps
CPU time 155.83 seconds
Started Jun 23 05:48:20 PM PDT 24
Finished Jun 23 05:50:57 PM PDT 24
Peak memory 249072 kb
Host smart-7709274a-2596-4990-b4f4-d3061e5b1dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179619803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1179619803
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2329640476
Short name T282
Test name
Test status
Simulation time 681575343 ps
CPU time 11.16 seconds
Started Jun 23 05:48:16 PM PDT 24
Finished Jun 23 05:48:28 PM PDT 24
Peak memory 217384 kb
Host smart-adad938c-8abf-4db2-9324-b75a87eabe83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329640476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2329640476
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.885110923
Short name T419
Test name
Test status
Simulation time 38520870515 ps
CPU time 8.67 seconds
Started Jun 23 05:48:17 PM PDT 24
Finished Jun 23 05:48:26 PM PDT 24
Peak memory 217436 kb
Host smart-42f20a83-733c-44eb-8f45-32d396b6301d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885110923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.885110923
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1708245718
Short name T297
Test name
Test status
Simulation time 2309763705 ps
CPU time 5.62 seconds
Started Jun 23 05:48:18 PM PDT 24
Finished Jun 23 05:48:24 PM PDT 24
Peak memory 217532 kb
Host smart-38225330-dd26-461e-8f59-e41a774c17ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708245718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1708245718
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.4068598814
Short name T531
Test name
Test status
Simulation time 20378969 ps
CPU time 0.81 seconds
Started Jun 23 05:48:16 PM PDT 24
Finished Jun 23 05:48:18 PM PDT 24
Peak memory 206904 kb
Host smart-652fcf21-3fa4-41c9-b769-21bd99049074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068598814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.4068598814
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2520785944
Short name T188
Test name
Test status
Simulation time 12514664687 ps
CPU time 16.29 seconds
Started Jun 23 05:48:19 PM PDT 24
Finished Jun 23 05:48:36 PM PDT 24
Peak memory 233852 kb
Host smart-b41baf08-5a97-4dcc-bc29-876e5e68cff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520785944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2520785944
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4101952921
Short name T746
Test name
Test status
Simulation time 12093449 ps
CPU time 0.72 seconds
Started Jun 23 05:48:24 PM PDT 24
Finished Jun 23 05:48:26 PM PDT 24
Peak memory 206340 kb
Host smart-713b9517-a0ff-4125-98c3-cd2425c35475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101952921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4101952921
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.447649317
Short name T87
Test name
Test status
Simulation time 2088562014 ps
CPU time 20.06 seconds
Started Jun 23 05:48:23 PM PDT 24
Finished Jun 23 05:48:44 PM PDT 24
Peak memory 225592 kb
Host smart-dcbb8f07-a2c9-47e9-90ee-f3b502ca38be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447649317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.447649317
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3176130734
Short name T800
Test name
Test status
Simulation time 68589525 ps
CPU time 0.81 seconds
Started Jun 23 05:48:22 PM PDT 24
Finished Jun 23 05:48:24 PM PDT 24
Peak memory 207828 kb
Host smart-1705263c-2335-4f4b-9e43-9bc1e5b00ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176130734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3176130734
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2562621241
Short name T38
Test name
Test status
Simulation time 34634934678 ps
CPU time 238.32 seconds
Started Jun 23 05:48:20 PM PDT 24
Finished Jun 23 05:52:19 PM PDT 24
Peak memory 251320 kb
Host smart-3f5abee7-2f67-45c7-83a0-a56136ba1656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562621241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2562621241
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.4292220646
Short name T698
Test name
Test status
Simulation time 7040621777 ps
CPU time 56.56 seconds
Started Jun 23 05:48:20 PM PDT 24
Finished Jun 23 05:49:17 PM PDT 24
Peak memory 250260 kb
Host smart-2ce07fa9-9923-415a-af1c-d3d870a01672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292220646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.4292220646
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1405717820
Short name T263
Test name
Test status
Simulation time 71054034138 ps
CPU time 118.27 seconds
Started Jun 23 05:48:21 PM PDT 24
Finished Jun 23 05:50:19 PM PDT 24
Peak memory 234000 kb
Host smart-b4e074bc-1a9f-4e82-af81-ab8b06347643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405717820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1405717820
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2202809248
Short name T671
Test name
Test status
Simulation time 704672194 ps
CPU time 10.63 seconds
Started Jun 23 05:48:23 PM PDT 24
Finished Jun 23 05:48:34 PM PDT 24
Peak memory 240288 kb
Host smart-6fbeba7a-7713-4d62-b1fb-99e7f711ac1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202809248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2202809248
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.165346524
Short name T861
Test name
Test status
Simulation time 331714059 ps
CPU time 4.08 seconds
Started Jun 23 05:48:23 PM PDT 24
Finished Jun 23 05:48:27 PM PDT 24
Peak memory 225528 kb
Host smart-451ddc01-9c2e-469b-a1fc-4234e43ecc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165346524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.165346524
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3693893483
Short name T740
Test name
Test status
Simulation time 5229727901 ps
CPU time 13.78 seconds
Started Jun 23 05:48:22 PM PDT 24
Finished Jun 23 05:48:36 PM PDT 24
Peak memory 233912 kb
Host smart-f6b84959-6234-47f9-a72d-e466f0b8219b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693893483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3693893483
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2542985574
Short name T816
Test name
Test status
Simulation time 11132595082 ps
CPU time 10.04 seconds
Started Jun 23 05:48:22 PM PDT 24
Finished Jun 23 05:48:32 PM PDT 24
Peak memory 225724 kb
Host smart-7d660d1e-e4d0-4a6a-9f66-253a7efce780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542985574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2542985574
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2274048324
Short name T598
Test name
Test status
Simulation time 30304335436 ps
CPU time 10.65 seconds
Started Jun 23 05:48:21 PM PDT 24
Finished Jun 23 05:48:32 PM PDT 24
Peak memory 241900 kb
Host smart-15cc600e-2479-4a32-8de3-5bdf7ce5afdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274048324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2274048324
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.4104122732
Short name T58
Test name
Test status
Simulation time 2657919990 ps
CPU time 6.81 seconds
Started Jun 23 05:48:23 PM PDT 24
Finished Jun 23 05:48:30 PM PDT 24
Peak memory 222212 kb
Host smart-80ed8934-7db4-48bc-90c6-1230d354dd41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4104122732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.4104122732
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2864477567
Short name T659
Test name
Test status
Simulation time 59633455179 ps
CPU time 242.64 seconds
Started Jun 23 05:48:20 PM PDT 24
Finished Jun 23 05:52:23 PM PDT 24
Peak memory 258560 kb
Host smart-8c7a23f4-b157-4116-b029-4573289b41a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864477567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2864477567
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3904237674
Short name T348
Test name
Test status
Simulation time 3332149459 ps
CPU time 13.14 seconds
Started Jun 23 05:48:22 PM PDT 24
Finished Jun 23 05:48:36 PM PDT 24
Peak memory 217436 kb
Host smart-57877a33-8468-43f0-aa15-a4d5e7b875b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904237674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3904237674
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2239182067
Short name T336
Test name
Test status
Simulation time 48011582652 ps
CPU time 9.55 seconds
Started Jun 23 05:48:21 PM PDT 24
Finished Jun 23 05:48:31 PM PDT 24
Peak memory 217408 kb
Host smart-085abf0c-768c-42b4-929f-457dc15ad92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239182067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2239182067
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3502398844
Short name T294
Test name
Test status
Simulation time 88354207 ps
CPU time 2.73 seconds
Started Jun 23 05:48:23 PM PDT 24
Finished Jun 23 05:48:26 PM PDT 24
Peak memory 217412 kb
Host smart-2dd95d00-3476-4847-90e2-7176cc2338ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502398844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3502398844
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.901779002
Short name T648
Test name
Test status
Simulation time 35871451 ps
CPU time 0.69 seconds
Started Jun 23 05:48:21 PM PDT 24
Finished Jun 23 05:48:22 PM PDT 24
Peak memory 206820 kb
Host smart-37592e4b-04d1-4769-b9b2-53511f761b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901779002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.901779002
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2752527914
Short name T886
Test name
Test status
Simulation time 112643964 ps
CPU time 2.31 seconds
Started Jun 23 05:48:22 PM PDT 24
Finished Jun 23 05:48:25 PM PDT 24
Peak memory 223984 kb
Host smart-9a9cac39-d465-4bb6-94de-49fa2f7d0caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752527914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2752527914
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3019027929
Short name T59
Test name
Test status
Simulation time 27120738 ps
CPU time 0.78 seconds
Started Jun 23 05:46:18 PM PDT 24
Finished Jun 23 05:46:19 PM PDT 24
Peak memory 206336 kb
Host smart-d6efa73f-70d1-44e3-8043-614966a7ae55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019027929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
019027929
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2454035502
Short name T924
Test name
Test status
Simulation time 443058928 ps
CPU time 5.67 seconds
Started Jun 23 05:46:18 PM PDT 24
Finished Jun 23 05:46:24 PM PDT 24
Peak memory 225532 kb
Host smart-1bc0535d-9553-4dca-a075-967e0726abd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454035502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2454035502
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.680971313
Short name T651
Test name
Test status
Simulation time 27369780 ps
CPU time 0.75 seconds
Started Jun 23 05:46:14 PM PDT 24
Finished Jun 23 05:46:15 PM PDT 24
Peak memory 207840 kb
Host smart-b6751a13-5576-4724-abf0-1ba54b7bf89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680971313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.680971313
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3418658792
Short name T558
Test name
Test status
Simulation time 26452611429 ps
CPU time 79.8 seconds
Started Jun 23 05:46:15 PM PDT 24
Finished Jun 23 05:47:36 PM PDT 24
Peak memory 242156 kb
Host smart-3ed27677-f9d7-4f38-a1eb-1dd7faf097da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418658792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3418658792
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.4108713125
Short name T261
Test name
Test status
Simulation time 99070295859 ps
CPU time 143.1 seconds
Started Jun 23 05:46:17 PM PDT 24
Finished Jun 23 05:48:41 PM PDT 24
Peak memory 252556 kb
Host smart-8fa8fd7c-88b1-4310-b610-1a22cb902c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108713125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.4108713125
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1698436187
Short name T274
Test name
Test status
Simulation time 789566708 ps
CPU time 19.22 seconds
Started Jun 23 05:46:17 PM PDT 24
Finished Jun 23 05:46:37 PM PDT 24
Peak memory 235340 kb
Host smart-c8b63ca2-7ddb-4790-8aa7-ed8e0342cb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698436187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1698436187
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1965835400
Short name T533
Test name
Test status
Simulation time 498616591 ps
CPU time 3.86 seconds
Started Jun 23 05:46:15 PM PDT 24
Finished Jun 23 05:46:20 PM PDT 24
Peak memory 233772 kb
Host smart-b00cc25e-4aa9-48af-b2cb-31de9aaa8007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965835400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1965835400
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3762635658
Short name T536
Test name
Test status
Simulation time 16665949346 ps
CPU time 28.46 seconds
Started Jun 23 05:46:18 PM PDT 24
Finished Jun 23 05:46:47 PM PDT 24
Peak memory 241640 kb
Host smart-a7ddd9bf-6cb7-4ce2-bbba-4bfa25481936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762635658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3762635658
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.4147066225
Short name T351
Test name
Test status
Simulation time 33431423 ps
CPU time 1.1 seconds
Started Jun 23 05:46:13 PM PDT 24
Finished Jun 23 05:46:14 PM PDT 24
Peak memory 217644 kb
Host smart-7d0fd8ca-6919-4642-a982-feb809e015c4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147066225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.4147066225
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3558361409
Short name T929
Test name
Test status
Simulation time 2065440436 ps
CPU time 7.57 seconds
Started Jun 23 05:46:13 PM PDT 24
Finished Jun 23 05:46:21 PM PDT 24
Peak memory 225536 kb
Host smart-fbab5f8e-fd60-49d1-9422-17507fe84797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558361409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3558361409
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2980716299
Short name T197
Test name
Test status
Simulation time 4327443442 ps
CPU time 9.78 seconds
Started Jun 23 05:46:15 PM PDT 24
Finished Jun 23 05:46:25 PM PDT 24
Peak memory 233888 kb
Host smart-33cd7d0b-52f7-4bbc-9ff2-4a73ed09b17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980716299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2980716299
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3719592959
Short name T512
Test name
Test status
Simulation time 1188107097 ps
CPU time 9.73 seconds
Started Jun 23 05:46:14 PM PDT 24
Finished Jun 23 05:46:25 PM PDT 24
Peak memory 219852 kb
Host smart-92741317-5bb9-4a19-988e-41fe17e56d7a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3719592959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3719592959
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2291850806
Short name T66
Test name
Test status
Simulation time 57344804 ps
CPU time 1.08 seconds
Started Jun 23 05:46:16 PM PDT 24
Finished Jun 23 05:46:18 PM PDT 24
Peak memory 235876 kb
Host smart-f918f25f-e84a-4cd8-bf8c-72018e94cb0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291850806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2291850806
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2156636749
Short name T601
Test name
Test status
Simulation time 134234835 ps
CPU time 0.95 seconds
Started Jun 23 05:46:19 PM PDT 24
Finished Jun 23 05:46:20 PM PDT 24
Peak memory 207720 kb
Host smart-82c706e6-10eb-45e6-8ec4-31abd278baaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156636749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2156636749
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.4119585051
Short name T416
Test name
Test status
Simulation time 2913469716 ps
CPU time 5.6 seconds
Started Jun 23 05:46:17 PM PDT 24
Finished Jun 23 05:46:23 PM PDT 24
Peak memory 217888 kb
Host smart-70c602e8-60de-4ac4-83c9-aa5acfc49148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119585051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.4119585051
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1155875662
Short name T427
Test name
Test status
Simulation time 19204740953 ps
CPU time 14.84 seconds
Started Jun 23 05:46:16 PM PDT 24
Finished Jun 23 05:46:32 PM PDT 24
Peak memory 217540 kb
Host smart-c7662cc4-110b-408a-887c-ba37b478b945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155875662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1155875662
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.879635488
Short name T893
Test name
Test status
Simulation time 17862981 ps
CPU time 0.81 seconds
Started Jun 23 05:46:15 PM PDT 24
Finished Jun 23 05:46:17 PM PDT 24
Peak memory 207696 kb
Host smart-b2638145-7647-4207-b561-42a070b130d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879635488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.879635488
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3199564617
Short name T479
Test name
Test status
Simulation time 21089239 ps
CPU time 0.71 seconds
Started Jun 23 05:46:16 PM PDT 24
Finished Jun 23 05:46:17 PM PDT 24
Peak memory 206908 kb
Host smart-777a1f71-7faa-4397-8a5c-0ebdef0eb5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199564617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3199564617
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2506342026
Short name T178
Test name
Test status
Simulation time 8216568300 ps
CPU time 8.11 seconds
Started Jun 23 05:46:18 PM PDT 24
Finished Jun 23 05:46:27 PM PDT 24
Peak memory 225716 kb
Host smart-af09ad19-34cb-4f85-bb96-d9cf69bde577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506342026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2506342026
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2860454516
Short name T515
Test name
Test status
Simulation time 14030618 ps
CPU time 0.79 seconds
Started Jun 23 05:48:30 PM PDT 24
Finished Jun 23 05:48:32 PM PDT 24
Peak memory 205636 kb
Host smart-67393e17-45e3-4fa2-9bfe-5386c63158b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860454516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2860454516
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3568693434
Short name T951
Test name
Test status
Simulation time 153433883 ps
CPU time 3.83 seconds
Started Jun 23 05:48:26 PM PDT 24
Finished Jun 23 05:48:30 PM PDT 24
Peak memory 225512 kb
Host smart-13168e9f-bc68-4649-a190-71e7fecaa86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568693434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3568693434
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2278959452
Short name T308
Test name
Test status
Simulation time 23687020 ps
CPU time 0.84 seconds
Started Jun 23 05:48:30 PM PDT 24
Finished Jun 23 05:48:32 PM PDT 24
Peak memory 207748 kb
Host smart-45e1d339-fb56-4592-b34e-4401ac94a60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278959452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2278959452
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1512404766
Short name T415
Test name
Test status
Simulation time 7519376655 ps
CPU time 76.86 seconds
Started Jun 23 05:48:30 PM PDT 24
Finished Jun 23 05:49:48 PM PDT 24
Peak memory 250308 kb
Host smart-71c20c29-478d-4fc3-9fa0-fb63fb3e7c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512404766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1512404766
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2192364677
Short name T289
Test name
Test status
Simulation time 863031795 ps
CPU time 4.3 seconds
Started Jun 23 05:48:28 PM PDT 24
Finished Jun 23 05:48:33 PM PDT 24
Peak memory 218328 kb
Host smart-eeb315ea-a9f8-4d00-938b-019c42a6789e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192364677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2192364677
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2651734856
Short name T252
Test name
Test status
Simulation time 227746904517 ps
CPU time 641.43 seconds
Started Jun 23 05:48:26 PM PDT 24
Finished Jun 23 05:59:08 PM PDT 24
Peak memory 267604 kb
Host smart-aca0dce8-444d-483b-bec9-288e34792a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651734856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2651734856
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.861931525
Short name T275
Test name
Test status
Simulation time 22617733794 ps
CPU time 28.04 seconds
Started Jun 23 05:48:27 PM PDT 24
Finished Jun 23 05:48:55 PM PDT 24
Peak memory 233892 kb
Host smart-3d14c8c8-3e64-481a-b18a-8301b5834dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861931525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.861931525
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1187173048
Short name T364
Test name
Test status
Simulation time 142302915 ps
CPU time 2.07 seconds
Started Jun 23 05:48:28 PM PDT 24
Finished Jun 23 05:48:30 PM PDT 24
Peak memory 224876 kb
Host smart-af60d6f1-6e2e-4930-b60d-c4a8ee46fc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187173048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1187173048
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1401544072
Short name T56
Test name
Test status
Simulation time 5863790419 ps
CPU time 32.75 seconds
Started Jun 23 05:48:26 PM PDT 24
Finished Jun 23 05:48:59 PM PDT 24
Peak memory 233892 kb
Host smart-7bbb6f3e-4bfd-4a6a-99e6-08aa287b7ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401544072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1401544072
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2363376355
Short name T171
Test name
Test status
Simulation time 5703678949 ps
CPU time 6.03 seconds
Started Jun 23 05:48:28 PM PDT 24
Finished Jun 23 05:48:34 PM PDT 24
Peak memory 225568 kb
Host smart-0359b4b9-5d44-442b-a130-808ee159fa1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363376355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2363376355
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3434169347
Short name T695
Test name
Test status
Simulation time 72934184 ps
CPU time 2.92 seconds
Started Jun 23 05:48:25 PM PDT 24
Finished Jun 23 05:48:28 PM PDT 24
Peak memory 225520 kb
Host smart-9bbc55d4-8ed2-4c83-b4b6-637e9624e203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434169347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3434169347
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3688922597
Short name T391
Test name
Test status
Simulation time 2227305872 ps
CPU time 5.23 seconds
Started Jun 23 05:48:33 PM PDT 24
Finished Jun 23 05:48:39 PM PDT 24
Peak memory 221904 kb
Host smart-8babe4c5-b2b0-4fe9-9c62-df0768e71b92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3688922597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3688922597
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3258322828
Short name T422
Test name
Test status
Simulation time 11923169073 ps
CPU time 107.35 seconds
Started Jun 23 05:48:26 PM PDT 24
Finished Jun 23 05:50:14 PM PDT 24
Peak memory 225784 kb
Host smart-c347fe23-653a-435b-a1f8-3366bcead8b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258322828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3258322828
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.751716628
Short name T29
Test name
Test status
Simulation time 953721422 ps
CPU time 5.4 seconds
Started Jun 23 05:48:27 PM PDT 24
Finished Jun 23 05:48:32 PM PDT 24
Peak memory 217424 kb
Host smart-9a7dda1a-125c-4792-b944-1a613acfd42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751716628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.751716628
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2036063732
Short name T577
Test name
Test status
Simulation time 89423399 ps
CPU time 0.69 seconds
Started Jun 23 05:48:32 PM PDT 24
Finished Jun 23 05:48:33 PM PDT 24
Peak memory 206652 kb
Host smart-2a364cd1-04c2-499c-9536-c082dc073987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036063732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2036063732
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2038562327
Short name T849
Test name
Test status
Simulation time 55770959 ps
CPU time 0.96 seconds
Started Jun 23 05:48:28 PM PDT 24
Finished Jun 23 05:48:29 PM PDT 24
Peak memory 207996 kb
Host smart-b43136f2-4d0c-478c-afd4-606fc492679a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038562327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2038562327
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1603172946
Short name T347
Test name
Test status
Simulation time 449466178 ps
CPU time 1.03 seconds
Started Jun 23 05:48:28 PM PDT 24
Finished Jun 23 05:48:29 PM PDT 24
Peak memory 206920 kb
Host smart-a69777ae-fb06-4389-b872-36c2a6b2d706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603172946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1603172946
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3241250010
Short name T955
Test name
Test status
Simulation time 59406903421 ps
CPU time 17.02 seconds
Started Jun 23 05:48:26 PM PDT 24
Finished Jun 23 05:48:44 PM PDT 24
Peak memory 225636 kb
Host smart-d44cfc55-428f-4ad5-90a8-af94ec36a068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241250010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3241250010
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.272148614
Short name T327
Test name
Test status
Simulation time 33042641 ps
CPU time 0.7 seconds
Started Jun 23 05:48:31 PM PDT 24
Finished Jun 23 05:48:32 PM PDT 24
Peak memory 206284 kb
Host smart-8bcd026e-71c4-499f-abad-718407863f7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272148614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.272148614
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1322775632
Short name T303
Test name
Test status
Simulation time 121382123 ps
CPU time 2.48 seconds
Started Jun 23 05:48:30 PM PDT 24
Finished Jun 23 05:48:33 PM PDT 24
Peak memory 233772 kb
Host smart-879346ad-51f8-4f85-96e9-c5d3d5c4dd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322775632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1322775632
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3083306950
Short name T901
Test name
Test status
Simulation time 46999801 ps
CPU time 0.78 seconds
Started Jun 23 05:48:32 PM PDT 24
Finished Jun 23 05:48:34 PM PDT 24
Peak memory 207860 kb
Host smart-828efd4c-07c2-470c-b677-b55efd9cb4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083306950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3083306950
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.631917203
Short name T255
Test name
Test status
Simulation time 276032093552 ps
CPU time 212.37 seconds
Started Jun 23 05:48:33 PM PDT 24
Finished Jun 23 05:52:06 PM PDT 24
Peak memory 256008 kb
Host smart-680294cd-00d6-4894-9543-089b529648f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631917203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.631917203
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1860217230
Short name T52
Test name
Test status
Simulation time 64748599081 ps
CPU time 155.56 seconds
Started Jun 23 05:48:33 PM PDT 24
Finished Jun 23 05:51:09 PM PDT 24
Peak memory 257864 kb
Host smart-e5d59274-1853-4b4a-9326-5e80fa2310fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860217230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1860217230
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1474605548
Short name T674
Test name
Test status
Simulation time 2460375305 ps
CPU time 18.9 seconds
Started Jun 23 05:48:34 PM PDT 24
Finished Jun 23 05:48:53 PM PDT 24
Peak memory 225704 kb
Host smart-24cc7383-bd3c-4828-aa24-7b590bc676e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474605548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1474605548
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.517660201
Short name T201
Test name
Test status
Simulation time 727440020 ps
CPU time 4.35 seconds
Started Jun 23 05:48:31 PM PDT 24
Finished Jun 23 05:48:36 PM PDT 24
Peak memory 225524 kb
Host smart-14fc064d-372e-4342-b7fa-c79b54274b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517660201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.517660201
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3197456595
Short name T544
Test name
Test status
Simulation time 3480927130 ps
CPU time 12.65 seconds
Started Jun 23 05:48:33 PM PDT 24
Finished Jun 23 05:48:46 PM PDT 24
Peak memory 241684 kb
Host smart-984ca843-d24c-403a-97c7-da78b9455cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197456595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3197456595
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.548878814
Short name T460
Test name
Test status
Simulation time 226878222 ps
CPU time 2.7 seconds
Started Jun 23 05:48:32 PM PDT 24
Finished Jun 23 05:48:36 PM PDT 24
Peak memory 233736 kb
Host smart-708b8521-2b67-473f-a94b-ec3606ffa376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548878814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.548878814
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3845310
Short name T743
Test name
Test status
Simulation time 1490740807 ps
CPU time 9.92 seconds
Started Jun 23 05:48:30 PM PDT 24
Finished Jun 23 05:48:41 PM PDT 24
Peak memory 233708 kb
Host smart-36ccabd4-7594-4160-a166-ecd7a10894b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3845310
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3223022549
Short name T636
Test name
Test status
Simulation time 1677091347 ps
CPU time 11.14 seconds
Started Jun 23 05:48:35 PM PDT 24
Finished Jun 23 05:48:47 PM PDT 24
Peak memory 223968 kb
Host smart-382d0ffd-7e51-4277-9200-5e9425e875ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3223022549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3223022549
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3582074818
Short name T899
Test name
Test status
Simulation time 19150941494 ps
CPU time 56.81 seconds
Started Jun 23 05:48:30 PM PDT 24
Finished Jun 23 05:49:28 PM PDT 24
Peak memory 250708 kb
Host smart-aff3e687-eed1-495f-8611-7e6e20530e1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582074818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3582074818
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.870257875
Short name T286
Test name
Test status
Simulation time 23911990013 ps
CPU time 34.03 seconds
Started Jun 23 05:48:34 PM PDT 24
Finished Jun 23 05:49:08 PM PDT 24
Peak memory 217468 kb
Host smart-4f76e2b8-b6a2-4c24-8044-1a056c3f4c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870257875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.870257875
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.690481552
Short name T920
Test name
Test status
Simulation time 27481428377 ps
CPU time 20.07 seconds
Started Jun 23 05:48:33 PM PDT 24
Finished Jun 23 05:48:54 PM PDT 24
Peak memory 217512 kb
Host smart-4791d0a3-e681-4076-9ff3-e1cbf5cd7a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690481552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.690481552
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.848727983
Short name T335
Test name
Test status
Simulation time 180352037 ps
CPU time 5.01 seconds
Started Jun 23 05:48:32 PM PDT 24
Finished Jun 23 05:48:38 PM PDT 24
Peak memory 217404 kb
Host smart-1fb112fd-0f01-4d2a-829b-b257146784ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848727983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.848727983
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2327695770
Short name T826
Test name
Test status
Simulation time 52775554 ps
CPU time 0.77 seconds
Started Jun 23 05:48:31 PM PDT 24
Finished Jun 23 05:48:32 PM PDT 24
Peak memory 206888 kb
Host smart-86627521-f41c-4ef8-a1ab-ddadbc7bf003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327695770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2327695770
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1596014691
Short name T735
Test name
Test status
Simulation time 343192260 ps
CPU time 6.38 seconds
Started Jun 23 05:48:31 PM PDT 24
Finished Jun 23 05:48:39 PM PDT 24
Peak memory 250176 kb
Host smart-147fb862-a3de-4f13-8ab8-12fe525bcbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596014691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1596014691
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3672973959
Short name T474
Test name
Test status
Simulation time 32484939 ps
CPU time 0.72 seconds
Started Jun 23 05:48:38 PM PDT 24
Finished Jun 23 05:48:39 PM PDT 24
Peak memory 206256 kb
Host smart-8dc6ba87-b7f8-423f-bc5e-ecb5f362b7e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672973959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3672973959
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3030817332
Short name T229
Test name
Test status
Simulation time 39766663 ps
CPU time 2.34 seconds
Started Jun 23 05:48:41 PM PDT 24
Finished Jun 23 05:48:44 PM PDT 24
Peak memory 233772 kb
Host smart-2497fadd-9cf8-48e4-90c4-32846ac46af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030817332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3030817332
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1290976954
Short name T562
Test name
Test status
Simulation time 15937273 ps
CPU time 0.76 seconds
Started Jun 23 05:48:30 PM PDT 24
Finished Jun 23 05:48:32 PM PDT 24
Peak memory 206828 kb
Host smart-6f3a49db-af24-4d08-aa77-068ef46a7d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290976954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1290976954
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3051858583
Short name T267
Test name
Test status
Simulation time 25978502832 ps
CPU time 147.51 seconds
Started Jun 23 05:48:36 PM PDT 24
Finished Jun 23 05:51:04 PM PDT 24
Peak memory 225664 kb
Host smart-637400a9-ce17-4373-b382-6294bcbbd53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051858583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3051858583
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.456838569
Short name T45
Test name
Test status
Simulation time 12943011359 ps
CPU time 88.89 seconds
Started Jun 23 05:48:36 PM PDT 24
Finished Jun 23 05:50:05 PM PDT 24
Peak memory 274080 kb
Host smart-b59c1eaf-9f29-4f9c-b3f4-fecf33a7e9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456838569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.456838569
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.887701466
Short name T183
Test name
Test status
Simulation time 21942346170 ps
CPU time 98.45 seconds
Started Jun 23 05:48:40 PM PDT 24
Finished Jun 23 05:50:19 PM PDT 24
Peak memory 254608 kb
Host smart-8635bdab-de94-4136-bbc6-a4f80e7e4e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887701466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.887701466
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.550153552
Short name T350
Test name
Test status
Simulation time 118391425 ps
CPU time 5.06 seconds
Started Jun 23 05:48:39 PM PDT 24
Finished Jun 23 05:48:45 PM PDT 24
Peak memory 233816 kb
Host smart-f313eb74-b9e5-4f1c-9491-f0cfca5e5455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550153552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.550153552
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1070283836
Short name T615
Test name
Test status
Simulation time 423063151 ps
CPU time 5.12 seconds
Started Jun 23 05:48:38 PM PDT 24
Finished Jun 23 05:48:44 PM PDT 24
Peak memory 233768 kb
Host smart-64d4b2ea-471c-4180-a8dc-c89870c01dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070283836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1070283836
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.181312932
Short name T840
Test name
Test status
Simulation time 7675641334 ps
CPU time 69.56 seconds
Started Jun 23 05:48:43 PM PDT 24
Finished Jun 23 05:49:53 PM PDT 24
Peak memory 233804 kb
Host smart-0e57b1ed-510a-4050-a7f0-2b2bdf531a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181312932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.181312932
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.257896454
Short name T180
Test name
Test status
Simulation time 850856312 ps
CPU time 4.75 seconds
Started Jun 23 05:48:31 PM PDT 24
Finished Jun 23 05:48:36 PM PDT 24
Peak memory 233720 kb
Host smart-76d3a64e-16ee-484f-84d1-24df13b288e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257896454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.257896454
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2751818948
Short name T739
Test name
Test status
Simulation time 470909856 ps
CPU time 3.46 seconds
Started Jun 23 05:48:32 PM PDT 24
Finished Jun 23 05:48:36 PM PDT 24
Peak memory 225536 kb
Host smart-ee1624e8-ef40-4537-8668-84da66e39438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751818948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2751818948
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.884296251
Short name T974
Test name
Test status
Simulation time 6234926445 ps
CPU time 9.98 seconds
Started Jun 23 05:48:41 PM PDT 24
Finished Jun 23 05:48:52 PM PDT 24
Peak memory 219992 kb
Host smart-0effdcf5-f6af-45d2-9449-3501c1fcadea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=884296251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.884296251
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1076487142
Short name T545
Test name
Test status
Simulation time 198077146869 ps
CPU time 290.65 seconds
Started Jun 23 05:48:35 PM PDT 24
Finished Jun 23 05:53:26 PM PDT 24
Peak memory 284276 kb
Host smart-334e1c40-16f0-43a7-9392-7cc9146f0016
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076487142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1076487142
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2013695024
Short name T318
Test name
Test status
Simulation time 4618210408 ps
CPU time 6.46 seconds
Started Jun 23 05:48:33 PM PDT 24
Finished Jun 23 05:48:41 PM PDT 24
Peak memory 217532 kb
Host smart-452aea71-dc97-4490-bf25-315ea30983af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013695024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2013695024
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.564817056
Short name T27
Test name
Test status
Simulation time 1930026908 ps
CPU time 10.77 seconds
Started Jun 23 05:48:31 PM PDT 24
Finished Jun 23 05:48:43 PM PDT 24
Peak memory 217272 kb
Host smart-b3a3e168-2fa8-4647-8333-c56ec89bb4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564817056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.564817056
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3354343933
Short name T858
Test name
Test status
Simulation time 334071512 ps
CPU time 3.77 seconds
Started Jun 23 05:48:32 PM PDT 24
Finished Jun 23 05:48:37 PM PDT 24
Peak memory 217440 kb
Host smart-fc54b36d-cab6-4cd7-8795-cfc4de779f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354343933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3354343933
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2925723250
Short name T451
Test name
Test status
Simulation time 78503707 ps
CPU time 0.95 seconds
Started Jun 23 05:48:32 PM PDT 24
Finished Jun 23 05:48:34 PM PDT 24
Peak memory 207912 kb
Host smart-2a3dc73b-7e64-45df-b31d-2b99c1355076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925723250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2925723250
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2829767199
Short name T728
Test name
Test status
Simulation time 12696798747 ps
CPU time 10.58 seconds
Started Jun 23 05:48:35 PM PDT 24
Finished Jun 23 05:48:46 PM PDT 24
Peak memory 233844 kb
Host smart-309ecf81-42d1-4af6-8933-545afc702348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829767199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2829767199
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.4216206498
Short name T439
Test name
Test status
Simulation time 30678248 ps
CPU time 0.7 seconds
Started Jun 23 05:48:39 PM PDT 24
Finished Jun 23 05:48:41 PM PDT 24
Peak memory 206308 kb
Host smart-86b44d2c-0141-42a7-9808-b48e0e554472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216206498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
4216206498
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1065294087
Short name T333
Test name
Test status
Simulation time 439985140 ps
CPU time 7.29 seconds
Started Jun 23 05:48:35 PM PDT 24
Finished Jun 23 05:48:43 PM PDT 24
Peak memory 233724 kb
Host smart-90163eb8-6369-4edb-8eb7-2506b53e1c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065294087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1065294087
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.988531755
Short name T411
Test name
Test status
Simulation time 27269658 ps
CPU time 0.74 seconds
Started Jun 23 05:48:37 PM PDT 24
Finished Jun 23 05:48:38 PM PDT 24
Peak memory 206504 kb
Host smart-42308890-b3b2-43cd-b145-770d1fae0a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988531755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.988531755
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1986756014
Short name T383
Test name
Test status
Simulation time 9285400311 ps
CPU time 38.2 seconds
Started Jun 23 05:48:42 PM PDT 24
Finished Jun 23 05:49:21 PM PDT 24
Peak memory 238444 kb
Host smart-83817e53-c745-4946-b28a-4a9392bb1f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986756014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1986756014
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1268523274
Short name T393
Test name
Test status
Simulation time 5898017533 ps
CPU time 58.43 seconds
Started Jun 23 05:48:36 PM PDT 24
Finished Jun 23 05:49:35 PM PDT 24
Peak memory 250552 kb
Host smart-3a8f6c34-8008-462f-8f1d-d9931f2c562c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268523274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1268523274
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2227690526
Short name T233
Test name
Test status
Simulation time 7178878093 ps
CPU time 138.02 seconds
Started Jun 23 05:48:37 PM PDT 24
Finished Jun 23 05:50:55 PM PDT 24
Peak memory 262432 kb
Host smart-064b9a4d-8195-4960-bf3c-feded8cce5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227690526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2227690526
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2480922840
Short name T452
Test name
Test status
Simulation time 8331230064 ps
CPU time 28.68 seconds
Started Jun 23 05:48:37 PM PDT 24
Finished Jun 23 05:49:06 PM PDT 24
Peak memory 233924 kb
Host smart-cc9b1a00-bcbc-4463-bf20-5a1b27073674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480922840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2480922840
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1086278392
Short name T593
Test name
Test status
Simulation time 1212146561 ps
CPU time 4.38 seconds
Started Jun 23 05:48:36 PM PDT 24
Finished Jun 23 05:48:41 PM PDT 24
Peak memory 225540 kb
Host smart-b0a477b9-67c4-41e9-b138-bc50850106d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086278392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1086278392
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1788308017
Short name T1
Test name
Test status
Simulation time 1900160403 ps
CPU time 15.81 seconds
Started Jun 23 05:48:37 PM PDT 24
Finished Jun 23 05:48:53 PM PDT 24
Peak memory 241848 kb
Host smart-8d216c1c-973d-49c0-8710-ff265035faf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788308017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1788308017
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.917423109
Short name T765
Test name
Test status
Simulation time 18519397737 ps
CPU time 21.95 seconds
Started Jun 23 05:48:39 PM PDT 24
Finished Jun 23 05:49:01 PM PDT 24
Peak memory 233780 kb
Host smart-926bb46d-dcb6-40bc-afad-e947c0c4b6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917423109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.917423109
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3911499884
Short name T135
Test name
Test status
Simulation time 221334093 ps
CPU time 3.76 seconds
Started Jun 23 05:48:41 PM PDT 24
Finished Jun 23 05:48:46 PM PDT 24
Peak memory 233772 kb
Host smart-189b5132-56d1-480c-b966-6704a8941ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911499884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3911499884
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2206715053
Short name T850
Test name
Test status
Simulation time 1316099665 ps
CPU time 13.07 seconds
Started Jun 23 05:48:35 PM PDT 24
Finished Jun 23 05:48:49 PM PDT 24
Peak memory 221184 kb
Host smart-b0817068-1e61-4918-9e93-8d6559092514
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2206715053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2206715053
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1962202304
Short name T20
Test name
Test status
Simulation time 53857912382 ps
CPU time 234.27 seconds
Started Jun 23 05:48:41 PM PDT 24
Finished Jun 23 05:52:36 PM PDT 24
Peak memory 255636 kb
Host smart-84f80c9b-9f7b-4d3f-b913-75e4f9c24a9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962202304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1962202304
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.857967957
Short name T931
Test name
Test status
Simulation time 8823258001 ps
CPU time 10.53 seconds
Started Jun 23 05:48:36 PM PDT 24
Finished Jun 23 05:48:47 PM PDT 24
Peak memory 217468 kb
Host smart-9d00c964-0922-4aef-b1b9-1a0f557ac65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857967957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.857967957
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.788371471
Short name T441
Test name
Test status
Simulation time 1742662232 ps
CPU time 3.06 seconds
Started Jun 23 05:48:43 PM PDT 24
Finished Jun 23 05:48:47 PM PDT 24
Peak memory 217308 kb
Host smart-908f235c-7d32-4916-99b8-ee5e2917b0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788371471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.788371471
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.494264896
Short name T788
Test name
Test status
Simulation time 71400161 ps
CPU time 1.64 seconds
Started Jun 23 05:48:43 PM PDT 24
Finished Jun 23 05:48:46 PM PDT 24
Peak memory 217312 kb
Host smart-fa9dde7e-b75d-4e36-9a95-dfcf9db45531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494264896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.494264896
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1873840037
Short name T629
Test name
Test status
Simulation time 113195530 ps
CPU time 0.89 seconds
Started Jun 23 05:48:41 PM PDT 24
Finished Jun 23 05:48:43 PM PDT 24
Peak memory 206916 kb
Host smart-1662847f-2ac2-4ede-96e3-62f418be60db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873840037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1873840037
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3343311832
Short name T947
Test name
Test status
Simulation time 153790810 ps
CPU time 2.21 seconds
Started Jun 23 05:48:40 PM PDT 24
Finished Jun 23 05:48:43 PM PDT 24
Peak memory 233448 kb
Host smart-193df255-90c4-45f9-8087-38ea03804186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343311832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3343311832
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.4105191391
Short name T892
Test name
Test status
Simulation time 13482957 ps
CPU time 0.74 seconds
Started Jun 23 05:48:42 PM PDT 24
Finished Jun 23 05:48:44 PM PDT 24
Peak memory 205668 kb
Host smart-ea0665f2-5939-4c06-b8fc-a3c8a03f6102
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105191391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
4105191391
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2707380704
Short name T727
Test name
Test status
Simulation time 130280078 ps
CPU time 2.63 seconds
Started Jun 23 05:48:39 PM PDT 24
Finished Jun 23 05:48:42 PM PDT 24
Peak memory 233448 kb
Host smart-22fc1ed6-9070-47d8-85d0-e1ec800f88e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707380704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2707380704
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1929314035
Short name T889
Test name
Test status
Simulation time 55180558 ps
CPU time 0.77 seconds
Started Jun 23 05:48:41 PM PDT 24
Finished Jun 23 05:48:43 PM PDT 24
Peak memory 207860 kb
Host smart-75d342ff-b9f9-4f8a-83c2-964c69b9437d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929314035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1929314035
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1371961664
Short name T213
Test name
Test status
Simulation time 1904114544 ps
CPU time 35.74 seconds
Started Jun 23 05:48:41 PM PDT 24
Finished Jun 23 05:49:18 PM PDT 24
Peak memory 257152 kb
Host smart-bf319cc1-2fc3-4faa-9d60-9a5a13046ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371961664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1371961664
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3948035842
Short name T754
Test name
Test status
Simulation time 38351418710 ps
CPU time 207.79 seconds
Started Jun 23 05:48:47 PM PDT 24
Finished Jun 23 05:52:15 PM PDT 24
Peak memory 255652 kb
Host smart-b61f4dad-5b16-4c57-b23e-d5f91a04aeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948035842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3948035842
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3233730391
Short name T200
Test name
Test status
Simulation time 617727397131 ps
CPU time 336.26 seconds
Started Jun 23 05:48:41 PM PDT 24
Finished Jun 23 05:54:18 PM PDT 24
Peak memory 255688 kb
Host smart-477a0fcd-e00b-470a-bc8b-0d5eca3f8dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233730391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3233730391
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1364130074
Short name T661
Test name
Test status
Simulation time 2364853435 ps
CPU time 34.87 seconds
Started Jun 23 05:48:45 PM PDT 24
Finished Jun 23 05:49:20 PM PDT 24
Peak memory 242028 kb
Host smart-518eedb9-eef8-470a-af09-b2b51e43d7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364130074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1364130074
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1491097003
Short name T9
Test name
Test status
Simulation time 658645589 ps
CPU time 5.05 seconds
Started Jun 23 05:48:46 PM PDT 24
Finished Jun 23 05:48:52 PM PDT 24
Peak memory 233696 kb
Host smart-998a2efa-ebb8-4843-a469-29cc9cf3dc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491097003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1491097003
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2409719551
Short name T465
Test name
Test status
Simulation time 11669228671 ps
CPU time 85.48 seconds
Started Jun 23 05:48:43 PM PDT 24
Finished Jun 23 05:50:09 PM PDT 24
Peak memory 225616 kb
Host smart-5dba8d28-84fa-4e9b-b3e6-a4583a248da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409719551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2409719551
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3381188176
Short name T7
Test name
Test status
Simulation time 2959328260 ps
CPU time 9.95 seconds
Started Jun 23 05:48:40 PM PDT 24
Finished Jun 23 05:48:51 PM PDT 24
Peak memory 225588 kb
Host smart-89367b1a-a9cf-45fc-9ff0-d71d3263518e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381188176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3381188176
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.892153808
Short name T843
Test name
Test status
Simulation time 511702000 ps
CPU time 3.39 seconds
Started Jun 23 05:48:39 PM PDT 24
Finished Jun 23 05:48:43 PM PDT 24
Peak memory 233784 kb
Host smart-6fe80c1a-e7a1-4699-909b-66cd798ba408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892153808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.892153808
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2997813591
Short name T897
Test name
Test status
Simulation time 1012478473 ps
CPU time 11.82 seconds
Started Jun 23 05:48:38 PM PDT 24
Finished Jun 23 05:48:50 PM PDT 24
Peak memory 223260 kb
Host smart-0d773979-8428-499a-acfe-be727479e0b1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2997813591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2997813591
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3079967523
Short name T295
Test name
Test status
Simulation time 56221417 ps
CPU time 0.74 seconds
Started Jun 23 05:48:40 PM PDT 24
Finished Jun 23 05:48:42 PM PDT 24
Peak memory 206672 kb
Host smart-f656879d-5269-483d-9947-c15d6a8043fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079967523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3079967523
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.620404395
Short name T304
Test name
Test status
Simulation time 16363318276 ps
CPU time 9.33 seconds
Started Jun 23 05:48:41 PM PDT 24
Finished Jun 23 05:48:51 PM PDT 24
Peak memory 217516 kb
Host smart-c1c40d84-717c-4ff2-a075-b3a8505ccbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620404395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.620404395
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2921564976
Short name T896
Test name
Test status
Simulation time 82819670 ps
CPU time 1.31 seconds
Started Jun 23 05:48:41 PM PDT 24
Finished Jun 23 05:48:43 PM PDT 24
Peak memory 209204 kb
Host smart-1f81a461-228d-4e7b-825f-109f474d05ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921564976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2921564976
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3937211496
Short name T781
Test name
Test status
Simulation time 43791586 ps
CPU time 0.79 seconds
Started Jun 23 05:48:35 PM PDT 24
Finished Jun 23 05:48:36 PM PDT 24
Peak memory 206908 kb
Host smart-37edc67c-324c-4647-9700-ddafbc63a102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937211496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3937211496
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.4228713225
Short name T424
Test name
Test status
Simulation time 770078476 ps
CPU time 3.93 seconds
Started Jun 23 05:48:40 PM PDT 24
Finished Jun 23 05:48:45 PM PDT 24
Peak memory 225496 kb
Host smart-91dd682a-4acf-42d1-a540-a96f57e691c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228713225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.4228713225
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2375398155
Short name T334
Test name
Test status
Simulation time 42573458 ps
CPU time 0.74 seconds
Started Jun 23 05:48:44 PM PDT 24
Finished Jun 23 05:48:46 PM PDT 24
Peak memory 206292 kb
Host smart-5f1dfeea-01cb-4557-a45c-93b3ec8f6818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375398155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2375398155
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1863359659
Short name T678
Test name
Test status
Simulation time 34261910 ps
CPU time 2.31 seconds
Started Jun 23 05:48:42 PM PDT 24
Finished Jun 23 05:48:45 PM PDT 24
Peak memory 233428 kb
Host smart-8e3279fb-1ed2-4c52-9e73-e5b51ffa6f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863359659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1863359659
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.804142109
Short name T846
Test name
Test status
Simulation time 15508003 ps
CPU time 0.73 seconds
Started Jun 23 05:48:39 PM PDT 24
Finished Jun 23 05:48:40 PM PDT 24
Peak memory 206836 kb
Host smart-516e6fdc-8f79-448e-879d-f1447bcbe2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804142109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.804142109
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1043585409
Short name T239
Test name
Test status
Simulation time 35472298437 ps
CPU time 163.87 seconds
Started Jun 23 05:48:44 PM PDT 24
Finished Jun 23 05:51:28 PM PDT 24
Peak memory 254068 kb
Host smart-eb3ceb19-2eeb-492c-94d4-f4cab7cb3f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043585409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1043585409
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1155741256
Short name T724
Test name
Test status
Simulation time 21913933901 ps
CPU time 86.55 seconds
Started Jun 23 05:48:47 PM PDT 24
Finished Jun 23 05:50:14 PM PDT 24
Peak memory 261544 kb
Host smart-c700dbaf-d731-48b8-949a-d42a309b742a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155741256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1155741256
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1217948436
Short name T288
Test name
Test status
Simulation time 60228591335 ps
CPU time 100.7 seconds
Started Jun 23 05:48:43 PM PDT 24
Finished Jun 23 05:50:24 PM PDT 24
Peak memory 252044 kb
Host smart-8bb78813-33ed-4713-a009-42b41ca6430c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217948436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1217948436
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1536486759
Short name T273
Test name
Test status
Simulation time 2751435702 ps
CPU time 15.76 seconds
Started Jun 23 05:48:41 PM PDT 24
Finished Jun 23 05:48:58 PM PDT 24
Peak memory 250316 kb
Host smart-5486753e-6eab-4676-851e-f4a70a758587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536486759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1536486759
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3191125912
Short name T500
Test name
Test status
Simulation time 9792456843 ps
CPU time 12.87 seconds
Started Jun 23 05:48:42 PM PDT 24
Finished Jun 23 05:48:56 PM PDT 24
Peak memory 233892 kb
Host smart-0c49110b-b1d1-4c95-a206-78e54cec64fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191125912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3191125912
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.4145189609
Short name T662
Test name
Test status
Simulation time 11087506535 ps
CPU time 144.96 seconds
Started Jun 23 05:48:40 PM PDT 24
Finished Jun 23 05:51:06 PM PDT 24
Peak memory 241024 kb
Host smart-1ef5f5cf-9b3a-497a-aef0-c3c4df238bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145189609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.4145189609
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.414773889
Short name T459
Test name
Test status
Simulation time 1568850638 ps
CPU time 5.23 seconds
Started Jun 23 05:48:40 PM PDT 24
Finished Jun 23 05:48:47 PM PDT 24
Peak memory 225504 kb
Host smart-b2915d16-aa14-406e-9502-464fea00a397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414773889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.414773889
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3729293125
Short name T891
Test name
Test status
Simulation time 2472530943 ps
CPU time 6.81 seconds
Started Jun 23 05:48:40 PM PDT 24
Finished Jun 23 05:48:48 PM PDT 24
Peak memory 233920 kb
Host smart-122aba6b-6146-4f13-8357-bc45dedbdd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729293125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3729293125
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2463046129
Short name T851
Test name
Test status
Simulation time 3538377447 ps
CPU time 11.61 seconds
Started Jun 23 05:48:41 PM PDT 24
Finished Jun 23 05:48:53 PM PDT 24
Peak memory 220412 kb
Host smart-65fa7f8c-d5cd-49fb-8e0e-700978e44c37
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2463046129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2463046129
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3975774892
Short name T669
Test name
Test status
Simulation time 153236318 ps
CPU time 1.27 seconds
Started Jun 23 05:48:46 PM PDT 24
Finished Jun 23 05:48:48 PM PDT 24
Peak memory 208184 kb
Host smart-637de525-f00e-4b16-a910-595e66f27a82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975774892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3975774892
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3862004509
Short name T446
Test name
Test status
Simulation time 364124571 ps
CPU time 3.12 seconds
Started Jun 23 05:48:45 PM PDT 24
Finished Jun 23 05:48:48 PM PDT 24
Peak memory 217512 kb
Host smart-d97d2955-bd43-41c5-956f-d6e717454ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862004509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3862004509
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1456802535
Short name T314
Test name
Test status
Simulation time 336461381 ps
CPU time 2.39 seconds
Started Jun 23 05:48:40 PM PDT 24
Finished Jun 23 05:48:43 PM PDT 24
Peak memory 217316 kb
Host smart-d9e692a8-729d-4ab6-959d-caeca4d7a1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456802535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1456802535
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.737516975
Short name T514
Test name
Test status
Simulation time 13119794 ps
CPU time 0.76 seconds
Started Jun 23 05:48:40 PM PDT 24
Finished Jun 23 05:48:42 PM PDT 24
Peak memory 206940 kb
Host smart-a58b9d96-5969-4cc9-95f6-72ffa2b0ae72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737516975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.737516975
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1709680202
Short name T354
Test name
Test status
Simulation time 13858809 ps
CPU time 0.67 seconds
Started Jun 23 05:48:40 PM PDT 24
Finished Jun 23 05:48:41 PM PDT 24
Peak memory 206568 kb
Host smart-a86d7f67-3606-43e6-affd-1a9add28446d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709680202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1709680202
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1793326953
Short name T238
Test name
Test status
Simulation time 1579147659 ps
CPU time 4.5 seconds
Started Jun 23 05:48:44 PM PDT 24
Finished Jun 23 05:48:50 PM PDT 24
Peak memory 225548 kb
Host smart-8107ca37-c80a-4a17-bd2e-d26dbcc46f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793326953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1793326953
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3159397140
Short name T330
Test name
Test status
Simulation time 14403632 ps
CPU time 0.73 seconds
Started Jun 23 05:48:52 PM PDT 24
Finished Jun 23 05:48:53 PM PDT 24
Peak memory 205740 kb
Host smart-5af4ce4c-1701-499d-a26c-8347862268fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159397140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3159397140
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.531923299
Short name T813
Test name
Test status
Simulation time 242253253 ps
CPU time 2.45 seconds
Started Jun 23 05:48:45 PM PDT 24
Finished Jun 23 05:48:48 PM PDT 24
Peak memory 233700 kb
Host smart-daa65da0-44ad-4908-9b6a-fdb6d1ba7023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531923299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.531923299
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3535446151
Short name T340
Test name
Test status
Simulation time 12655240 ps
CPU time 0.7 seconds
Started Jun 23 05:48:43 PM PDT 24
Finished Jun 23 05:48:45 PM PDT 24
Peak memory 206828 kb
Host smart-e08e7d80-ca5b-47c7-bdd9-46a7eca3a80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535446151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3535446151
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1914063567
Short name T39
Test name
Test status
Simulation time 1419662222 ps
CPU time 22.02 seconds
Started Jun 23 05:48:47 PM PDT 24
Finished Jun 23 05:49:10 PM PDT 24
Peak memory 239708 kb
Host smart-44642fdc-7266-49b8-8e5d-75e1bd581ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914063567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1914063567
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1501808496
Short name T222
Test name
Test status
Simulation time 74716557151 ps
CPU time 103.26 seconds
Started Jun 23 05:48:49 PM PDT 24
Finished Jun 23 05:50:32 PM PDT 24
Peak memory 255972 kb
Host smart-d6f1de21-0c50-436e-ae0d-d41f9cd44276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501808496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1501808496
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1278901209
Short name T218
Test name
Test status
Simulation time 60858444619 ps
CPU time 535.37 seconds
Started Jun 23 05:48:52 PM PDT 24
Finished Jun 23 05:57:48 PM PDT 24
Peak memory 257056 kb
Host smart-2b4bcc55-cbda-416e-b4c9-8dbfd0f60262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278901209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1278901209
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3634299247
Short name T908
Test name
Test status
Simulation time 440878699 ps
CPU time 6.6 seconds
Started Jun 23 05:48:47 PM PDT 24
Finished Jun 23 05:48:54 PM PDT 24
Peak memory 225492 kb
Host smart-d7696883-139b-4362-9dc1-d27ec4f9abca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634299247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3634299247
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.244984433
Short name T8
Test name
Test status
Simulation time 309284871 ps
CPU time 7.91 seconds
Started Jun 23 05:48:45 PM PDT 24
Finished Jun 23 05:48:53 PM PDT 24
Peak memory 225532 kb
Host smart-f898facd-5d7c-4896-9c70-e2ad9696eb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244984433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.244984433
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1190536154
Short name T823
Test name
Test status
Simulation time 7575515751 ps
CPU time 19.48 seconds
Started Jun 23 05:48:46 PM PDT 24
Finished Jun 23 05:49:06 PM PDT 24
Peak memory 233884 kb
Host smart-0a9b9e88-34a1-416e-9b38-41097e21149f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190536154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1190536154
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1941406658
Short name T657
Test name
Test status
Simulation time 208189824 ps
CPU time 3.75 seconds
Started Jun 23 05:48:45 PM PDT 24
Finished Jun 23 05:48:49 PM PDT 24
Peak memory 233744 kb
Host smart-d077d860-8a01-434f-8743-94c43d6bd673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941406658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1941406658
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2447723563
Short name T663
Test name
Test status
Simulation time 760617392 ps
CPU time 5.07 seconds
Started Jun 23 05:48:46 PM PDT 24
Finished Jun 23 05:48:52 PM PDT 24
Peak memory 221072 kb
Host smart-6ad915bf-f4f7-4603-af0a-740ede8de153
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2447723563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2447723563
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2469170806
Short name T266
Test name
Test status
Simulation time 21487054502 ps
CPU time 196.19 seconds
Started Jun 23 05:48:56 PM PDT 24
Finished Jun 23 05:52:12 PM PDT 24
Peak memory 250352 kb
Host smart-b25dd49d-05f9-49db-9de2-d1da7af4d168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469170806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2469170806
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.639606906
Short name T557
Test name
Test status
Simulation time 3816958788 ps
CPU time 20.23 seconds
Started Jun 23 05:48:45 PM PDT 24
Finished Jun 23 05:49:06 PM PDT 24
Peak memory 217420 kb
Host smart-8e93fcd9-462d-4562-9134-d65ba17c0797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639606906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.639606906
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2366558442
Short name T366
Test name
Test status
Simulation time 8196240066 ps
CPU time 19.73 seconds
Started Jun 23 05:48:44 PM PDT 24
Finished Jun 23 05:49:04 PM PDT 24
Peak memory 217480 kb
Host smart-7f80fb9d-fcf5-4d32-8aec-d3d378c15aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366558442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2366558442
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.514831074
Short name T382
Test name
Test status
Simulation time 49584707 ps
CPU time 1.29 seconds
Started Jun 23 05:48:47 PM PDT 24
Finished Jun 23 05:48:49 PM PDT 24
Peak memory 209096 kb
Host smart-f5457ebb-cd41-41de-a9dc-c1aff688a4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514831074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.514831074
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2689576657
Short name T653
Test name
Test status
Simulation time 79187115 ps
CPU time 0.79 seconds
Started Jun 23 05:48:44 PM PDT 24
Finished Jun 23 05:48:45 PM PDT 24
Peak memory 206852 kb
Host smart-448986a2-7a07-4533-998c-3f11cd179d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689576657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2689576657
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2552972000
Short name T475
Test name
Test status
Simulation time 39251792532 ps
CPU time 23.84 seconds
Started Jun 23 05:48:46 PM PDT 24
Finished Jun 23 05:49:11 PM PDT 24
Peak memory 250260 kb
Host smart-8c267cc2-4126-4c68-abbe-60acbb6ec081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552972000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2552972000
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2106846341
Short name T933
Test name
Test status
Simulation time 183260348 ps
CPU time 0.73 seconds
Started Jun 23 05:48:50 PM PDT 24
Finished Jun 23 05:48:51 PM PDT 24
Peak memory 206624 kb
Host smart-491c6970-d9c2-4e46-a220-f49a0d408c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106846341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2106846341
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3722893465
Short name T969
Test name
Test status
Simulation time 480381282 ps
CPU time 5.37 seconds
Started Jun 23 05:48:51 PM PDT 24
Finished Jun 23 05:48:57 PM PDT 24
Peak memory 225596 kb
Host smart-3d921f8a-ba2f-4e70-ae89-487cc458f92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722893465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3722893465
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1612759534
Short name T570
Test name
Test status
Simulation time 24209263 ps
CPU time 0.78 seconds
Started Jun 23 05:48:51 PM PDT 24
Finished Jun 23 05:48:52 PM PDT 24
Peak memory 207440 kb
Host smart-5d4198e8-7fdd-46cf-ab04-e27ba98bd76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612759534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1612759534
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3354639936
Short name T375
Test name
Test status
Simulation time 109879611473 ps
CPU time 80.95 seconds
Started Jun 23 05:48:51 PM PDT 24
Finished Jun 23 05:50:12 PM PDT 24
Peak memory 250280 kb
Host smart-3f442e2b-11c3-4da1-8f81-eaeb1cb343cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354639936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3354639936
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1608314364
Short name T214
Test name
Test status
Simulation time 7179896961 ps
CPU time 56.72 seconds
Started Jun 23 05:48:49 PM PDT 24
Finished Jun 23 05:49:46 PM PDT 24
Peak memory 233940 kb
Host smart-e924dd43-cf6c-4bbc-9a7f-c52a39e8739a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608314364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1608314364
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.433622235
Short name T68
Test name
Test status
Simulation time 74608442085 ps
CPU time 398.49 seconds
Started Jun 23 05:48:52 PM PDT 24
Finished Jun 23 05:55:31 PM PDT 24
Peak memory 266776 kb
Host smart-70f51be6-83f8-410f-b617-4300783e59a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433622235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.433622235
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.868377681
Short name T493
Test name
Test status
Simulation time 2043409945 ps
CPU time 8.08 seconds
Started Jun 23 05:48:50 PM PDT 24
Finished Jun 23 05:48:59 PM PDT 24
Peak memory 225600 kb
Host smart-cfc9cf92-5278-4e40-a7be-5a881d4bdb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868377681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.868377681
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3667519059
Short name T508
Test name
Test status
Simulation time 2712609426 ps
CPU time 8.62 seconds
Started Jun 23 05:48:52 PM PDT 24
Finished Jun 23 05:49:01 PM PDT 24
Peak memory 233848 kb
Host smart-0e8972f1-b5af-4b0c-8183-c6ab6a94b161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667519059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3667519059
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3684256280
Short name T824
Test name
Test status
Simulation time 65674652 ps
CPU time 2.59 seconds
Started Jun 23 05:48:54 PM PDT 24
Finished Jun 23 05:48:57 PM PDT 24
Peak memory 233492 kb
Host smart-ca00bb7c-8296-4d8a-903f-52efb516697e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684256280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3684256280
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1072830618
Short name T580
Test name
Test status
Simulation time 3455075062 ps
CPU time 5.91 seconds
Started Jun 23 05:48:54 PM PDT 24
Finished Jun 23 05:49:00 PM PDT 24
Peak memory 233916 kb
Host smart-ed49ee44-d4e8-4c81-8c8d-7cb5fb092e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072830618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1072830618
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2460505925
Short name T764
Test name
Test status
Simulation time 1948985065 ps
CPU time 8.18 seconds
Started Jun 23 05:48:50 PM PDT 24
Finished Jun 23 05:48:58 PM PDT 24
Peak memory 225468 kb
Host smart-7c40d488-1c25-4667-9441-5196aff15caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460505925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2460505925
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1230537599
Short name T568
Test name
Test status
Simulation time 110769010 ps
CPU time 3.08 seconds
Started Jun 23 05:48:51 PM PDT 24
Finished Jun 23 05:48:54 PM PDT 24
Peak memory 220196 kb
Host smart-a9c4eb9c-b953-4c46-9d5d-be3bc2de9a7b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1230537599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1230537599
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3209885985
Short name T613
Test name
Test status
Simulation time 2793149030 ps
CPU time 29.89 seconds
Started Jun 23 05:48:51 PM PDT 24
Finished Jun 23 05:49:21 PM PDT 24
Peak memory 235008 kb
Host smart-41cb593f-7676-4297-a00b-a6c809094504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209885985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3209885985
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.17183749
Short name T885
Test name
Test status
Simulation time 6320353227 ps
CPU time 19.55 seconds
Started Jun 23 05:48:54 PM PDT 24
Finished Jun 23 05:49:14 PM PDT 24
Peak memory 217480 kb
Host smart-119ee2c1-8f6e-472d-bd51-d79fdfdd837f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17183749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.17183749
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2175333639
Short name T838
Test name
Test status
Simulation time 5898735763 ps
CPU time 5.73 seconds
Started Jun 23 05:48:47 PM PDT 24
Finished Jun 23 05:48:53 PM PDT 24
Peak memory 217468 kb
Host smart-cca6d357-f921-492b-a39f-96e0745a5514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175333639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2175333639
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1803719207
Short name T814
Test name
Test status
Simulation time 226824242 ps
CPU time 2.77 seconds
Started Jun 23 05:48:54 PM PDT 24
Finished Jun 23 05:48:58 PM PDT 24
Peak memory 217384 kb
Host smart-30168e6b-519f-458d-8bf6-92264ca1ce44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803719207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1803719207
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3553725140
Short name T903
Test name
Test status
Simulation time 27480114 ps
CPU time 0.79 seconds
Started Jun 23 05:48:53 PM PDT 24
Finished Jun 23 05:48:54 PM PDT 24
Peak memory 206904 kb
Host smart-b056d245-a273-47b8-b6d2-2f160782c9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553725140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3553725140
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3120348663
Short name T842
Test name
Test status
Simulation time 1141714902 ps
CPU time 4.53 seconds
Started Jun 23 05:48:47 PM PDT 24
Finished Jun 23 05:48:52 PM PDT 24
Peak memory 233684 kb
Host smart-10d77f9c-9ca1-4185-9364-6a57fbfe6cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120348663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3120348663
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3895561291
Short name T133
Test name
Test status
Simulation time 49354252 ps
CPU time 0.8 seconds
Started Jun 23 05:48:57 PM PDT 24
Finished Jun 23 05:48:58 PM PDT 24
Peak memory 206316 kb
Host smart-c04c4add-1323-40f9-a545-f1092d650c23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895561291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3895561291
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.709228738
Short name T738
Test name
Test status
Simulation time 217611578 ps
CPU time 2.45 seconds
Started Jun 23 05:48:56 PM PDT 24
Finished Jun 23 05:48:59 PM PDT 24
Peak memory 233800 kb
Host smart-f73c6ca4-4a2a-4276-896d-25c588f5a884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709228738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.709228738
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.951266510
Short name T865
Test name
Test status
Simulation time 19857196 ps
CPU time 0.74 seconds
Started Jun 23 05:48:46 PM PDT 24
Finished Jun 23 05:48:47 PM PDT 24
Peak memory 206440 kb
Host smart-7cebe3cc-5c35-4e94-bb7f-f358df8c135c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951266510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.951266510
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3674597801
Short name T912
Test name
Test status
Simulation time 15518891518 ps
CPU time 109.72 seconds
Started Jun 23 05:48:58 PM PDT 24
Finished Jun 23 05:50:49 PM PDT 24
Peak memory 250228 kb
Host smart-66c76237-6a15-4930-800c-cf5c7e5b899c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674597801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3674597801
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2875033765
Short name T634
Test name
Test status
Simulation time 4310466841 ps
CPU time 28.7 seconds
Started Jun 23 05:48:53 PM PDT 24
Finished Jun 23 05:49:22 PM PDT 24
Peak memory 235804 kb
Host smart-b38c9725-fcf3-4e7f-aff6-8c0014000162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875033765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2875033765
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.4023361937
Short name T206
Test name
Test status
Simulation time 259408220014 ps
CPU time 519.79 seconds
Started Jun 23 05:48:56 PM PDT 24
Finished Jun 23 05:57:36 PM PDT 24
Peak memory 258228 kb
Host smart-15190ab2-51b2-43e0-bd2f-293a5580fbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023361937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.4023361937
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2064114865
Short name T688
Test name
Test status
Simulation time 468683528 ps
CPU time 12.28 seconds
Started Jun 23 05:48:55 PM PDT 24
Finished Jun 23 05:49:08 PM PDT 24
Peak memory 250180 kb
Host smart-7c003716-2789-433d-aa41-db3447145524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064114865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2064114865
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.4255290282
Short name T673
Test name
Test status
Simulation time 1429508206 ps
CPU time 5.37 seconds
Started Jun 23 05:48:51 PM PDT 24
Finished Jun 23 05:48:57 PM PDT 24
Peak memory 225568 kb
Host smart-228561f0-5ef4-42df-927c-2dc03887f869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255290282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.4255290282
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1864024562
Short name T604
Test name
Test status
Simulation time 6537151556 ps
CPU time 71.8 seconds
Started Jun 23 05:48:56 PM PDT 24
Finished Jun 23 05:50:08 PM PDT 24
Peak memory 233804 kb
Host smart-90bf572f-10ee-4b6c-aad7-ab54f81ebb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864024562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1864024562
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1143991293
Short name T627
Test name
Test status
Simulation time 111145060 ps
CPU time 2.38 seconds
Started Jun 23 05:48:51 PM PDT 24
Finished Jun 23 05:48:54 PM PDT 24
Peak memory 233812 kb
Host smart-cf8077e9-170a-45e4-a075-54e14d831a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143991293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1143991293
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1691511047
Short name T705
Test name
Test status
Simulation time 4243659337 ps
CPU time 6.95 seconds
Started Jun 23 05:48:54 PM PDT 24
Finished Jun 23 05:49:02 PM PDT 24
Peak memory 240436 kb
Host smart-451a1e35-cd0c-45ce-a2c4-9d10a0559339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691511047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1691511047
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3043883184
Short name T448
Test name
Test status
Simulation time 611205061 ps
CPU time 9.19 seconds
Started Jun 23 05:48:52 PM PDT 24
Finished Jun 23 05:49:02 PM PDT 24
Peak memory 223468 kb
Host smart-190805a9-179c-4df1-a642-524b794c1fa2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3043883184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3043883184
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3382686597
Short name T949
Test name
Test status
Simulation time 118089488030 ps
CPU time 940.82 seconds
Started Jun 23 05:48:58 PM PDT 24
Finished Jun 23 06:04:39 PM PDT 24
Peak memory 287244 kb
Host smart-ee6ba253-a798-4dd3-a4c7-1752f5f40541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382686597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3382686597
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3011546844
Short name T829
Test name
Test status
Simulation time 18107922817 ps
CPU time 33.57 seconds
Started Jun 23 05:48:50 PM PDT 24
Finished Jun 23 05:49:24 PM PDT 24
Peak memory 217404 kb
Host smart-0fe714c8-d66f-4e49-a331-cda45db2f10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011546844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3011546844
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.934594112
Short name T454
Test name
Test status
Simulation time 459146085 ps
CPU time 1.44 seconds
Started Jun 23 05:48:55 PM PDT 24
Finished Jun 23 05:48:57 PM PDT 24
Peak memory 208904 kb
Host smart-ed1d3f09-f1b4-48a2-bba7-17c442e0aef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934594112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.934594112
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2695894700
Short name T967
Test name
Test status
Simulation time 166155205 ps
CPU time 3.08 seconds
Started Jun 23 05:48:48 PM PDT 24
Finished Jun 23 05:48:51 PM PDT 24
Peak memory 217480 kb
Host smart-13c445e4-ac56-4ab5-8671-2732d2ab7ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695894700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2695894700
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2718373697
Short name T943
Test name
Test status
Simulation time 180057533 ps
CPU time 0.85 seconds
Started Jun 23 05:48:51 PM PDT 24
Finished Jun 23 05:48:52 PM PDT 24
Peak memory 206904 kb
Host smart-c842a554-d913-4c4a-8253-2c9bae1ee56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718373697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2718373697
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2059396276
Short name T676
Test name
Test status
Simulation time 9819241475 ps
CPU time 9.87 seconds
Started Jun 23 05:48:52 PM PDT 24
Finished Jun 23 05:49:02 PM PDT 24
Peak memory 233916 kb
Host smart-ce20d111-4c40-43c1-a5f4-a77a52d544b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059396276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2059396276
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.649408224
Short name T848
Test name
Test status
Simulation time 16686288 ps
CPU time 0.69 seconds
Started Jun 23 05:48:58 PM PDT 24
Finished Jun 23 05:48:59 PM PDT 24
Peak memory 205748 kb
Host smart-e59d244d-a43f-46b2-857e-5a051d0a89ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649408224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.649408224
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3243536603
Short name T86
Test name
Test status
Simulation time 216652078 ps
CPU time 4.28 seconds
Started Jun 23 05:48:58 PM PDT 24
Finished Jun 23 05:49:02 PM PDT 24
Peak memory 225588 kb
Host smart-0c9ffa01-2c19-4e32-a0c9-ad6e3e91030c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243536603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3243536603
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3540841734
Short name T795
Test name
Test status
Simulation time 18662167 ps
CPU time 0.77 seconds
Started Jun 23 05:48:53 PM PDT 24
Finished Jun 23 05:48:54 PM PDT 24
Peak memory 207520 kb
Host smart-e3fc42a3-4773-4057-9364-725e95853d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540841734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3540841734
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.221587557
Short name T836
Test name
Test status
Simulation time 4351378124 ps
CPU time 60.78 seconds
Started Jun 23 05:48:54 PM PDT 24
Finished Jun 23 05:49:56 PM PDT 24
Peak memory 254568 kb
Host smart-de9a2570-5e34-4f04-84eb-ac165375b0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221587557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.221587557
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1119285901
Short name T370
Test name
Test status
Simulation time 29717841750 ps
CPU time 155.83 seconds
Started Jun 23 05:48:56 PM PDT 24
Finished Jun 23 05:51:33 PM PDT 24
Peak memory 257580 kb
Host smart-4cc8e4f6-aad4-4dc1-bb40-199ef5b3c2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119285901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1119285901
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1648499526
Short name T259
Test name
Test status
Simulation time 52997839268 ps
CPU time 144.53 seconds
Started Jun 23 05:49:01 PM PDT 24
Finished Jun 23 05:51:26 PM PDT 24
Peak memory 250352 kb
Host smart-58ddddfa-ca3d-4610-9b20-8ea2e6b4c76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648499526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1648499526
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2294857358
Short name T401
Test name
Test status
Simulation time 629971229 ps
CPU time 3.64 seconds
Started Jun 23 05:48:53 PM PDT 24
Finished Jun 23 05:48:57 PM PDT 24
Peak memory 225540 kb
Host smart-a323a7a8-ff7c-4b0d-b793-1248c13a4f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294857358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2294857358
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2153870353
Short name T192
Test name
Test status
Simulation time 680292502 ps
CPU time 4.89 seconds
Started Jun 23 05:48:54 PM PDT 24
Finished Jun 23 05:49:00 PM PDT 24
Peak memory 233844 kb
Host smart-aafb153b-ad73-4acd-bbc6-a40a8bdaf9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153870353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2153870353
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1522008212
Short name T821
Test name
Test status
Simulation time 1055104012 ps
CPU time 12.83 seconds
Started Jun 23 05:49:01 PM PDT 24
Finished Jun 23 05:49:15 PM PDT 24
Peak memory 233788 kb
Host smart-f90f987a-5918-453c-81a5-a32fd65085c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522008212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1522008212
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.407171019
Short name T48
Test name
Test status
Simulation time 11523780286 ps
CPU time 11.82 seconds
Started Jun 23 05:48:56 PM PDT 24
Finished Jun 23 05:49:08 PM PDT 24
Peak memory 238712 kb
Host smart-f749efcb-9218-414a-99b8-0d38931ca207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407171019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.407171019
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.4033767006
Short name T784
Test name
Test status
Simulation time 35655102003 ps
CPU time 23.27 seconds
Started Jun 23 05:48:55 PM PDT 24
Finished Jun 23 05:49:18 PM PDT 24
Peak memory 225636 kb
Host smart-2dd50629-fe4b-4020-9a69-94cd4a98a6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033767006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.4033767006
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.477179515
Short name T810
Test name
Test status
Simulation time 734876934 ps
CPU time 4 seconds
Started Jun 23 05:48:56 PM PDT 24
Finished Jun 23 05:49:01 PM PDT 24
Peak memory 224196 kb
Host smart-1d63d091-924e-4db9-82b8-45a357db9fee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=477179515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.477179515
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1188453068
Short name T54
Test name
Test status
Simulation time 40604559977 ps
CPU time 388.11 seconds
Started Jun 23 05:48:58 PM PDT 24
Finished Jun 23 05:55:27 PM PDT 24
Peak memory 282916 kb
Host smart-79ae6e13-8c46-4fe8-a748-e8c2afc91305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188453068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1188453068
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.4114115523
Short name T290
Test name
Test status
Simulation time 557894878 ps
CPU time 3.65 seconds
Started Jun 23 05:48:52 PM PDT 24
Finished Jun 23 05:48:56 PM PDT 24
Peak memory 218544 kb
Host smart-92e6308f-57ec-417a-aebd-1bd400562ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114115523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.4114115523
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2533104466
Short name T915
Test name
Test status
Simulation time 806808672 ps
CPU time 5.78 seconds
Started Jun 23 05:48:53 PM PDT 24
Finished Jun 23 05:49:00 PM PDT 24
Peak memory 217316 kb
Host smart-98686609-3683-4eed-b165-6af3d06d1e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533104466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2533104466
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1031546664
Short name T619
Test name
Test status
Simulation time 260436311 ps
CPU time 3.72 seconds
Started Jun 23 05:48:54 PM PDT 24
Finished Jun 23 05:48:58 PM PDT 24
Peak memory 217296 kb
Host smart-73b77173-df41-4635-9618-01b3bf9803c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031546664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1031546664
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.416248869
Short name T643
Test name
Test status
Simulation time 138629100 ps
CPU time 0.9 seconds
Started Jun 23 05:48:53 PM PDT 24
Finished Jun 23 05:48:54 PM PDT 24
Peak memory 207352 kb
Host smart-e9344326-eca4-4498-8d78-978baa8d991a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416248869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.416248869
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.404597698
Short name T862
Test name
Test status
Simulation time 22367469052 ps
CPU time 15 seconds
Started Jun 23 05:48:56 PM PDT 24
Finished Jun 23 05:49:12 PM PDT 24
Peak memory 225620 kb
Host smart-55e2685f-e9f0-43c2-ae5e-206544258366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404597698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.404597698
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1901712918
Short name T343
Test name
Test status
Simulation time 218999331 ps
CPU time 0.7 seconds
Started Jun 23 05:46:22 PM PDT 24
Finished Jun 23 05:46:23 PM PDT 24
Peak memory 206292 kb
Host smart-a4688639-1380-4199-b878-afac27f11038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901712918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
901712918
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1307605129
Short name T833
Test name
Test status
Simulation time 224554536 ps
CPU time 3.08 seconds
Started Jun 23 05:46:23 PM PDT 24
Finished Jun 23 05:46:27 PM PDT 24
Peak memory 225520 kb
Host smart-63613247-4e9e-4449-a436-81d342bb296c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307605129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1307605129
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3484739476
Short name T582
Test name
Test status
Simulation time 22152114 ps
CPU time 0.76 seconds
Started Jun 23 05:46:15 PM PDT 24
Finished Jun 23 05:46:16 PM PDT 24
Peak memory 206488 kb
Host smart-c79d3aa8-6d49-4b67-9824-740809f00eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484739476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3484739476
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.868290011
Short name T614
Test name
Test status
Simulation time 1633658642 ps
CPU time 27.65 seconds
Started Jun 23 05:46:20 PM PDT 24
Finished Jun 23 05:46:48 PM PDT 24
Peak memory 250184 kb
Host smart-112f8eea-696b-431f-b50a-0a74a6c7a7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868290011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.868290011
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.728052395
Short name T40
Test name
Test status
Simulation time 50279068050 ps
CPU time 468.47 seconds
Started Jun 23 05:46:21 PM PDT 24
Finished Jun 23 05:54:10 PM PDT 24
Peak memory 252740 kb
Host smart-555fbcb7-9850-4201-a22e-a04b72a8cf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728052395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.728052395
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1272804607
Short name T175
Test name
Test status
Simulation time 193585789169 ps
CPU time 475.07 seconds
Started Jun 23 05:46:22 PM PDT 24
Finished Jun 23 05:54:18 PM PDT 24
Peak memory 266692 kb
Host smart-44288da8-d632-45f1-9936-9b6bb4f19687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272804607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1272804607
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1461792518
Short name T269
Test name
Test status
Simulation time 2490680531 ps
CPU time 21.46 seconds
Started Jun 23 05:46:22 PM PDT 24
Finished Jun 23 05:46:43 PM PDT 24
Peak memory 225740 kb
Host smart-1b28c026-b3c1-473e-84dd-6db751e8996a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461792518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1461792518
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3796092209
Short name T388
Test name
Test status
Simulation time 9441306311 ps
CPU time 23.18 seconds
Started Jun 23 05:46:23 PM PDT 24
Finished Jun 23 05:46:47 PM PDT 24
Peak memory 220736 kb
Host smart-8df126bd-c4d5-4708-b6e6-05fcb5be7d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796092209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3796092209
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.4109283851
Short name T212
Test name
Test status
Simulation time 3099581533 ps
CPU time 27.78 seconds
Started Jun 23 05:46:22 PM PDT 24
Finished Jun 23 05:46:51 PM PDT 24
Peak memory 242024 kb
Host smart-764fb15a-c83f-4fe7-be80-6d7df6b23f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109283851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.4109283851
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2343546181
Short name T797
Test name
Test status
Simulation time 15627936 ps
CPU time 1.06 seconds
Started Jun 23 05:46:19 PM PDT 24
Finished Jun 23 05:46:20 PM PDT 24
Peak memory 217608 kb
Host smart-9da10462-982b-4176-b9a3-db33df5cb3b2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343546181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2343546181
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1631602271
Short name T523
Test name
Test status
Simulation time 8630770262 ps
CPU time 15.31 seconds
Started Jun 23 05:46:23 PM PDT 24
Finished Jun 23 05:46:38 PM PDT 24
Peak memory 233900 kb
Host smart-c6ed27c0-15b3-4a8a-97cc-51c28266958d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631602271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1631602271
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1930067035
Short name T664
Test name
Test status
Simulation time 9569546203 ps
CPU time 18.12 seconds
Started Jun 23 05:46:21 PM PDT 24
Finished Jun 23 05:46:39 PM PDT 24
Peak memory 234112 kb
Host smart-dfa21cf2-fce7-4a75-96cd-5c1085ce9dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930067035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1930067035
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1279745424
Short name T679
Test name
Test status
Simulation time 690183069 ps
CPU time 5.57 seconds
Started Jun 23 05:46:19 PM PDT 24
Finished Jun 23 05:46:25 PM PDT 24
Peak memory 221124 kb
Host smart-df19c892-759b-43f8-87f6-caa5fc242b31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1279745424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1279745424
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2461870762
Short name T654
Test name
Test status
Simulation time 99570242 ps
CPU time 0.97 seconds
Started Jun 23 05:46:23 PM PDT 24
Finished Jun 23 05:46:25 PM PDT 24
Peak memory 207896 kb
Host smart-c518a6e0-046a-40f2-93ec-81ef130296cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461870762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2461870762
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1966958890
Short name T585
Test name
Test status
Simulation time 1457725379 ps
CPU time 9.48 seconds
Started Jun 23 05:46:21 PM PDT 24
Finished Jun 23 05:46:31 PM PDT 24
Peak memory 217292 kb
Host smart-116945f6-6595-4ddc-ad64-05b428f8698b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966958890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1966958890
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3123443766
Short name T596
Test name
Test status
Simulation time 4260294294 ps
CPU time 3.84 seconds
Started Jun 23 05:46:26 PM PDT 24
Finished Jun 23 05:46:30 PM PDT 24
Peak memory 217428 kb
Host smart-0c016f84-d4a9-4d47-a9a5-abe8e05c1e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123443766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3123443766
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.4057553806
Short name T403
Test name
Test status
Simulation time 28264887 ps
CPU time 0.98 seconds
Started Jun 23 05:46:22 PM PDT 24
Finished Jun 23 05:46:24 PM PDT 24
Peak memory 207756 kb
Host smart-86ef0e3e-9d75-41c7-be15-d0ee6370214a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057553806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.4057553806
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3491378895
Short name T484
Test name
Test status
Simulation time 446440362 ps
CPU time 0.98 seconds
Started Jun 23 05:46:22 PM PDT 24
Finished Jun 23 05:46:23 PM PDT 24
Peak memory 207388 kb
Host smart-ec5a2e0f-cbb6-4add-b6a0-a1faadd757cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491378895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3491378895
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3233337042
Short name T704
Test name
Test status
Simulation time 953909078 ps
CPU time 5.45 seconds
Started Jun 23 05:46:23 PM PDT 24
Finished Jun 23 05:46:29 PM PDT 24
Peak memory 233796 kb
Host smart-cec3bdd8-0284-43bc-b384-094989aaad8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233337042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3233337042
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3112818167
Short name T927
Test name
Test status
Simulation time 23498443 ps
CPU time 0.73 seconds
Started Jun 23 05:46:29 PM PDT 24
Finished Jun 23 05:46:30 PM PDT 24
Peak memory 206688 kb
Host smart-1c2c1d42-2d57-41f1-ac1f-f9c8a9dc5e68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112818167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
112818167
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1408204318
Short name T130
Test name
Test status
Simulation time 72066138 ps
CPU time 2.58 seconds
Started Jun 23 05:46:24 PM PDT 24
Finished Jun 23 05:46:27 PM PDT 24
Peak memory 233748 kb
Host smart-d8a9b772-4629-4ae0-a05f-fb612f60eada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408204318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1408204318
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3437233505
Short name T410
Test name
Test status
Simulation time 14825717 ps
CPU time 0.74 seconds
Started Jun 23 05:46:24 PM PDT 24
Finished Jun 23 05:46:26 PM PDT 24
Peak memory 206832 kb
Host smart-9ec2bb28-8630-4ea3-952a-89dfe415a919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437233505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3437233505
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2873294459
Short name T205
Test name
Test status
Simulation time 11851488930 ps
CPU time 110.19 seconds
Started Jun 23 05:46:28 PM PDT 24
Finished Jun 23 05:48:19 PM PDT 24
Peak memory 271740 kb
Host smart-35faed5c-b1a6-4d8d-b0cc-62b1f4802026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873294459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2873294459
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3801021090
Short name T736
Test name
Test status
Simulation time 84689055329 ps
CPU time 779.55 seconds
Started Jun 23 05:46:28 PM PDT 24
Finished Jun 23 05:59:29 PM PDT 24
Peak memory 251380 kb
Host smart-2385ebf6-d27b-4912-8fca-d597027f0248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801021090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3801021090
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3849000654
Short name T50
Test name
Test status
Simulation time 14677960977 ps
CPU time 70.22 seconds
Started Jun 23 05:46:29 PM PDT 24
Finished Jun 23 05:47:40 PM PDT 24
Peak memory 250348 kb
Host smart-d3568fe4-70b7-47b7-8471-9c7630a6c057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849000654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3849000654
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3628007846
Short name T778
Test name
Test status
Simulation time 2435750694 ps
CPU time 18.05 seconds
Started Jun 23 05:46:28 PM PDT 24
Finished Jun 23 05:46:46 PM PDT 24
Peak memory 242120 kb
Host smart-5f37586e-7770-4473-ad63-69d4b96fd154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628007846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3628007846
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2546648761
Short name T919
Test name
Test status
Simulation time 7417295322 ps
CPU time 20.03 seconds
Started Jun 23 05:46:25 PM PDT 24
Finished Jun 23 05:46:46 PM PDT 24
Peak memory 233888 kb
Host smart-af617449-2ceb-4250-9db0-c6baa9b4c69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546648761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2546648761
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.70825657
Short name T860
Test name
Test status
Simulation time 58459316654 ps
CPU time 34.62 seconds
Started Jun 23 05:46:33 PM PDT 24
Finished Jun 23 05:47:09 PM PDT 24
Peak memory 240656 kb
Host smart-5c80fadc-c797-4512-800c-a12a402fb982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70825657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.70825657
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.494493025
Short name T811
Test name
Test status
Simulation time 27612613 ps
CPU time 1.09 seconds
Started Jun 23 05:46:22 PM PDT 24
Finished Jun 23 05:46:23 PM PDT 24
Peak memory 217656 kb
Host smart-fcab56ac-0dd6-479d-aeb7-885c4b8629a2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494493025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.494493025
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.104068518
Short name T701
Test name
Test status
Simulation time 521108968 ps
CPU time 5.06 seconds
Started Jun 23 05:46:27 PM PDT 24
Finished Jun 23 05:46:32 PM PDT 24
Peak memory 233736 kb
Host smart-8f394caa-2079-430a-9055-c44b38f39f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104068518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
104068518
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.155492881
Short name T863
Test name
Test status
Simulation time 4083735084 ps
CPU time 6.13 seconds
Started Jun 23 05:46:34 PM PDT 24
Finished Jun 23 05:46:41 PM PDT 24
Peak memory 241668 kb
Host smart-fb69c3cc-5478-4aa2-81b6-36044168aac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155492881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.155492881
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2138543300
Short name T306
Test name
Test status
Simulation time 874549613 ps
CPU time 4.52 seconds
Started Jun 23 05:46:25 PM PDT 24
Finished Jun 23 05:46:30 PM PDT 24
Peak memory 224092 kb
Host smart-02b1d5f5-b08e-46c0-bd7a-f7d216cbf1db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2138543300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2138543300
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.771799070
Short name T149
Test name
Test status
Simulation time 273102903 ps
CPU time 1.19 seconds
Started Jun 23 05:46:25 PM PDT 24
Finished Jun 23 05:46:27 PM PDT 24
Peak memory 208044 kb
Host smart-db36e948-51b4-4792-8b45-86b357480b48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771799070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.771799070
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2623821437
Short name T687
Test name
Test status
Simulation time 21152257527 ps
CPU time 27.52 seconds
Started Jun 23 05:46:21 PM PDT 24
Finished Jun 23 05:46:49 PM PDT 24
Peak memory 217500 kb
Host smart-e903c6fb-9e25-486d-b304-5d20671a5377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623821437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2623821437
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.185607739
Short name T384
Test name
Test status
Simulation time 8062332302 ps
CPU time 8.84 seconds
Started Jun 23 05:46:20 PM PDT 24
Finished Jun 23 05:46:29 PM PDT 24
Peak memory 217532 kb
Host smart-8bb524bc-9d4d-4b4c-8514-9567f93ac05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185607739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.185607739
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.854944408
Short name T779
Test name
Test status
Simulation time 310996424 ps
CPU time 2.34 seconds
Started Jun 23 05:46:21 PM PDT 24
Finished Jun 23 05:46:24 PM PDT 24
Peak memory 217308 kb
Host smart-eb8a712b-f5bb-473d-97f8-ee99eafdc309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854944408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.854944408
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.383544932
Short name T772
Test name
Test status
Simulation time 89539949 ps
CPU time 0.77 seconds
Started Jun 23 05:46:21 PM PDT 24
Finished Jun 23 05:46:22 PM PDT 24
Peak memory 206912 kb
Host smart-2e8e713d-716f-435a-a182-343a3125a139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383544932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.383544932
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1778113744
Short name T485
Test name
Test status
Simulation time 2698410448 ps
CPU time 14.78 seconds
Started Jun 23 05:46:30 PM PDT 24
Finished Jun 23 05:46:45 PM PDT 24
Peak memory 233876 kb
Host smart-de9467b1-f418-4e2c-9539-293ec0e5c1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778113744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1778113744
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.4145713090
Short name T75
Test name
Test status
Simulation time 40733679 ps
CPU time 0.72 seconds
Started Jun 23 05:46:37 PM PDT 24
Finished Jun 23 05:46:38 PM PDT 24
Peak memory 205736 kb
Host smart-4e24b7ab-4cc6-4c2a-9c77-71166b27fc1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145713090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.4
145713090
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.4090283828
Short name T228
Test name
Test status
Simulation time 2513423056 ps
CPU time 6.32 seconds
Started Jun 23 05:46:37 PM PDT 24
Finished Jun 23 05:46:45 PM PDT 24
Peak memory 233892 kb
Host smart-dcbb71bd-06cf-4e57-aefc-714488a10f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090283828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.4090283828
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.486170991
Short name T462
Test name
Test status
Simulation time 45792500 ps
CPU time 0.72 seconds
Started Jun 23 05:46:25 PM PDT 24
Finished Jun 23 05:46:26 PM PDT 24
Peak memory 206480 kb
Host smart-3536b777-aad6-4c54-bb42-192f9dfcae0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486170991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.486170991
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1122592620
Short name T435
Test name
Test status
Simulation time 4011226564 ps
CPU time 9.49 seconds
Started Jun 23 05:46:29 PM PDT 24
Finished Jun 23 05:46:39 PM PDT 24
Peak memory 235156 kb
Host smart-d77137aa-c9bd-4ec5-b1c8-2b9851eac7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122592620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1122592620
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1399915592
Short name T284
Test name
Test status
Simulation time 94460780715 ps
CPU time 228.43 seconds
Started Jun 23 05:46:31 PM PDT 24
Finished Jun 23 05:50:21 PM PDT 24
Peak memory 263232 kb
Host smart-db7166f0-5c3b-412c-a244-973d4b5850f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399915592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1399915592
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2216769683
Short name T349
Test name
Test status
Simulation time 71256518032 ps
CPU time 156.66 seconds
Started Jun 23 05:46:28 PM PDT 24
Finished Jun 23 05:49:06 PM PDT 24
Peak memory 251812 kb
Host smart-17b15d28-305c-4212-b839-f8401fa25c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216769683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2216769683
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1296636057
Short name T782
Test name
Test status
Simulation time 314728715 ps
CPU time 4.67 seconds
Started Jun 23 05:46:33 PM PDT 24
Finished Jun 23 05:46:39 PM PDT 24
Peak memory 225620 kb
Host smart-e5c4ba7b-643d-47a6-a853-13c5262854e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296636057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1296636057
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1389588822
Short name T181
Test name
Test status
Simulation time 456653308 ps
CPU time 7.22 seconds
Started Jun 23 05:46:26 PM PDT 24
Finished Jun 23 05:46:34 PM PDT 24
Peak memory 233776 kb
Host smart-0c2f7e20-cab8-47a4-8e98-7a0e8ab1c7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389588822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1389588822
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3878153158
Short name T569
Test name
Test status
Simulation time 7669161978 ps
CPU time 76.83 seconds
Started Jun 23 05:46:26 PM PDT 24
Finished Jun 23 05:47:43 PM PDT 24
Peak memory 225612 kb
Host smart-7ce15111-ac80-420c-809b-a9a382b10237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878153158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3878153158
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3374740783
Short name T357
Test name
Test status
Simulation time 48721133 ps
CPU time 1.04 seconds
Started Jun 23 05:46:28 PM PDT 24
Finished Jun 23 05:46:30 PM PDT 24
Peak memory 217532 kb
Host smart-4501ea77-9516-4827-8952-6e30b4d735f4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374740783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3374740783
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2782803790
Short name T414
Test name
Test status
Simulation time 1804203897 ps
CPU time 4.44 seconds
Started Jun 23 05:46:29 PM PDT 24
Finished Jun 23 05:46:34 PM PDT 24
Peak memory 225528 kb
Host smart-8bca0228-2dfb-49d5-b6b7-b658d78ee451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782803790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2782803790
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3703003053
Short name T510
Test name
Test status
Simulation time 809911654 ps
CPU time 2.73 seconds
Started Jun 23 05:46:29 PM PDT 24
Finished Jun 23 05:46:32 PM PDT 24
Peak memory 225548 kb
Host smart-54e2b012-d3fd-42f8-8a9d-4d2a7a502ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703003053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3703003053
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2132416525
Short name T700
Test name
Test status
Simulation time 913221591 ps
CPU time 9.46 seconds
Started Jun 23 05:46:28 PM PDT 24
Finished Jun 23 05:46:38 PM PDT 24
Peak memory 223708 kb
Host smart-a9fbb5b5-e3b9-44c5-b0a8-b0d6786000d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2132416525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2132416525
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2555687620
Short name T932
Test name
Test status
Simulation time 29065065 ps
CPU time 0.69 seconds
Started Jun 23 05:46:24 PM PDT 24
Finished Jun 23 05:46:25 PM PDT 24
Peak memory 206644 kb
Host smart-203c8892-684c-489f-93a5-78d0205f2ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555687620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2555687620
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3009582528
Short name T525
Test name
Test status
Simulation time 16683294 ps
CPU time 0.71 seconds
Started Jun 23 05:46:27 PM PDT 24
Finished Jun 23 05:46:28 PM PDT 24
Peak memory 206648 kb
Host smart-120e0c20-e7a7-437b-8ee5-7f3864c67bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009582528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3009582528
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1000107957
Short name T385
Test name
Test status
Simulation time 28370253 ps
CPU time 1.04 seconds
Started Jun 23 05:46:28 PM PDT 24
Finished Jun 23 05:46:29 PM PDT 24
Peak memory 208296 kb
Host smart-7b51d688-610a-4f2e-a9de-64e677ddb21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000107957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1000107957
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2947585957
Short name T24
Test name
Test status
Simulation time 107568357 ps
CPU time 0.77 seconds
Started Jun 23 05:46:29 PM PDT 24
Finished Jun 23 05:46:31 PM PDT 24
Peak memory 206904 kb
Host smart-d252068d-4593-4172-91fb-e0266ef74f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947585957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2947585957
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.471044498
Short name T959
Test name
Test status
Simulation time 553581713 ps
CPU time 5.95 seconds
Started Jun 23 05:46:25 PM PDT 24
Finished Jun 23 05:46:32 PM PDT 24
Peak memory 233744 kb
Host smart-c30d1acf-7945-4bfc-a97e-47da1aeb26a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471044498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.471044498
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2115584659
Short name T854
Test name
Test status
Simulation time 14357763 ps
CPU time 0.72 seconds
Started Jun 23 05:46:41 PM PDT 24
Finished Jun 23 05:46:42 PM PDT 24
Peak memory 206328 kb
Host smart-99fe8fe9-899b-4dd2-b503-7be1defd18b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115584659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
115584659
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3564903794
Short name T83
Test name
Test status
Simulation time 102389098 ps
CPU time 2.37 seconds
Started Jun 23 05:46:34 PM PDT 24
Finished Jun 23 05:46:37 PM PDT 24
Peak memory 225552 kb
Host smart-6555d8b2-e79b-4b8d-9349-5c35751f5665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564903794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3564903794
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2917202567
Short name T398
Test name
Test status
Simulation time 22228822 ps
CPU time 0.8 seconds
Started Jun 23 05:46:34 PM PDT 24
Finished Jun 23 05:46:36 PM PDT 24
Peak memory 207500 kb
Host smart-562db29a-05ae-4cce-9bbb-3af6a36f9d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917202567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2917202567
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1708421803
Short name T413
Test name
Test status
Simulation time 124264268 ps
CPU time 0.91 seconds
Started Jun 23 05:46:31 PM PDT 24
Finished Jun 23 05:46:33 PM PDT 24
Peak memory 217112 kb
Host smart-c2a502e7-b772-4dc9-a9c6-700afca42aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708421803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1708421803
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.40523301
Short name T418
Test name
Test status
Simulation time 45819407453 ps
CPU time 99.95 seconds
Started Jun 23 05:46:33 PM PDT 24
Finished Jun 23 05:48:14 PM PDT 24
Peak memory 254856 kb
Host smart-cd1c751c-33dd-4017-ad0b-3c96e1d40269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40523301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.40523301
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2054929055
Short name T815
Test name
Test status
Simulation time 714645928645 ps
CPU time 375.03 seconds
Started Jun 23 05:46:41 PM PDT 24
Finished Jun 23 05:52:56 PM PDT 24
Peak memory 255780 kb
Host smart-00a1782f-b39e-42fe-8108-c633b68c52ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054929055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2054929055
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.574527600
Short name T277
Test name
Test status
Simulation time 135675399 ps
CPU time 3.34 seconds
Started Jun 23 05:46:31 PM PDT 24
Finished Jun 23 05:46:35 PM PDT 24
Peak memory 233724 kb
Host smart-e572a539-c189-47fb-b1d6-83e94d1f198e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574527600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.574527600
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1924680277
Short name T520
Test name
Test status
Simulation time 4189823370 ps
CPU time 8 seconds
Started Jun 23 05:46:31 PM PDT 24
Finished Jun 23 05:46:40 PM PDT 24
Peak memory 233920 kb
Host smart-7ae51c5e-8704-4010-9204-470897e2b157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924680277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1924680277
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.720239524
Short name T576
Test name
Test status
Simulation time 3932488426 ps
CPU time 12.1 seconds
Started Jun 23 05:46:31 PM PDT 24
Finished Jun 23 05:46:44 PM PDT 24
Peak memory 233928 kb
Host smart-1aa17264-a1be-4b2b-938b-a1f93a939239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720239524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.720239524
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1032983039
Short name T35
Test name
Test status
Simulation time 28826819 ps
CPU time 1.03 seconds
Started Jun 23 05:46:34 PM PDT 24
Finished Jun 23 05:46:36 PM PDT 24
Peak memory 217532 kb
Host smart-c05c00af-b7ce-4337-97e8-9e9cff089b46
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032983039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1032983039
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3159783414
Short name T234
Test name
Test status
Simulation time 843769628 ps
CPU time 3.5 seconds
Started Jun 23 05:46:32 PM PDT 24
Finished Jun 23 05:46:37 PM PDT 24
Peak memory 225600 kb
Host smart-4af70feb-92d5-434d-b6b6-80a00b7dc1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159783414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3159783414
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.790990532
Short name T720
Test name
Test status
Simulation time 605834531 ps
CPU time 3.82 seconds
Started Jun 23 05:46:32 PM PDT 24
Finished Jun 23 05:46:36 PM PDT 24
Peak memory 225604 kb
Host smart-4f91702d-2690-4edb-b2df-fd52e6fc52b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790990532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.790990532
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2725038379
Short name T2
Test name
Test status
Simulation time 1941299598 ps
CPU time 8.36 seconds
Started Jun 23 05:46:32 PM PDT 24
Finished Jun 23 05:46:42 PM PDT 24
Peak memory 221204 kb
Host smart-3d00ea57-e73b-4b82-9621-74a61611a62e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2725038379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2725038379
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3104220450
Short name T150
Test name
Test status
Simulation time 6933990828 ps
CPU time 68.96 seconds
Started Jun 23 05:46:34 PM PDT 24
Finished Jun 23 05:47:44 PM PDT 24
Peak memory 250224 kb
Host smart-ace6e424-7468-4954-abed-0e1eacf1e6ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104220450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3104220450
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.552914814
Short name T822
Test name
Test status
Simulation time 1372189088 ps
CPU time 8.57 seconds
Started Jun 23 05:46:34 PM PDT 24
Finished Jun 23 05:46:44 PM PDT 24
Peak memory 217296 kb
Host smart-e8b12a24-83ae-4dea-a273-311fa786c694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552914814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.552914814
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.164243027
Short name T337
Test name
Test status
Simulation time 434433402 ps
CPU time 2.73 seconds
Started Jun 23 05:46:37 PM PDT 24
Finished Jun 23 05:46:41 PM PDT 24
Peak memory 217320 kb
Host smart-d32275e0-c1ce-4b13-afa6-527042defa9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164243027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.164243027
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.83922281
Short name T691
Test name
Test status
Simulation time 169546855 ps
CPU time 1.18 seconds
Started Jun 23 05:46:32 PM PDT 24
Finished Jun 23 05:46:35 PM PDT 24
Peak memory 217280 kb
Host smart-062ba022-0b50-4af9-9aac-cb1b572f65ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83922281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.83922281
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.825478939
Short name T376
Test name
Test status
Simulation time 74945087 ps
CPU time 0.83 seconds
Started Jun 23 05:46:32 PM PDT 24
Finished Jun 23 05:46:35 PM PDT 24
Peak memory 206880 kb
Host smart-6af48643-8472-4579-9866-a96a95d1bd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825478939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.825478939
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2114486479
Short name T498
Test name
Test status
Simulation time 360604772 ps
CPU time 3.18 seconds
Started Jun 23 05:46:35 PM PDT 24
Finished Jun 23 05:46:39 PM PDT 24
Peak memory 233984 kb
Host smart-bca0234e-85c0-4ef2-983c-1c8aca0da02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114486479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2114486479
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2879800785
Short name T420
Test name
Test status
Simulation time 27470970 ps
CPU time 0.71 seconds
Started Jun 23 05:46:36 PM PDT 24
Finished Jun 23 05:46:38 PM PDT 24
Peak memory 205744 kb
Host smart-9aeb7899-47bf-463f-8196-af00bc78b1dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879800785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
879800785
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1127733534
Short name T928
Test name
Test status
Simulation time 146954813 ps
CPU time 3.42 seconds
Started Jun 23 05:46:41 PM PDT 24
Finished Jun 23 05:46:45 PM PDT 24
Peak memory 225492 kb
Host smart-6045eacc-2d1c-4aaa-a0ef-81b0c43a2970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127733534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1127733534
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2948195789
Short name T923
Test name
Test status
Simulation time 126600825 ps
CPU time 0.77 seconds
Started Jun 23 05:46:32 PM PDT 24
Finished Jun 23 05:46:33 PM PDT 24
Peak memory 207516 kb
Host smart-ecf1a327-0b00-4e04-8164-6a490aedf5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948195789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2948195789
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.4177357513
Short name T196
Test name
Test status
Simulation time 16880395007 ps
CPU time 91.33 seconds
Started Jun 23 05:46:34 PM PDT 24
Finished Jun 23 05:48:07 PM PDT 24
Peak memory 256724 kb
Host smart-de79babd-80a9-4ba2-9cd1-4a214d3fc9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177357513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.4177357513
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2199043619
Short name T628
Test name
Test status
Simulation time 39623571235 ps
CPU time 50.3 seconds
Started Jun 23 05:46:37 PM PDT 24
Finished Jun 23 05:47:29 PM PDT 24
Peak memory 241776 kb
Host smart-c07a2ec5-a3e1-4474-99d7-a92b591075eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199043619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2199043619
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1691943754
Short name T755
Test name
Test status
Simulation time 2163115379 ps
CPU time 21.21 seconds
Started Jun 23 05:46:38 PM PDT 24
Finished Jun 23 05:47:00 PM PDT 24
Peak memory 225596 kb
Host smart-8a613fc0-2d97-4f7c-8f3d-45b8ab418ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691943754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1691943754
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.72967662
Short name T681
Test name
Test status
Simulation time 7143003996 ps
CPU time 17.24 seconds
Started Jun 23 05:46:36 PM PDT 24
Finished Jun 23 05:46:54 PM PDT 24
Peak memory 225536 kb
Host smart-c0467cc2-a55b-4371-98dd-87b689c4b530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72967662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.72967662
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1752485899
Short name T626
Test name
Test status
Simulation time 15994411335 ps
CPU time 98.4 seconds
Started Jun 23 05:46:39 PM PDT 24
Finished Jun 23 05:48:18 PM PDT 24
Peak memory 234544 kb
Host smart-ae9b7fe7-66da-40d9-a93d-1b01636693d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752485899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1752485899
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2231748179
Short name T625
Test name
Test status
Simulation time 56610663 ps
CPU time 1 seconds
Started Jun 23 05:46:37 PM PDT 24
Finished Jun 23 05:46:39 PM PDT 24
Peak memory 218880 kb
Host smart-da76ec58-472e-4a55-898e-b7cf7bc12bf4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231748179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2231748179
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.900166148
Short name T209
Test name
Test status
Simulation time 26056849025 ps
CPU time 20.36 seconds
Started Jun 23 05:46:35 PM PDT 24
Finished Jun 23 05:46:56 PM PDT 24
Peak memory 250416 kb
Host smart-d00968a4-974c-4f5e-b13b-d712396eb773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900166148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
900166148
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3868728618
Short name T477
Test name
Test status
Simulation time 24761807918 ps
CPU time 18.35 seconds
Started Jun 23 05:46:36 PM PDT 24
Finished Jun 23 05:46:56 PM PDT 24
Peak memory 233872 kb
Host smart-1ff0918e-d2f5-436a-8bfc-48bb431761be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868728618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3868728618
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3788766050
Short name T310
Test name
Test status
Simulation time 915199282 ps
CPU time 8.29 seconds
Started Jun 23 05:46:36 PM PDT 24
Finished Jun 23 05:46:46 PM PDT 24
Peak memory 221096 kb
Host smart-824b2264-142d-450f-ab5c-60545e90c8d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3788766050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3788766050
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.764897481
Short name T34
Test name
Test status
Simulation time 34098130329 ps
CPU time 345.5 seconds
Started Jun 23 05:46:38 PM PDT 24
Finished Jun 23 05:52:24 PM PDT 24
Peak memory 251392 kb
Host smart-b068fceb-e91d-46f2-b0c4-57da5a9d11bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764897481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.764897481
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1785953226
Short name T677
Test name
Test status
Simulation time 6404752442 ps
CPU time 26.75 seconds
Started Jun 23 05:46:31 PM PDT 24
Finished Jun 23 05:46:59 PM PDT 24
Peak memory 217528 kb
Host smart-055a10a7-b7c3-4ec5-a922-51e87ed21be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785953226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1785953226
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.281959229
Short name T827
Test name
Test status
Simulation time 994418625 ps
CPU time 4.47 seconds
Started Jun 23 05:46:37 PM PDT 24
Finished Jun 23 05:46:42 PM PDT 24
Peak memory 217384 kb
Host smart-18293cd7-4ef1-4dd5-bb8f-c43faccd4062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281959229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.281959229
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1573423171
Short name T60
Test name
Test status
Simulation time 31431883 ps
CPU time 1.01 seconds
Started Jun 23 05:46:33 PM PDT 24
Finished Jun 23 05:46:35 PM PDT 24
Peak memory 208292 kb
Host smart-7c03d231-2b26-4177-bfc2-18860f7c33ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573423171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1573423171
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.963280023
Short name T380
Test name
Test status
Simulation time 36569139 ps
CPU time 0.87 seconds
Started Jun 23 05:46:31 PM PDT 24
Finished Jun 23 05:46:33 PM PDT 24
Peak memory 207908 kb
Host smart-36e96a89-7cb9-48f8-8c08-82139bc17925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963280023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.963280023
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.973768591
Short name T225
Test name
Test status
Simulation time 171814554 ps
CPU time 3.42 seconds
Started Jun 23 05:46:36 PM PDT 24
Finished Jun 23 05:46:41 PM PDT 24
Peak memory 233716 kb
Host smart-14b3de2d-ac8d-4439-af74-d39435782503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973768591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.973768591
Directory /workspace/9.spi_device_upload/latest
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