Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2691267	1			T1	4593		T2	1		T4	1
all_values[1]	2691267	1			T1	4593		T2	1		T4	1
all_values[2]	2691267	1			T1	4593		T2	1		T4	1
all_values[3]	2691267	1			T1	4593		T2	1		T4	1
all_values[4]	2691267	1			T1	4593		T2	1		T4	1
all_values[5]	2691267	1			T1	4593		T2	1		T4	1
all_values[6]	2691267	1			T1	4593		T2	1		T4	1
all_values[7]	2691267	1			T1	4593		T2	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20626444

1

T1

36744

T2

8

T4

8

auto[1]

903692

1

T20

40

T22

46

T24

130

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21507275

1

T1

36245

T2

8

T4

8

auto[1]

22861

1

T1

499

T15

8

T29

117

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2536294	1			T1	4365		T2	1		T4	1
all_values[0]	auto[0]	auto[1]	10488	1			T1	228		T15	4		T29	65
all_values[0]	auto[1]	auto[0]	143592	1			T20	3		T22	5		T24	8
all_values[0]	auto[1]	auto[1]	893	1			T20	3		T22	4		T24	3
all_values[1]	auto[0]	auto[0]	2517301	1			T1	4432		T2	1		T4	1
all_values[1]	auto[0]	auto[1]	6318	1			T1	161		T15	4		T29	52
all_values[1]	auto[1]	auto[0]	167125	1			T20	5		T22	1		T24	13
all_values[1]	auto[1]	auto[1]	523	1			T20	2		T22	1		T24	5
all_values[2]	auto[0]	auto[0]	2572747	1			T1	4483		T2	1		T4	1
all_values[2]	auto[0]	auto[1]	2508	1			T1	110		T20	88		T21	44
all_values[2]	auto[1]	auto[0]	115777	1			T20	1		T22	9		T24	7
all_values[2]	auto[1]	auto[1]	235	1			T20	1		T22	1		T24	8
all_values[3]	auto[0]	auto[0]	2667417	1			T1	4593		T2	1		T4	1
all_values[3]	auto[0]	auto[1]	180	1			T20	1		T22	5		T24	4
all_values[3]	auto[1]	auto[0]	23488	1			T20	3		T22	1		T24	11
all_values[3]	auto[1]	auto[1]	182	1			T20	3		T22	3		T24	5
all_values[4]	auto[0]	auto[0]	2601669	1			T1	4593		T2	1		T4	1
all_values[4]	auto[0]	auto[1]	209	1			T22	1		T24	5		T33	3
all_values[4]	auto[1]	auto[0]	89214	1			T20	4		T22	7		T24	7
all_values[4]	auto[1]	auto[1]	175	1			T20	1		T22	4		T24	14
all_values[5]	auto[0]	auto[0]	2673676	1			T1	4593		T2	1		T4	1
all_values[5]	auto[0]	auto[1]	189	1			T20	1		T22	1		T24	6
all_values[5]	auto[1]	auto[0]	17232	1			T20	4		T22	3		T24	13
all_values[5]	auto[1]	auto[1]	170	1			T22	1		T24	6		T33	3
all_values[6]	auto[0]	auto[0]	2541257	1			T1	4593		T2	1		T4	1
all_values[6]	auto[0]	auto[1]	213	1			T22	5		T24	2		T33	5
all_values[6]	auto[1]	auto[0]	149616	1			T20	6		T22	1		T24	12
all_values[6]	auto[1]	auto[1]	181	1			T20	1		T22	2		T24	9
all_values[7]	auto[0]	auto[0]	2495773	1			T1	4593		T2	1		T4	1
all_values[7]	auto[0]	auto[1]	205	1			T20	1		T22	5		T24	8
all_values[7]	auto[1]	auto[0]	195097	1			T20	3		T22	1		T24	3
all_values[7]	auto[1]	auto[1]	192	1			T22	2		T24	6		T33	3